Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	117096	1			T1	3		T2	6		T3	1
all_values[1]	117096	1			T1	3		T2	6		T3	1
all_values[2]	117096	1			T1	3		T2	6		T3	1
all_values[3]	117096	1			T1	3		T2	6		T3	1
all_values[4]	117096	1			T1	3		T2	6		T3	1
all_values[5]	117096	1			T1	3		T2	6		T3	1
all_values[6]	117096	1			T1	3		T2	6		T3	1
all_values[7]	117096	1			T1	3		T2	6		T3	1
all_values[8]	117096	1			T1	3		T2	6		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

533587

1

T1

13

T2

36

T3

6

auto[1]

520277

1

T1

14

T2

18

T3

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958273

1

T1

20

T2

48

T3

7

auto[1]

95591

1

T1

7

T2

6

T3

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	35543	1			T2	1		T5	5		T8	303
all_values[0]	auto[0]	auto[1]	24729	1			T1	3		T2	2		T3	1
all_values[0]	auto[1]	auto[0]	33692	1			T2	3		T4	6		T6	3
all_values[0]	auto[1]	auto[1]	23132	1			T4	4		T5	1		T6	3
all_values[1]	auto[0]	auto[0]	56466	1			T1	2		T2	6		T3	1
all_values[1]	auto[0]	auto[1]	1569	1			T6	1		T8	2		T10	5
all_values[1]	auto[1]	auto[0]	57422	1			T1	1		T4	1		T5	6
all_values[1]	auto[1]	auto[1]	1639	1			T8	1		T9	2		T10	4
all_values[2]	auto[0]	auto[0]	55126	1			T2	4		T4	6		T5	16
all_values[2]	auto[0]	auto[1]	2911	1			T2	2		T4	5		T5	2
all_values[2]	auto[1]	auto[0]	56612	1			T1	2		T3	1		T5	1
all_values[2]	auto[1]	auto[1]	2447	1			T1	1		T4	1		T5	4
all_values[3]	auto[0]	auto[0]	58844	1			T1	2		T2	3		T3	1
all_values[3]	auto[0]	auto[1]	358	1			T4	2		T8	2		T10	1
all_values[3]	auto[1]	auto[0]	57560	1			T1	1		T2	3		T5	17
all_values[3]	auto[1]	auto[1]	334	1			T8	1		T12	1		T28	4
all_values[4]	auto[0]	auto[0]	56596	1			T1	1		T2	6		T3	1
all_values[4]	auto[0]	auto[1]	414	1			T10	1		T13	2		T12	6
all_values[4]	auto[1]	auto[0]	59629	1			T1	2		T4	1		T5	11
all_values[4]	auto[1]	auto[1]	457	1			T8	2		T10	1		T13	2
all_values[5]	auto[0]	auto[0]	57509	1			T1	2		T2	6		T3	1
all_values[5]	auto[0]	auto[1]	183	1			T8	2		T10	3		T13	1
all_values[5]	auto[1]	auto[0]	59204	1			T1	1		T5	17		T6	3
all_values[5]	auto[1]	auto[1]	200	1			T10	3		T28	3		T14	3
all_values[6]	auto[0]	auto[0]	60921	1			T4	4		T5	6		T6	1
all_values[6]	auto[0]	auto[1]	171	1			T8	2		T13	3		T28	4
all_values[6]	auto[1]	auto[0]	55811	1			T1	3		T2	6		T3	1
all_values[6]	auto[1]	auto[1]	193	1			T13	1		T27	3		T28	4
all_values[7]	auto[0]	auto[0]	63489	1			T1	3		T2	6		T3	1
all_values[7]	auto[0]	auto[1]	371	1			T6	1		T8	3		T13	1
all_values[7]	auto[1]	auto[0]	52865	1			T5	12		T6	5		T8	274
all_values[7]	auto[1]	auto[1]	371	1			T6	2		T8	1		T10	1
all_values[8]	auto[0]	auto[0]	40687	1			T5	7		T8	236		T10	22
all_values[8]	auto[0]	auto[1]	17700	1			T4	5		T5	16		T6	1
all_values[8]	auto[1]	auto[0]	40297	1			T2	4		T4	6		T6	4
all_values[8]	auto[1]	auto[1]	18412	1			T1	3		T2	2		T3	1