Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2394	1			T1	1		T3	10		T4	1
auto[BaudRate115200]	2102	1			T5	4		T6	3		T8	34
auto[BaudRate230400]	2120	1			T1	1		T2	1		T4	1
auto[BaudRate128Kbps]	2054	1			T4	2		T6	2		T8	28
auto[BaudRate256Kbps]	2359	1			T1	8		T2	2		T4	1
auto[BaudRate1Mbps]	1977	1			T4	1		T5	1		T7	1
auto[BaudRate1p5Mbps]	1573	1			T2	1		T4	1		T5	4

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1221	1			T6	10		T7	2		T33	9
freqs[25]	1428	1			T2	4		T229	9		T237	8
freqs[48]	408	1			T230	20		T106	10		T138	10
freqs[50]	924	1			T241	5		T90	7		T258	2
freqs[100]	1346	1			T3	10		T11	20		T26	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	210	1			T6	3		T7	1		T33	1
auto[BaudRate9600]	freqs[25]	270	1			T120	2		T29	14		T227	2
auto[BaudRate9600]	freqs[48]	60	1			T230	2		T106	1		T138	2
auto[BaudRate9600]	freqs[50]	104	1			T90	1		T258	1		T151	1
auto[BaudRate9600]	freqs[100]	186	1			T3	10		T11	5		T26	3
auto[BaudRate115200]	freqs[24]	182	1			T6	3		T33	1		T13	1
auto[BaudRate115200]	freqs[25]	183	1			T237	2		T107	1		T110	2
auto[BaudRate115200]	freqs[48]	53	1			T230	3		T106	3		T138	1
auto[BaudRate115200]	freqs[50]	125	1			T241	1		T90	1		T151	1
auto[BaudRate115200]	freqs[100]	169	1			T11	1		T26	1		T115	2
auto[BaudRate230400]	freqs[24]	185	1			T27	3		T36	2		T96	1
auto[BaudRate230400]	freqs[25]	200	1			T2	1		T237	1		T107	4
auto[BaudRate230400]	freqs[48]	54	1			T230	2		T106	1		T275	1
auto[BaudRate230400]	freqs[50]	141	1			T90	3		T294	2		T295	1
auto[BaudRate230400]	freqs[100]	176	1			T11	3		T233	1		T101	14
auto[BaudRate128Kbps]	freqs[24]	163	1			T6	2		T13	1		T27	2
auto[BaudRate128Kbps]	freqs[25]	225	1			T107	2		T110	4		T270	1
auto[BaudRate128Kbps]	freqs[48]	51	1			T230	5		T106	2		T138	1
auto[BaudRate128Kbps]	freqs[50]	119	1			T241	2		T90	1		T258	1
auto[BaudRate128Kbps]	freqs[100]	184	1			T11	4		T26	1		T115	3
auto[BaudRate256Kbps]	freqs[24]	209	1			T6	1		T33	3		T13	3
auto[BaudRate256Kbps]	freqs[25]	210	1			T2	2		T229	2		T237	3
auto[BaudRate256Kbps]	freqs[48]	56	1			T230	4		T138	1		T275	2
auto[BaudRate256Kbps]	freqs[50]	121	1			T296	3		T294	1		T295	1
auto[BaudRate256Kbps]	freqs[100]	229	1			T11	4		T115	1		T91	1
auto[BaudRate1Mbps]	freqs[24]	177	1			T7	1		T33	4		T34	1
auto[BaudRate1Mbps]	freqs[25]	218	1			T229	5		T237	2		T107	1
auto[BaudRate1Mbps]	freqs[48]	63	1			T230	4		T106	2		T138	1
auto[BaudRate1Mbps]	freqs[50]	162	1			T296	2		T294	1		T297	5
auto[BaudRate1Mbps]	freqs[100]	195	1			T11	1		T26	3		T115	1
auto[BaudRate1p5Mbps]	freqs[25]	122	1			T2	1		T229	2		T110	1
auto[BaudRate1p5Mbps]	freqs[48]	71	1			T106	1		T138	4		T247	2
auto[BaudRate1p5Mbps]	freqs[50]	152	1			T241	2		T90	1		T296	1
auto[BaudRate1p5Mbps]	freqs[100]	207	1			T11	2		T26	1		T243	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded