Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	32963900	1			T1	27		T2	32		T3	1
all_levels[1]	194158	1			T1	1		T2	2		T4	4
all_levels[2]	2440	1			T2	2		T4	2		T5	2
all_levels[3]	1015	1			T2	2		T4	5		T5	2
all_levels[4]	690	1			T2	1		T6	3		T8	2
all_levels[5]	523	1			T2	1		T5	4		T10	2
all_levels[6]	428	1			T5	1		T10	4		T115	3
all_levels[7]	334	1			T5	2		T10	2		T35	2
all_levels[8]	271	1			T6	1		T10	2		T115	1
all_levels[9]	249	1			T5	1		T9	2		T115	1
all_levels[10]	209	1			T6	2		T35	1		T37	1
all_levels[11]	161	1			T31	1		T106	1		T107	1
all_levels[12]	160	1			T8	1		T10	1		T35	2
all_levels[13]	157	1			T10	1		T31	1		T116	1
all_levels[14]	143	1			T1	2		T10	1		T33	1
all_levels[15]	141	1			T8	1		T31	3		T14	1
all_levels[16]	119	1			T37	1		T38	2		T96	2
all_levels[17]	107	1			T1	1		T6	1		T115	1
all_levels[18]	81	1			T10	2		T35	2		T96	2
all_levels[19]	87	1			T33	2		T115	1		T107	1
all_levels[20]	85	1			T1	1		T6	1		T115	1
all_levels[21]	65	1			T18	1		T96	1		T42	2
all_levels[22]	81	1			T31	1		T38	1		T96	1
all_levels[23]	77	1			T10	1		T31	1		T115	1
all_levels[24]	76	1			T117	1		T29	1		T42	1
all_levels[25]	69	1			T6	1		T33	3		T37	1
all_levels[26]	64	1			T10	1		T31	1		T37	1
all_levels[27]	49	1			T1	1		T6	2		T14	1
all_levels[28]	38	1			T14	1		T48	1		T118	3
all_levels[29]	43	1			T91	1		T98	1		T117	1
all_levels[30]	40	1			T107	1		T117	2		T119	1
all_levels[31]	36	1			T1	1		T115	1		T107	2
all_levels[32]	34	1			T120	2		T117	1		T121	1
all_levels[33]	26	1			T18	1		T122	1		T123	1
all_levels[34]	33	1			T37	2		T96	1		T42	1
all_levels[35]	17	1			T117	1		T62	1		T124	1
all_levels[36]	38	1			T125	3		T42	1		T45	1
all_levels[37]	28	1			T35	2		T117	1		T44	1
all_levels[38]	18	1			T119	1		T126	1		T109	1
all_levels[39]	13	1			T37	1		T48	1		T127	1
all_levels[40]	27	1			T41	1		T42	3		T46	1
all_levels[41]	15	1			T14	1		T107	1		T96	1
all_levels[42]	10	1			T117	1		T46	1		T128	1
all_levels[43]	27	1			T31	2		T117	3		T41	1
all_levels[44]	19	1			T107	1		T129	1		T103	2
all_levels[45]	15	1			T130	1		T131	1		T132	2
all_levels[46]	14	1			T112	1		T133	1		T134	1
all_levels[47]	13	1			T107	2		T130	1		T103	1
all_levels[48]	12	1			T135	1		T41	1		T136	1
all_levels[49]	9	1			T137	2		T103	2		T128	1
all_levels[50]	15	1			T138	1		T123	2		T139	1
all_levels[51]	6	1			T140	1		T141	1		T142	1
all_levels[52]	14	1			T96	1		T123	1		T128	1
all_levels[53]	17	1			T18	1		T143	1		T103	1
all_levels[54]	18	1			T8	2		T119	1		T29	1
all_levels[55]	13	1			T1	1		T44	2		T144	1
all_levels[56]	8	1			T136	2		T145	1		T146	1
all_levels[57]	9	1			T147	1		T139	1		T148	1
all_levels[58]	9	1			T92	4		T94	2		T149	1
all_levels[59]	10	1			T150	2		T151	3		T152	1
all_levels[60]	11	1			T119	1		T150	1		T153	1
all_levels[61]	9	1			T154	2		T155	1		T132	2
all_levels[62]	4	1			T123	1		T156	1		T157	1
all_levels[63]	3	1			T126	1		T53	1		T158	1
all_levels[64]	102	1			T1	2		T8	2		T94	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33161907

1

T1

37

T2

40

T4

14

auto[1]

4805

1

T3

1

T4

7

T8

24

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[38] , all_levels[39]]	[auto[1]]	--	--	2
[all_levels[41] , all_levels[42]]	[auto[1]]	--	--	2
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	32959601	1			T1	27		T2	32		T4	6
all_levels[0]	auto[1]	4299	1			T3	1		T4	4		T8	24
all_levels[1]	auto[0]	194069	1			T1	1		T2	2		T4	4
all_levels[1]	auto[1]	89	1			T154	1		T138	1		T47	2
all_levels[2]	auto[0]	2406	1			T2	2		T4	2		T5	2
all_levels[2]	auto[1]	34	1			T47	1		T101	1		T159	2
all_levels[3]	auto[0]	994	1			T2	2		T4	2		T5	2
all_levels[3]	auto[1]	21	1			T4	3		T160	2		T161	1
all_levels[4]	auto[0]	670	1			T2	1		T6	3		T8	2
all_levels[4]	auto[1]	20	1			T47	2		T162	1		T163	2
all_levels[5]	auto[0]	498	1			T2	1		T5	4		T10	2
all_levels[5]	auto[1]	25	1			T107	1		T154	1		T164	1
all_levels[6]	auto[0]	406	1			T5	1		T10	4		T115	3
all_levels[6]	auto[1]	22	1			T154	1		T135	2		T165	5
all_levels[7]	auto[0]	328	1			T5	2		T10	2		T35	2
all_levels[7]	auto[1]	6	1			T166	1		T167	1		T168	1
all_levels[8]	auto[0]	253	1			T6	1		T10	2		T115	1
all_levels[8]	auto[1]	18	1			T29	2		T169	2		T139	1
all_levels[9]	auto[0]	228	1			T5	1		T9	2		T115	1
all_levels[9]	auto[1]	21	1			T170	1		T171	1		T50	4
all_levels[10]	auto[0]	198	1			T6	2		T35	1		T37	1
all_levels[10]	auto[1]	11	1			T44	1		T172	1		T127	1
all_levels[11]	auto[0]	156	1			T31	1		T106	1		T107	1
all_levels[11]	auto[1]	5	1			T173	1		T174	1		T175	1
all_levels[12]	auto[0]	152	1			T8	1		T10	1		T35	1
all_levels[12]	auto[1]	8	1			T35	1		T98	1		T176	1
all_levels[13]	auto[0]	146	1			T10	1		T31	1		T116	1
all_levels[13]	auto[1]	11	1			T42	1		T47	2		T177	1
all_levels[14]	auto[0]	133	1			T1	2		T10	1		T33	1
all_levels[14]	auto[1]	10	1			T178	1		T145	1		T179	1
all_levels[15]	auto[0]	124	1			T8	1		T31	1		T14	1
all_levels[15]	auto[1]	17	1			T31	2		T180	3		T181	1
all_levels[16]	auto[0]	106	1			T37	1		T38	2		T96	2
all_levels[16]	auto[1]	13	1			T100	2		T127	1		T182	6
all_levels[17]	auto[0]	90	1			T1	1		T6	1		T115	1
all_levels[17]	auto[1]	17	1			T41	1		T150	1		T183	2
all_levels[18]	auto[0]	76	1			T10	2		T35	1		T96	2
all_levels[18]	auto[1]	5	1			T35	1		T184	1		T185	1
all_levels[19]	auto[0]	79	1			T33	1		T115	1		T107	1
all_levels[19]	auto[1]	8	1			T33	1		T91	1		T186	1
all_levels[20]	auto[0]	75	1			T1	1		T6	1		T115	1
all_levels[20]	auto[1]	10	1			T44	1		T187	2		T188	1
all_levels[21]	auto[0]	63	1			T18	1		T96	1		T42	2
all_levels[21]	auto[1]	2	1			T100	1		T189	1		-	-
all_levels[22]	auto[0]	75	1			T31	1		T38	1		T96	1
all_levels[22]	auto[1]	6	1			T186	1		T155	2		T190	1
all_levels[23]	auto[0]	69	1			T10	1		T31	1		T115	1
all_levels[23]	auto[1]	8	1			T125	1		T191	2		T192	2
all_levels[24]	auto[0]	68	1			T117	1		T29	1		T42	1
all_levels[24]	auto[1]	8	1			T139	1		T181	2		T193	2
all_levels[25]	auto[0]	58	1			T6	1		T33	2		T37	1
all_levels[25]	auto[1]	11	1			T33	1		T124	2		T194	2
all_levels[26]	auto[0]	58	1			T10	1		T31	1		T37	1
all_levels[26]	auto[1]	6	1			T44	1		T195	1		T196	3
all_levels[27]	auto[0]	47	1			T1	1		T6	2		T14	1
all_levels[27]	auto[1]	2	1			T197	1		T198	1		-	-
all_levels[28]	auto[0]	34	1			T14	1		T48	1		T118	3
all_levels[28]	auto[1]	4	1			T197	2		T199	1		T200	1
all_levels[29]	auto[0]	41	1			T91	1		T98	1		T117	1
all_levels[29]	auto[1]	2	1			T186	1		T201	1		-	-
all_levels[30]	auto[0]	37	1			T107	1		T117	2		T119	1
all_levels[30]	auto[1]	3	1			T202	1		T203	2		-	-
all_levels[31]	auto[0]	34	1			T1	1		T115	1		T107	2
all_levels[31]	auto[1]	2	1			T204	1		T205	1		-	-
all_levels[32]	auto[0]	23	1			T120	2		T117	1		T121	1
all_levels[32]	auto[1]	11	1			T42	7		T206	3		T205	1
all_levels[33]	auto[0]	26	1			T18	1		T122	1		T123	1
all_levels[34]	auto[0]	30	1			T37	2		T96	1		T42	1
all_levels[34]	auto[1]	3	1			T48	1		T207	2		-	-
all_levels[35]	auto[0]	15	1			T117	1		T62	1		T124	1
all_levels[35]	auto[1]	2	1			T208	2		-	-		-	-
all_levels[36]	auto[0]	32	1			T125	2		T42	1		T45	1
all_levels[36]	auto[1]	6	1			T125	1		T145	1		T209	1
all_levels[37]	auto[0]	21	1			T35	1		T117	1		T44	1
all_levels[37]	auto[1]	7	1			T35	1		T145	1		T210	2
all_levels[38]	auto[0]	18	1			T119	1		T126	1		T109	1
all_levels[39]	auto[0]	13	1			T37	1		T48	1		T127	1
all_levels[40]	auto[0]	22	1			T41	1		T42	1		T46	1
all_levels[40]	auto[1]	5	1			T42	2		T211	2		T212	1
all_levels[41]	auto[0]	15	1			T14	1		T107	1		T96	1
all_levels[42]	auto[0]	10	1			T117	1		T46	1		T128	1
all_levels[43]	auto[0]	24	1			T31	1		T117	2		T41	1
all_levels[43]	auto[1]	3	1			T31	1		T117	1		T213	1
all_levels[44]	auto[0]	15	1			T107	1		T129	1		T103	2
all_levels[44]	auto[1]	4	1			T214	1		T215	2		T200	1
all_levels[45]	auto[0]	12	1			T130	1		T131	1		T132	1
all_levels[45]	auto[1]	3	1			T132	1		T216	1		T217	1
all_levels[46]	auto[0]	11	1			T112	1		T133	1		T134	1
all_levels[46]	auto[1]	3	1			T218	2		T219	1		-	-
all_levels[47]	auto[0]	11	1			T107	1		T130	1		T103	1
all_levels[47]	auto[1]	2	1			T107	1		T142	1		-	-
all_levels[48]	auto[0]	11	1			T135	1		T41	1		T136	1
all_levels[48]	auto[1]	1	1			T190	1		-	-		-	-
all_levels[49]	auto[0]	8	1			T137	1		T103	2		T128	1
all_levels[49]	auto[1]	1	1			T137	1		-	-		-	-
all_levels[50]	auto[0]	15	1			T138	1		T123	2		T139	1
all_levels[51]	auto[0]	5	1			T140	1		T141	1		T142	1
all_levels[51]	auto[1]	1	1			T220	1		-	-		-	-
all_levels[52]	auto[0]	14	1			T96	1		T123	1		T128	1
all_levels[53]	auto[0]	15	1			T18	1		T143	1		T103	1
all_levels[53]	auto[1]	2	1			T181	2		-	-		-	-
all_levels[54]	auto[0]	15	1			T8	2		T119	1		T29	1
all_levels[54]	auto[1]	3	1			T147	2		T221	1		-	-
all_levels[55]	auto[0]	12	1			T1	1		T44	1		T144	1
all_levels[55]	auto[1]	1	1			T44	1		-	-		-	-
all_levels[56]	auto[0]	7	1			T136	1		T145	1		T146	1
all_levels[56]	auto[1]	1	1			T136	1		-	-		-	-
all_levels[57]	auto[0]	9	1			T147	1		T139	1		T148	1
all_levels[58]	auto[0]	5	1			T92	1		T94	1		T149	1
all_levels[58]	auto[1]	4	1			T92	3		T94	1		-	-
all_levels[59]	auto[0]	6	1			T150	1		T151	1		T152	1
all_levels[59]	auto[1]	4	1			T150	1		T151	2		T222	1
all_levels[60]	auto[0]	9	1			T119	1		T150	1		T153	1
all_levels[60]	auto[1]	2	1			T223	2		-	-		-	-
all_levels[61]	auto[0]	7	1			T154	1		T155	1		T132	1
all_levels[61]	auto[1]	2	1			T154	1		T132	1		-	-
all_levels[62]	auto[0]	4	1			T123	1		T156	1		T157	1
all_levels[63]	auto[0]	3	1			T126	1		T53	1		T158	1
all_levels[64]	auto[0]	92	1			T1	2		T8	2		T94	1
all_levels[64]	auto[1]	10	1			T211	3		T224	1		T225	1