Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	117096	1			T1	3		T2	6		T3	1
all_pins[1]	117096	1			T1	3		T2	6		T3	1
all_pins[2]	117096	1			T1	3		T2	6		T3	1
all_pins[3]	117096	1			T1	3		T2	6		T3	1
all_pins[4]	117096	1			T1	3		T2	6		T3	1
all_pins[5]	117096	1			T1	3		T2	6		T3	1
all_pins[6]	117096	1			T1	3		T2	6		T3	1
all_pins[7]	117096	1			T1	3		T2	6		T3	1
all_pins[8]	117096	1			T1	3		T2	6		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1005712	1			T1	22		T2	50		T3	8
values[0x1]	48152	1			T1	5		T2	4		T3	1
transitions[0x0=>0x1]	38271	1			T1	4		T2	4		T4	10
transitions[0x1=>0x0]	38076	1			T1	5		T2	4		T3	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	93891	1			T1	3		T2	6		T3	1
all_pins[0]	values[0x1]	23205	1			T4	4		T5	1		T6	3
all_pins[0]	transitions[0x0=>0x1]	22663	1			T4	4		T5	1		T6	3
all_pins[0]	transitions[0x1=>0x0]	1090	1			T8	1		T9	2		T10	3
all_pins[1]	values[0x0]	115464	1			T1	3		T2	6		T3	1
all_pins[1]	values[0x1]	1632	1			T8	1		T9	2		T10	4
all_pins[1]	transitions[0x0=>0x1]	1499	1			T8	1		T9	2		T10	2
all_pins[1]	transitions[0x1=>0x0]	2377	1			T1	1		T4	1		T5	4
all_pins[2]	values[0x0]	114586	1			T1	2		T2	6		T3	1
all_pins[2]	values[0x1]	2510	1			T1	1		T4	1		T5	4
all_pins[2]	transitions[0x0=>0x1]	2432	1			T1	1		T4	1		T5	4
all_pins[2]	transitions[0x1=>0x0]	256	1			T12	1		T28	3		T14	4
all_pins[3]	values[0x0]	116762	1			T1	3		T2	6		T3	1
all_pins[3]	values[0x1]	334	1			T8	1		T12	1		T28	4
all_pins[3]	transitions[0x0=>0x1]	275	1			T12	1		T28	2		T14	2
all_pins[3]	transitions[0x1=>0x0]	398	1			T8	1		T10	1		T13	2
all_pins[4]	values[0x0]	116639	1			T1	3		T2	6		T3	1
all_pins[4]	values[0x1]	457	1			T8	2		T10	1		T13	2
all_pins[4]	transitions[0x0=>0x1]	382	1			T8	2		T10	1		T13	2
all_pins[4]	transitions[0x1=>0x0]	182	1			T10	3		T12	1		T28	2
all_pins[5]	values[0x0]	116839	1			T1	3		T2	6		T3	1
all_pins[5]	values[0x1]	257	1			T10	3		T12	1		T28	3
all_pins[5]	transitions[0x0=>0x1]	202	1			T10	3		T12	1		T28	3
all_pins[5]	transitions[0x1=>0x0]	843	1			T1	1		T2	2		T4	4
all_pins[6]	values[0x0]	116198	1			T1	2		T2	4		T3	1
all_pins[6]	values[0x1]	898	1			T1	1		T2	2		T4	4
all_pins[6]	transitions[0x0=>0x1]	836	1			T1	1		T2	2		T4	4
all_pins[6]	transitions[0x1=>0x0]	309	1			T6	1		T8	1		T10	1
all_pins[7]	values[0x0]	116725	1			T1	3		T2	6		T3	1
all_pins[7]	values[0x1]	371	1			T6	2		T8	1		T10	1
all_pins[7]	transitions[0x0=>0x1]	221	1			T6	1		T8	1		T13	1
all_pins[7]	transitions[0x1=>0x0]	18338	1			T1	3		T2	2		T3	1
all_pins[8]	values[0x0]	98608	1			T2	4		T4	11		T5	23
all_pins[8]	values[0x1]	18488	1			T1	3		T2	2		T3	1
all_pins[8]	transitions[0x0=>0x1]	9761	1			T1	2		T2	2		T4	1
all_pins[8]	transitions[0x1=>0x0]	14283	1			T4	3		T5	1		T6	2