Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8835704	1			T1	13		T2	2		T4	5
all_levels[1]	1179237	1			T1	6		T5	77		T8	9297
all_levels[2]	561518	1			T1	2		T5	10		T8	1223
all_levels[3]	345585	1			T2	7		T5	8		T6	2
all_levels[4]	352958	1			T1	2		T5	10		T6	1
all_levels[5]	271599	1			T5	15		T8	1548		T10	25
all_levels[6]	265404	1			T2	2		T6	1		T8	1198
all_levels[7]	262824	1			T5	4		T8	804		T9	15
all_levels[8]	240902	1			T2	1		T6	1		T8	760
all_levels[9]	584225	1			T5	1		T8	992		T10	20
all_levels[10]	237148	1			T5	2		T6	1		T8	758
all_levels[11]	409079	1			T5	2		T8	617		T10	24
all_levels[12]	215039	1			T5	8		T6	1		T8	1001
all_levels[13]	324073	1			T1	1		T2	7		T8	995
all_levels[14]	642059	1			T8	1000		T9	2		T10	30
all_levels[15]	203081	1			T4	1		T5	12		T8	621
all_levels[16]	257427	1			T4	3		T6	4		T8	693
all_levels[17]	270653	1			T2	2		T5	124		T8	533
all_levels[18]	210556	1			T6	4		T8	980		T10	29
all_levels[19]	206249	1			T4	3		T6	2		T8	878
all_levels[20]	234231	1			T4	1		T8	759		T10	18
all_levels[21]	473706	1			T6	1		T8	837		T10	19
all_levels[22]	185669	1			T2	1		T8	701		T10	27
all_levels[23]	296124	1			T4	2		T8	982		T10	22
all_levels[24]	413593	1			T4	2		T8	1000		T10	25
all_levels[25]	246804	1			T8	998		T10	25		T32	69
all_levels[26]	279017	1			T2	1		T4	1		T6	1
all_levels[27]	259831	1			T2	3		T4	1		T6	2
all_levels[28]	702289	1			T8	831		T10	21		T32	57
all_levels[29]	321160	1			T2	2		T8	666		T10	30
all_levels[30]	204369	1			T8	845		T10	36		T32	52
all_levels[31]	722747	1			T2	1		T8	5261		T10	693
all_levels[32]	12951314	1			T1	14		T2	12		T6	24

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33161907

1

T1

37

T2

40

T4

14

auto[1]

4267

1

T1

1

T2

1

T4

5

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8833129	1			T1	13		T2	2		T4	4
all_levels[0]	auto[1]	2575	1			T4	1		T6	1		T8	1
all_levels[1]	auto[0]	1178995	1			T1	6		T5	77		T8	9294
all_levels[1]	auto[1]	242	1			T8	3		T33	1		T27	1
all_levels[2]	auto[0]	561478	1			T1	2		T5	10		T8	1223
all_levels[2]	auto[1]	40	1			T172	1		T268	1		T178	2
all_levels[3]	auto[0]	345442	1			T2	6		T5	8		T6	2
all_levels[3]	auto[1]	143	1			T2	1		T107	1		T154	1
all_levels[4]	auto[0]	352932	1			T1	2		T5	10		T6	1
all_levels[4]	auto[1]	26	1			T113	1		T300	1		T188	1
all_levels[5]	auto[0]	271577	1			T5	15		T8	1548		T10	24
all_levels[5]	auto[1]	22	1			T10	1		T107	2		T114	1
all_levels[6]	auto[0]	265377	1			T2	2		T6	1		T8	1198
all_levels[6]	auto[1]	27	1			T154	1		T121	1		T44	1
all_levels[7]	auto[0]	262757	1			T5	4		T8	804		T9	14
all_levels[7]	auto[1]	67	1			T9	1		T97	1		T282	7
all_levels[8]	auto[0]	240867	1			T2	1		T6	1		T8	760
all_levels[8]	auto[1]	35	1			T35	1		T164	1		T121	2
all_levels[9]	auto[0]	584191	1			T5	1		T8	992		T10	20
all_levels[9]	auto[1]	34	1			T41	1		T47	1		T63	1
all_levels[10]	auto[0]	237126	1			T5	2		T6	1		T8	758
all_levels[10]	auto[1]	22	1			T228	2		T184	1		T301	2
all_levels[11]	auto[0]	409057	1			T5	2		T8	617		T10	24
all_levels[11]	auto[1]	22	1			T143	1		T183	2		T113	1
all_levels[12]	auto[0]	215016	1			T5	8		T6	1		T8	1001
all_levels[12]	auto[1]	23	1			T110	1		T226	1		T137	2
all_levels[13]	auto[0]	324059	1			T1	1		T2	7		T8	995
all_levels[13]	auto[1]	14	1			T33	1		T276	1		T302	1
all_levels[14]	auto[0]	642032	1			T8	1000		T9	2		T10	30
all_levels[14]	auto[1]	27	1			T35	1		T303	1		T126	4
all_levels[15]	auto[0]	202976	1			T4	1		T5	12		T8	621
all_levels[15]	auto[1]	105	1			T112	9		T279	5		T99	4
all_levels[16]	auto[0]	257396	1			T4	1		T6	4		T8	693
all_levels[16]	auto[1]	31	1			T4	2		T107	1		T246	3
all_levels[17]	auto[0]	270626	1			T2	2		T5	123		T8	533
all_levels[17]	auto[1]	27	1			T5	1		T41	2		T304	1
all_levels[18]	auto[0]	210532	1			T6	4		T8	980		T10	29
all_levels[18]	auto[1]	24	1			T91	1		T125	1		T269	1
all_levels[19]	auto[0]	206233	1			T4	1		T6	2		T8	878
all_levels[19]	auto[1]	16	1			T4	2		T247	1		T48	1
all_levels[20]	auto[0]	234197	1			T4	1		T8	759		T10	18
all_levels[20]	auto[1]	34	1			T243	1		T162	2		T104	1
all_levels[21]	auto[0]	473680	1			T6	1		T8	837		T10	19
all_levels[21]	auto[1]	26	1			T18	2		T165	1		T277	1
all_levels[22]	auto[0]	185651	1			T2	1		T8	701		T10	27
all_levels[22]	auto[1]	18	1			T48	1		T194	1		T305	1
all_levels[23]	auto[0]	296107	1			T4	2		T8	982		T10	22
all_levels[23]	auto[1]	17	1			T31	1		T125	1		T186	1
all_levels[24]	auto[0]	413570	1			T4	2		T8	1000		T10	25
all_levels[24]	auto[1]	23	1			T170	1		T195	1		T306	1
all_levels[25]	auto[0]	246794	1			T8	998		T10	25		T32	69
all_levels[25]	auto[1]	10	1			T112	1		T243	2		T307	1
all_levels[26]	auto[0]	279003	1			T2	1		T4	1		T6	1
all_levels[26]	auto[1]	14	1			T256	1		T165	5		T308	3
all_levels[27]	auto[0]	259810	1			T2	3		T4	1		T6	2
all_levels[27]	auto[1]	21	1			T44	1		T161	2		T186	1
all_levels[28]	auto[0]	702277	1			T8	831		T10	21		T32	57
all_levels[28]	auto[1]	12	1			T309	1		T183	1		T113	1
all_levels[29]	auto[0]	321145	1			T2	2		T8	666		T10	30
all_levels[29]	auto[1]	15	1			T154	1		T186	2		T310	1
all_levels[30]	auto[0]	204352	1			T8	845		T10	36		T32	52
all_levels[30]	auto[1]	17	1			T187	2		T311	2		T312	1
all_levels[31]	auto[0]	722724	1			T2	1		T8	5261		T10	693
all_levels[31]	auto[1]	23	1			T90	2		T117	1		T125	1
all_levels[32]	auto[0]	12950799	1			T1	13		T2	12		T6	24
all_levels[32]	auto[1]	515	1			T1	1		T31	1		T25	2