Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	808	1			T8	7		T10	8		T13	4
all_values[1]	808	1			T8	7		T10	8		T13	4
all_values[2]	808	1			T8	7		T10	8		T13	4
all_values[3]	808	1			T8	7		T10	8		T13	4
all_values[4]	808	1			T8	7		T10	8		T13	4
all_values[5]	808	1			T8	7		T10	8		T13	4
all_values[6]	808	1			T8	7		T10	8		T13	4
all_values[7]	808	1			T8	7		T10	8		T13	4
all_values[8]	808	1			T8	7		T10	8		T13	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3849

1

T8

38

T10

41

T13

23

auto[1]

3423

1

T8

25

T10

31

T13

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2348

1

T8

19

T10

35

T13

6

auto[1]

4924

1

T8

44

T10

37

T13

30

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4278

1

T8

37

T10

51

T13

18

auto[1]

2994

1

T8

26

T10

21

T13

18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	250	1			T8	3		T10	2		T13	1
all_values[0]	auto[0]	auto[1]	auto[1]	229	1			T8	4		T10	3		T13	1
all_values[0]	auto[1]	auto[0]	auto[1]	172	1			T10	2		T13	1		T27	1
all_values[0]	auto[1]	auto[1]	auto[1]	157	1			T10	1		T13	1		T27	2
all_values[1]	auto[0]	auto[0]	auto[0]	247	1			T8	1		T10	3		T28	3
all_values[1]	auto[0]	auto[1]	auto[0]	237	1			T8	3		T10	2		T13	2
all_values[1]	auto[1]	auto[0]	auto[1]	182	1			T8	2		T10	1		T13	1
all_values[1]	auto[1]	auto[1]	auto[1]	142	1			T8	1		T10	2		T13	1
all_values[2]	auto[0]	auto[0]	auto[0]	171	1			T8	1		T10	2		T13	1
all_values[2]	auto[0]	auto[0]	auto[1]	88	1			T8	2		T47	1		T103	1
all_values[2]	auto[0]	auto[1]	auto[0]	128	1			T10	1		T27	2		T28	2
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T10	2		T13	1		T28	1
all_values[2]	auto[1]	auto[0]	auto[1]	183	1			T8	2		T10	1		T13	2
all_values[2]	auto[1]	auto[1]	auto[1]	156	1			T8	2		T10	2		T28	5
all_values[3]	auto[0]	auto[0]	auto[0]	160	1			T8	2		T10	4		T13	1
all_values[3]	auto[0]	auto[0]	auto[1]	94	1			T8	2		T13	2		T28	1
all_values[3]	auto[0]	auto[1]	auto[0]	122	1			T10	3		T27	1		T28	1
all_values[3]	auto[0]	auto[1]	auto[1]	89	1			T28	4		T14	2		T17	1
all_values[3]	auto[1]	auto[0]	auto[1]	180	1			T10	1		T13	1		T27	2
all_values[3]	auto[1]	auto[1]	auto[1]	163	1			T8	3		T28	4		T14	5
all_values[4]	auto[0]	auto[0]	auto[0]	187	1			T8	1		T10	3		T27	1
all_values[4]	auto[0]	auto[0]	auto[1]	69	1			T13	1		T29	1		T48	3
all_values[4]	auto[0]	auto[1]	auto[0]	145	1			T8	3		T10	2		T27	3
all_values[4]	auto[0]	auto[1]	auto[1]	86	1			T10	1		T28	3		T14	3
all_values[4]	auto[1]	auto[0]	auto[1]	164	1			T10	1		T13	1		T28	2
all_values[4]	auto[1]	auto[1]	auto[1]	157	1			T8	3		T10	1		T13	2
all_values[5]	auto[0]	auto[0]	auto[0]	191	1			T8	1		T10	1		T13	1
all_values[5]	auto[0]	auto[0]	auto[1]	77	1			T8	2		T10	2		T13	1
all_values[5]	auto[0]	auto[1]	auto[0]	138	1			T8	1		T13	1		T27	2
all_values[5]	auto[0]	auto[1]	auto[1]	86	1			T10	1		T28	1		T14	1
all_values[5]	auto[1]	auto[0]	auto[1]	162	1			T8	2		T10	2		T13	1
all_values[5]	auto[1]	auto[1]	auto[1]	154	1			T8	1		T10	2		T27	1
all_values[6]	auto[0]	auto[0]	auto[0]	169	1			T8	3		T10	8		T28	1
all_values[6]	auto[0]	auto[0]	auto[1]	65	1			T8	1		T13	2		T28	1
all_values[6]	auto[0]	auto[1]	auto[0]	158	1			T8	1		T27	1		T28	3
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T27	2		T28	2		T14	1
all_values[6]	auto[1]	auto[0]	auto[1]	177	1			T8	2		T13	2		T28	5
all_values[6]	auto[1]	auto[1]	auto[1]	155	1			T27	1		T28	2		T14	5
all_values[7]	auto[0]	auto[0]	auto[0]	155	1			T8	2		T10	4		T27	2
all_values[7]	auto[0]	auto[0]	auto[1]	87	1			T28	3		T14	1		T29	1
all_values[7]	auto[0]	auto[1]	auto[0]	140	1			T10	2		T28	3		T14	5
all_values[7]	auto[0]	auto[1]	auto[1]	87	1			T8	2		T13	2		T28	1
all_values[7]	auto[1]	auto[0]	auto[1]	176	1			T8	3		T10	1		T13	1
all_values[7]	auto[1]	auto[1]	auto[1]	163	1			T10	1		T13	1		T27	2
all_values[8]	auto[0]	auto[0]	auto[1]	247	1			T8	2		T10	3		T27	1
all_values[8]	auto[0]	auto[1]	auto[1]	210	1			T10	2		T13	1		T27	2
all_values[8]	auto[1]	auto[0]	auto[1]	196	1			T8	4		T13	3		T27	1
all_values[8]	auto[1]	auto[1]	auto[1]	155	1			T8	1		T10	3		T28	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal