Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.55


Total test records in report: 1319
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T1253 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3118454022 Jul 15 04:26:21 PM PDT 24 Jul 15 04:26:23 PM PDT 24 14994712 ps
T1254 /workspace/coverage/cover_reg_top/1.uart_intr_test.2534654093 Jul 15 04:21:34 PM PDT 24 Jul 15 04:21:35 PM PDT 24 15474779 ps
T1255 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2295546156 Jul 15 04:21:44 PM PDT 24 Jul 15 04:21:46 PM PDT 24 98569261 ps
T1256 /workspace/coverage/cover_reg_top/15.uart_intr_test.3560669344 Jul 15 04:26:50 PM PDT 24 Jul 15 04:26:53 PM PDT 24 15474918 ps
T1257 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.865011058 Jul 15 04:28:08 PM PDT 24 Jul 15 04:28:12 PM PDT 24 30031270 ps
T1258 /workspace/coverage/cover_reg_top/17.uart_csr_rw.179922218 Jul 15 04:23:49 PM PDT 24 Jul 15 04:23:50 PM PDT 24 105455708 ps
T1259 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3458313493 Jul 15 04:26:19 PM PDT 24 Jul 15 04:26:23 PM PDT 24 220348499 ps
T1260 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2317076513 Jul 15 04:25:55 PM PDT 24 Jul 15 04:25:58 PM PDT 24 63096489 ps
T1261 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2041437508 Jul 15 04:26:23 PM PDT 24 Jul 15 04:26:26 PM PDT 24 15580341 ps
T1262 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3190592988 Jul 15 04:26:38 PM PDT 24 Jul 15 04:26:40 PM PDT 24 97383074 ps
T1263 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2711527016 Jul 15 04:28:06 PM PDT 24 Jul 15 04:28:10 PM PDT 24 90770058 ps
T1264 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.136005449 Jul 15 04:21:31 PM PDT 24 Jul 15 04:21:33 PM PDT 24 31472129 ps
T1265 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.465309215 Jul 15 04:27:06 PM PDT 24 Jul 15 04:27:07 PM PDT 24 24618869 ps
T1266 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.323333391 Jul 15 04:24:14 PM PDT 24 Jul 15 04:24:16 PM PDT 24 510290260 ps
T1267 /workspace/coverage/cover_reg_top/14.uart_intr_test.645889485 Jul 15 04:26:48 PM PDT 24 Jul 15 04:26:50 PM PDT 24 39506782 ps
T1268 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3108198881 Jul 15 04:26:35 PM PDT 24 Jul 15 04:26:37 PM PDT 24 15724209 ps
T1269 /workspace/coverage/cover_reg_top/3.uart_csr_rw.141124131 Jul 15 04:28:28 PM PDT 24 Jul 15 04:28:30 PM PDT 24 18359596 ps
T1270 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1084787301 Jul 15 04:27:50 PM PDT 24 Jul 15 04:27:54 PM PDT 24 24371051 ps
T1271 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1660327703 Jul 15 04:26:33 PM PDT 24 Jul 15 04:26:35 PM PDT 24 69720536 ps
T1272 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.207319618 Jul 15 04:27:51 PM PDT 24 Jul 15 04:27:56 PM PDT 24 71461320 ps
T1273 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3401064126 Jul 15 04:26:17 PM PDT 24 Jul 15 04:26:18 PM PDT 24 81970222 ps
T1274 /workspace/coverage/cover_reg_top/46.uart_intr_test.33636076 Jul 15 04:29:36 PM PDT 24 Jul 15 04:29:38 PM PDT 24 23803724 ps
T1275 /workspace/coverage/cover_reg_top/33.uart_intr_test.141648501 Jul 15 04:28:08 PM PDT 24 Jul 15 04:28:12 PM PDT 24 79943999 ps
T1276 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1261717573 Jul 15 04:23:39 PM PDT 24 Jul 15 04:23:41 PM PDT 24 327517159 ps
T1277 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2783264878 Jul 15 04:21:39 PM PDT 24 Jul 15 04:21:42 PM PDT 24 58355676 ps
T1278 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3673171 Jul 15 04:26:56 PM PDT 24 Jul 15 04:26:59 PM PDT 24 186568650 ps
T1279 /workspace/coverage/cover_reg_top/2.uart_csr_rw.3458527110 Jul 15 04:26:45 PM PDT 24 Jul 15 04:26:47 PM PDT 24 49256308 ps
T86 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1697285012 Jul 15 04:24:50 PM PDT 24 Jul 15 04:24:52 PM PDT 24 95134034 ps
T1280 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3653069745 Jul 15 04:26:50 PM PDT 24 Jul 15 04:26:53 PM PDT 24 177922277 ps
T1281 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2489821514 Jul 15 04:27:33 PM PDT 24 Jul 15 04:27:36 PM PDT 24 19506914 ps
T1282 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.348827039 Jul 15 04:27:09 PM PDT 24 Jul 15 04:27:11 PM PDT 24 35997677 ps
T1283 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3138192212 Jul 15 04:27:33 PM PDT 24 Jul 15 04:27:36 PM PDT 24 70884494 ps
T1284 /workspace/coverage/cover_reg_top/36.uart_intr_test.3052064135 Jul 15 04:28:04 PM PDT 24 Jul 15 04:28:08 PM PDT 24 120077125 ps
T1285 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3251148978 Jul 15 04:21:25 PM PDT 24 Jul 15 04:21:26 PM PDT 24 123055867 ps
T1286 /workspace/coverage/cover_reg_top/35.uart_intr_test.662863207 Jul 15 04:28:02 PM PDT 24 Jul 15 04:28:06 PM PDT 24 20965596 ps
T1287 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.136390113 Jul 15 04:27:02 PM PDT 24 Jul 15 04:27:04 PM PDT 24 78618395 ps
T1288 /workspace/coverage/cover_reg_top/16.uart_intr_test.1788787087 Jul 15 04:24:48 PM PDT 24 Jul 15 04:24:50 PM PDT 24 40171634 ps
T1289 /workspace/coverage/cover_reg_top/30.uart_intr_test.2217721800 Jul 15 04:28:02 PM PDT 24 Jul 15 04:28:07 PM PDT 24 50383532 ps
T1290 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1020674717 Jul 15 04:24:01 PM PDT 24 Jul 15 04:24:03 PM PDT 24 162809990 ps
T1291 /workspace/coverage/cover_reg_top/26.uart_intr_test.3507949327 Jul 15 04:28:00 PM PDT 24 Jul 15 04:28:05 PM PDT 24 74324118 ps
T1292 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1990773831 Jul 15 04:27:35 PM PDT 24 Jul 15 04:27:42 PM PDT 24 303646396 ps
T1293 /workspace/coverage/cover_reg_top/47.uart_intr_test.2893369284 Jul 15 04:29:29 PM PDT 24 Jul 15 04:29:32 PM PDT 24 12509549 ps
T1294 /workspace/coverage/cover_reg_top/8.uart_intr_test.1800219017 Jul 15 04:22:51 PM PDT 24 Jul 15 04:22:52 PM PDT 24 14135739 ps
T1295 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3105322040 Jul 15 04:25:11 PM PDT 24 Jul 15 04:25:12 PM PDT 24 65622372 ps
T1296 /workspace/coverage/cover_reg_top/37.uart_intr_test.2954451143 Jul 15 04:29:25 PM PDT 24 Jul 15 04:29:27 PM PDT 24 34034249 ps
T1297 /workspace/coverage/cover_reg_top/45.uart_intr_test.2110363666 Jul 15 04:28:01 PM PDT 24 Jul 15 04:28:05 PM PDT 24 39872469 ps
T1298 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1716324081 Jul 15 04:23:25 PM PDT 24 Jul 15 04:23:26 PM PDT 24 78945984 ps
T1299 /workspace/coverage/cover_reg_top/49.uart_intr_test.1768605430 Jul 15 04:28:12 PM PDT 24 Jul 15 04:28:14 PM PDT 24 25662550 ps
T1300 /workspace/coverage/cover_reg_top/31.uart_intr_test.759700761 Jul 15 04:28:07 PM PDT 24 Jul 15 04:28:11 PM PDT 24 40889402 ps
T1301 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1216669387 Jul 15 04:27:10 PM PDT 24 Jul 15 04:27:12 PM PDT 24 29456558 ps
T1302 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3907911071 Jul 15 04:22:26 PM PDT 24 Jul 15 04:22:27 PM PDT 24 49479199 ps
T1303 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3240726387 Jul 15 04:24:14 PM PDT 24 Jul 15 04:24:15 PM PDT 24 39419656 ps
T1304 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1340089355 Jul 15 04:29:42 PM PDT 24 Jul 15 04:29:44 PM PDT 24 313596039 ps
T1305 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2106558478 Jul 15 04:24:14 PM PDT 24 Jul 15 04:24:15 PM PDT 24 73776447 ps
T1306 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1262202545 Jul 15 04:28:06 PM PDT 24 Jul 15 04:28:10 PM PDT 24 80580528 ps
T1307 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4145446307 Jul 15 04:24:04 PM PDT 24 Jul 15 04:24:06 PM PDT 24 401973745 ps
T1308 /workspace/coverage/cover_reg_top/1.uart_csr_rw.467488487 Jul 15 04:23:14 PM PDT 24 Jul 15 04:23:15 PM PDT 24 21768218 ps
T1309 /workspace/coverage/cover_reg_top/29.uart_intr_test.447716235 Jul 15 04:28:01 PM PDT 24 Jul 15 04:28:06 PM PDT 24 61187358 ps
T1310 /workspace/coverage/cover_reg_top/20.uart_intr_test.2639575483 Jul 15 04:28:01 PM PDT 24 Jul 15 04:28:06 PM PDT 24 35448624 ps
T1311 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3073380054 Jul 15 04:27:02 PM PDT 24 Jul 15 04:27:04 PM PDT 24 18582034 ps
T1312 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2771284938 Jul 15 04:26:33 PM PDT 24 Jul 15 04:26:35 PM PDT 24 41213059 ps
T1313 /workspace/coverage/cover_reg_top/25.uart_intr_test.1609899280 Jul 15 04:28:16 PM PDT 24 Jul 15 04:28:17 PM PDT 24 106666584 ps
T1314 /workspace/coverage/cover_reg_top/2.uart_intr_test.3172368112 Jul 15 04:21:44 PM PDT 24 Jul 15 04:21:45 PM PDT 24 22460988 ps
T1315 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1209069528 Jul 15 04:26:51 PM PDT 24 Jul 15 04:26:53 PM PDT 24 39384964 ps
T1316 /workspace/coverage/cover_reg_top/2.uart_tl_errors.4263745836 Jul 15 04:26:26 PM PDT 24 Jul 15 04:26:28 PM PDT 24 504114734 ps
T1317 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4175030936 Jul 15 04:26:19 PM PDT 24 Jul 15 04:26:22 PM PDT 24 47338384 ps
T1318 /workspace/coverage/cover_reg_top/11.uart_intr_test.2508376036 Jul 15 04:26:39 PM PDT 24 Jul 15 04:26:40 PM PDT 24 13141367 ps
T1319 /workspace/coverage/cover_reg_top/21.uart_intr_test.2006183951 Jul 15 04:28:02 PM PDT 24 Jul 15 04:28:06 PM PDT 24 11728085 ps
T70 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3526730842 Jul 15 04:23:15 PM PDT 24 Jul 15 04:23:16 PM PDT 24 15508762 ps

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.995675873
Short name T8
Test name
Test status
Simulation time 160518666144 ps
CPU time 682.75 seconds
Started Jul 15 04:34:08 PM PDT 24
Finished Jul 15 04:45:33 PM PDT 24
Peak memory 216248 kb
Host smart-085b10ee-1654-4a2e-aa0e-4fc2ebed578d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995675873 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.995675873
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1180193375
Short name T48
Test name
Test status
Simulation time 316842484697 ps
CPU time 1115.84 seconds
Started Jul 15 04:31:44 PM PDT 24
Finished Jul 15 04:50:20 PM PDT 24
Peak memory 224700 kb
Host smart-088edf40-d519-4f7a-aadf-7b0f3346fb51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180193375 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1180193375
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all.3683517155
Short name T42
Test name
Test status
Simulation time 315554601504 ps
CPU time 378.84 seconds
Started Jul 15 04:31:08 PM PDT 24
Finished Jul 15 04:37:29 PM PDT 24
Peak memory 199744 kb
Host smart-585b3c01-761e-43d5-af11-6ee301cb56c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683517155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3683517155
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all.1976937709
Short name T164
Test name
Test status
Simulation time 408223449531 ps
CPU time 986.08 seconds
Started Jul 15 04:30:54 PM PDT 24
Finished Jul 15 04:47:22 PM PDT 24
Peak memory 199712 kb
Host smart-b8e5c802-7661-4f30-a571-115b89896f05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976937709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1976937709
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.4240041948
Short name T99
Test name
Test status
Simulation time 115030667590 ps
CPU time 451.34 seconds
Started Jul 15 04:33:52 PM PDT 24
Finished Jul 15 04:41:24 PM PDT 24
Peak memory 216440 kb
Host smart-bb420a0f-99c9-4436-8647-3e29589b46f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240041948 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.4240041948
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.455220034
Short name T18
Test name
Test status
Simulation time 382669647939 ps
CPU time 495.72 seconds
Started Jul 15 04:33:50 PM PDT 24
Finished Jul 15 04:42:06 PM PDT 24
Peak memory 224660 kb
Host smart-5ecc57c8-0995-4e78-be38-c31cd343bbd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455220034 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.455220034
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2568679751
Short name T22
Test name
Test status
Simulation time 49215001 ps
CPU time 0.75 seconds
Started Jul 15 04:26:51 PM PDT 24
Finished Jul 15 04:26:54 PM PDT 24
Peak memory 217308 kb
Host smart-a137b7ab-9b4f-4b74-aded-faff72730f4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568679751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2568679751
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3559076096
Short name T4
Test name
Test status
Simulation time 75448122608 ps
CPU time 151.95 seconds
Started Jul 15 04:34:46 PM PDT 24
Finished Jul 15 04:37:18 PM PDT 24
Peak memory 199848 kb
Host smart-d3b87603-0ab7-4aad-8f70-a8738e973a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559076096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3559076096
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3933625789
Short name T29
Test name
Test status
Simulation time 188456773022 ps
CPU time 448.03 seconds
Started Jul 15 04:31:55 PM PDT 24
Finished Jul 15 04:39:23 PM PDT 24
Peak memory 228224 kb
Host smart-7f51a627-7222-49c2-afd8-8db200a723d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933625789 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3933625789
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1052491976
Short name T103
Test name
Test status
Simulation time 1094724441717 ps
CPU time 673.76 seconds
Started Jul 15 04:33:58 PM PDT 24
Finished Jul 15 04:45:12 PM PDT 24
Peak memory 224916 kb
Host smart-cd37005d-1277-4241-aea5-7174eb9df975
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052491976 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1052491976
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all.1161092261
Short name T112
Test name
Test status
Simulation time 376543300161 ps
CPU time 261.07 seconds
Started Jul 15 04:33:14 PM PDT 24
Finished Jul 15 04:37:36 PM PDT 24
Peak memory 199664 kb
Host smart-2dd780ca-5b62-40f8-aced-528ec369d810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161092261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1161092261
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1618606156
Short name T296
Test name
Test status
Simulation time 100809368721 ps
CPU time 529.03 seconds
Started Jul 15 04:31:08 PM PDT 24
Finished Jul 15 04:39:59 PM PDT 24
Peak memory 199724 kb
Host smart-e0f9db3b-4dfb-442d-aa14-2a9eedd151a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1618606156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1618606156
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1528016030
Short name T27
Test name
Test status
Simulation time 207494261987 ps
CPU time 823.89 seconds
Started Jul 15 04:33:49 PM PDT 24
Finished Jul 15 04:47:34 PM PDT 24
Peak memory 215528 kb
Host smart-7c6443a9-f923-4722-8de5-64a5cfd84d28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528016030 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1528016030
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3213010040
Short name T41
Test name
Test status
Simulation time 238034671148 ps
CPU time 77.05 seconds
Started Jul 15 04:33:03 PM PDT 24
Finished Jul 15 04:34:22 PM PDT 24
Peak memory 199652 kb
Host smart-0e3a23e1-ebbb-4867-bb94-5957cea5ab76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213010040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3213010040
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3976786448
Short name T83
Test name
Test status
Simulation time 136732751 ps
CPU time 1.35 seconds
Started Jul 15 04:21:26 PM PDT 24
Finished Jul 15 04:21:29 PM PDT 24
Peak memory 199108 kb
Host smart-09210395-4003-42f1-8dcd-d477887e0cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976786448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3976786448
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/33.uart_stress_all.916657531
Short name T117
Test name
Test status
Simulation time 62436746633 ps
CPU time 53.82 seconds
Started Jul 15 04:32:39 PM PDT 24
Finished Jul 15 04:33:34 PM PDT 24
Peak memory 199688 kb
Host smart-60616ee8-6924-4c4b-b47d-e4bc89258613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916657531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.916657531
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all.965399433
Short name T143
Test name
Test status
Simulation time 705086957260 ps
CPU time 561.22 seconds
Started Jul 15 04:32:07 PM PDT 24
Finished Jul 15 04:41:30 PM PDT 24
Peak memory 199680 kb
Host smart-7d92480a-5397-4e0c-8422-8164d794093e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965399433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.965399433
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_alert_test.3724548263
Short name T20
Test name
Test status
Simulation time 15996362 ps
CPU time 0.55 seconds
Started Jul 15 04:25:38 PM PDT 24
Finished Jul 15 04:25:39 PM PDT 24
Peak memory 195056 kb
Host smart-ce5b4362-4dad-409c-b861-a0aeb4b0f77a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724548263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3724548263
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.775102770
Short name T66
Test name
Test status
Simulation time 12795808 ps
CPU time 0.6 seconds
Started Jul 15 04:23:10 PM PDT 24
Finished Jul 15 04:23:11 PM PDT 24
Peak memory 195988 kb
Host smart-5a0aa3a1-3433-42e8-a94d-23a1b329004e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775102770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.775102770
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/default/29.uart_stress_all.2618238959
Short name T153
Test name
Test status
Simulation time 213566216097 ps
CPU time 1439.35 seconds
Started Jul 15 04:32:18 PM PDT 24
Finished Jul 15 04:56:19 PM PDT 24
Peak memory 199664 kb
Host smart-8fb5abc0-4ce8-4378-ab0d-9756a4f7d1af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618238959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2618238959
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all.4108418511
Short name T44
Test name
Test status
Simulation time 59230133606 ps
CPU time 66.23 seconds
Started Jul 15 04:33:23 PM PDT 24
Finished Jul 15 04:34:31 PM PDT 24
Peak memory 199752 kb
Host smart-9d27f936-99b6-4dda-bd5e-46ce6873d015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108418511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.4108418511
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3255423807
Short name T107
Test name
Test status
Simulation time 82588135482 ps
CPU time 31.17 seconds
Started Jul 15 04:33:42 PM PDT 24
Finished Jul 15 04:34:14 PM PDT 24
Peak memory 199672 kb
Host smart-5fcef3e0-5ad5-4fe1-8460-8419fd04f7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255423807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3255423807
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2830179291
Short name T230
Test name
Test status
Simulation time 108690472383 ps
CPU time 102.56 seconds
Started Jul 15 04:30:38 PM PDT 24
Finished Jul 15 04:32:22 PM PDT 24
Peak memory 199756 kb
Host smart-aac0c73a-df00-4433-9dd1-3ca551d36ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830179291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2830179291
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2297431034
Short name T151
Test name
Test status
Simulation time 85072110898 ps
CPU time 70.32 seconds
Started Jul 15 04:34:32 PM PDT 24
Finished Jul 15 04:35:45 PM PDT 24
Peak memory 199768 kb
Host smart-f0806db9-f6e8-48c8-b851-cccba7d076aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297431034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2297431034
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2053082367
Short name T94
Test name
Test status
Simulation time 346501200356 ps
CPU time 49.39 seconds
Started Jul 15 04:34:56 PM PDT 24
Finished Jul 15 04:35:47 PM PDT 24
Peak memory 199776 kb
Host smart-2a4ce226-feab-4ddd-9d88-5a65a79b5341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053082367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2053082367
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3149419919
Short name T181
Test name
Test status
Simulation time 254881878141 ps
CPU time 148.36 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:33:45 PM PDT 24
Peak memory 199692 kb
Host smart-631f2c16-5b30-468d-b421-f733d3528b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149419919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3149419919
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1984696927
Short name T136
Test name
Test status
Simulation time 25560597907 ps
CPU time 28.89 seconds
Started Jul 15 04:34:24 PM PDT 24
Finished Jul 15 04:34:55 PM PDT 24
Peak memory 199760 kb
Host smart-eeaa64d8-5396-4d95-9150-e1ce6b4d165d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984696927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1984696927
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.4248232723
Short name T243
Test name
Test status
Simulation time 120309993369 ps
CPU time 229.28 seconds
Started Jul 15 04:34:39 PM PDT 24
Finished Jul 15 04:38:29 PM PDT 24
Peak memory 199696 kb
Host smart-903e5616-1ed6-48d4-9ef8-fe9a81c22ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248232723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.4248232723
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2839575650
Short name T35
Test name
Test status
Simulation time 63738593700 ps
CPU time 78.74 seconds
Started Jul 15 04:35:10 PM PDT 24
Finished Jul 15 04:36:30 PM PDT 24
Peak memory 199788 kb
Host smart-d6aac0e2-8027-4bab-b8da-872e2dcb30a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839575650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2839575650
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.616347296
Short name T192
Test name
Test status
Simulation time 373930690938 ps
CPU time 1190.37 seconds
Started Jul 15 04:30:37 PM PDT 24
Finished Jul 15 04:50:29 PM PDT 24
Peak memory 226284 kb
Host smart-b74e96f7-9bf5-47ad-aa19-dc404a498fef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616347296 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.616347296
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1074195178
Short name T178
Test name
Test status
Simulation time 72579494385 ps
CPU time 55.39 seconds
Started Jul 15 04:33:53 PM PDT 24
Finished Jul 15 04:34:50 PM PDT 24
Peak memory 199752 kb
Host smart-b766e221-2643-477d-b3d5-3d925a428ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074195178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1074195178
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1697285012
Short name T86
Test name
Test status
Simulation time 95134034 ps
CPU time 1.26 seconds
Started Jul 15 04:24:50 PM PDT 24
Finished Jul 15 04:24:52 PM PDT 24
Peak memory 200136 kb
Host smart-5659c4f1-c9fd-4072-9576-9dfe7aaf8fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697285012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1697285012
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.782592818
Short name T186
Test name
Test status
Simulation time 26840235758 ps
CPU time 32.03 seconds
Started Jul 15 04:31:08 PM PDT 24
Finished Jul 15 04:31:42 PM PDT 24
Peak memory 199680 kb
Host smart-9dbfe69f-1194-4ddb-8479-50c347006f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782592818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.782592818
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3176158779
Short name T100
Test name
Test status
Simulation time 211703279542 ps
CPU time 228.22 seconds
Started Jul 15 04:32:41 PM PDT 24
Finished Jul 15 04:36:30 PM PDT 24
Peak memory 216264 kb
Host smart-a6a5ced6-8d38-45d4-843a-96aa3bdada4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176158779 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3176158779
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3422794936
Short name T216
Test name
Test status
Simulation time 98462406207 ps
CPU time 150.09 seconds
Started Jul 15 04:34:13 PM PDT 24
Finished Jul 15 04:36:45 PM PDT 24
Peak memory 199800 kb
Host smart-c691f749-7de4-421a-b485-bfb843342b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422794936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3422794936
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3298722207
Short name T264
Test name
Test status
Simulation time 309585163848 ps
CPU time 201.94 seconds
Started Jul 15 04:31:34 PM PDT 24
Finished Jul 15 04:34:57 PM PDT 24
Peak memory 199796 kb
Host smart-af718362-8c9a-496f-9c27-29bb7bff1975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298722207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3298722207
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2190213933
Short name T294
Test name
Test status
Simulation time 48657006435 ps
CPU time 48.17 seconds
Started Jul 15 04:34:39 PM PDT 24
Finished Jul 15 04:35:27 PM PDT 24
Peak memory 199716 kb
Host smart-9be6dc46-9a5d-462c-96df-bb23bffdb81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190213933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2190213933
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2709270621
Short name T137
Test name
Test status
Simulation time 216118209174 ps
CPU time 30.45 seconds
Started Jul 15 04:34:20 PM PDT 24
Finished Jul 15 04:34:51 PM PDT 24
Peak memory 199716 kb
Host smart-01ad34de-15dd-4d78-90fb-a47716e5fe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709270621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2709270621
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.421200993
Short name T746
Test name
Test status
Simulation time 498020510323 ps
CPU time 1498.36 seconds
Started Jul 15 04:31:14 PM PDT 24
Finished Jul 15 04:56:14 PM PDT 24
Peak memory 227460 kb
Host smart-e68be804-694b-4bb0-8dc0-3f4e886a0395
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421200993 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.421200993
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3090443765
Short name T197
Test name
Test status
Simulation time 130426556514 ps
CPU time 190.93 seconds
Started Jul 15 04:34:24 PM PDT 24
Finished Jul 15 04:37:36 PM PDT 24
Peak memory 199700 kb
Host smart-41e9e555-d338-4bcf-a32b-64b70fc374e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090443765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3090443765
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_noise_filter.4127072224
Short name T263
Test name
Test status
Simulation time 77721349086 ps
CPU time 285.22 seconds
Started Jul 15 04:30:25 PM PDT 24
Finished Jul 15 04:35:12 PM PDT 24
Peak memory 199936 kb
Host smart-b9254e76-86c5-4c33-866e-0290f41a2a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127072224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.4127072224
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3898820792
Short name T139
Test name
Test status
Simulation time 23697583354 ps
CPU time 41.08 seconds
Started Jul 15 04:33:51 PM PDT 24
Finished Jul 15 04:34:33 PM PDT 24
Peak memory 199736 kb
Host smart-a7f4ceee-c262-4f73-a595-8742d66fc010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898820792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3898820792
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3482025013
Short name T165
Test name
Test status
Simulation time 193293771855 ps
CPU time 41.1 seconds
Started Jul 15 04:34:05 PM PDT 24
Finished Jul 15 04:34:48 PM PDT 24
Peak memory 199512 kb
Host smart-45453b83-e829-45f7-97d2-e39f48ce0da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482025013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3482025013
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3551589615
Short name T33
Test name
Test status
Simulation time 140406440577 ps
CPU time 94.54 seconds
Started Jul 15 04:34:23 PM PDT 24
Finished Jul 15 04:35:59 PM PDT 24
Peak memory 199660 kb
Host smart-1dcece8c-64d2-45d3-86f7-230c6e0d077d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551589615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3551589615
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1818526990
Short name T265
Test name
Test status
Simulation time 31868326520 ps
CPU time 51.93 seconds
Started Jul 15 04:31:13 PM PDT 24
Finished Jul 15 04:32:06 PM PDT 24
Peak memory 199760 kb
Host smart-b46faf2b-47b9-43a4-ac63-d0a79f7925f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818526990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1818526990
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.232426539
Short name T218
Test name
Test status
Simulation time 38969852717 ps
CPU time 19.06 seconds
Started Jul 15 04:34:23 PM PDT 24
Finished Jul 15 04:34:43 PM PDT 24
Peak memory 199516 kb
Host smart-21c2b4de-6cf3-44df-b546-bbac6269d00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232426539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.232426539
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2136021103
Short name T291
Test name
Test status
Simulation time 48094594994 ps
CPU time 1031.44 seconds
Started Jul 15 04:30:31 PM PDT 24
Finished Jul 15 04:47:44 PM PDT 24
Peak memory 216512 kb
Host smart-6c8b8004-5453-420c-9aff-7a2f0a896c78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136021103 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2136021103
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1685323873
Short name T125
Test name
Test status
Simulation time 25292408849 ps
CPU time 39.74 seconds
Started Jul 15 04:34:57 PM PDT 24
Finished Jul 15 04:35:37 PM PDT 24
Peak memory 199740 kb
Host smart-8f3b2eea-e6f3-49a0-9e06-6a32876ecc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685323873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1685323873
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2918469129
Short name T252
Test name
Test status
Simulation time 123124891598 ps
CPU time 179.44 seconds
Started Jul 15 04:32:10 PM PDT 24
Finished Jul 15 04:35:11 PM PDT 24
Peak memory 199708 kb
Host smart-e43057be-664b-49dd-a7c2-4d82aca572b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918469129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2918469129
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.6642342
Short name T168
Test name
Test status
Simulation time 32224756388 ps
CPU time 54.24 seconds
Started Jul 15 04:35:12 PM PDT 24
Finished Jul 15 04:36:07 PM PDT 24
Peak memory 199784 kb
Host smart-3df623fe-1e4b-4dc7-a69f-667ff96c501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6642342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.6642342
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3044537159
Short name T126
Test name
Test status
Simulation time 66210711268 ps
CPU time 20.82 seconds
Started Jul 15 04:35:18 PM PDT 24
Finished Jul 15 04:35:39 PM PDT 24
Peak memory 199660 kb
Host smart-d3cb4b82-2adc-41d1-8424-b4019a94cf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044537159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3044537159
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1767749193
Short name T286
Test name
Test status
Simulation time 95310354842 ps
CPU time 200.12 seconds
Started Jul 15 04:30:33 PM PDT 24
Finished Jul 15 04:33:54 PM PDT 24
Peak memory 199828 kb
Host smart-38acdd1d-c195-4530-96fa-11c53706481b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767749193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1767749193
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.451300373
Short name T225
Test name
Test status
Simulation time 129161525587 ps
CPU time 25.06 seconds
Started Jul 15 04:30:51 PM PDT 24
Finished Jul 15 04:31:17 PM PDT 24
Peak memory 199604 kb
Host smart-5ebaec76-321e-4164-ac24-cf6db759d01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451300373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.451300373
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.871295666
Short name T630
Test name
Test status
Simulation time 12923275742 ps
CPU time 21.67 seconds
Started Jul 15 04:30:51 PM PDT 24
Finished Jul 15 04:31:14 PM PDT 24
Peak memory 199772 kb
Host smart-f8d8145a-37d4-4c3f-a192-289ba976016e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871295666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.871295666
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.4012967358
Short name T204
Test name
Test status
Simulation time 54696656768 ps
CPU time 25.78 seconds
Started Jul 15 04:31:00 PM PDT 24
Finished Jul 15 04:31:26 PM PDT 24
Peak memory 199740 kb
Host smart-8b1a0179-2e59-4d2e-aae1-49729642c4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012967358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.4012967358
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2025958643
Short name T1137
Test name
Test status
Simulation time 84101790053 ps
CPU time 68.01 seconds
Started Jul 15 04:34:25 PM PDT 24
Finished Jul 15 04:35:35 PM PDT 24
Peak memory 199752 kb
Host smart-fc6c1654-c381-4f76-b5a1-1fb921bafee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025958643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2025958643
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2662733136
Short name T200
Test name
Test status
Simulation time 50388428974 ps
CPU time 23.23 seconds
Started Jul 15 04:34:34 PM PDT 24
Finished Jul 15 04:34:58 PM PDT 24
Peak memory 199712 kb
Host smart-dcfb3563-15eb-4136-88ee-d2212378c824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662733136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2662733136
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.358485841
Short name T202
Test name
Test status
Simulation time 135962712885 ps
CPU time 99.75 seconds
Started Jul 15 04:34:46 PM PDT 24
Finished Jul 15 04:36:26 PM PDT 24
Peak memory 199764 kb
Host smart-ca5aad90-16d4-484f-9336-3e1db17d2fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358485841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.358485841
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.860697451
Short name T154
Test name
Test status
Simulation time 35701800458 ps
CPU time 58.68 seconds
Started Jul 15 04:35:08 PM PDT 24
Finished Jul 15 04:36:07 PM PDT 24
Peak memory 199800 kb
Host smart-8f76abab-54e6-490b-b469-b2ace5c30b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860697451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.860697451
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3997476375
Short name T208
Test name
Test status
Simulation time 93753741978 ps
CPU time 221.95 seconds
Started Jul 15 04:32:20 PM PDT 24
Finished Jul 15 04:36:03 PM PDT 24
Peak memory 199752 kb
Host smart-d283be30-e80b-46c5-b77a-db38e0e55186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997476375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3997476375
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3840146480
Short name T190
Test name
Test status
Simulation time 57922646145 ps
CPU time 76.5 seconds
Started Jul 15 04:33:52 PM PDT 24
Finished Jul 15 04:35:10 PM PDT 24
Peak memory 199680 kb
Host smart-428d9388-8aef-4816-9384-87a175b447b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840146480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3840146480
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.4130908072
Short name T221
Test name
Test status
Simulation time 177131847139 ps
CPU time 256.04 seconds
Started Jul 15 04:33:51 PM PDT 24
Finished Jul 15 04:38:07 PM PDT 24
Peak memory 199792 kb
Host smart-3307f227-9f2f-4d39-8581-eed207e90646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130908072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4130908072
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2275131547
Short name T220
Test name
Test status
Simulation time 15514362297 ps
CPU time 22.01 seconds
Started Jul 15 04:33:59 PM PDT 24
Finished Jul 15 04:34:22 PM PDT 24
Peak memory 199604 kb
Host smart-82b9aa58-894c-4456-a95e-6e6e3312b05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275131547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2275131547
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1675409266
Short name T223
Test name
Test status
Simulation time 196224804379 ps
CPU time 279.35 seconds
Started Jul 15 04:30:44 PM PDT 24
Finished Jul 15 04:35:25 PM PDT 24
Peak memory 199824 kb
Host smart-c8cb6d83-d5f7-44ac-8668-e8deaaec468a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675409266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1675409266
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1336583602
Short name T1190
Test name
Test status
Simulation time 27034641 ps
CPU time 0.93 seconds
Started Jul 15 04:21:29 PM PDT 24
Finished Jul 15 04:21:30 PM PDT 24
Peak memory 195988 kb
Host smart-2afb812c-84df-4de6-b139-7d1794488b07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336583602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1336583602
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.640094420
Short name T67
Test name
Test status
Simulation time 34604879 ps
CPU time 1.49 seconds
Started Jul 15 04:21:37 PM PDT 24
Finished Jul 15 04:21:39 PM PDT 24
Peak memory 197224 kb
Host smart-a9317daa-ad0e-4008-b23b-efb766fbcd1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640094420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.640094420
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.856306082
Short name T1195
Test name
Test status
Simulation time 38003813 ps
CPU time 0.59 seconds
Started Jul 15 04:21:30 PM PDT 24
Finished Jul 15 04:21:31 PM PDT 24
Peak memory 195972 kb
Host smart-36c6cba9-a68c-4004-9bcb-bbad7dd5bcb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856306082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.856306082
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.136005449
Short name T1264
Test name
Test status
Simulation time 31472129 ps
CPU time 0.95 seconds
Started Jul 15 04:21:31 PM PDT 24
Finished Jul 15 04:21:33 PM PDT 24
Peak memory 198104 kb
Host smart-bfd8cb91-00ae-4fdf-8413-69490a10a884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136005449 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.136005449
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1348594437
Short name T71
Test name
Test status
Simulation time 12778425 ps
CPU time 0.62 seconds
Started Jul 15 04:21:37 PM PDT 24
Finished Jul 15 04:21:38 PM PDT 24
Peak memory 194056 kb
Host smart-e5bd3475-0ad6-427e-bab6-1dc8fe67a7a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348594437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1348594437
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1687399210
Short name T1189
Test name
Test status
Simulation time 12679619 ps
CPU time 0.56 seconds
Started Jul 15 04:21:30 PM PDT 24
Finished Jul 15 04:21:31 PM PDT 24
Peak memory 195040 kb
Host smart-7af9eaef-68ad-4118-934e-3ac7bc94006c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687399210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1687399210
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3250725458
Short name T77
Test name
Test status
Simulation time 32261144 ps
CPU time 0.82 seconds
Started Jul 15 04:21:31 PM PDT 24
Finished Jul 15 04:21:33 PM PDT 24
Peak memory 196680 kb
Host smart-b2452b12-4359-4a29-bd4f-2e78f7a266e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250725458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3250725458
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3251148978
Short name T1285
Test name
Test status
Simulation time 123055867 ps
CPU time 1.49 seconds
Started Jul 15 04:21:25 PM PDT 24
Finished Jul 15 04:21:26 PM PDT 24
Peak memory 200948 kb
Host smart-0a4f66b7-6d47-4368-a7f1-23a7cbc8221c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251148978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3251148978
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2489821514
Short name T1281
Test name
Test status
Simulation time 19506914 ps
CPU time 0.7 seconds
Started Jul 15 04:27:33 PM PDT 24
Finished Jul 15 04:27:36 PM PDT 24
Peak memory 194720 kb
Host smart-ebd8a927-f5fa-4156-8414-950ebbf8a8e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489821514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2489821514
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2783264878
Short name T1277
Test name
Test status
Simulation time 58355676 ps
CPU time 2.21 seconds
Started Jul 15 04:21:39 PM PDT 24
Finished Jul 15 04:21:42 PM PDT 24
Peak memory 198200 kb
Host smart-b0cee653-3f8f-4209-9c1e-693038a206d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783264878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2783264878
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3426866669
Short name T1184
Test name
Test status
Simulation time 47179196 ps
CPU time 0.57 seconds
Started Jul 15 04:25:13 PM PDT 24
Finished Jul 15 04:25:14 PM PDT 24
Peak memory 196116 kb
Host smart-75506cda-ee71-42f2-9e0f-0321230de2d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426866669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3426866669
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1981419840
Short name T1236
Test name
Test status
Simulation time 58970493 ps
CPU time 0.69 seconds
Started Jul 15 04:21:39 PM PDT 24
Finished Jul 15 04:21:40 PM PDT 24
Peak memory 198468 kb
Host smart-03818cb3-1c66-4e41-a9e2-5dc567c5280a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981419840 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1981419840
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.467488487
Short name T1308
Test name
Test status
Simulation time 21768218 ps
CPU time 0.59 seconds
Started Jul 15 04:23:14 PM PDT 24
Finished Jul 15 04:23:15 PM PDT 24
Peak memory 195988 kb
Host smart-b8050305-742e-4acb-bc2f-c35e97e98e0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467488487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.467488487
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2534654093
Short name T1254
Test name
Test status
Simulation time 15474779 ps
CPU time 0.58 seconds
Started Jul 15 04:21:34 PM PDT 24
Finished Jul 15 04:21:35 PM PDT 24
Peak memory 195296 kb
Host smart-2adaeb5f-b22d-4d71-bc10-d9e53c7c5529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534654093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2534654093
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1337022989
Short name T73
Test name
Test status
Simulation time 21074497 ps
CPU time 0.67 seconds
Started Jul 15 04:27:02 PM PDT 24
Finished Jul 15 04:27:04 PM PDT 24
Peak memory 196100 kb
Host smart-076f436a-82fb-40cb-91f4-a45c7bede94a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337022989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1337022989
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1703930480
Short name T1192
Test name
Test status
Simulation time 885649500 ps
CPU time 1.25 seconds
Started Jul 15 04:21:37 PM PDT 24
Finished Jul 15 04:21:39 PM PDT 24
Peak memory 198604 kb
Host smart-b00645b0-c45a-47d6-9c0e-5ce064de4130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703930480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1703930480
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4175030936
Short name T1317
Test name
Test status
Simulation time 47338384 ps
CPU time 0.97 seconds
Started Jul 15 04:26:19 PM PDT 24
Finished Jul 15 04:26:22 PM PDT 24
Peak memory 198100 kb
Host smart-15f6bc70-c2dd-4250-8eeb-b610d25c88fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175030936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.4175030936
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2182141680
Short name T1194
Test name
Test status
Simulation time 36792521 ps
CPU time 0.74 seconds
Started Jul 15 04:26:20 PM PDT 24
Finished Jul 15 04:26:24 PM PDT 24
Peak memory 197104 kb
Host smart-46de41c0-ad7a-4f32-b031-95547668fb8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182141680 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2182141680
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.4115290589
Short name T65
Test name
Test status
Simulation time 11350546 ps
CPU time 0.63 seconds
Started Jul 15 04:26:20 PM PDT 24
Finished Jul 15 04:26:24 PM PDT 24
Peak memory 194320 kb
Host smart-1f0f9949-51ad-47af-94e5-afc78f47ad97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115290589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.4115290589
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.798552260
Short name T1212
Test name
Test status
Simulation time 12807401 ps
CPU time 0.56 seconds
Started Jul 15 04:27:09 PM PDT 24
Finished Jul 15 04:27:10 PM PDT 24
Peak memory 194852 kb
Host smart-eb46defa-9dc5-4872-aa6b-9dca0b053a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798552260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.798552260
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.348827039
Short name T1282
Test name
Test status
Simulation time 35997677 ps
CPU time 0.65 seconds
Started Jul 15 04:27:09 PM PDT 24
Finished Jul 15 04:27:11 PM PDT 24
Peak memory 196256 kb
Host smart-690304f9-a029-4d1f-ab1c-c4e3ca88b55f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348827039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.348827039
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2143893553
Short name T1203
Test name
Test status
Simulation time 125712822 ps
CPU time 1.39 seconds
Started Jul 15 04:23:22 PM PDT 24
Finished Jul 15 04:23:24 PM PDT 24
Peak memory 200624 kb
Host smart-1f40990b-a522-4cc7-862e-efad54dde9a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143893553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2143893553
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1020674717
Short name T1290
Test name
Test status
Simulation time 162809990 ps
CPU time 0.94 seconds
Started Jul 15 04:24:01 PM PDT 24
Finished Jul 15 04:24:03 PM PDT 24
Peak memory 199484 kb
Host smart-71da8aef-10ba-4d32-b3a4-e7ca9baf6289
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020674717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1020674717
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.977449508
Short name T1182
Test name
Test status
Simulation time 90460305 ps
CPU time 1.15 seconds
Started Jul 15 04:27:19 PM PDT 24
Finished Jul 15 04:27:22 PM PDT 24
Peak memory 200540 kb
Host smart-f848766e-960b-4e42-ac97-ff69380eb062
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977449508 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.977449508
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2869599088
Short name T68
Test name
Test status
Simulation time 14349426 ps
CPU time 0.65 seconds
Started Jul 15 04:23:09 PM PDT 24
Finished Jul 15 04:23:10 PM PDT 24
Peak memory 196244 kb
Host smart-72def0d2-1769-434c-a61a-259f323e934e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869599088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2869599088
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2508376036
Short name T1318
Test name
Test status
Simulation time 13141367 ps
CPU time 0.57 seconds
Started Jul 15 04:26:39 PM PDT 24
Finished Jul 15 04:26:40 PM PDT 24
Peak memory 194956 kb
Host smart-71f0b756-b776-4f13-ac4e-5ca462d2a658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508376036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2508376036
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.760961395
Short name T1224
Test name
Test status
Simulation time 58741151 ps
CPU time 0.77 seconds
Started Jul 15 04:23:30 PM PDT 24
Finished Jul 15 04:23:31 PM PDT 24
Peak memory 198268 kb
Host smart-af13405a-1288-483f-8f00-69720d876e13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760961395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.760961395
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3726127469
Short name T1233
Test name
Test status
Simulation time 289580721 ps
CPU time 1.74 seconds
Started Jul 15 04:24:05 PM PDT 24
Finished Jul 15 04:24:07 PM PDT 24
Peak memory 200596 kb
Host smart-c40e2b11-880c-4bdf-a1d4-217b3ebd80f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726127469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3726127469
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4056397269
Short name T1241
Test name
Test status
Simulation time 928740555 ps
CPU time 1.32 seconds
Started Jul 15 04:27:09 PM PDT 24
Finished Jul 15 04:27:11 PM PDT 24
Peak memory 199796 kb
Host smart-34efa28b-3a45-4e14-ac25-1c7a48c5476b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056397269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.4056397269
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.49899585
Short name T1209
Test name
Test status
Simulation time 47931986 ps
CPU time 0.71 seconds
Started Jul 15 04:22:15 PM PDT 24
Finished Jul 15 04:22:16 PM PDT 24
Peak memory 198028 kb
Host smart-326ba9ad-776d-4656-8d82-f92b193b3158
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49899585 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.49899585
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2041437508
Short name T1261
Test name
Test status
Simulation time 15580341 ps
CPU time 0.68 seconds
Started Jul 15 04:26:23 PM PDT 24
Finished Jul 15 04:26:26 PM PDT 24
Peak memory 194232 kb
Host smart-2ed2b101-60c0-47e2-bd22-4d764016b046
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041437508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2041437508
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2880825580
Short name T1193
Test name
Test status
Simulation time 14294997 ps
CPU time 0.55 seconds
Started Jul 15 04:26:24 PM PDT 24
Finished Jul 15 04:26:26 PM PDT 24
Peak memory 194552 kb
Host smart-fa2a85d2-9883-46db-8e26-63f77c0c119d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880825580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2880825580
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1177028615
Short name T72
Test name
Test status
Simulation time 26928753 ps
CPU time 0.73 seconds
Started Jul 15 04:26:23 PM PDT 24
Finished Jul 15 04:26:26 PM PDT 24
Peak memory 194936 kb
Host smart-f4d34d86-9da4-4891-bf1e-9888d7e13de9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177028615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1177028615
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2209459403
Short name T1180
Test name
Test status
Simulation time 329069904 ps
CPU time 1.66 seconds
Started Jul 15 04:27:11 PM PDT 24
Finished Jul 15 04:27:13 PM PDT 24
Peak memory 200612 kb
Host smart-83b57d81-810c-494d-ba06-c22ccadbbb33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209459403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2209459403
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2533565317
Short name T87
Test name
Test status
Simulation time 646826643 ps
CPU time 0.93 seconds
Started Jul 15 04:26:20 PM PDT 24
Finished Jul 15 04:26:22 PM PDT 24
Peak memory 199316 kb
Host smart-a78139f4-7f43-4265-977b-2914238f7670
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533565317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2533565317
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1084787301
Short name T1270
Test name
Test status
Simulation time 24371051 ps
CPU time 0.71 seconds
Started Jul 15 04:27:50 PM PDT 24
Finished Jul 15 04:27:54 PM PDT 24
Peak memory 198864 kb
Host smart-9fd81dfb-1a89-4662-ae28-b0b5e246f189
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084787301 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1084787301
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.349334663
Short name T1242
Test name
Test status
Simulation time 23328382 ps
CPU time 0.56 seconds
Started Jul 15 04:26:20 PM PDT 24
Finished Jul 15 04:26:22 PM PDT 24
Peak memory 195688 kb
Host smart-052efc3e-d0ac-411a-bd97-31fbfb59cb47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349334663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.349334663
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2555024023
Short name T1219
Test name
Test status
Simulation time 16397618 ps
CPU time 0.57 seconds
Started Jul 15 04:26:35 PM PDT 24
Finished Jul 15 04:26:36 PM PDT 24
Peak memory 194972 kb
Host smart-b5ca862d-d1b1-4164-a0c9-c400318d65f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555024023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2555024023
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.483900719
Short name T1243
Test name
Test status
Simulation time 35150064 ps
CPU time 0.67 seconds
Started Jul 15 04:26:35 PM PDT 24
Finished Jul 15 04:26:37 PM PDT 24
Peak memory 196400 kb
Host smart-008b3ace-f2ad-4ba7-91e9-f384c4e80943
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483900719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.483900719
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3458313493
Short name T1259
Test name
Test status
Simulation time 220348499 ps
CPU time 2.54 seconds
Started Jul 15 04:26:19 PM PDT 24
Finished Jul 15 04:26:23 PM PDT 24
Peak memory 198736 kb
Host smart-9b13433d-0ca4-4c56-812d-9b219d92e444
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458313493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3458313493
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3190592988
Short name T1262
Test name
Test status
Simulation time 97383074 ps
CPU time 1.3 seconds
Started Jul 15 04:26:38 PM PDT 24
Finished Jul 15 04:26:40 PM PDT 24
Peak memory 199896 kb
Host smart-3ac514c0-32a4-43dd-8f1e-cf07034ec16e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190592988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3190592988
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2393717664
Short name T1198
Test name
Test status
Simulation time 120443050 ps
CPU time 0.7 seconds
Started Jul 15 04:23:10 PM PDT 24
Finished Jul 15 04:23:11 PM PDT 24
Peak memory 198540 kb
Host smart-0a7924fe-f3f6-4d96-b587-de8439ae9e78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393717664 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2393717664
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1209069528
Short name T1315
Test name
Test status
Simulation time 39384964 ps
CPU time 0.55 seconds
Started Jul 15 04:26:51 PM PDT 24
Finished Jul 15 04:26:53 PM PDT 24
Peak memory 195632 kb
Host smart-dd2b3e31-54ae-442c-8665-045131081cf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209069528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1209069528
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.645889485
Short name T1267
Test name
Test status
Simulation time 39506782 ps
CPU time 0.57 seconds
Started Jul 15 04:26:48 PM PDT 24
Finished Jul 15 04:26:50 PM PDT 24
Peak memory 194692 kb
Host smart-5d9f5328-f261-4b18-92c1-7211687d1385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645889485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.645889485
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2507174110
Short name T76
Test name
Test status
Simulation time 18087921 ps
CPU time 0.74 seconds
Started Jul 15 04:24:14 PM PDT 24
Finished Jul 15 04:24:16 PM PDT 24
Peak memory 197744 kb
Host smart-e6834e33-34c8-4ee4-998c-5e9fb08f8973
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507174110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2507174110
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.638807843
Short name T1218
Test name
Test status
Simulation time 452151692 ps
CPU time 2.23 seconds
Started Jul 15 04:25:17 PM PDT 24
Finished Jul 15 04:25:20 PM PDT 24
Peak memory 200632 kb
Host smart-a064f2aa-1f82-46bc-a1a3-6a4bdb3de17d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638807843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.638807843
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3907911071
Short name T1302
Test name
Test status
Simulation time 49479199 ps
CPU time 1 seconds
Started Jul 15 04:22:26 PM PDT 24
Finished Jul 15 04:22:27 PM PDT 24
Peak memory 199412 kb
Host smart-d4e272b2-7d60-4dc6-9dcb-ecc1aec3ca1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907911071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3907911071
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1821750649
Short name T1226
Test name
Test status
Simulation time 97431572 ps
CPU time 0.78 seconds
Started Jul 15 04:25:31 PM PDT 24
Finished Jul 15 04:25:32 PM PDT 24
Peak memory 199396 kb
Host smart-f605c0f6-9fcd-4257-9d1b-96d45d051bc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821750649 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1821750649
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1118990801
Short name T1246
Test name
Test status
Simulation time 16815727 ps
CPU time 0.62 seconds
Started Jul 15 04:22:29 PM PDT 24
Finished Jul 15 04:22:30 PM PDT 24
Peak memory 195984 kb
Host smart-eb85cdb2-a565-454b-a593-658bf3d7e260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118990801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1118990801
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3560669344
Short name T1256
Test name
Test status
Simulation time 15474918 ps
CPU time 0.56 seconds
Started Jul 15 04:26:50 PM PDT 24
Finished Jul 15 04:26:53 PM PDT 24
Peak memory 193396 kb
Host smart-e097e04b-dc10-49b3-aba0-1fa89f78c153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560669344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3560669344
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2771284938
Short name T1312
Test name
Test status
Simulation time 41213059 ps
CPU time 0.67 seconds
Started Jul 15 04:26:33 PM PDT 24
Finished Jul 15 04:26:35 PM PDT 24
Peak memory 194688 kb
Host smart-8244aa24-5e3f-4e27-b167-2fee91bacd2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771284938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2771284938
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.4180732273
Short name T1213
Test name
Test status
Simulation time 276197161 ps
CPU time 1.5 seconds
Started Jul 15 04:25:35 PM PDT 24
Finished Jul 15 04:25:38 PM PDT 24
Peak memory 200648 kb
Host smart-a1f8dca0-7f4a-409e-a5ac-935759bb576c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180732273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.4180732273
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1660327703
Short name T1271
Test name
Test status
Simulation time 69720536 ps
CPU time 0.82 seconds
Started Jul 15 04:26:33 PM PDT 24
Finished Jul 15 04:26:35 PM PDT 24
Peak memory 197292 kb
Host smart-b365be93-4d74-4957-8a79-3f200c39cb84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660327703 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1660327703
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3073380054
Short name T1311
Test name
Test status
Simulation time 18582034 ps
CPU time 0.59 seconds
Started Jul 15 04:27:02 PM PDT 24
Finished Jul 15 04:27:04 PM PDT 24
Peak memory 196060 kb
Host smart-4109e407-eb51-40a5-a774-bbcf36e7ea2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073380054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3073380054
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1788787087
Short name T1288
Test name
Test status
Simulation time 40171634 ps
CPU time 0.6 seconds
Started Jul 15 04:24:48 PM PDT 24
Finished Jul 15 04:24:50 PM PDT 24
Peak memory 194900 kb
Host smart-8b3fb9e6-954e-4f07-9eca-9f8fc2b12045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788787087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1788787087
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2690380689
Short name T75
Test name
Test status
Simulation time 57673576 ps
CPU time 0.74 seconds
Started Jul 15 04:26:50 PM PDT 24
Finished Jul 15 04:26:53 PM PDT 24
Peak memory 195768 kb
Host smart-ffc393a9-ca69-4183-ac66-11301492dd27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690380689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2690380689
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2469070125
Short name T1201
Test name
Test status
Simulation time 164353978 ps
CPU time 2.25 seconds
Started Jul 15 04:25:09 PM PDT 24
Finished Jul 15 04:25:12 PM PDT 24
Peak memory 200628 kb
Host smart-5bcc474d-b1cb-48aa-aa0e-3b76de98c336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469070125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2469070125
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1261717573
Short name T1276
Test name
Test status
Simulation time 327517159 ps
CPU time 1.4 seconds
Started Jul 15 04:23:39 PM PDT 24
Finished Jul 15 04:23:41 PM PDT 24
Peak memory 200096 kb
Host smart-869008cf-6bfb-4542-9e97-14730686cccb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261717573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1261717573
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1336106462
Short name T1200
Test name
Test status
Simulation time 265842773 ps
CPU time 0.88 seconds
Started Jul 15 04:26:35 PM PDT 24
Finished Jul 15 04:26:37 PM PDT 24
Peak memory 200320 kb
Host smart-884dcac3-3e5f-4cd9-95fe-15a00d48a37d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336106462 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1336106462
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.179922218
Short name T1258
Test name
Test status
Simulation time 105455708 ps
CPU time 0.62 seconds
Started Jul 15 04:23:49 PM PDT 24
Finished Jul 15 04:23:50 PM PDT 24
Peak memory 196072 kb
Host smart-0380bbfa-ceb0-4174-87a9-a0c0f14e3b6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179922218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.179922218
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3746350699
Short name T1207
Test name
Test status
Simulation time 13335053 ps
CPU time 0.54 seconds
Started Jul 15 04:26:34 PM PDT 24
Finished Jul 15 04:26:35 PM PDT 24
Peak memory 194612 kb
Host smart-c9dce54a-6053-4831-a16d-cdf84d352f4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746350699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3746350699
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1716324081
Short name T1298
Test name
Test status
Simulation time 78945984 ps
CPU time 0.65 seconds
Started Jul 15 04:23:25 PM PDT 24
Finished Jul 15 04:23:26 PM PDT 24
Peak memory 196300 kb
Host smart-5ff90f39-e21b-40ef-bf68-09b4540f53a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716324081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1716324081
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3744058354
Short name T1215
Test name
Test status
Simulation time 81171353 ps
CPU time 1.22 seconds
Started Jul 15 04:24:45 PM PDT 24
Finished Jul 15 04:24:47 PM PDT 24
Peak memory 200608 kb
Host smart-3ded2a74-727b-4406-b0c3-90197d9e1ce7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744058354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3744058354
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3570389290
Short name T79
Test name
Test status
Simulation time 66820160 ps
CPU time 1.24 seconds
Started Jul 15 04:26:33 PM PDT 24
Finished Jul 15 04:26:35 PM PDT 24
Peak memory 199092 kb
Host smart-407637ca-177f-4910-acf8-98905008cc08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570389290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3570389290
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2711527016
Short name T1263
Test name
Test status
Simulation time 90770058 ps
CPU time 0.8 seconds
Started Jul 15 04:28:06 PM PDT 24
Finished Jul 15 04:28:10 PM PDT 24
Peak memory 200420 kb
Host smart-fef45d3b-e08a-4858-a853-8a9aa53dd525
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711527016 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2711527016
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1983133363
Short name T1221
Test name
Test status
Simulation time 13279365 ps
CPU time 0.66 seconds
Started Jul 15 04:28:04 PM PDT 24
Finished Jul 15 04:28:08 PM PDT 24
Peak memory 195992 kb
Host smart-33ce036b-299e-4a19-a849-2155942227e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983133363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1983133363
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3962674086
Short name T1210
Test name
Test status
Simulation time 20638323 ps
CPU time 0.59 seconds
Started Jul 15 04:23:09 PM PDT 24
Finished Jul 15 04:23:11 PM PDT 24
Peak memory 194976 kb
Host smart-81d5d566-0f27-4e15-a141-d0bb07f093c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962674086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3962674086
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.384201337
Short name T1235
Test name
Test status
Simulation time 74477184 ps
CPU time 0.63 seconds
Started Jul 15 04:28:10 PM PDT 24
Finished Jul 15 04:28:13 PM PDT 24
Peak memory 196488 kb
Host smart-54aa9d26-5e66-4dd4-83ed-aa5e85d53008
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384201337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.384201337
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2651482363
Short name T1230
Test name
Test status
Simulation time 25871138 ps
CPU time 1.11 seconds
Started Jul 15 04:26:24 PM PDT 24
Finished Jul 15 04:26:27 PM PDT 24
Peak memory 200660 kb
Host smart-2a5924a6-0372-4898-a158-b76b303b0359
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651482363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2651482363
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1363490994
Short name T85
Test name
Test status
Simulation time 186232317 ps
CPU time 0.95 seconds
Started Jul 15 04:24:37 PM PDT 24
Finished Jul 15 04:24:39 PM PDT 24
Peak memory 199984 kb
Host smart-d8cefce4-5134-4ca5-ac94-f8af3bc5b622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363490994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1363490994
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.865011058
Short name T1257
Test name
Test status
Simulation time 30031270 ps
CPU time 0.64 seconds
Started Jul 15 04:28:08 PM PDT 24
Finished Jul 15 04:28:12 PM PDT 24
Peak memory 198124 kb
Host smart-9b17e2b0-7296-48e9-aef9-61da78756b84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865011058 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.865011058
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2086470968
Short name T78
Test name
Test status
Simulation time 11941850 ps
CPU time 0.61 seconds
Started Jul 15 04:27:58 PM PDT 24
Finished Jul 15 04:28:03 PM PDT 24
Peak memory 196124 kb
Host smart-1b546a0d-036b-47d9-ac43-4297654c7161
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086470968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2086470968
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1325643397
Short name T1223
Test name
Test status
Simulation time 35359259 ps
CPU time 0.56 seconds
Started Jul 15 04:28:00 PM PDT 24
Finished Jul 15 04:28:04 PM PDT 24
Peak memory 194964 kb
Host smart-a5153938-8469-4da5-a7e9-7d4a30badd9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325643397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1325643397
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1262202545
Short name T1306
Test name
Test status
Simulation time 80580528 ps
CPU time 0.72 seconds
Started Jul 15 04:28:06 PM PDT 24
Finished Jul 15 04:28:10 PM PDT 24
Peak memory 197648 kb
Host smart-a6b3d3e4-756d-4b9e-8877-fdb9568fb8b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262202545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1262202545
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3917586869
Short name T1229
Test name
Test status
Simulation time 22204077 ps
CPU time 1.01 seconds
Started Jul 15 04:28:02 PM PDT 24
Finished Jul 15 04:28:07 PM PDT 24
Peak memory 200360 kb
Host smart-aacbb404-a25d-4c9a-bec0-f56738006419
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917586869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3917586869
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1340089355
Short name T1304
Test name
Test status
Simulation time 313596039 ps
CPU time 1.2 seconds
Started Jul 15 04:29:42 PM PDT 24
Finished Jul 15 04:29:44 PM PDT 24
Peak memory 199948 kb
Host smart-003f459e-e7ce-445a-bafd-36d28303a4a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340089355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1340089355
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.771359864
Short name T1204
Test name
Test status
Simulation time 163919636 ps
CPU time 0.76 seconds
Started Jul 15 04:27:02 PM PDT 24
Finished Jul 15 04:27:04 PM PDT 24
Peak memory 196964 kb
Host smart-b4b6884e-18d5-4647-92d8-034e57914e83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771359864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.771359864
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3003834227
Short name T64
Test name
Test status
Simulation time 112095030 ps
CPU time 2.32 seconds
Started Jul 15 04:22:39 PM PDT 24
Finished Jul 15 04:22:42 PM PDT 24
Peak memory 198244 kb
Host smart-89911b9c-e16b-4d23-8e7e-04d5b3e478bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003834227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3003834227
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4138338682
Short name T1187
Test name
Test status
Simulation time 96519056 ps
CPU time 0.62 seconds
Started Jul 15 04:21:40 PM PDT 24
Finished Jul 15 04:21:41 PM PDT 24
Peak memory 195972 kb
Host smart-2e890824-194f-42dd-b2e9-1fcbcdc60c9b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138338682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.4138338682
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3467652792
Short name T1225
Test name
Test status
Simulation time 98983372 ps
CPU time 1.31 seconds
Started Jul 15 04:25:06 PM PDT 24
Finished Jul 15 04:25:09 PM PDT 24
Peak memory 200972 kb
Host smart-621eba4e-a1af-4ee3-b290-ab52b8113af5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467652792 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3467652792
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3458527110
Short name T1279
Test name
Test status
Simulation time 49256308 ps
CPU time 0.59 seconds
Started Jul 15 04:26:45 PM PDT 24
Finished Jul 15 04:26:47 PM PDT 24
Peak memory 196084 kb
Host smart-e6b5a489-8e44-48df-9af7-db4bbee2c994
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458527110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3458527110
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3172368112
Short name T1314
Test name
Test status
Simulation time 22460988 ps
CPU time 0.59 seconds
Started Jul 15 04:21:44 PM PDT 24
Finished Jul 15 04:21:45 PM PDT 24
Peak memory 194948 kb
Host smart-06501cb3-34d8-4de4-b1a3-56b0725dba75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172368112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3172368112
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3693814643
Short name T1252
Test name
Test status
Simulation time 275368398 ps
CPU time 0.76 seconds
Started Jul 15 04:24:24 PM PDT 24
Finished Jul 15 04:24:26 PM PDT 24
Peak memory 197648 kb
Host smart-71633950-1ff6-4a7a-9c45-e1dcc71b3198
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693814643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3693814643
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4263745836
Short name T1316
Test name
Test status
Simulation time 504114734 ps
CPU time 2.14 seconds
Started Jul 15 04:26:26 PM PDT 24
Finished Jul 15 04:26:28 PM PDT 24
Peak memory 200584 kb
Host smart-b4e4f0f1-9f91-4317-af6a-cadbf3bb87ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263745836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4263745836
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.253315890
Short name T82
Test name
Test status
Simulation time 317163899 ps
CPU time 1.2 seconds
Started Jul 15 04:27:49 PM PDT 24
Finished Jul 15 04:27:53 PM PDT 24
Peak memory 199992 kb
Host smart-14c9e3d1-5aa2-4402-864d-8ad51068767e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253315890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.253315890
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2639575483
Short name T1310
Test name
Test status
Simulation time 35448624 ps
CPU time 0.58 seconds
Started Jul 15 04:28:01 PM PDT 24
Finished Jul 15 04:28:06 PM PDT 24
Peak memory 194956 kb
Host smart-5a11fe93-07fb-409a-b114-30b17e97a6b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639575483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2639575483
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2006183951
Short name T1319
Test name
Test status
Simulation time 11728085 ps
CPU time 0.59 seconds
Started Jul 15 04:28:02 PM PDT 24
Finished Jul 15 04:28:06 PM PDT 24
Peak memory 195240 kb
Host smart-b04a1d91-e135-491a-9e74-8750a4cfafb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006183951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2006183951
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.20667975
Short name T1196
Test name
Test status
Simulation time 10943447 ps
CPU time 0.57 seconds
Started Jul 15 04:28:03 PM PDT 24
Finished Jul 15 04:28:07 PM PDT 24
Peak memory 194944 kb
Host smart-05ed18b6-f6dc-4dd2-b39c-7ef445128766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20667975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.20667975
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3280230850
Short name T1234
Test name
Test status
Simulation time 52700612 ps
CPU time 0.54 seconds
Started Jul 15 04:28:08 PM PDT 24
Finished Jul 15 04:28:12 PM PDT 24
Peak memory 194996 kb
Host smart-5183e049-3eb2-4896-8ae7-973cb9cd718e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280230850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3280230850
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3249721242
Short name T1181
Test name
Test status
Simulation time 39635733 ps
CPU time 0.56 seconds
Started Jul 15 04:28:07 PM PDT 24
Finished Jul 15 04:28:12 PM PDT 24
Peak memory 195012 kb
Host smart-4510428e-d09c-4008-822a-d66dfefeff14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249721242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3249721242
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1609899280
Short name T1313
Test name
Test status
Simulation time 106666584 ps
CPU time 0.57 seconds
Started Jul 15 04:28:16 PM PDT 24
Finished Jul 15 04:28:17 PM PDT 24
Peak memory 195028 kb
Host smart-e74a6df8-9884-405e-8bfb-8a5d918e581a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609899280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1609899280
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3507949327
Short name T1291
Test name
Test status
Simulation time 74324118 ps
CPU time 0.62 seconds
Started Jul 15 04:28:00 PM PDT 24
Finished Jul 15 04:28:05 PM PDT 24
Peak memory 195320 kb
Host smart-bf760adb-eb00-4aad-8ac8-a2203440140d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507949327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3507949327
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3428508000
Short name T1191
Test name
Test status
Simulation time 28239722 ps
CPU time 0.57 seconds
Started Jul 15 04:28:17 PM PDT 24
Finished Jul 15 04:28:18 PM PDT 24
Peak memory 195012 kb
Host smart-34b71232-7098-4321-874a-cc6c7d99524b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428508000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3428508000
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3303753521
Short name T1199
Test name
Test status
Simulation time 46489107 ps
CPU time 0.65 seconds
Started Jul 15 04:29:08 PM PDT 24
Finished Jul 15 04:29:11 PM PDT 24
Peak memory 194048 kb
Host smart-8812232f-3f4b-4363-b4a4-805a60d13ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303753521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3303753521
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.447716235
Short name T1309
Test name
Test status
Simulation time 61187358 ps
CPU time 0.59 seconds
Started Jul 15 04:28:01 PM PDT 24
Finished Jul 15 04:28:06 PM PDT 24
Peak memory 194956 kb
Host smart-7e395d5e-ad45-42fc-96fe-5524eb1a821f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447716235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.447716235
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2856501135
Short name T69
Test name
Test status
Simulation time 232446313 ps
CPU time 0.78 seconds
Started Jul 15 04:23:57 PM PDT 24
Finished Jul 15 04:23:58 PM PDT 24
Peak memory 196924 kb
Host smart-041bd65e-e965-4924-8b5a-c45343a266b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856501135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2856501135
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.323333391
Short name T1266
Test name
Test status
Simulation time 510290260 ps
CPU time 1.48 seconds
Started Jul 15 04:24:14 PM PDT 24
Finished Jul 15 04:24:16 PM PDT 24
Peak memory 198184 kb
Host smart-cd618921-493e-4bc5-bd26-65e8c357578e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323333391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.323333391
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.136390113
Short name T1287
Test name
Test status
Simulation time 78618395 ps
CPU time 0.56 seconds
Started Jul 15 04:27:02 PM PDT 24
Finished Jul 15 04:27:04 PM PDT 24
Peak memory 195972 kb
Host smart-40932e8a-a89e-4959-8263-fe585886fdcf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136390113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.136390113
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3653069745
Short name T1280
Test name
Test status
Simulation time 177922277 ps
CPU time 0.86 seconds
Started Jul 15 04:26:50 PM PDT 24
Finished Jul 15 04:26:53 PM PDT 24
Peak memory 200008 kb
Host smart-9ad6f9f1-6804-4f7a-a066-090f3951fe1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653069745 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3653069745
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.141124131
Short name T1269
Test name
Test status
Simulation time 18359596 ps
CPU time 0.59 seconds
Started Jul 15 04:28:28 PM PDT 24
Finished Jul 15 04:28:30 PM PDT 24
Peak memory 194672 kb
Host smart-b3a81e4c-e629-4b31-8c3e-bc0483680bcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141124131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.141124131
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1962591148
Short name T1249
Test name
Test status
Simulation time 84764366 ps
CPU time 0.56 seconds
Started Jul 15 04:22:58 PM PDT 24
Finished Jul 15 04:22:59 PM PDT 24
Peak memory 194892 kb
Host smart-f846b944-b574-45f0-8cda-34d860c82b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962591148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1962591148
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3240726387
Short name T1303
Test name
Test status
Simulation time 39419656 ps
CPU time 0.68 seconds
Started Jul 15 04:24:14 PM PDT 24
Finished Jul 15 04:24:15 PM PDT 24
Peak memory 197380 kb
Host smart-f55ebda2-47fa-491e-8511-c78b0939dc1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240726387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3240726387
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1980213033
Short name T1248
Test name
Test status
Simulation time 280478903 ps
CPU time 1.28 seconds
Started Jul 15 04:27:05 PM PDT 24
Finished Jul 15 04:27:07 PM PDT 24
Peak memory 200664 kb
Host smart-25349582-d04a-4207-af27-7a3005dc2dbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980213033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1980213033
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1836186340
Short name T81
Test name
Test status
Simulation time 306109216 ps
CPU time 0.93 seconds
Started Jul 15 04:28:19 PM PDT 24
Finished Jul 15 04:28:21 PM PDT 24
Peak memory 198404 kb
Host smart-f0acde82-e2cb-4a69-b392-2515558e8bf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836186340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1836186340
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2217721800
Short name T1289
Test name
Test status
Simulation time 50383532 ps
CPU time 0.58 seconds
Started Jul 15 04:28:02 PM PDT 24
Finished Jul 15 04:28:07 PM PDT 24
Peak memory 194912 kb
Host smart-cdc77333-edc8-4860-985f-80a7282823d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217721800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2217721800
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.759700761
Short name T1300
Test name
Test status
Simulation time 40889402 ps
CPU time 0.56 seconds
Started Jul 15 04:28:07 PM PDT 24
Finished Jul 15 04:28:11 PM PDT 24
Peak memory 194984 kb
Host smart-cc41e711-7bb6-4cc1-9231-61d7146d4d7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759700761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.759700761
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1904872186
Short name T1202
Test name
Test status
Simulation time 66377586 ps
CPU time 0.57 seconds
Started Jul 15 04:28:02 PM PDT 24
Finished Jul 15 04:28:06 PM PDT 24
Peak memory 194776 kb
Host smart-d1d56fd7-98b7-420d-8eb2-9811f2b3299a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904872186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1904872186
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.141648501
Short name T1275
Test name
Test status
Simulation time 79943999 ps
CPU time 0.55 seconds
Started Jul 15 04:28:08 PM PDT 24
Finished Jul 15 04:28:12 PM PDT 24
Peak memory 194936 kb
Host smart-b269ccd3-9c8b-4ce0-9b14-19d8d2c77594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141648501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.141648501
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.609959554
Short name T1208
Test name
Test status
Simulation time 11914638 ps
CPU time 0.55 seconds
Started Jul 15 04:28:08 PM PDT 24
Finished Jul 15 04:28:12 PM PDT 24
Peak memory 195024 kb
Host smart-3f6a46de-5c96-4200-9a20-6b9c1298061c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609959554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.609959554
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.662863207
Short name T1286
Test name
Test status
Simulation time 20965596 ps
CPU time 0.58 seconds
Started Jul 15 04:28:02 PM PDT 24
Finished Jul 15 04:28:06 PM PDT 24
Peak memory 194760 kb
Host smart-ffd148e1-daf9-4e2b-a4fe-d4e46bb0f773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662863207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.662863207
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3052064135
Short name T1284
Test name
Test status
Simulation time 120077125 ps
CPU time 0.62 seconds
Started Jul 15 04:28:04 PM PDT 24
Finished Jul 15 04:28:08 PM PDT 24
Peak memory 194968 kb
Host smart-b0d3aaae-a212-44f7-9862-277f31255479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052064135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3052064135
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2954451143
Short name T1296
Test name
Test status
Simulation time 34034249 ps
CPU time 0.54 seconds
Started Jul 15 04:29:25 PM PDT 24
Finished Jul 15 04:29:27 PM PDT 24
Peak memory 194936 kb
Host smart-91b97226-9154-4d82-bb9b-293d12272004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954451143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2954451143
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3013283212
Short name T1251
Test name
Test status
Simulation time 17141746 ps
CPU time 0.53 seconds
Started Jul 15 04:29:33 PM PDT 24
Finished Jul 15 04:29:35 PM PDT 24
Peak memory 194904 kb
Host smart-9a05e253-2fd8-4a94-95e9-5ee252a55d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013283212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3013283212
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3974757174
Short name T1247
Test name
Test status
Simulation time 41023608 ps
CPU time 0.57 seconds
Started Jul 15 04:28:00 PM PDT 24
Finished Jul 15 04:28:05 PM PDT 24
Peak memory 195004 kb
Host smart-bcf242b7-4726-4fb2-bd12-837ae214e862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974757174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3974757174
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2295546156
Short name T1255
Test name
Test status
Simulation time 98569261 ps
CPU time 0.77 seconds
Started Jul 15 04:21:44 PM PDT 24
Finished Jul 15 04:21:46 PM PDT 24
Peak memory 196864 kb
Host smart-25ed3587-9de4-4995-8963-512577864b9e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295546156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2295546156
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4145446307
Short name T1307
Test name
Test status
Simulation time 401973745 ps
CPU time 1.48 seconds
Started Jul 15 04:24:04 PM PDT 24
Finished Jul 15 04:24:06 PM PDT 24
Peak memory 198264 kb
Host smart-be1e936c-be37-4c68-8f83-153197a28d11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145446307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.4145446307
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3332401348
Short name T1188
Test name
Test status
Simulation time 48436634 ps
CPU time 0.66 seconds
Started Jul 15 04:26:49 PM PDT 24
Finished Jul 15 04:26:52 PM PDT 24
Peak memory 194788 kb
Host smart-b9d3ed72-b64c-4a4c-942c-b70c6353860f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332401348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3332401348
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3343049576
Short name T1217
Test name
Test status
Simulation time 19674677 ps
CPU time 0.67 seconds
Started Jul 15 04:26:36 PM PDT 24
Finished Jul 15 04:26:37 PM PDT 24
Peak memory 198880 kb
Host smart-0d98c8e4-fad0-4605-bf58-64cd758b2186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343049576 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3343049576
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3105322040
Short name T1295
Test name
Test status
Simulation time 65622372 ps
CPU time 0.59 seconds
Started Jul 15 04:25:11 PM PDT 24
Finished Jul 15 04:25:12 PM PDT 24
Peak memory 195988 kb
Host smart-574bd3c5-f45e-4206-ac40-d09f61975cb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105322040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3105322040
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3550039407
Short name T1227
Test name
Test status
Simulation time 19131359 ps
CPU time 0.55 seconds
Started Jul 15 04:25:30 PM PDT 24
Finished Jul 15 04:25:31 PM PDT 24
Peak memory 194972 kb
Host smart-ca53a73d-1ae9-48a7-a35a-72bc618363bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550039407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3550039407
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3457766659
Short name T1232
Test name
Test status
Simulation time 26856536 ps
CPU time 0.72 seconds
Started Jul 15 04:26:37 PM PDT 24
Finished Jul 15 04:26:39 PM PDT 24
Peak memory 197076 kb
Host smart-0459a03c-60c7-4043-9ae1-77f2e0885682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457766659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3457766659
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3042840258
Short name T1211
Test name
Test status
Simulation time 187237497 ps
CPU time 1.33 seconds
Started Jul 15 04:22:15 PM PDT 24
Finished Jul 15 04:22:18 PM PDT 24
Peak memory 200592 kb
Host smart-9025475e-52a3-47a2-acbf-8e90f0e8e769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042840258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3042840258
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2418482457
Short name T80
Test name
Test status
Simulation time 316603177 ps
CPU time 0.88 seconds
Started Jul 15 04:27:48 PM PDT 24
Finished Jul 15 04:27:50 PM PDT 24
Peak memory 199688 kb
Host smart-76330402-04f3-419e-ae43-994692deedbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418482457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2418482457
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.4256285779
Short name T1186
Test name
Test status
Simulation time 57058737 ps
CPU time 0.55 seconds
Started Jul 15 04:29:28 PM PDT 24
Finished Jul 15 04:29:29 PM PDT 24
Peak memory 194848 kb
Host smart-eb2070ab-9711-45d0-a1f6-6d09e76f9981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256285779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.4256285779
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.216824068
Short name T1206
Test name
Test status
Simulation time 16627013 ps
CPU time 0.59 seconds
Started Jul 15 04:29:25 PM PDT 24
Finished Jul 15 04:29:27 PM PDT 24
Peak memory 194924 kb
Host smart-2a47fbd3-43eb-47df-869e-4525dcf265c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216824068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.216824068
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.69668560
Short name T1179
Test name
Test status
Simulation time 25065353 ps
CPU time 0.54 seconds
Started Jul 15 04:29:29 PM PDT 24
Finished Jul 15 04:29:31 PM PDT 24
Peak memory 194972 kb
Host smart-c22900ee-8818-4aa9-99d8-05a55c1a02f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69668560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.69668560
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1424864893
Short name T1231
Test name
Test status
Simulation time 44654453 ps
CPU time 0.53 seconds
Started Jul 15 04:29:37 PM PDT 24
Finished Jul 15 04:29:39 PM PDT 24
Peak memory 194904 kb
Host smart-56cae5c8-e38e-449d-96c6-0f7623b0cca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424864893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1424864893
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.208741381
Short name T1240
Test name
Test status
Simulation time 59388688 ps
CPU time 0.55 seconds
Started Jul 15 04:29:28 PM PDT 24
Finished Jul 15 04:29:29 PM PDT 24
Peak memory 194924 kb
Host smart-369e1567-d12e-430e-a746-ae7f0148e28d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208741381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.208741381
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2110363666
Short name T1297
Test name
Test status
Simulation time 39872469 ps
CPU time 0.53 seconds
Started Jul 15 04:28:01 PM PDT 24
Finished Jul 15 04:28:05 PM PDT 24
Peak memory 194940 kb
Host smart-aeb3c109-f6ff-4db5-b6c3-f1a0cf3138d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110363666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2110363666
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.33636076
Short name T1274
Test name
Test status
Simulation time 23803724 ps
CPU time 0.58 seconds
Started Jul 15 04:29:36 PM PDT 24
Finished Jul 15 04:29:38 PM PDT 24
Peak memory 194984 kb
Host smart-b7bd14a1-672c-4817-ba97-7dd35f7ad149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33636076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.33636076
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2893369284
Short name T1293
Test name
Test status
Simulation time 12509549 ps
CPU time 0.54 seconds
Started Jul 15 04:29:29 PM PDT 24
Finished Jul 15 04:29:32 PM PDT 24
Peak memory 194900 kb
Host smart-41e28e29-ead8-4856-a444-534bfe29079b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893369284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2893369284
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3186316973
Short name T1239
Test name
Test status
Simulation time 36784698 ps
CPU time 0.56 seconds
Started Jul 15 04:29:24 PM PDT 24
Finished Jul 15 04:29:26 PM PDT 24
Peak memory 194980 kb
Host smart-31435219-2cbc-46ba-a421-df51d99acb0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186316973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3186316973
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1768605430
Short name T1299
Test name
Test status
Simulation time 25662550 ps
CPU time 0.55 seconds
Started Jul 15 04:28:12 PM PDT 24
Finished Jul 15 04:28:14 PM PDT 24
Peak memory 194976 kb
Host smart-de1573ee-4f21-440d-9858-6cbccc319dd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768605430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1768605430
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3401064126
Short name T1273
Test name
Test status
Simulation time 81970222 ps
CPU time 0.7 seconds
Started Jul 15 04:26:17 PM PDT 24
Finished Jul 15 04:26:18 PM PDT 24
Peak memory 198804 kb
Host smart-9dbe8998-385d-435c-afc9-913b4965ee1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401064126 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3401064126
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3118454022
Short name T1253
Test name
Test status
Simulation time 14994712 ps
CPU time 0.66 seconds
Started Jul 15 04:26:21 PM PDT 24
Finished Jul 15 04:26:23 PM PDT 24
Peak memory 196112 kb
Host smart-7e28bbad-0c8c-444c-8a01-22e8230a8aa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118454022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3118454022
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1779925154
Short name T1183
Test name
Test status
Simulation time 16558224 ps
CPU time 0.61 seconds
Started Jul 15 04:25:39 PM PDT 24
Finished Jul 15 04:25:40 PM PDT 24
Peak memory 194960 kb
Host smart-64f17c39-ef76-4237-8fd5-7504e5bb1bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779925154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1779925154
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2317076513
Short name T1260
Test name
Test status
Simulation time 63096489 ps
CPU time 0.67 seconds
Started Jul 15 04:25:55 PM PDT 24
Finished Jul 15 04:25:58 PM PDT 24
Peak memory 197556 kb
Host smart-0e465cc2-04cf-4b8a-a0b9-3a2dbc2ad5be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317076513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2317076513
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3138192212
Short name T1283
Test name
Test status
Simulation time 70884494 ps
CPU time 1.18 seconds
Started Jul 15 04:27:33 PM PDT 24
Finished Jul 15 04:27:36 PM PDT 24
Peak memory 199284 kb
Host smart-26415563-ada2-4d42-888e-b4b4f8b91980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138192212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3138192212
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1403030341
Short name T84
Test name
Test status
Simulation time 326381488 ps
CPU time 1.35 seconds
Started Jul 15 04:23:02 PM PDT 24
Finished Jul 15 04:23:04 PM PDT 24
Peak memory 200272 kb
Host smart-9c1a5587-74c0-432e-86aa-e8f9f9ab7b6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403030341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1403030341
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3655905054
Short name T1216
Test name
Test status
Simulation time 140470615 ps
CPU time 0.78 seconds
Started Jul 15 04:26:09 PM PDT 24
Finished Jul 15 04:26:10 PM PDT 24
Peak memory 199044 kb
Host smart-e3baf064-a106-4595-b7a0-e39e1db6ac91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655905054 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3655905054
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.778795308
Short name T1222
Test name
Test status
Simulation time 45242015 ps
CPU time 0.59 seconds
Started Jul 15 04:23:25 PM PDT 24
Finished Jul 15 04:23:26 PM PDT 24
Peak memory 195984 kb
Host smart-27f81024-bfe3-4d07-9005-8f3b3cc71956
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778795308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.778795308
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2099666108
Short name T1205
Test name
Test status
Simulation time 129251126 ps
CPU time 0.53 seconds
Started Jul 15 04:27:58 PM PDT 24
Finished Jul 15 04:28:03 PM PDT 24
Peak memory 194924 kb
Host smart-4dd9f5f8-f5ec-4ba7-9eb6-317408cff428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099666108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2099666108
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.465309215
Short name T1265
Test name
Test status
Simulation time 24618869 ps
CPU time 0.7 seconds
Started Jul 15 04:27:06 PM PDT 24
Finished Jul 15 04:27:07 PM PDT 24
Peak memory 197436 kb
Host smart-0b2c243a-2ee3-4608-b542-8baec1761f62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465309215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.465309215
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3673171
Short name T1278
Test name
Test status
Simulation time 186568650 ps
CPU time 1.75 seconds
Started Jul 15 04:26:56 PM PDT 24
Finished Jul 15 04:26:59 PM PDT 24
Peak memory 200488 kb
Host smart-89d71dc2-c009-4507-a8a3-385fde1978fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3673171
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2472482803
Short name T1238
Test name
Test status
Simulation time 266513273 ps
CPU time 1.28 seconds
Started Jul 15 04:24:33 PM PDT 24
Finished Jul 15 04:24:35 PM PDT 24
Peak memory 199896 kb
Host smart-181b9e9f-661e-403c-bc11-e447ce69d9d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472482803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2472482803
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2106558478
Short name T1305
Test name
Test status
Simulation time 73776447 ps
CPU time 0.7 seconds
Started Jul 15 04:24:14 PM PDT 24
Finished Jul 15 04:24:15 PM PDT 24
Peak memory 198744 kb
Host smart-409c10f5-c04e-4492-9fae-06cfb33fb912
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106558478 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2106558478
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3185702564
Short name T1237
Test name
Test status
Simulation time 12664798 ps
CPU time 0.63 seconds
Started Jul 15 04:21:45 PM PDT 24
Finished Jul 15 04:21:46 PM PDT 24
Peak memory 195972 kb
Host smart-73762c68-bcfe-4e06-856e-ca2f929e7b7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185702564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3185702564
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3663059951
Short name T1185
Test name
Test status
Simulation time 13492288 ps
CPU time 0.61 seconds
Started Jul 15 04:27:40 PM PDT 24
Finished Jul 15 04:27:43 PM PDT 24
Peak memory 193656 kb
Host smart-28c72b09-2826-4fef-bf40-7ebf57e1c9e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663059951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3663059951
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2941348828
Short name T1220
Test name
Test status
Simulation time 19911791 ps
CPU time 0.76 seconds
Started Jul 15 04:21:53 PM PDT 24
Finished Jul 15 04:21:55 PM PDT 24
Peak memory 197440 kb
Host smart-6d097b41-028d-47d2-a17b-a9ab9ad81ed9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941348828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2941348828
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1397805678
Short name T1228
Test name
Test status
Simulation time 46453469 ps
CPU time 1.13 seconds
Started Jul 15 04:26:51 PM PDT 24
Finished Jul 15 04:26:54 PM PDT 24
Peak memory 199372 kb
Host smart-5646a75d-b146-4023-98c8-54db66dd883e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397805678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1397805678
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3976116243
Short name T1250
Test name
Test status
Simulation time 342233928 ps
CPU time 1.42 seconds
Started Jul 15 04:24:39 PM PDT 24
Finished Jul 15 04:24:41 PM PDT 24
Peak memory 199896 kb
Host smart-4d8924be-6e60-4173-b5eb-2697bb101570
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976116243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3976116243
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3948629114
Short name T1244
Test name
Test status
Simulation time 76837194 ps
CPU time 0.75 seconds
Started Jul 15 04:26:41 PM PDT 24
Finished Jul 15 04:26:43 PM PDT 24
Peak memory 200428 kb
Host smart-eb333011-4615-45be-88e0-b1bdca5dad44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948629114 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3948629114
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3526730842
Short name T70
Test name
Test status
Simulation time 15508762 ps
CPU time 0.63 seconds
Started Jul 15 04:23:15 PM PDT 24
Finished Jul 15 04:23:16 PM PDT 24
Peak memory 195984 kb
Host smart-d5a4cd1f-3098-4536-af0c-426051ac04dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526730842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3526730842
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1800219017
Short name T1294
Test name
Test status
Simulation time 14135739 ps
CPU time 0.58 seconds
Started Jul 15 04:22:51 PM PDT 24
Finished Jul 15 04:22:52 PM PDT 24
Peak memory 194892 kb
Host smart-ec48283e-3684-443c-a414-0394ff5deb13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800219017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1800219017
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.20422155
Short name T74
Test name
Test status
Simulation time 30472316 ps
CPU time 0.76 seconds
Started Jul 15 04:27:37 PM PDT 24
Finished Jul 15 04:27:42 PM PDT 24
Peak memory 194444 kb
Host smart-d13ab50e-ecc3-46e1-b052-22c7874df0b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20422155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_o
utstanding.20422155
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.564760329
Short name T1214
Test name
Test status
Simulation time 493407893 ps
CPU time 2.19 seconds
Started Jul 15 04:24:46 PM PDT 24
Finished Jul 15 04:24:49 PM PDT 24
Peak memory 200756 kb
Host smart-cb7b775e-dd6c-4642-8b9e-ec2d64577294
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564760329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.564760329
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1990773831
Short name T1292
Test name
Test status
Simulation time 303646396 ps
CPU time 1.33 seconds
Started Jul 15 04:27:35 PM PDT 24
Finished Jul 15 04:27:42 PM PDT 24
Peak memory 199016 kb
Host smart-5aadaab7-e048-4253-9093-7a4f9671a80a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990773831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1990773831
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1216669387
Short name T1301
Test name
Test status
Simulation time 29456558 ps
CPU time 0.86 seconds
Started Jul 15 04:27:10 PM PDT 24
Finished Jul 15 04:27:12 PM PDT 24
Peak memory 200356 kb
Host smart-cf481ea0-69b5-42c4-918a-70ff1b2cd326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216669387 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1216669387
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1701787078
Short name T1245
Test name
Test status
Simulation time 41964837 ps
CPU time 0.64 seconds
Started Jul 15 04:27:37 PM PDT 24
Finished Jul 15 04:27:42 PM PDT 24
Peak memory 193264 kb
Host smart-8851f72a-b74e-4401-b011-a5a31544f872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701787078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1701787078
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3108198881
Short name T1268
Test name
Test status
Simulation time 15724209 ps
CPU time 0.72 seconds
Started Jul 15 04:26:35 PM PDT 24
Finished Jul 15 04:26:37 PM PDT 24
Peak memory 196568 kb
Host smart-7dcd4ada-229d-4c9c-924b-b22650100b89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108198881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3108198881
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.289393965
Short name T1197
Test name
Test status
Simulation time 111382455 ps
CPU time 1.37 seconds
Started Jul 15 04:24:06 PM PDT 24
Finished Jul 15 04:24:08 PM PDT 24
Peak memory 200644 kb
Host smart-0615d9d9-70a0-4334-a4d9-73b60b55c577
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289393965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.289393965
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.207319618
Short name T1272
Test name
Test status
Simulation time 71461320 ps
CPU time 1.16 seconds
Started Jul 15 04:27:51 PM PDT 24
Finished Jul 15 04:27:56 PM PDT 24
Peak memory 199632 kb
Host smart-bb1e3b24-b1cd-4543-b46b-58adf2140366
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207319618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.207319618
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.854556784
Short name T130
Test name
Test status
Simulation time 61017141348 ps
CPU time 25.21 seconds
Started Jul 15 04:23:13 PM PDT 24
Finished Jul 15 04:23:38 PM PDT 24
Peak memory 199748 kb
Host smart-de348373-d745-42c6-8e25-6f02170843a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854556784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.854556784
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3296742400
Short name T1134
Test name
Test status
Simulation time 36618116046 ps
CPU time 33.92 seconds
Started Jul 15 04:21:45 PM PDT 24
Finished Jul 15 04:22:20 PM PDT 24
Peak memory 199760 kb
Host smart-d0d24b22-9528-47c2-bded-6a4acd2d0028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296742400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3296742400
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.852507805
Short name T766
Test name
Test status
Simulation time 61136309326 ps
CPU time 30 seconds
Started Jul 15 04:24:04 PM PDT 24
Finished Jul 15 04:24:35 PM PDT 24
Peak memory 199684 kb
Host smart-af36ca4e-6bd5-4be2-98cd-909ce87e9c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852507805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.852507805
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3429647193
Short name T962
Test name
Test status
Simulation time 138440373344 ps
CPU time 184.59 seconds
Started Jul 15 04:24:51 PM PDT 24
Finished Jul 15 04:27:56 PM PDT 24
Peak memory 199596 kb
Host smart-ecd1be74-8dc1-40a5-86c0-f7db04d123fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429647193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3429647193
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3439506122
Short name T1155
Test name
Test status
Simulation time 78499818447 ps
CPU time 305.12 seconds
Started Jul 15 04:23:54 PM PDT 24
Finished Jul 15 04:29:00 PM PDT 24
Peak memory 199752 kb
Host smart-424eda85-1320-475c-96a6-577e0284ed5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439506122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3439506122
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.498372740
Short name T794
Test name
Test status
Simulation time 4674835331 ps
CPU time 8.74 seconds
Started Jul 15 04:26:29 PM PDT 24
Finished Jul 15 04:26:38 PM PDT 24
Peak memory 198096 kb
Host smart-7785fca5-8de5-49e5-896c-da5c16916f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498372740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.498372740
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1759013402
Short name T829
Test name
Test status
Simulation time 84082466565 ps
CPU time 76.35 seconds
Started Jul 15 04:26:06 PM PDT 24
Finished Jul 15 04:27:23 PM PDT 24
Peak memory 200200 kb
Host smart-c6ae300d-1818-4f9d-8c8d-8f312c094549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759013402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1759013402
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1790735590
Short name T458
Test name
Test status
Simulation time 16838566834 ps
CPU time 531.65 seconds
Started Jul 15 04:26:51 PM PDT 24
Finished Jul 15 04:35:45 PM PDT 24
Peak memory 199408 kb
Host smart-f462cc87-0b83-42bf-9e90-0db1b296e12a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790735590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1790735590
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3011570190
Short name T1136
Test name
Test status
Simulation time 5611509256 ps
CPU time 12.16 seconds
Started Jul 15 04:26:55 PM PDT 24
Finished Jul 15 04:27:09 PM PDT 24
Peak memory 198404 kb
Host smart-b8c7346a-03a8-4c31-9fdc-ca862a97478b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3011570190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3011570190
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3254169830
Short name T6
Test name
Test status
Simulation time 86741440212 ps
CPU time 36.63 seconds
Started Jul 15 04:24:53 PM PDT 24
Finished Jul 15 04:25:30 PM PDT 24
Peak memory 199684 kb
Host smart-e1b3dca0-5224-47d0-a889-076beb40b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254169830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3254169830
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3834105396
Short name T1141
Test name
Test status
Simulation time 5485928319 ps
CPU time 4.75 seconds
Started Jul 15 04:27:49 PM PDT 24
Finished Jul 15 04:27:56 PM PDT 24
Peak memory 195808 kb
Host smart-ecd7a624-3322-4c69-96ea-3b1819be3bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834105396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3834105396
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3357888715
Short name T752
Test name
Test status
Simulation time 5880477803 ps
CPU time 8.98 seconds
Started Jul 15 04:26:50 PM PDT 24
Finished Jul 15 04:27:01 PM PDT 24
Peak memory 198696 kb
Host smart-0dcc17b2-77a0-4652-9a04-c1d65d30c94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357888715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3357888715
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2808417555
Short name T441
Test name
Test status
Simulation time 23663038788 ps
CPU time 41.58 seconds
Started Jul 15 04:24:53 PM PDT 24
Finished Jul 15 04:25:35 PM PDT 24
Peak memory 199728 kb
Host smart-c8401e86-8361-4320-aef9-6ac7ef608312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808417555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2808417555
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.4078265515
Short name T864
Test name
Test status
Simulation time 67075099152 ps
CPU time 245.68 seconds
Started Jul 15 04:27:05 PM PDT 24
Finished Jul 15 04:31:12 PM PDT 24
Peak memory 216376 kb
Host smart-dc943b77-ad27-493a-8953-6a3f40c80193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078265515 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.4078265515
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.867800021
Short name T790
Test name
Test status
Simulation time 6071286004 ps
CPU time 21.43 seconds
Started Jul 15 04:27:28 PM PDT 24
Finished Jul 15 04:27:51 PM PDT 24
Peak memory 198336 kb
Host smart-5bd31602-51b2-421e-bf36-956354cc3795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867800021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.867800021
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1723905225
Short name T271
Test name
Test status
Simulation time 107579843597 ps
CPU time 61.43 seconds
Started Jul 15 04:25:02 PM PDT 24
Finished Jul 15 04:26:04 PM PDT 24
Peak memory 199692 kb
Host smart-95971784-da55-436c-a1d8-6ab9f86926e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723905225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1723905225
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3665615316
Short name T324
Test name
Test status
Simulation time 22485130 ps
CPU time 0.58 seconds
Started Jul 15 04:30:30 PM PDT 24
Finished Jul 15 04:30:33 PM PDT 24
Peak memory 194420 kb
Host smart-f516e6e1-1f29-46b8-9e00-2ff3f82d8726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665615316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3665615316
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2154914130
Short name T484
Test name
Test status
Simulation time 21105305127 ps
CPU time 18.39 seconds
Started Jul 15 04:30:12 PM PDT 24
Finished Jul 15 04:30:34 PM PDT 24
Peak memory 199732 kb
Host smart-16fb6b2f-c63c-4e47-a962-911b7f50ed07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154914130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2154914130
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.4234366792
Short name T798
Test name
Test status
Simulation time 65326474817 ps
CPU time 106.64 seconds
Started Jul 15 04:30:22 PM PDT 24
Finished Jul 15 04:32:10 PM PDT 24
Peak memory 199728 kb
Host smart-532670b3-431a-441e-98c6-76211808670d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234366792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.4234366792
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1298372171
Short name T152
Test name
Test status
Simulation time 13609918898 ps
CPU time 14.87 seconds
Started Jul 15 04:30:20 PM PDT 24
Finished Jul 15 04:30:36 PM PDT 24
Peak memory 199744 kb
Host smart-468adbbd-6438-426b-95d2-e23e39894dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298372171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1298372171
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3551997545
Short name T349
Test name
Test status
Simulation time 235888627399 ps
CPU time 369.83 seconds
Started Jul 15 04:30:21 PM PDT 24
Finished Jul 15 04:36:32 PM PDT 24
Peak memory 197436 kb
Host smart-19c14bb2-d40d-43f2-8010-055c35e719e8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551997545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3551997545
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_loopback.19046060
Short name T635
Test name
Test status
Simulation time 6315301210 ps
CPU time 9.91 seconds
Started Jul 15 04:30:27 PM PDT 24
Finished Jul 15 04:30:39 PM PDT 24
Peak memory 199776 kb
Host smart-bb3bdc1e-ba76-45f3-b802-263625b02eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19046060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.19046060
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2031738966
Short name T503
Test name
Test status
Simulation time 107850338363 ps
CPU time 43.89 seconds
Started Jul 15 04:30:28 PM PDT 24
Finished Jul 15 04:31:14 PM PDT 24
Peak memory 199540 kb
Host smart-aa1b6348-06a0-445d-b496-d54c10ec6d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031738966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2031738966
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.4112422655
Short name T272
Test name
Test status
Simulation time 8223838257 ps
CPU time 78.7 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 04:31:36 PM PDT 24
Peak memory 199808 kb
Host smart-63e17005-9019-4c25-aab2-82dcda596695
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4112422655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.4112422655
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3323244321
Short name T422
Test name
Test status
Simulation time 1324727237 ps
CPU time 1.14 seconds
Started Jul 15 04:30:18 PM PDT 24
Finished Jul 15 04:30:21 PM PDT 24
Peak memory 197824 kb
Host smart-0408f95d-4849-42f4-a26f-ef286af3bd6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323244321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3323244321
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1683376284
Short name T946
Test name
Test status
Simulation time 173259735215 ps
CPU time 610.92 seconds
Started Jul 15 04:30:21 PM PDT 24
Finished Jul 15 04:40:33 PM PDT 24
Peak memory 199668 kb
Host smart-72115e6b-2361-49d0-b2c1-061db157a773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683376284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1683376284
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2957656469
Short name T394
Test name
Test status
Simulation time 656482075 ps
CPU time 1.67 seconds
Started Jul 15 04:30:28 PM PDT 24
Finished Jul 15 04:30:32 PM PDT 24
Peak memory 195344 kb
Host smart-103d3323-06d6-4c05-b611-a30a71373114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957656469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2957656469
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.273589600
Short name T24
Test name
Test status
Simulation time 33082912 ps
CPU time 0.76 seconds
Started Jul 15 04:30:20 PM PDT 24
Finished Jul 15 04:30:22 PM PDT 24
Peak memory 217888 kb
Host smart-d10c933c-15e6-4224-b29a-82401ef2d7cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273589600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.273589600
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3400305285
Short name T1064
Test name
Test status
Simulation time 5954232865 ps
CPU time 18.46 seconds
Started Jul 15 04:27:46 PM PDT 24
Finished Jul 15 04:28:06 PM PDT 24
Peak memory 199676 kb
Host smart-a976d4f1-b48f-49c1-90eb-1918a2704185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400305285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3400305285
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1520976692
Short name T649
Test name
Test status
Simulation time 390650860850 ps
CPU time 1108.66 seconds
Started Jul 15 04:30:25 PM PDT 24
Finished Jul 15 04:48:55 PM PDT 24
Peak memory 208412 kb
Host smart-f1a5452f-9336-422d-b401-74c9f72d605f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520976692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1520976692
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2107111084
Short name T183
Test name
Test status
Simulation time 104450089978 ps
CPU time 1109.53 seconds
Started Jul 15 04:30:18 PM PDT 24
Finished Jul 15 04:48:49 PM PDT 24
Peak memory 216240 kb
Host smart-60166b6f-d46f-46ad-a2e0-e3f4fa9de6ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107111084 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2107111084
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3093092551
Short name T821
Test name
Test status
Simulation time 6636649261 ps
CPU time 15.3 seconds
Started Jul 15 04:30:24 PM PDT 24
Finished Jul 15 04:30:41 PM PDT 24
Peak memory 199524 kb
Host smart-d52d187a-dd8d-4062-8e72-9e0269b86e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093092551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3093092551
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3263538992
Short name T816
Test name
Test status
Simulation time 69836219196 ps
CPU time 51.31 seconds
Started Jul 15 04:26:32 PM PDT 24
Finished Jul 15 04:27:24 PM PDT 24
Peak memory 199724 kb
Host smart-0ac8ae30-a4ed-4fa6-8246-bbd6be678af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263538992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3263538992
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.674478245
Short name T965
Test name
Test status
Simulation time 19595588 ps
CPU time 0.56 seconds
Started Jul 15 04:30:53 PM PDT 24
Finished Jul 15 04:30:55 PM PDT 24
Peak memory 195368 kb
Host smart-0aad7e96-427f-4e1f-af99-548d4e4485ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674478245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.674478245
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3077775431
Short name T696
Test name
Test status
Simulation time 34817017679 ps
CPU time 23.23 seconds
Started Jul 15 04:30:51 PM PDT 24
Finished Jul 15 04:31:16 PM PDT 24
Peak memory 199700 kb
Host smart-e07bdcac-f668-4630-b471-5d05c9b80b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077775431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3077775431
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3869167357
Short name T524
Test name
Test status
Simulation time 27000861252 ps
CPU time 25.98 seconds
Started Jul 15 04:30:51 PM PDT 24
Finished Jul 15 04:31:18 PM PDT 24
Peak memory 199724 kb
Host smart-e5fec3dc-bcaa-481a-951d-c2f0374df69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869167357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3869167357
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.3333311695
Short name T344
Test name
Test status
Simulation time 36523629046 ps
CPU time 11.36 seconds
Started Jul 15 04:30:52 PM PDT 24
Finished Jul 15 04:31:05 PM PDT 24
Peak memory 199552 kb
Host smart-5b1d8126-acb6-4a9b-b11b-8755e42f608f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333311695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3333311695
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3235998994
Short name T1168
Test name
Test status
Simulation time 60076433483 ps
CPU time 291.37 seconds
Started Jul 15 04:30:52 PM PDT 24
Finished Jul 15 04:35:45 PM PDT 24
Peak memory 199688 kb
Host smart-f2a1be08-81e5-4c20-bff3-246a6ba2ff90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235998994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3235998994
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.635749197
Short name T818
Test name
Test status
Simulation time 3535376674 ps
CPU time 3.54 seconds
Started Jul 15 04:30:56 PM PDT 24
Finished Jul 15 04:31:01 PM PDT 24
Peak memory 195932 kb
Host smart-135a3a32-e939-41cd-adea-5ada4d64df63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635749197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.635749197
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2939889581
Short name T805
Test name
Test status
Simulation time 38877909640 ps
CPU time 64.42 seconds
Started Jul 15 04:30:52 PM PDT 24
Finished Jul 15 04:31:58 PM PDT 24
Peak memory 208000 kb
Host smart-d2151f55-ac1e-4569-b2a4-0fb99028a2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939889581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2939889581
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.1482093870
Short name T1076
Test name
Test status
Simulation time 8016249836 ps
CPU time 117.92 seconds
Started Jul 15 04:30:50 PM PDT 24
Finished Jul 15 04:32:50 PM PDT 24
Peak memory 199688 kb
Host smart-1882392d-e298-415d-9ae2-97b715a5cd10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482093870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1482093870
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1468953741
Short name T558
Test name
Test status
Simulation time 1806867198 ps
CPU time 2.74 seconds
Started Jul 15 04:30:53 PM PDT 24
Finished Jul 15 04:30:57 PM PDT 24
Peak memory 198940 kb
Host smart-cdcbd22f-fffc-46d3-8b48-040b3ba61882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468953741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1468953741
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1907793222
Short name T640
Test name
Test status
Simulation time 26899135866 ps
CPU time 39.63 seconds
Started Jul 15 04:30:54 PM PDT 24
Finished Jul 15 04:31:35 PM PDT 24
Peak memory 200072 kb
Host smart-3ae7c79e-36e3-4e7a-8cbd-ef3669d8fbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907793222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1907793222
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2578505283
Short name T796
Test name
Test status
Simulation time 4562731032 ps
CPU time 3.09 seconds
Started Jul 15 04:30:52 PM PDT 24
Finished Jul 15 04:30:58 PM PDT 24
Peak memory 195948 kb
Host smart-1d8c2746-a6e5-41a5-afc5-67e649d33778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578505283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2578505283
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1333947481
Short name T883
Test name
Test status
Simulation time 740722309 ps
CPU time 2.14 seconds
Started Jul 15 04:30:53 PM PDT 24
Finished Jul 15 04:30:57 PM PDT 24
Peak memory 199064 kb
Host smart-3ae27294-c8cc-47f1-879a-441bdd67019f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333947481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1333947481
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3526668188
Short name T1159
Test name
Test status
Simulation time 127162138044 ps
CPU time 528.03 seconds
Started Jul 15 04:30:52 PM PDT 24
Finished Jul 15 04:39:41 PM PDT 24
Peak memory 227212 kb
Host smart-c0066f2c-2e83-47d8-8ba3-1aae5e2ce6bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526668188 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3526668188
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.552200032
Short name T849
Test name
Test status
Simulation time 1032633784 ps
CPU time 1.29 seconds
Started Jul 15 04:30:51 PM PDT 24
Finished Jul 15 04:30:53 PM PDT 24
Peak memory 198224 kb
Host smart-bb07ce9f-d704-4af8-b3aa-cdd4c820d121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552200032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.552200032
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1687857291
Short name T694
Test name
Test status
Simulation time 77798543086 ps
CPU time 36.55 seconds
Started Jul 15 04:30:52 PM PDT 24
Finished Jul 15 04:31:30 PM PDT 24
Peak memory 199716 kb
Host smart-b5d201f4-5c61-4f36-bb91-eb0478b73406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687857291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1687857291
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1322883576
Short name T1058
Test name
Test status
Simulation time 48269988446 ps
CPU time 20.02 seconds
Started Jul 15 04:34:15 PM PDT 24
Finished Jul 15 04:34:37 PM PDT 24
Peak memory 199848 kb
Host smart-29bb4444-6a37-4739-ae30-98386dd025cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322883576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1322883576
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3707958418
Short name T440
Test name
Test status
Simulation time 100313559253 ps
CPU time 167.19 seconds
Started Jul 15 04:34:14 PM PDT 24
Finished Jul 15 04:37:02 PM PDT 24
Peak memory 199668 kb
Host smart-d28310d6-0b1e-4f13-98f4-64b05a97ebaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707958418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3707958418
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3715817837
Short name T176
Test name
Test status
Simulation time 137629848168 ps
CPU time 152.86 seconds
Started Jul 15 04:34:15 PM PDT 24
Finished Jul 15 04:36:49 PM PDT 24
Peak memory 199704 kb
Host smart-0e140d87-fcef-4af4-bd79-a70ffa789c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715817837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3715817837
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.514009212
Short name T769
Test name
Test status
Simulation time 54039195035 ps
CPU time 81.89 seconds
Started Jul 15 04:34:13 PM PDT 24
Finished Jul 15 04:35:36 PM PDT 24
Peak memory 200092 kb
Host smart-45f4da6b-9897-4784-ba91-7f9653e6f61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514009212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.514009212
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2101378727
Short name T320
Test name
Test status
Simulation time 13045227221 ps
CPU time 35.31 seconds
Started Jul 15 04:34:16 PM PDT 24
Finished Jul 15 04:34:53 PM PDT 24
Peak memory 199648 kb
Host smart-c4fd1160-6924-42ce-8f1e-43339ed4b34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101378727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2101378727
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1440829739
Short name T180
Test name
Test status
Simulation time 130686912041 ps
CPU time 55.16 seconds
Started Jul 15 04:34:14 PM PDT 24
Finished Jul 15 04:35:11 PM PDT 24
Peak memory 199752 kb
Host smart-d58cbabe-a9a8-4b44-91e7-49c09da3aad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440829739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1440829739
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1278648034
Short name T935
Test name
Test status
Simulation time 13252074049 ps
CPU time 19.17 seconds
Started Jul 15 04:34:17 PM PDT 24
Finished Jul 15 04:34:37 PM PDT 24
Peak memory 199652 kb
Host smart-556c58f4-d79d-4201-b108-e929bd6a9cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278648034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1278648034
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.4170178672
Short name T1167
Test name
Test status
Simulation time 12055617658 ps
CPU time 20.07 seconds
Started Jul 15 04:34:13 PM PDT 24
Finished Jul 15 04:34:34 PM PDT 24
Peak memory 199692 kb
Host smart-f3356dc3-e40f-4474-b37e-f546c6dba47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170178672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.4170178672
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1523781785
Short name T625
Test name
Test status
Simulation time 50032232150 ps
CPU time 38.41 seconds
Started Jul 15 04:34:17 PM PDT 24
Finished Jul 15 04:34:57 PM PDT 24
Peak memory 199676 kb
Host smart-0e019e17-b265-436d-ac66-2aa2408bcfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523781785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1523781785
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2256742669
Short name T661
Test name
Test status
Simulation time 36522331 ps
CPU time 0.56 seconds
Started Jul 15 04:30:59 PM PDT 24
Finished Jul 15 04:31:01 PM PDT 24
Peak memory 195064 kb
Host smart-61c55566-e81e-4653-a23e-92231728c619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256742669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2256742669
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1540089883
Short name T672
Test name
Test status
Simulation time 96694286928 ps
CPU time 184.11 seconds
Started Jul 15 04:30:52 PM PDT 24
Finished Jul 15 04:33:58 PM PDT 24
Peak memory 199644 kb
Host smart-47ec456a-b0a3-4d36-9826-2420e3438d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540089883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1540089883
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2410897586
Short name T674
Test name
Test status
Simulation time 61608525712 ps
CPU time 77.4 seconds
Started Jul 15 04:30:53 PM PDT 24
Finished Jul 15 04:32:12 PM PDT 24
Peak memory 199708 kb
Host smart-5393b339-ef30-42a6-a4ba-9e5a4b36283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410897586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2410897586
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.2804594993
Short name T424
Test name
Test status
Simulation time 47352695130 ps
CPU time 27.74 seconds
Started Jul 15 04:30:52 PM PDT 24
Finished Jul 15 04:31:22 PM PDT 24
Peak memory 199792 kb
Host smart-f7efe2a2-b9a2-4cd2-a6e1-b5b834cf876f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804594993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2804594993
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.960624785
Short name T333
Test name
Test status
Simulation time 75533442956 ps
CPU time 99.66 seconds
Started Jul 15 04:30:59 PM PDT 24
Finished Jul 15 04:32:40 PM PDT 24
Peak memory 199664 kb
Host smart-36f8923e-032e-410a-b82b-b7fe54970f84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960624785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.960624785
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3644748252
Short name T1150
Test name
Test status
Simulation time 8585668227 ps
CPU time 3.23 seconds
Started Jul 15 04:31:02 PM PDT 24
Finished Jul 15 04:31:06 PM PDT 24
Peak memory 198788 kb
Host smart-700c9a04-1323-49f2-a7e8-3cb9e0b5d452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644748252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3644748252
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.624138635
Short name T872
Test name
Test status
Simulation time 63401378650 ps
CPU time 25.68 seconds
Started Jul 15 04:30:52 PM PDT 24
Finished Jul 15 04:31:19 PM PDT 24
Peak memory 199936 kb
Host smart-2fa41758-4844-48d2-b5cc-49701894d56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624138635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.624138635
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.848567472
Short name T473
Test name
Test status
Simulation time 14115867953 ps
CPU time 860.99 seconds
Started Jul 15 04:31:01 PM PDT 24
Finished Jul 15 04:45:23 PM PDT 24
Peak memory 199668 kb
Host smart-ff8e2736-21b9-4476-af4b-9cdb9f76389a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=848567472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.848567472
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3510355563
Short name T576
Test name
Test status
Simulation time 1329416165 ps
CPU time 0.7 seconds
Started Jul 15 04:30:55 PM PDT 24
Finished Jul 15 04:30:57 PM PDT 24
Peak memory 195204 kb
Host smart-bcf8b89b-3e7e-40ac-a5d1-d0b5672a340c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510355563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3510355563
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1300090042
Short name T685
Test name
Test status
Simulation time 55486823642 ps
CPU time 46.78 seconds
Started Jul 15 04:30:59 PM PDT 24
Finished Jul 15 04:31:47 PM PDT 24
Peak memory 199492 kb
Host smart-7c7793da-9960-4693-92c2-a98aa49b1645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300090042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1300090042
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2547824773
Short name T1017
Test name
Test status
Simulation time 36407527137 ps
CPU time 23.67 seconds
Started Jul 15 04:30:52 PM PDT 24
Finished Jul 15 04:31:18 PM PDT 24
Peak memory 195688 kb
Host smart-ae90f3d3-1082-4914-8dcb-b5fb978dd931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547824773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2547824773
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.4045523670
Short name T850
Test name
Test status
Simulation time 562925701 ps
CPU time 2.31 seconds
Started Jul 15 04:30:51 PM PDT 24
Finished Jul 15 04:30:55 PM PDT 24
Peak memory 198664 kb
Host smart-800c8516-f704-4da7-8b0e-3bf481fd6974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045523670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.4045523670
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1406365420
Short name T266
Test name
Test status
Simulation time 119193709520 ps
CPU time 125.05 seconds
Started Jul 15 04:30:59 PM PDT 24
Finished Jul 15 04:33:06 PM PDT 24
Peak memory 199716 kb
Host smart-8047c5a2-a728-4371-9fc8-15648c2964ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406365420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1406365420
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1182679951
Short name T104
Test name
Test status
Simulation time 105945485564 ps
CPU time 994.12 seconds
Started Jul 15 04:30:59 PM PDT 24
Finished Jul 15 04:47:35 PM PDT 24
Peak memory 232748 kb
Host smart-72b00af4-3abd-4c08-8b8c-1bc6f8abb756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182679951 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1182679951
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1721732161
Short name T823
Test name
Test status
Simulation time 7213802471 ps
CPU time 12.11 seconds
Started Jul 15 04:30:59 PM PDT 24
Finished Jul 15 04:31:12 PM PDT 24
Peak memory 199076 kb
Host smart-62e87088-edfb-4bc0-84a6-602f7281eb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721732161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1721732161
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1146000447
Short name T227
Test name
Test status
Simulation time 77658924789 ps
CPU time 64.51 seconds
Started Jul 15 04:30:53 PM PDT 24
Finished Jul 15 04:31:59 PM PDT 24
Peak memory 199708 kb
Host smart-7a475ca9-dd8b-4a16-ae18-c51a00b33484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146000447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1146000447
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3775933241
Short name T25
Test name
Test status
Simulation time 8385896810 ps
CPU time 12.07 seconds
Started Jul 15 04:34:16 PM PDT 24
Finished Jul 15 04:34:30 PM PDT 24
Peak memory 198568 kb
Host smart-d4e77bab-4403-4f95-9098-27a45bc9f57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775933241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3775933241
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1252127513
Short name T912
Test name
Test status
Simulation time 116440277744 ps
CPU time 124.6 seconds
Started Jul 15 04:34:11 PM PDT 24
Finished Jul 15 04:36:17 PM PDT 24
Peak memory 199700 kb
Host smart-3856c6a8-01de-4428-8ec5-6e49cb4cd905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252127513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1252127513
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3945839088
Short name T578
Test name
Test status
Simulation time 58980027205 ps
CPU time 26.13 seconds
Started Jul 15 04:34:15 PM PDT 24
Finished Jul 15 04:34:43 PM PDT 24
Peak memory 199848 kb
Host smart-082add5f-49bb-4bdd-9fa4-066218ede209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945839088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3945839088
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2494312556
Short name T1041
Test name
Test status
Simulation time 117570708198 ps
CPU time 92.89 seconds
Started Jul 15 04:34:14 PM PDT 24
Finished Jul 15 04:35:49 PM PDT 24
Peak memory 199884 kb
Host smart-0b184b6e-8b1a-4bd2-827a-c9bd4f2e9cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494312556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2494312556
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3691382101
Short name T969
Test name
Test status
Simulation time 132886735898 ps
CPU time 33.57 seconds
Started Jul 15 04:34:15 PM PDT 24
Finished Jul 15 04:34:50 PM PDT 24
Peak memory 199760 kb
Host smart-0539dc2c-67b5-4137-adff-bfe0fd98ea2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691382101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3691382101
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.190628217
Short name T734
Test name
Test status
Simulation time 24085681983 ps
CPU time 40.7 seconds
Started Jul 15 04:34:13 PM PDT 24
Finished Jul 15 04:34:55 PM PDT 24
Peak memory 199792 kb
Host smart-4b146dcc-895b-4e89-8d94-a3fc86dfcdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190628217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.190628217
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3146809657
Short name T526
Test name
Test status
Simulation time 33041399455 ps
CPU time 14.76 seconds
Started Jul 15 04:34:16 PM PDT 24
Finished Jul 15 04:34:32 PM PDT 24
Peak memory 199792 kb
Host smart-2885511a-56c2-4a2a-80a0-e7317a45cade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146809657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3146809657
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.986084869
Short name T1065
Test name
Test status
Simulation time 67290115014 ps
CPU time 88.52 seconds
Started Jul 15 04:34:13 PM PDT 24
Finished Jul 15 04:35:43 PM PDT 24
Peak memory 199732 kb
Host smart-93e4f4be-6191-425f-ad2e-bd28916dcf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986084869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.986084869
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2604575307
Short name T857
Test name
Test status
Simulation time 15809244589 ps
CPU time 12.93 seconds
Started Jul 15 04:34:13 PM PDT 24
Finished Jul 15 04:34:27 PM PDT 24
Peak memory 199660 kb
Host smart-7bae13fe-e680-4135-8375-5245e7ddfa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604575307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2604575307
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2435317309
Short name T187
Test name
Test status
Simulation time 31956642405 ps
CPU time 13.54 seconds
Started Jul 15 04:34:16 PM PDT 24
Finished Jul 15 04:34:31 PM PDT 24
Peak memory 199012 kb
Host smart-497e6f27-ce91-49f8-a774-e3a57f781e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435317309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2435317309
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.279539313
Short name T61
Test name
Test status
Simulation time 12112936 ps
CPU time 0.56 seconds
Started Jul 15 04:31:06 PM PDT 24
Finished Jul 15 04:31:08 PM PDT 24
Peak memory 195308 kb
Host smart-19b86671-3fcc-41f4-98a8-2b01854d3b87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279539313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.279539313
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3119286163
Short name T96
Test name
Test status
Simulation time 201665560909 ps
CPU time 125.16 seconds
Started Jul 15 04:30:59 PM PDT 24
Finished Jul 15 04:33:05 PM PDT 24
Peak memory 199608 kb
Host smart-adaea597-0784-4890-b0e4-424031e8ed10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119286163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3119286163
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2698927213
Short name T854
Test name
Test status
Simulation time 169288651622 ps
CPU time 110.78 seconds
Started Jul 15 04:30:59 PM PDT 24
Finished Jul 15 04:32:50 PM PDT 24
Peak memory 199732 kb
Host smart-7607728d-577f-49b9-965b-5b556b0a220a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698927213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2698927213
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.403825220
Short name T995
Test name
Test status
Simulation time 11575591298 ps
CPU time 11.2 seconds
Started Jul 15 04:30:59 PM PDT 24
Finished Jul 15 04:31:11 PM PDT 24
Peak memory 199692 kb
Host smart-2954e2af-18df-4eec-92c2-8387435be5ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403825220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.403825220
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1252736297
Short name T1018
Test name
Test status
Simulation time 85494654968 ps
CPU time 569.39 seconds
Started Jul 15 04:31:07 PM PDT 24
Finished Jul 15 04:40:38 PM PDT 24
Peak memory 199752 kb
Host smart-36834576-e365-4e54-b8ce-4fbd07063bb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252736297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1252736297
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1889593591
Short name T1092
Test name
Test status
Simulation time 8355016046 ps
CPU time 14.99 seconds
Started Jul 15 04:30:59 PM PDT 24
Finished Jul 15 04:31:15 PM PDT 24
Peak memory 199624 kb
Host smart-61d9627a-8fff-4070-ba78-55427e0e9b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889593591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1889593591
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3594174787
Short name T97
Test name
Test status
Simulation time 42650397699 ps
CPU time 49.31 seconds
Started Jul 15 04:30:59 PM PDT 24
Finished Jul 15 04:31:49 PM PDT 24
Peak memory 198788 kb
Host smart-e6db79b3-2589-442d-9f4d-5ccbac387898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594174787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3594174787
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1721910992
Short name T588
Test name
Test status
Simulation time 16896745889 ps
CPU time 122.73 seconds
Started Jul 15 04:31:00 PM PDT 24
Finished Jul 15 04:33:04 PM PDT 24
Peak memory 199772 kb
Host smart-6d257b91-89f1-4604-9fc2-c62e71356af2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1721910992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1721910992
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.482255769
Short name T475
Test name
Test status
Simulation time 8159040958 ps
CPU time 60.04 seconds
Started Jul 15 04:30:58 PM PDT 24
Finished Jul 15 04:31:59 PM PDT 24
Peak memory 197968 kb
Host smart-0863ffd7-3ed4-4ef3-8841-6fc4e6b3627a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482255769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.482255769
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3266331823
Short name T761
Test name
Test status
Simulation time 43161572828 ps
CPU time 61.8 seconds
Started Jul 15 04:31:06 PM PDT 24
Finished Jul 15 04:32:08 PM PDT 24
Peak memory 199740 kb
Host smart-1b064cfe-fa62-4d80-8329-7ce8e8589458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266331823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3266331823
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3560692942
Short name T963
Test name
Test status
Simulation time 55901991238 ps
CPU time 72.86 seconds
Started Jul 15 04:30:59 PM PDT 24
Finished Jul 15 04:32:13 PM PDT 24
Peak memory 195880 kb
Host smart-dfdb4840-3f8d-44c3-80d6-d48d6c2eb6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560692942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3560692942
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.354962066
Short name T775
Test name
Test status
Simulation time 6292333517 ps
CPU time 14.96 seconds
Started Jul 15 04:31:00 PM PDT 24
Finished Jul 15 04:31:16 PM PDT 24
Peak memory 199644 kb
Host smart-8ea11c9a-ba3b-412c-9581-d6cdf25af008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354962066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.354962066
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2685524963
Short name T917
Test name
Test status
Simulation time 241221646008 ps
CPU time 426.99 seconds
Started Jul 15 04:31:07 PM PDT 24
Finished Jul 15 04:38:15 PM PDT 24
Peak memory 216280 kb
Host smart-158c265e-b25b-4800-b644-f15570a69243
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685524963 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2685524963
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.857508868
Short name T1123
Test name
Test status
Simulation time 781199375 ps
CPU time 3.19 seconds
Started Jul 15 04:31:01 PM PDT 24
Finished Jul 15 04:31:04 PM PDT 24
Peak memory 198708 kb
Host smart-0466be7a-1429-40c5-87f8-4228ac1cdeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857508868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.857508868
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2335885919
Short name T419
Test name
Test status
Simulation time 51779912387 ps
CPU time 32.24 seconds
Started Jul 15 04:31:00 PM PDT 24
Finished Jul 15 04:31:33 PM PDT 24
Peak memory 199840 kb
Host smart-338bcabf-d3a8-4fb8-8679-77ebcef41c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335885919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2335885919
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3750486474
Short name T407
Test name
Test status
Simulation time 40357958016 ps
CPU time 15.89 seconds
Started Jul 15 04:34:15 PM PDT 24
Finished Jul 15 04:34:33 PM PDT 24
Peak memory 199828 kb
Host smart-fa7690f0-f87e-44e3-8c04-26f4ed7d443a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750486474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3750486474
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1621231509
Short name T897
Test name
Test status
Simulation time 18924038634 ps
CPU time 7.62 seconds
Started Jul 15 04:34:13 PM PDT 24
Finished Jul 15 04:34:22 PM PDT 24
Peak memory 199796 kb
Host smart-c8f1bc0c-e259-4caf-82ed-e57d69762a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621231509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1621231509
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.4056674298
Short name T655
Test name
Test status
Simulation time 9952438874 ps
CPU time 17.05 seconds
Started Jul 15 04:34:15 PM PDT 24
Finished Jul 15 04:34:33 PM PDT 24
Peak memory 199736 kb
Host smart-ab768f42-34c9-4bd7-b9a2-be6355798be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056674298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.4056674298
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3850398153
Short name T778
Test name
Test status
Simulation time 137075247749 ps
CPU time 59 seconds
Started Jul 15 04:34:16 PM PDT 24
Finished Jul 15 04:35:16 PM PDT 24
Peak memory 199748 kb
Host smart-88a76acb-8972-4adf-bd44-ca6f2962b9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850398153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3850398153
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1459089024
Short name T754
Test name
Test status
Simulation time 19481752669 ps
CPU time 12.87 seconds
Started Jul 15 04:34:12 PM PDT 24
Finished Jul 15 04:34:26 PM PDT 24
Peak memory 199744 kb
Host smart-f5b0b331-0815-48f2-ab99-f6e046f37119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459089024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1459089024
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3532191074
Short name T958
Test name
Test status
Simulation time 108876432725 ps
CPU time 51.17 seconds
Started Jul 15 04:34:16 PM PDT 24
Finished Jul 15 04:35:09 PM PDT 24
Peak memory 199652 kb
Host smart-0e9519e4-4fc5-46e1-a51a-6c1c23d6a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532191074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3532191074
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3394787843
Short name T800
Test name
Test status
Simulation time 65764913727 ps
CPU time 11.3 seconds
Started Jul 15 04:34:21 PM PDT 24
Finished Jul 15 04:34:33 PM PDT 24
Peak memory 199680 kb
Host smart-44e2c705-842a-479c-81ff-3aefe71b97a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394787843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3394787843
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2591475321
Short name T832
Test name
Test status
Simulation time 39651898262 ps
CPU time 17.86 seconds
Started Jul 15 04:34:24 PM PDT 24
Finished Jul 15 04:34:44 PM PDT 24
Peak memory 199680 kb
Host smart-fb2c2718-b444-4d97-a29a-8c695a266289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591475321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2591475321
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2287753664
Short name T1103
Test name
Test status
Simulation time 238918414951 ps
CPU time 167.39 seconds
Started Jul 15 04:34:25 PM PDT 24
Finished Jul 15 04:37:14 PM PDT 24
Peak memory 199728 kb
Host smart-5d2b80c5-1d69-472e-8ece-b38332ddb20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287753664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2287753664
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3340131704
Short name T355
Test name
Test status
Simulation time 44907490 ps
CPU time 0.56 seconds
Started Jul 15 04:31:07 PM PDT 24
Finished Jul 15 04:31:10 PM PDT 24
Peak memory 195096 kb
Host smart-6310ec37-67e1-4a2f-afea-f2de552d7089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340131704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3340131704
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.923248780
Short name T575
Test name
Test status
Simulation time 23513608970 ps
CPU time 33.78 seconds
Started Jul 15 04:31:07 PM PDT 24
Finished Jul 15 04:31:43 PM PDT 24
Peak memory 199728 kb
Host smart-98bfbfb0-74ae-49eb-9e89-292ef90047e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923248780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.923248780
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.267026378
Short name T680
Test name
Test status
Simulation time 28017399498 ps
CPU time 20.59 seconds
Started Jul 15 04:31:08 PM PDT 24
Finished Jul 15 04:31:31 PM PDT 24
Peak memory 199680 kb
Host smart-30052191-3dcf-496c-a1b0-537d18acdc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267026378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.267026378
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.2520165038
Short name T56
Test name
Test status
Simulation time 73691967952 ps
CPU time 37.71 seconds
Started Jul 15 04:31:08 PM PDT 24
Finished Jul 15 04:31:48 PM PDT 24
Peak memory 199336 kb
Host smart-da08e03b-7ec6-41ad-9446-21a2c30c45c4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520165038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2520165038
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_loopback.1773527548
Short name T1131
Test name
Test status
Simulation time 8856315663 ps
CPU time 14.53 seconds
Started Jul 15 04:31:07 PM PDT 24
Finished Jul 15 04:31:23 PM PDT 24
Peak memory 198624 kb
Host smart-cf72d399-119c-4c5e-999e-2c1dc781ce11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773527548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1773527548
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2316076769
Short name T953
Test name
Test status
Simulation time 77581539149 ps
CPU time 113.59 seconds
Started Jul 15 04:31:07 PM PDT 24
Finished Jul 15 04:33:02 PM PDT 24
Peak memory 199912 kb
Host smart-7cb7c53d-1636-4a16-8f6f-51fbf54acc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316076769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2316076769
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2360523342
Short name T357
Test name
Test status
Simulation time 9121124031 ps
CPU time 558.01 seconds
Started Jul 15 04:31:06 PM PDT 24
Finished Jul 15 04:40:26 PM PDT 24
Peak memory 199748 kb
Host smart-cd841c01-f268-491b-8e36-610a60359125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360523342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2360523342
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1938922086
Short name T452
Test name
Test status
Simulation time 7333102681 ps
CPU time 42.64 seconds
Started Jul 15 04:31:07 PM PDT 24
Finished Jul 15 04:31:50 PM PDT 24
Peak memory 198816 kb
Host smart-fe0a315d-e45a-4d30-816c-25500f9ca8d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938922086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1938922086
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1460314638
Short name T564
Test name
Test status
Simulation time 58716903001 ps
CPU time 24.51 seconds
Started Jul 15 04:31:08 PM PDT 24
Finished Jul 15 04:31:35 PM PDT 24
Peak memory 199784 kb
Host smart-d890544e-3ed3-4a30-a757-cc99327d0127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460314638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1460314638
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3525249804
Short name T434
Test name
Test status
Simulation time 31552522954 ps
CPU time 19.75 seconds
Started Jul 15 04:31:08 PM PDT 24
Finished Jul 15 04:31:30 PM PDT 24
Peak memory 196252 kb
Host smart-890c78ab-cd7c-4cdd-91b7-c57e3159f7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525249804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3525249804
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.6122789
Short name T973
Test name
Test status
Simulation time 658191925 ps
CPU time 1.56 seconds
Started Jul 15 04:31:07 PM PDT 24
Finished Jul 15 04:31:10 PM PDT 24
Peak memory 199496 kb
Host smart-a0fe609b-1b2d-4440-a846-94e9926b2894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6122789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.6122789
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.735764082
Short name T741
Test name
Test status
Simulation time 177323706329 ps
CPU time 1084.29 seconds
Started Jul 15 04:31:08 PM PDT 24
Finished Jul 15 04:49:15 PM PDT 24
Peak memory 199660 kb
Host smart-0ec31fb6-7927-44e9-979a-36f5683e4870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735764082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.735764082
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3044779580
Short name T584
Test name
Test status
Simulation time 58853933858 ps
CPU time 497.38 seconds
Started Jul 15 04:31:08 PM PDT 24
Finished Jul 15 04:39:28 PM PDT 24
Peak memory 215752 kb
Host smart-2345a54b-c9d5-4056-b702-3d5e0a52e382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044779580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3044779580
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2007901414
Short name T1158
Test name
Test status
Simulation time 823223758 ps
CPU time 1.9 seconds
Started Jul 15 04:31:07 PM PDT 24
Finished Jul 15 04:31:11 PM PDT 24
Peak memory 199580 kb
Host smart-8bca0ed2-227d-4970-88f3-caa746348a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007901414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2007901414
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2135520943
Short name T744
Test name
Test status
Simulation time 24995037669 ps
CPU time 33.53 seconds
Started Jul 15 04:31:07 PM PDT 24
Finished Jul 15 04:31:43 PM PDT 24
Peak memory 199712 kb
Host smart-358ec638-f775-4447-8f6f-a2919ceae95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135520943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2135520943
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3785958046
Short name T708
Test name
Test status
Simulation time 122581720875 ps
CPU time 29.99 seconds
Started Jul 15 04:34:23 PM PDT 24
Finished Jul 15 04:34:54 PM PDT 24
Peak memory 199768 kb
Host smart-56123c3e-c1a4-4b0d-a52a-23e18cb1eaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785958046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3785958046
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3672846751
Short name T513
Test name
Test status
Simulation time 99252825738 ps
CPU time 116.5 seconds
Started Jul 15 04:34:24 PM PDT 24
Finished Jul 15 04:36:21 PM PDT 24
Peak memory 199708 kb
Host smart-71b38bce-8283-4d13-ae64-34961fd81016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672846751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3672846751
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.4139360463
Short name T370
Test name
Test status
Simulation time 23217949995 ps
CPU time 20.47 seconds
Started Jul 15 04:34:26 PM PDT 24
Finished Jul 15 04:34:48 PM PDT 24
Peak memory 199708 kb
Host smart-2fe2ed2e-7089-496b-90b7-92b33e07ce0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139360463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.4139360463
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1671749513
Short name T516
Test name
Test status
Simulation time 62482986603 ps
CPU time 25.59 seconds
Started Jul 15 04:34:23 PM PDT 24
Finished Jul 15 04:34:49 PM PDT 24
Peak memory 199472 kb
Host smart-19c11287-7b48-4ffc-b5c1-42bd03fd4e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671749513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1671749513
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3101201611
Short name T148
Test name
Test status
Simulation time 23885312708 ps
CPU time 23.06 seconds
Started Jul 15 04:34:20 PM PDT 24
Finished Jul 15 04:34:44 PM PDT 24
Peak memory 199704 kb
Host smart-3c3ec41d-7af2-47cb-bf32-121a51fb9664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101201611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3101201611
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1493425501
Short name T1174
Test name
Test status
Simulation time 29214701496 ps
CPU time 43.85 seconds
Started Jul 15 04:34:22 PM PDT 24
Finished Jul 15 04:35:07 PM PDT 24
Peak memory 199728 kb
Host smart-ccadbbfd-511a-4bb7-a2aa-74e6eb3b5f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493425501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1493425501
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1716303911
Short name T418
Test name
Test status
Simulation time 61524721583 ps
CPU time 24.46 seconds
Started Jul 15 04:34:23 PM PDT 24
Finished Jul 15 04:34:48 PM PDT 24
Peak memory 199728 kb
Host smart-caec327b-618b-4ee8-a053-f79cc3ef1bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716303911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1716303911
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.516331919
Short name T1101
Test name
Test status
Simulation time 20647830055 ps
CPU time 20.5 seconds
Started Jul 15 04:34:24 PM PDT 24
Finished Jul 15 04:34:47 PM PDT 24
Peak memory 199776 kb
Host smart-6933448d-2d4b-4f08-8bc2-b12948d87920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516331919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.516331919
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3244790043
Short name T1157
Test name
Test status
Simulation time 130443346233 ps
CPU time 45.12 seconds
Started Jul 15 04:34:24 PM PDT 24
Finished Jul 15 04:35:11 PM PDT 24
Peak memory 199440 kb
Host smart-83bb8d85-24e0-4e6f-81bd-e1f5e56a8bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244790043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3244790043
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.49251160
Short name T612
Test name
Test status
Simulation time 51369444 ps
CPU time 0.54 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:31:18 PM PDT 24
Peak memory 195088 kb
Host smart-e8e93adf-26ac-468e-9757-2d99aca92d9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49251160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.49251160
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3893630119
Short name T459
Test name
Test status
Simulation time 41748390228 ps
CPU time 15.65 seconds
Started Jul 15 04:31:16 PM PDT 24
Finished Jul 15 04:31:33 PM PDT 24
Peak memory 199824 kb
Host smart-907fec15-47d6-4e4c-894b-15494e2eca7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893630119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3893630119
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3325504847
Short name T1113
Test name
Test status
Simulation time 32589315485 ps
CPU time 42.09 seconds
Started Jul 15 04:31:14 PM PDT 24
Finished Jul 15 04:31:57 PM PDT 24
Peak memory 199648 kb
Host smart-b643dbb1-4b17-499c-a626-ce884f319c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325504847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3325504847
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.4169584762
Short name T15
Test name
Test status
Simulation time 22067192216 ps
CPU time 18.35 seconds
Started Jul 15 04:31:14 PM PDT 24
Finished Jul 15 04:31:35 PM PDT 24
Peak memory 197784 kb
Host smart-ffd99757-8bd6-44d3-af7a-3647732fae82
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169584762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.4169584762
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1251813365
Short name T1114
Test name
Test status
Simulation time 110841765860 ps
CPU time 978.49 seconds
Started Jul 15 04:31:12 PM PDT 24
Finished Jul 15 04:47:32 PM PDT 24
Peak memory 199752 kb
Host smart-62409c88-25ea-4614-9f79-4c6f302ce50d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1251813365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1251813365
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3834422730
Short name T522
Test name
Test status
Simulation time 4477811579 ps
CPU time 3.51 seconds
Started Jul 15 04:31:16 PM PDT 24
Finished Jul 15 04:31:21 PM PDT 24
Peak memory 199736 kb
Host smart-83bccbf3-7aee-4888-b30d-3dadd2847d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834422730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3834422730
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2483255539
Short name T717
Test name
Test status
Simulation time 91011617422 ps
CPU time 35.43 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:31:52 PM PDT 24
Peak memory 200340 kb
Host smart-1006046e-2b93-4260-bcb5-0ac1bfdbe7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483255539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2483255539
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3216431481
Short name T915
Test name
Test status
Simulation time 17430623821 ps
CPU time 351.46 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:37:08 PM PDT 24
Peak memory 199752 kb
Host smart-712fe503-e3db-447b-84db-8fd7bee15f20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216431481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3216431481
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2128843990
Short name T532
Test name
Test status
Simulation time 6049939462 ps
CPU time 11.65 seconds
Started Jul 15 04:31:16 PM PDT 24
Finished Jul 15 04:31:30 PM PDT 24
Peak memory 197864 kb
Host smart-4cc64496-7303-4273-9606-583d6f4b381b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128843990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2128843990
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2649337827
Short name T269
Test name
Test status
Simulation time 151738600892 ps
CPU time 79.25 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:32:36 PM PDT 24
Peak memory 199756 kb
Host smart-68522432-1e61-4dd1-ab28-9a00dcd36b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649337827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2649337827
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.304463811
Short name T346
Test name
Test status
Simulation time 776970167 ps
CPU time 1.27 seconds
Started Jul 15 04:31:13 PM PDT 24
Finished Jul 15 04:31:16 PM PDT 24
Peak memory 195288 kb
Host smart-fd005836-340f-49ab-8708-1f9a779ce176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304463811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.304463811
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2010447811
Short name T1098
Test name
Test status
Simulation time 6172997225 ps
CPU time 8.82 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:31:25 PM PDT 24
Peak memory 199148 kb
Host smart-ec5460d1-6e7f-4aba-94ea-4a8786a29981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010447811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2010447811
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.295093450
Short name T711
Test name
Test status
Simulation time 319346908240 ps
CPU time 92.94 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:32:50 PM PDT 24
Peak memory 208100 kb
Host smart-367147fb-c58d-4cc6-88e9-05944196d31e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295093450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.295093450
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1271885070
Short name T451
Test name
Test status
Simulation time 419665683 ps
CPU time 1.57 seconds
Started Jul 15 04:31:16 PM PDT 24
Finished Jul 15 04:31:19 PM PDT 24
Peak memory 198376 kb
Host smart-371f646a-a985-4397-bcf9-96eeb31aab59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271885070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1271885070
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2170434621
Short name T242
Test name
Test status
Simulation time 130690816908 ps
CPU time 15.92 seconds
Started Jul 15 04:31:14 PM PDT 24
Finished Jul 15 04:31:31 PM PDT 24
Peak memory 199708 kb
Host smart-b59bec67-3eda-4fb1-8e02-2fe70f388419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170434621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2170434621
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.4149891521
Short name T591
Test name
Test status
Simulation time 41663830438 ps
CPU time 30.24 seconds
Started Jul 15 04:34:26 PM PDT 24
Finished Jul 15 04:34:58 PM PDT 24
Peak memory 199332 kb
Host smart-c1ac3bfa-d28b-4480-882a-4e4ef5a6c9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149891521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.4149891521
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.995376001
Short name T1146
Test name
Test status
Simulation time 11415324087 ps
CPU time 15.97 seconds
Started Jul 15 04:34:23 PM PDT 24
Finished Jul 15 04:34:40 PM PDT 24
Peak memory 199768 kb
Host smart-0b5897d5-fea9-4f9a-95ef-bf6a2a29469f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995376001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.995376001
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2549076308
Short name T201
Test name
Test status
Simulation time 71256899372 ps
CPU time 105.38 seconds
Started Jul 15 04:34:21 PM PDT 24
Finished Jul 15 04:36:07 PM PDT 24
Peak memory 199712 kb
Host smart-769e327c-4386-4f19-b8b9-433fbe5a702b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549076308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2549076308
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2157488747
Short name T718
Test name
Test status
Simulation time 57171273323 ps
CPU time 77.89 seconds
Started Jul 15 04:34:23 PM PDT 24
Finished Jul 15 04:35:42 PM PDT 24
Peak memory 199708 kb
Host smart-8ea7e278-e98c-4faa-808e-9f2306f2f7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157488747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2157488747
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.760121330
Short name T207
Test name
Test status
Simulation time 39823851298 ps
CPU time 19.38 seconds
Started Jul 15 04:34:25 PM PDT 24
Finished Jul 15 04:34:47 PM PDT 24
Peak memory 199724 kb
Host smart-45d536a2-943e-4c6d-bcad-37c1fa57ba24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760121330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.760121330
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3688377910
Short name T985
Test name
Test status
Simulation time 21841082536 ps
CPU time 37.6 seconds
Started Jul 15 04:34:24 PM PDT 24
Finished Jul 15 04:35:03 PM PDT 24
Peak memory 199704 kb
Host smart-4a0bc6b9-20ff-4eae-a5fb-869b2bd8bcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688377910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3688377910
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3922106432
Short name T730
Test name
Test status
Simulation time 47466017408 ps
CPU time 19.46 seconds
Started Jul 15 04:34:21 PM PDT 24
Finished Jul 15 04:34:41 PM PDT 24
Peak memory 199588 kb
Host smart-0dd72d4e-1a10-4e3d-9c3f-f3a112048523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922106432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3922106432
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.814474531
Short name T31
Test name
Test status
Simulation time 10679416196 ps
CPU time 15.76 seconds
Started Jul 15 04:34:24 PM PDT 24
Finished Jul 15 04:34:42 PM PDT 24
Peak memory 199608 kb
Host smart-c8a279fe-abfb-4e8e-9a33-9ee72fcce2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814474531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.814474531
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2385306270
Short name T1011
Test name
Test status
Simulation time 12901322218 ps
CPU time 20.06 seconds
Started Jul 15 04:34:22 PM PDT 24
Finished Jul 15 04:34:43 PM PDT 24
Peak memory 199668 kb
Host smart-fb9e9ea5-ddf2-4b49-9c79-34e273add29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385306270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2385306270
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3590401285
Short name T228
Test name
Test status
Simulation time 90807980595 ps
CPU time 35.88 seconds
Started Jul 15 04:34:24 PM PDT 24
Finished Jul 15 04:35:01 PM PDT 24
Peak memory 199748 kb
Host smart-9f83cc41-a1e8-4683-8fc3-f0744f956b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590401285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3590401285
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.210091072
Short name T898
Test name
Test status
Simulation time 35419800 ps
CPU time 0.55 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:31:18 PM PDT 24
Peak memory 195144 kb
Host smart-757ccd05-f112-4dc7-a38d-9ea3f87ee89f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210091072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.210091072
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1564712986
Short name T1048
Test name
Test status
Simulation time 103130705426 ps
CPU time 44.29 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:32:01 PM PDT 24
Peak memory 199708 kb
Host smart-96fe574e-cf17-40e2-92aa-d27c2b0d5a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564712986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1564712986
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1908837098
Short name T162
Test name
Test status
Simulation time 171558821540 ps
CPU time 29.78 seconds
Started Jul 15 04:31:14 PM PDT 24
Finished Jul 15 04:31:45 PM PDT 24
Peak memory 199752 kb
Host smart-9afa5a0e-bc2b-4506-85ee-8d6157dce414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908837098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1908837098
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1471856853
Short name T763
Test name
Test status
Simulation time 42591917674 ps
CPU time 61.34 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:32:18 PM PDT 24
Peak memory 199324 kb
Host smart-e9c9660b-7269-4f4c-8915-5674c94a6b0f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471856853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1471856853
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2721591338
Short name T833
Test name
Test status
Simulation time 132746915433 ps
CPU time 390.55 seconds
Started Jul 15 04:31:16 PM PDT 24
Finished Jul 15 04:37:48 PM PDT 24
Peak memory 199676 kb
Host smart-435536d4-8cff-4346-9e5f-499d05a4889c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721591338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2721591338
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1192497910
Short name T716
Test name
Test status
Simulation time 12825361792 ps
CPU time 13.21 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:31:30 PM PDT 24
Peak memory 199696 kb
Host smart-5b256c06-a566-4182-8da6-4b0d313dae82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192497910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1192497910
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2075418073
Short name T116
Test name
Test status
Simulation time 34955847347 ps
CPU time 14.06 seconds
Started Jul 15 04:31:13 PM PDT 24
Finished Jul 15 04:31:29 PM PDT 24
Peak memory 198028 kb
Host smart-7807df4f-7d37-4dcb-af81-cab5ddb93f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075418073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2075418073
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2187129815
Short name T611
Test name
Test status
Simulation time 11187226020 ps
CPU time 141.34 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:33:38 PM PDT 24
Peak memory 199724 kb
Host smart-2b60760e-a6c7-4df1-a529-59d5d84cd421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187129815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2187129815
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3370588463
Short name T618
Test name
Test status
Simulation time 3062545792 ps
CPU time 22.39 seconds
Started Jul 15 04:31:16 PM PDT 24
Finished Jul 15 04:31:40 PM PDT 24
Peak memory 197956 kb
Host smart-abdab485-ee37-4814-8565-d222095cf2ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370588463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3370588463
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.806390637
Short name T628
Test name
Test status
Simulation time 50023686161 ps
CPU time 53.63 seconds
Started Jul 15 04:31:16 PM PDT 24
Finished Jul 15 04:32:11 PM PDT 24
Peak memory 199704 kb
Host smart-ed60f112-9da0-4237-9629-aab73de26ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806390637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.806390637
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1258669680
Short name T1002
Test name
Test status
Simulation time 71287109586 ps
CPU time 25.54 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:31:43 PM PDT 24
Peak memory 195872 kb
Host smart-6685cc9a-92bc-4715-85a0-faf0b603dba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258669680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1258669680
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1489025869
Short name T626
Test name
Test status
Simulation time 5884700528 ps
CPU time 17.52 seconds
Started Jul 15 04:31:14 PM PDT 24
Finished Jul 15 04:31:34 PM PDT 24
Peak memory 199772 kb
Host smart-1c23e38c-ca38-4a4d-881c-b22219f2898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489025869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1489025869
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2010093012
Short name T916
Test name
Test status
Simulation time 113361232811 ps
CPU time 300.11 seconds
Started Jul 15 04:31:15 PM PDT 24
Finished Jul 15 04:36:17 PM PDT 24
Peak memory 199792 kb
Host smart-e35f4aeb-baf6-4dd4-865c-0d1536174537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010093012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2010093012
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2146587448
Short name T693
Test name
Test status
Simulation time 171632300778 ps
CPU time 171.58 seconds
Started Jul 15 04:31:19 PM PDT 24
Finished Jul 15 04:34:11 PM PDT 24
Peak memory 216516 kb
Host smart-88773616-3115-4817-8035-380eb87ae796
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146587448 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2146587448
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1266958467
Short name T1165
Test name
Test status
Simulation time 7502089291 ps
CPU time 7.51 seconds
Started Jul 15 04:31:14 PM PDT 24
Finished Jul 15 04:31:23 PM PDT 24
Peak memory 199652 kb
Host smart-99a04ba8-57c3-4a8a-b0f9-c59d3b8c3254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266958467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1266958467
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2799368054
Short name T2
Test name
Test status
Simulation time 28124462841 ps
CPU time 11.52 seconds
Started Jul 15 04:31:14 PM PDT 24
Finished Jul 15 04:31:28 PM PDT 24
Peak memory 199488 kb
Host smart-ad59dbf2-68a3-4683-8389-de76d91bb876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799368054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2799368054
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1828024860
Short name T300
Test name
Test status
Simulation time 29239177777 ps
CPU time 8.53 seconds
Started Jul 15 04:34:24 PM PDT 24
Finished Jul 15 04:34:33 PM PDT 24
Peak memory 199716 kb
Host smart-a017d3d0-b227-4987-bfaa-bf344aabf862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828024860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1828024860
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2577356802
Short name T972
Test name
Test status
Simulation time 125637170288 ps
CPU time 49.92 seconds
Started Jul 15 04:34:24 PM PDT 24
Finished Jul 15 04:35:16 PM PDT 24
Peak memory 199664 kb
Host smart-1232c2f1-c129-4d10-b23b-15fd2c7891f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577356802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2577356802
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1651404888
Short name T791
Test name
Test status
Simulation time 55914510383 ps
CPU time 84.61 seconds
Started Jul 15 04:34:25 PM PDT 24
Finished Jul 15 04:35:51 PM PDT 24
Peak memory 199824 kb
Host smart-6948de00-6462-4c91-93a2-08d4ddcb077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651404888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1651404888
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.4217024031
Short name T812
Test name
Test status
Simulation time 194980885906 ps
CPU time 26.57 seconds
Started Jul 15 04:34:22 PM PDT 24
Finished Jul 15 04:34:49 PM PDT 24
Peak memory 199680 kb
Host smart-3ebad242-d347-483b-8c21-87c96f9f0898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217024031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4217024031
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.4209303035
Short name T900
Test name
Test status
Simulation time 22346969725 ps
CPU time 17.79 seconds
Started Jul 15 04:34:23 PM PDT 24
Finished Jul 15 04:34:41 PM PDT 24
Peak memory 199836 kb
Host smart-6be5c494-7e2a-4cc4-ba81-894758142909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209303035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.4209303035
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3799746514
Short name T405
Test name
Test status
Simulation time 121359064080 ps
CPU time 21.11 seconds
Started Jul 15 04:34:25 PM PDT 24
Finished Jul 15 04:34:48 PM PDT 24
Peak memory 199728 kb
Host smart-cd4079c7-4036-4c46-ba83-b4f3ea8b5ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799746514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3799746514
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2413750511
Short name T689
Test name
Test status
Simulation time 12422470 ps
CPU time 0.55 seconds
Started Jul 15 04:31:20 PM PDT 24
Finished Jul 15 04:31:22 PM PDT 24
Peak memory 195192 kb
Host smart-17b0e0ce-aa99-4faa-b554-5d5864b8526d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413750511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2413750511
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1964987258
Short name T146
Test name
Test status
Simulation time 17618782696 ps
CPU time 7.92 seconds
Started Jul 15 04:31:16 PM PDT 24
Finished Jul 15 04:31:26 PM PDT 24
Peak memory 199696 kb
Host smart-8218c09b-e902-4a1c-ba3f-e4fb9e9dc738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964987258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1964987258
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.4020272094
Short name T724
Test name
Test status
Simulation time 94534856964 ps
CPU time 124.49 seconds
Started Jul 15 04:31:28 PM PDT 24
Finished Jul 15 04:33:34 PM PDT 24
Peak memory 199728 kb
Host smart-b58bcfc5-f99b-4657-b2e2-0d2dc2238dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020272094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.4020272094
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1856101811
Short name T276
Test name
Test status
Simulation time 18930342453 ps
CPU time 30.5 seconds
Started Jul 15 04:31:21 PM PDT 24
Finished Jul 15 04:31:52 PM PDT 24
Peak memory 199736 kb
Host smart-42b0ec5a-3c84-4173-889e-f6c2850b20bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856101811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1856101811
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.439271278
Short name T1152
Test name
Test status
Simulation time 39874342575 ps
CPU time 48.27 seconds
Started Jul 15 04:31:21 PM PDT 24
Finished Jul 15 04:32:10 PM PDT 24
Peak memory 199732 kb
Host smart-c55d3772-d300-4ba6-a69c-6c1297b6521b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439271278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.439271278
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1780940302
Short name T629
Test name
Test status
Simulation time 277667317303 ps
CPU time 226.67 seconds
Started Jul 15 04:31:22 PM PDT 24
Finished Jul 15 04:35:09 PM PDT 24
Peak memory 199740 kb
Host smart-b672f48a-3a4a-4204-ba33-4cb48a7eaccb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780940302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1780940302
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1506769328
Short name T733
Test name
Test status
Simulation time 8711516987 ps
CPU time 11.44 seconds
Started Jul 15 04:31:22 PM PDT 24
Finished Jul 15 04:31:34 PM PDT 24
Peak memory 198476 kb
Host smart-2ad5fd8c-37b1-4e14-9dd8-0f617515ac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506769328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1506769328
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3380292577
Short name T261
Test name
Test status
Simulation time 120060912774 ps
CPU time 102.2 seconds
Started Jul 15 04:31:21 PM PDT 24
Finished Jul 15 04:33:05 PM PDT 24
Peak memory 199940 kb
Host smart-120fd690-f353-4864-9d0c-5d697afe04cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380292577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3380292577
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1846076596
Short name T241
Test name
Test status
Simulation time 11340540738 ps
CPU time 338.16 seconds
Started Jul 15 04:31:22 PM PDT 24
Finished Jul 15 04:37:01 PM PDT 24
Peak memory 199664 kb
Host smart-3b2ea570-43c2-4887-99f4-0d4903ff3baf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1846076596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1846076596
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3971669764
Short name T1166
Test name
Test status
Simulation time 6010414908 ps
CPU time 15.09 seconds
Started Jul 15 04:31:21 PM PDT 24
Finished Jul 15 04:31:37 PM PDT 24
Peak memory 197972 kb
Host smart-9bcbdd83-47f6-4486-8bed-b55c892064a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971669764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3971669764
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3899395732
Short name T354
Test name
Test status
Simulation time 58517494824 ps
CPU time 32.33 seconds
Started Jul 15 04:31:21 PM PDT 24
Finished Jul 15 04:31:55 PM PDT 24
Peak memory 199624 kb
Host smart-5a32e56b-c3d0-4a37-8b97-d27d6c8570a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899395732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3899395732
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.4230529513
Short name T257
Test name
Test status
Simulation time 1747327088 ps
CPU time 1.19 seconds
Started Jul 15 04:31:20 PM PDT 24
Finished Jul 15 04:31:22 PM PDT 24
Peak memory 195456 kb
Host smart-0a8a8fc2-574b-4fd2-a86c-34fcd63cb318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230529513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.4230529513
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.434749771
Short name T258
Test name
Test status
Simulation time 6269874582 ps
CPU time 11.11 seconds
Started Jul 15 04:31:14 PM PDT 24
Finished Jul 15 04:31:26 PM PDT 24
Peak memory 199748 kb
Host smart-f2f2ed1f-babb-4a79-b266-2063c8961d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434749771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.434749771
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.573139194
Short name T822
Test name
Test status
Simulation time 203830861209 ps
CPU time 977.72 seconds
Started Jul 15 04:31:26 PM PDT 24
Finished Jul 15 04:47:46 PM PDT 24
Peak memory 199700 kb
Host smart-669e78db-d240-4b20-8283-80b68dee40c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573139194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.573139194
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3066524058
Short name T990
Test name
Test status
Simulation time 58245799223 ps
CPU time 819.68 seconds
Started Jul 15 04:31:25 PM PDT 24
Finished Jul 15 04:45:07 PM PDT 24
Peak memory 216496 kb
Host smart-bf162f87-df1d-467a-a124-54ac60afb59b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066524058 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3066524058
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2421774894
Short name T986
Test name
Test status
Simulation time 898891477 ps
CPU time 2.92 seconds
Started Jul 15 04:31:20 PM PDT 24
Finished Jul 15 04:31:24 PM PDT 24
Peak memory 199704 kb
Host smart-74857ecc-13dc-4068-bf2c-cabe92046d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421774894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2421774894
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3179323123
Short name T884
Test name
Test status
Simulation time 69625897203 ps
CPU time 33.09 seconds
Started Jul 15 04:31:14 PM PDT 24
Finished Jul 15 04:31:49 PM PDT 24
Peak memory 199772 kb
Host smart-3c495c3f-e4ec-4802-b73e-1db457ef5499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179323123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3179323123
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2448786335
Short name T1077
Test name
Test status
Simulation time 156848961302 ps
CPU time 180.95 seconds
Started Jul 15 04:34:23 PM PDT 24
Finished Jul 15 04:37:26 PM PDT 24
Peak memory 199768 kb
Host smart-fa4d7621-85e7-4766-b32a-c6e92a3cacee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448786335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2448786335
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.947546002
Short name T808
Test name
Test status
Simulation time 13447712601 ps
CPU time 38.92 seconds
Started Jul 15 04:34:21 PM PDT 24
Finished Jul 15 04:35:01 PM PDT 24
Peak memory 199756 kb
Host smart-c41e3c8a-7363-471c-a4b1-c1309bef6460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947546002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.947546002
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1622530046
Short name T160
Test name
Test status
Simulation time 104977094537 ps
CPU time 165.18 seconds
Started Jul 15 04:34:34 PM PDT 24
Finished Jul 15 04:37:20 PM PDT 24
Peak memory 199788 kb
Host smart-dfe388a4-3941-4b03-b8ea-f00335e1e4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622530046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1622530046
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.367865986
Short name T498
Test name
Test status
Simulation time 46838864455 ps
CPU time 15.66 seconds
Started Jul 15 04:34:32 PM PDT 24
Finished Jul 15 04:34:50 PM PDT 24
Peak memory 199724 kb
Host smart-25be408f-5c7a-4422-bdec-3cd483f91ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367865986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.367865986
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.742333298
Short name T586
Test name
Test status
Simulation time 73251689109 ps
CPU time 79.87 seconds
Started Jul 15 04:34:31 PM PDT 24
Finished Jul 15 04:35:53 PM PDT 24
Peak memory 199704 kb
Host smart-cb3a0b03-e0e1-4578-b404-4dddbc2e447f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742333298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.742333298
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3581177503
Short name T161
Test name
Test status
Simulation time 62373713740 ps
CPU time 26.46 seconds
Started Jul 15 04:34:31 PM PDT 24
Finished Jul 15 04:35:00 PM PDT 24
Peak memory 199692 kb
Host smart-a0e73225-8050-40a8-bca9-bfcb5162ecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581177503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3581177503
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3245637234
Short name T595
Test name
Test status
Simulation time 183404236063 ps
CPU time 16.81 seconds
Started Jul 15 04:34:31 PM PDT 24
Finished Jul 15 04:34:50 PM PDT 24
Peak memory 199672 kb
Host smart-3d45041f-8e70-46e9-98cc-38547c7f3a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245637234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3245637234
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2600122519
Short name T1105
Test name
Test status
Simulation time 74158942505 ps
CPU time 96.86 seconds
Started Jul 15 04:34:32 PM PDT 24
Finished Jul 15 04:36:11 PM PDT 24
Peak memory 199692 kb
Host smart-31350868-5038-42b4-a01f-53eb88e7b123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600122519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2600122519
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3910212709
Short name T114
Test name
Test status
Simulation time 57503093952 ps
CPU time 93.33 seconds
Started Jul 15 04:34:34 PM PDT 24
Finished Jul 15 04:36:08 PM PDT 24
Peak memory 200040 kb
Host smart-222ab89b-73a2-4d48-877b-b6c8e84f9bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910212709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3910212709
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1110533078
Short name T1090
Test name
Test status
Simulation time 13316483 ps
CPU time 0.56 seconds
Started Jul 15 04:31:26 PM PDT 24
Finished Jul 15 04:31:28 PM PDT 24
Peak memory 194068 kb
Host smart-706b3908-9db2-4e34-a352-d5790b75ff58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110533078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1110533078
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1665264468
Short name T574
Test name
Test status
Simulation time 34552461909 ps
CPU time 15.46 seconds
Started Jul 15 04:31:20 PM PDT 24
Finished Jul 15 04:31:35 PM PDT 24
Peak memory 199476 kb
Host smart-1b3dfee9-c3f2-4884-860e-e47e0b88ed77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665264468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1665264468
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.69807413
Short name T481
Test name
Test status
Simulation time 25254655848 ps
CPU time 41.07 seconds
Started Jul 15 04:31:26 PM PDT 24
Finished Jul 15 04:32:09 PM PDT 24
Peak memory 199744 kb
Host smart-41e822a4-8360-4a97-b99a-19d2a0c29323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69807413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.69807413
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.4034096491
Short name T196
Test name
Test status
Simulation time 150408962395 ps
CPU time 69.29 seconds
Started Jul 15 04:31:30 PM PDT 24
Finished Jul 15 04:32:40 PM PDT 24
Peak memory 199720 kb
Host smart-b0d251aa-089d-4709-881d-73b37fb755d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034096491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.4034096491
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2094225004
Short name T979
Test name
Test status
Simulation time 27013609921 ps
CPU time 10.48 seconds
Started Jul 15 04:31:22 PM PDT 24
Finished Jul 15 04:31:34 PM PDT 24
Peak memory 199732 kb
Host smart-bf2454bf-3c8c-4cda-9c55-9d02503482b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094225004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2094225004
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3246859725
Short name T1125
Test name
Test status
Simulation time 104112527509 ps
CPU time 804.29 seconds
Started Jul 15 04:31:24 PM PDT 24
Finished Jul 15 04:44:50 PM PDT 24
Peak memory 199712 kb
Host smart-27eb46a3-3db3-4507-9fe7-e76037a217d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3246859725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3246859725
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.937502619
Short name T714
Test name
Test status
Simulation time 10675057946 ps
CPU time 17.38 seconds
Started Jul 15 04:31:28 PM PDT 24
Finished Jul 15 04:31:48 PM PDT 24
Peak memory 197428 kb
Host smart-1ed62ae6-5bca-4f88-808b-f5d1bb9fd539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937502619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.937502619
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2746315093
Short name T372
Test name
Test status
Simulation time 128526395351 ps
CPU time 61.27 seconds
Started Jul 15 04:31:20 PM PDT 24
Finished Jul 15 04:32:22 PM PDT 24
Peak memory 199716 kb
Host smart-1ee816fe-eeba-4212-bfc7-127ad1a96bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746315093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2746315093
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1886170720
Short name T392
Test name
Test status
Simulation time 14553457365 ps
CPU time 762.1 seconds
Started Jul 15 04:31:28 PM PDT 24
Finished Jul 15 04:44:12 PM PDT 24
Peak memory 199728 kb
Host smart-c1dcb264-f478-4614-a0c1-9d41bdf6f0b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886170720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1886170720
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.4121010567
Short name T494
Test name
Test status
Simulation time 6100050614 ps
CPU time 3.74 seconds
Started Jul 15 04:31:25 PM PDT 24
Finished Jul 15 04:31:31 PM PDT 24
Peak memory 197988 kb
Host smart-81336b7b-3c81-48f2-8b36-f2662f85e4bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121010567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.4121010567
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1042909435
Short name T888
Test name
Test status
Simulation time 91454871676 ps
CPU time 173.26 seconds
Started Jul 15 04:31:24 PM PDT 24
Finished Jul 15 04:34:19 PM PDT 24
Peak memory 199724 kb
Host smart-a8cacd4f-f952-44c7-8176-beb40229de09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042909435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1042909435
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4281698370
Short name T352
Test name
Test status
Simulation time 4712654908 ps
CPU time 4 seconds
Started Jul 15 04:31:21 PM PDT 24
Finished Jul 15 04:31:27 PM PDT 24
Peak memory 195908 kb
Host smart-6018b930-4451-46d5-b3e3-600eb02f46c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281698370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4281698370
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.4207678003
Short name T7
Test name
Test status
Simulation time 5304316229 ps
CPU time 10 seconds
Started Jul 15 04:31:21 PM PDT 24
Finished Jul 15 04:31:32 PM PDT 24
Peak memory 199576 kb
Host smart-34216ba8-5e27-41a2-a7ae-2db9850e4f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207678003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.4207678003
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3302363315
Short name T450
Test name
Test status
Simulation time 78442318460 ps
CPU time 216.07 seconds
Started Jul 15 04:31:24 PM PDT 24
Finished Jul 15 04:35:01 PM PDT 24
Peak memory 199712 kb
Host smart-d5e370fc-e524-4262-8564-8e07fb80c110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302363315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3302363315
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2469853627
Short name T406
Test name
Test status
Simulation time 78749619957 ps
CPU time 1003.9 seconds
Started Jul 15 04:31:25 PM PDT 24
Finished Jul 15 04:48:10 PM PDT 24
Peak memory 216212 kb
Host smart-f6d5961a-4a09-4cbf-8041-e885d346a327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469853627 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2469853627
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1662255336
Short name T848
Test name
Test status
Simulation time 2005210027 ps
CPU time 2.64 seconds
Started Jul 15 04:31:25 PM PDT 24
Finished Jul 15 04:31:28 PM PDT 24
Peak memory 198800 kb
Host smart-6783f3ce-5f40-4535-bb93-78d2c919bf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662255336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1662255336
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.160338745
Short name T5
Test name
Test status
Simulation time 75968914712 ps
CPU time 56.76 seconds
Started Jul 15 04:31:21 PM PDT 24
Finished Jul 15 04:32:19 PM PDT 24
Peak memory 199756 kb
Host smart-1d9cdc44-2b25-4466-835f-5fc1dffee5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160338745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.160338745
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.281829595
Short name T417
Test name
Test status
Simulation time 106062243305 ps
CPU time 83.52 seconds
Started Jul 15 04:34:31 PM PDT 24
Finished Jul 15 04:35:56 PM PDT 24
Peak memory 199764 kb
Host smart-898417aa-f1b9-478d-962f-f59ad067a577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281829595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.281829595
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2519569113
Short name T98
Test name
Test status
Simulation time 55755109417 ps
CPU time 133.65 seconds
Started Jul 15 04:34:31 PM PDT 24
Finished Jul 15 04:36:47 PM PDT 24
Peak memory 199676 kb
Host smart-a4e01116-7351-4a5a-b3fb-3581fe7e102b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519569113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2519569113
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1946898866
Short name T910
Test name
Test status
Simulation time 99898932928 ps
CPU time 49.02 seconds
Started Jul 15 04:34:32 PM PDT 24
Finished Jul 15 04:35:23 PM PDT 24
Peak memory 199604 kb
Host smart-d1b47f0e-afcb-4dfb-acf5-81bb846ad7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946898866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1946898866
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3096307034
Short name T493
Test name
Test status
Simulation time 17518518252 ps
CPU time 27.38 seconds
Started Jul 15 04:34:31 PM PDT 24
Finished Jul 15 04:35:01 PM PDT 24
Peak memory 199684 kb
Host smart-f5ed6fb3-674c-43de-aef3-0df4a6bab30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096307034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3096307034
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.842897278
Short name T159
Test name
Test status
Simulation time 230765107009 ps
CPU time 29.42 seconds
Started Jul 15 04:34:31 PM PDT 24
Finished Jul 15 04:35:03 PM PDT 24
Peak memory 199752 kb
Host smart-846be910-d1f2-4891-b087-eb778fa5223b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842897278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.842897278
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2915337391
Short name T704
Test name
Test status
Simulation time 75531826290 ps
CPU time 98.64 seconds
Started Jul 15 04:34:31 PM PDT 24
Finished Jul 15 04:36:12 PM PDT 24
Peak memory 199728 kb
Host smart-74745efe-572c-4fef-af3f-3f3f2b449691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915337391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2915337391
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.749451518
Short name T1043
Test name
Test status
Simulation time 138632137443 ps
CPU time 18.22 seconds
Started Jul 15 04:34:30 PM PDT 24
Finished Jul 15 04:34:50 PM PDT 24
Peak memory 199748 kb
Host smart-a5fa1cbb-42ec-4c1d-a60c-0a3a72b50486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749451518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.749451518
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3095347262
Short name T1008
Test name
Test status
Simulation time 23679275364 ps
CPU time 8.69 seconds
Started Jul 15 04:34:29 PM PDT 24
Finished Jul 15 04:34:39 PM PDT 24
Peak memory 199072 kb
Host smart-1e5ee928-93e0-426a-8997-22834f74af12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095347262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3095347262
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2357280413
Short name T927
Test name
Test status
Simulation time 117781297025 ps
CPU time 27.06 seconds
Started Jul 15 04:34:32 PM PDT 24
Finished Jul 15 04:35:01 PM PDT 24
Peak memory 199652 kb
Host smart-e676ef00-0aab-45f2-a79f-bc8506819f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357280413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2357280413
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2114040556
Short name T169
Test name
Test status
Simulation time 26145895267 ps
CPU time 43.1 seconds
Started Jul 15 04:34:35 PM PDT 24
Finished Jul 15 04:35:19 PM PDT 24
Peak memory 199796 kb
Host smart-af38d3cf-32f8-4b0d-98f7-5d184452018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114040556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2114040556
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.4143291677
Short name T479
Test name
Test status
Simulation time 38581970 ps
CPU time 0.54 seconds
Started Jul 15 04:31:34 PM PDT 24
Finished Jul 15 04:31:35 PM PDT 24
Peak memory 195296 kb
Host smart-4eb0c89e-5593-4fc2-81d3-23ae103cd09d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143291677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.4143291677
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2250565263
Short name T120
Test name
Test status
Simulation time 123610209105 ps
CPU time 45.94 seconds
Started Jul 15 04:31:26 PM PDT 24
Finished Jul 15 04:32:14 PM PDT 24
Peak memory 199672 kb
Host smart-cc0887d4-5b43-4c82-9639-7e1f8b3147a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250565263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2250565263
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3981326979
Short name T1132
Test name
Test status
Simulation time 10555285367 ps
CPU time 18.34 seconds
Started Jul 15 04:31:25 PM PDT 24
Finished Jul 15 04:31:45 PM PDT 24
Peak memory 199736 kb
Host smart-649aa20d-7386-41f1-83fd-330376bbd521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981326979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3981326979
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3402387546
Short name T869
Test name
Test status
Simulation time 12652783420 ps
CPU time 17.96 seconds
Started Jul 15 04:31:30 PM PDT 24
Finished Jul 15 04:31:50 PM PDT 24
Peak memory 199716 kb
Host smart-703fe8a5-fa26-466f-b518-b3a56a15170a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402387546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3402387546
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3430908164
Short name T842
Test name
Test status
Simulation time 17556735611 ps
CPU time 27.44 seconds
Started Jul 15 04:31:26 PM PDT 24
Finished Jul 15 04:31:55 PM PDT 24
Peak memory 197148 kb
Host smart-8c3fcc66-7a16-461f-8958-66695bded0c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430908164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3430908164
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4246644735
Short name T941
Test name
Test status
Simulation time 44482235077 ps
CPU time 224.31 seconds
Started Jul 15 04:31:25 PM PDT 24
Finished Jul 15 04:35:11 PM PDT 24
Peak memory 199712 kb
Host smart-ce3aaf5c-d8da-4066-849c-dde61175e77d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246644735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4246644735
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1607399791
Short name T847
Test name
Test status
Simulation time 75242154 ps
CPU time 0.65 seconds
Started Jul 15 04:31:25 PM PDT 24
Finished Jul 15 04:31:28 PM PDT 24
Peak memory 196036 kb
Host smart-e87bef88-d93a-49d9-af03-bbf0d7758a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607399791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1607399791
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.4072670511
Short name T885
Test name
Test status
Simulation time 59438640698 ps
CPU time 49.42 seconds
Started Jul 15 04:31:27 PM PDT 24
Finished Jul 15 04:32:18 PM PDT 24
Peak memory 208000 kb
Host smart-58e9cfcb-c813-42c9-9ece-be7c7aeccb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072670511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.4072670511
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3604324283
Short name T245
Test name
Test status
Simulation time 24621094955 ps
CPU time 280.26 seconds
Started Jul 15 04:31:29 PM PDT 24
Finished Jul 15 04:36:11 PM PDT 24
Peak memory 199788 kb
Host smart-4f688cc1-f3d0-4997-b75b-fd73849539bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604324283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3604324283
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.495945012
Short name T345
Test name
Test status
Simulation time 5487241938 ps
CPU time 45.19 seconds
Started Jul 15 04:31:27 PM PDT 24
Finished Jul 15 04:32:14 PM PDT 24
Peak memory 199060 kb
Host smart-38d3db31-2665-4827-acf0-a4046e508dcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=495945012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.495945012
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1823991920
Short name T373
Test name
Test status
Simulation time 121741805983 ps
CPU time 65.15 seconds
Started Jul 15 04:31:32 PM PDT 24
Finished Jul 15 04:32:38 PM PDT 24
Peak memory 199716 kb
Host smart-27f70e8c-9eba-418c-a2bf-9f75ca24eac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823991920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1823991920
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1633938789
Short name T781
Test name
Test status
Simulation time 729570624 ps
CPU time 1.16 seconds
Started Jul 15 04:31:27 PM PDT 24
Finished Jul 15 04:31:30 PM PDT 24
Peak memory 195264 kb
Host smart-054bf94d-3c0f-4573-b749-740f24dd2015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633938789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1633938789
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1855498168
Short name T43
Test name
Test status
Simulation time 647617920 ps
CPU time 2.83 seconds
Started Jul 15 04:31:25 PM PDT 24
Finished Jul 15 04:31:29 PM PDT 24
Peak memory 198684 kb
Host smart-bc4d64e4-cb1c-4229-b12c-3f7e511dbd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855498168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1855498168
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.729401249
Short name T738
Test name
Test status
Simulation time 119868259300 ps
CPU time 1214.13 seconds
Started Jul 15 04:31:32 PM PDT 24
Finished Jul 15 04:51:47 PM PDT 24
Peak memory 199908 kb
Host smart-7b755626-f241-45e9-8851-43e6a7cd87a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729401249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.729401249
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1720275625
Short name T111
Test name
Test status
Simulation time 33493526138 ps
CPU time 314.16 seconds
Started Jul 15 04:31:31 PM PDT 24
Finished Jul 15 04:36:46 PM PDT 24
Peak memory 215232 kb
Host smart-9d8ab87f-b819-456a-86fe-9fd0f60ab78e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720275625 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1720275625
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2075394566
Short name T267
Test name
Test status
Simulation time 630655780 ps
CPU time 2.04 seconds
Started Jul 15 04:31:26 PM PDT 24
Finished Jul 15 04:31:30 PM PDT 24
Peak memory 198136 kb
Host smart-143319bd-04c0-49fe-9b49-7df0e5a4b600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075394566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2075394566
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3111766680
Short name T9
Test name
Test status
Simulation time 43517537577 ps
CPU time 7.01 seconds
Started Jul 15 04:31:31 PM PDT 24
Finished Jul 15 04:31:39 PM PDT 24
Peak memory 199448 kb
Host smart-d54a2c1a-d48b-46c2-8e63-f2dd24e33a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111766680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3111766680
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.242953580
Short name T501
Test name
Test status
Simulation time 167408907069 ps
CPU time 36.81 seconds
Started Jul 15 04:34:30 PM PDT 24
Finished Jul 15 04:35:09 PM PDT 24
Peak memory 199760 kb
Host smart-dcbb5b23-ae9e-4d3d-b67e-1a24f6bb44d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242953580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.242953580
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.244750365
Short name T644
Test name
Test status
Simulation time 17518031735 ps
CPU time 9.25 seconds
Started Jul 15 04:34:35 PM PDT 24
Finished Jul 15 04:34:45 PM PDT 24
Peak memory 199704 kb
Host smart-50a37bc4-ee0e-4be0-a18a-13be2dff605a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244750365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.244750365
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3350970076
Short name T144
Test name
Test status
Simulation time 49146274886 ps
CPU time 19.13 seconds
Started Jul 15 04:34:32 PM PDT 24
Finished Jul 15 04:34:53 PM PDT 24
Peak memory 199764 kb
Host smart-9c2d8132-d641-47e3-b321-b384f50284ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350970076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3350970076
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3482241478
Short name T776
Test name
Test status
Simulation time 8274488282 ps
CPU time 13.12 seconds
Started Jul 15 04:34:33 PM PDT 24
Finished Jul 15 04:34:48 PM PDT 24
Peak memory 199340 kb
Host smart-4e0e78ce-e1af-42bc-95d8-26a00543fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482241478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3482241478
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.4277551879
Short name T486
Test name
Test status
Simulation time 21754279569 ps
CPU time 9.37 seconds
Started Jul 15 04:34:35 PM PDT 24
Finished Jul 15 04:34:45 PM PDT 24
Peak memory 199756 kb
Host smart-dd04c6a4-0cfe-4d3d-89e6-76503cd4ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277551879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.4277551879
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3510070361
Short name T311
Test name
Test status
Simulation time 161570425144 ps
CPU time 239.46 seconds
Started Jul 15 04:34:31 PM PDT 24
Finished Jul 15 04:38:32 PM PDT 24
Peak memory 199764 kb
Host smart-17e3e560-5ec4-4ae7-a1ac-f5b81a0fa9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510070361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3510070361
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1156405424
Short name T890
Test name
Test status
Simulation time 188818274086 ps
CPU time 143.14 seconds
Started Jul 15 04:34:30 PM PDT 24
Finished Jul 15 04:36:55 PM PDT 24
Peak memory 199824 kb
Host smart-83a10289-60ca-4382-9132-3e7cdc898381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156405424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1156405424
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3652258270
Short name T395
Test name
Test status
Simulation time 136479696019 ps
CPU time 51.11 seconds
Started Jul 15 04:34:41 PM PDT 24
Finished Jul 15 04:35:33 PM PDT 24
Peak memory 199800 kb
Host smart-77ea7bfa-e5d2-42f6-952b-f9d4420962c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652258270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3652258270
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1959800481
Short name T477
Test name
Test status
Simulation time 30851196130 ps
CPU time 42.65 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:35:31 PM PDT 24
Peak memory 199788 kb
Host smart-423127e5-40bb-4cd4-8598-810030411348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959800481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1959800481
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.848478668
Short name T937
Test name
Test status
Simulation time 12647149 ps
CPU time 0.55 seconds
Started Jul 15 04:31:34 PM PDT 24
Finished Jul 15 04:31:35 PM PDT 24
Peak memory 195084 kb
Host smart-7bf0b092-3536-4588-97ef-cced28abd267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848478668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.848478668
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.191992927
Short name T959
Test name
Test status
Simulation time 68322476847 ps
CPU time 49.49 seconds
Started Jul 15 04:31:36 PM PDT 24
Finished Jul 15 04:32:26 PM PDT 24
Peak memory 199612 kb
Host smart-54dad4a9-431b-4fd9-84a1-8d47c25eb9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191992927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.191992927
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2977094537
Short name T150
Test name
Test status
Simulation time 221351420765 ps
CPU time 24.6 seconds
Started Jul 15 04:31:37 PM PDT 24
Finished Jul 15 04:32:02 PM PDT 24
Peak memory 199736 kb
Host smart-8cbc8a97-d830-4ffa-afe4-2f063df14bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977094537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2977094537
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.186233662
Short name T298
Test name
Test status
Simulation time 13355862066 ps
CPU time 29.5 seconds
Started Jul 15 04:31:32 PM PDT 24
Finished Jul 15 04:32:02 PM PDT 24
Peak memory 199700 kb
Host smart-9f00f57c-2f58-4dc8-b6f7-a54cbcfeb320
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186233662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.186233662
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2840901770
Short name T377
Test name
Test status
Simulation time 46102571280 ps
CPU time 154.95 seconds
Started Jul 15 04:31:35 PM PDT 24
Finished Jul 15 04:34:11 PM PDT 24
Peak memory 199728 kb
Host smart-f7f1fd52-2b61-4a3b-8a73-ed5f17e000a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2840901770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2840901770
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.843971192
Short name T722
Test name
Test status
Simulation time 4829776196 ps
CPU time 3.18 seconds
Started Jul 15 04:31:33 PM PDT 24
Finished Jul 15 04:31:37 PM PDT 24
Peak memory 199684 kb
Host smart-5a96709a-38eb-44bf-a42c-34fb94f425e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843971192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.843971192
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2154787767
Short name T11
Test name
Test status
Simulation time 140366574673 ps
CPU time 328.54 seconds
Started Jul 15 04:31:37 PM PDT 24
Finished Jul 15 04:37:06 PM PDT 24
Peak memory 199884 kb
Host smart-47efdb23-835c-4493-8287-e3066d224b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154787767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2154787767
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2365710628
Short name T557
Test name
Test status
Simulation time 24873580186 ps
CPU time 1174.36 seconds
Started Jul 15 04:31:34 PM PDT 24
Finished Jul 15 04:51:09 PM PDT 24
Peak memory 199652 kb
Host smart-f17fda5b-bc88-4a2a-b10e-ceef481a16f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2365710628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2365710628
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2421217039
Short name T1086
Test name
Test status
Simulation time 3883156357 ps
CPU time 7.02 seconds
Started Jul 15 04:31:34 PM PDT 24
Finished Jul 15 04:31:41 PM PDT 24
Peak memory 198744 kb
Host smart-dbc6c216-41a3-4969-b52a-7ef48ccd94ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2421217039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2421217039
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1662218903
Short name T624
Test name
Test status
Simulation time 30824820556 ps
CPU time 58.47 seconds
Started Jul 15 04:31:37 PM PDT 24
Finished Jul 15 04:32:36 PM PDT 24
Peak memory 199616 kb
Host smart-715e543c-98eb-4ad2-8f37-f6f65ef0b5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662218903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1662218903
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1819857604
Short name T1037
Test name
Test status
Simulation time 4684453143 ps
CPU time 3.79 seconds
Started Jul 15 04:31:34 PM PDT 24
Finished Jul 15 04:31:39 PM PDT 24
Peak memory 196040 kb
Host smart-3a46feea-c42d-4726-b081-031332c1f600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819857604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1819857604
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3292961887
Short name T327
Test name
Test status
Simulation time 938572198 ps
CPU time 3.78 seconds
Started Jul 15 04:31:35 PM PDT 24
Finished Jul 15 04:31:40 PM PDT 24
Peak memory 200016 kb
Host smart-751a7d4f-943f-4fa0-a1c8-47e1c0f54803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292961887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3292961887
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2285067273
Short name T948
Test name
Test status
Simulation time 516530094861 ps
CPU time 757.94 seconds
Started Jul 15 04:31:34 PM PDT 24
Finished Jul 15 04:44:13 PM PDT 24
Peak memory 199816 kb
Host smart-473ea665-e392-474a-8c6b-b20458e44e6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285067273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2285067273
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3326057463
Short name T10
Test name
Test status
Simulation time 77002659831 ps
CPU time 983.28 seconds
Started Jul 15 04:31:39 PM PDT 24
Finished Jul 15 04:48:03 PM PDT 24
Peak memory 216056 kb
Host smart-4d685010-595e-4c3b-a61e-3d3e0124750f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326057463 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3326057463
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1190889471
Short name T363
Test name
Test status
Simulation time 979727177 ps
CPU time 1.41 seconds
Started Jul 15 04:31:36 PM PDT 24
Finished Jul 15 04:31:38 PM PDT 24
Peak memory 198496 kb
Host smart-5e3c827d-806c-43aa-a6c0-625a4570d79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190889471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1190889471
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1912275282
Short name T455
Test name
Test status
Simulation time 83252246761 ps
CPU time 132.79 seconds
Started Jul 15 04:31:34 PM PDT 24
Finished Jul 15 04:33:48 PM PDT 24
Peak memory 199792 kb
Host smart-1f0b2a85-6415-471d-8d58-2cd61cc3e775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912275282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1912275282
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2259039205
Short name T177
Test name
Test status
Simulation time 114351513372 ps
CPU time 192.17 seconds
Started Jul 15 04:34:41 PM PDT 24
Finished Jul 15 04:37:54 PM PDT 24
Peak memory 199704 kb
Host smart-0eaa81d3-029f-4c03-94c2-fdd489f1798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259039205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2259039205
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.423440324
Short name T691
Test name
Test status
Simulation time 100477065342 ps
CPU time 206.64 seconds
Started Jul 15 04:34:40 PM PDT 24
Finished Jul 15 04:38:07 PM PDT 24
Peak memory 199608 kb
Host smart-6e976f2e-846a-468e-b12f-8ce68471ca5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423440324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.423440324
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1216556197
Short name T1091
Test name
Test status
Simulation time 53555742806 ps
CPU time 84.76 seconds
Started Jul 15 04:34:41 PM PDT 24
Finished Jul 15 04:36:06 PM PDT 24
Peak memory 199632 kb
Host smart-476deaa4-4aae-436a-8583-7e9541664b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216556197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1216556197
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3207846874
Short name T824
Test name
Test status
Simulation time 21495791420 ps
CPU time 19.15 seconds
Started Jul 15 04:34:43 PM PDT 24
Finished Jul 15 04:35:03 PM PDT 24
Peak memory 199708 kb
Host smart-cc561dd9-b530-4dd0-837e-42e7c2086e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207846874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3207846874
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.567323742
Short name T1107
Test name
Test status
Simulation time 40376113530 ps
CPU time 48.83 seconds
Started Jul 15 04:34:39 PM PDT 24
Finished Jul 15 04:35:29 PM PDT 24
Peak memory 199684 kb
Host smart-1d4ad0db-60c8-4749-9065-1f998c7708ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567323742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.567323742
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2586160015
Short name T213
Test name
Test status
Simulation time 136739302203 ps
CPU time 43.88 seconds
Started Jul 15 04:34:40 PM PDT 24
Finished Jul 15 04:35:25 PM PDT 24
Peak memory 199752 kb
Host smart-d1b8d734-7d56-43ab-9752-6b2528e0a1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586160015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2586160015
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2848162584
Short name T807
Test name
Test status
Simulation time 31258108155 ps
CPU time 54.62 seconds
Started Jul 15 04:34:37 PM PDT 24
Finished Jul 15 04:35:32 PM PDT 24
Peak memory 199796 kb
Host smart-d6e1a235-bcdd-4424-a9bd-6532bfca4cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848162584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2848162584
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1622710166
Short name T353
Test name
Test status
Simulation time 50437997 ps
CPU time 0.53 seconds
Started Jul 15 04:30:31 PM PDT 24
Finished Jul 15 04:30:33 PM PDT 24
Peak memory 195164 kb
Host smart-42c9cf45-ae1a-4131-bb71-3b5804387aae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622710166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1622710166
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1922434800
Short name T445
Test name
Test status
Simulation time 64828527967 ps
CPU time 29.41 seconds
Started Jul 15 04:30:28 PM PDT 24
Finished Jul 15 04:31:00 PM PDT 24
Peak memory 199744 kb
Host smart-0f65966c-cf97-4539-ae33-e58bd03ad53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922434800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1922434800
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3883852235
Short name T797
Test name
Test status
Simulation time 114426767696 ps
CPU time 10.85 seconds
Started Jul 15 04:30:35 PM PDT 24
Finished Jul 15 04:30:47 PM PDT 24
Peak memory 199468 kb
Host smart-fbb34278-7e6a-4d53-b985-345f7b35663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883852235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3883852235
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3539043787
Short name T212
Test name
Test status
Simulation time 59720112619 ps
CPU time 27.12 seconds
Started Jul 15 04:30:25 PM PDT 24
Finished Jul 15 04:30:54 PM PDT 24
Peak memory 199824 kb
Host smart-28f102e5-21a6-41e5-be8f-65f7b96ef960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539043787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3539043787
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2168158692
Short name T499
Test name
Test status
Simulation time 55046135618 ps
CPU time 7.26 seconds
Started Jul 15 04:30:27 PM PDT 24
Finished Jul 15 04:30:36 PM PDT 24
Peak memory 199736 kb
Host smart-d090bf67-0c2e-42d5-8752-41878d9158cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168158692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2168158692
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3022387187
Short name T631
Test name
Test status
Simulation time 52248845029 ps
CPU time 170.37 seconds
Started Jul 15 04:30:30 PM PDT 24
Finished Jul 15 04:33:23 PM PDT 24
Peak memory 199668 kb
Host smart-d30637ec-69a7-4b50-adce-bf5092bd2fc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022387187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3022387187
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3144453251
Short name T669
Test name
Test status
Simulation time 853805760 ps
CPU time 1.7 seconds
Started Jul 15 04:30:19 PM PDT 24
Finished Jul 15 04:30:22 PM PDT 24
Peak memory 195364 kb
Host smart-4c8f03f5-7b2b-453d-986c-c16021fa2f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144453251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3144453251
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.83518228
Short name T307
Test name
Test status
Simulation time 11703433875 ps
CPU time 597.01 seconds
Started Jul 15 04:30:36 PM PDT 24
Finished Jul 15 04:40:34 PM PDT 24
Peak memory 199612 kb
Host smart-251e9cf2-3440-43b8-9356-5c6a918b8bc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83518228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.83518228
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2930584029
Short name T1028
Test name
Test status
Simulation time 3035293327 ps
CPU time 18 seconds
Started Jul 15 04:30:25 PM PDT 24
Finished Jul 15 04:30:45 PM PDT 24
Peak memory 197908 kb
Host smart-f63b6abf-3364-4102-87ae-df65b323f155
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2930584029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2930584029
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.941617430
Short name T1019
Test name
Test status
Simulation time 33754642243 ps
CPU time 54.91 seconds
Started Jul 15 04:30:30 PM PDT 24
Finished Jul 15 04:31:27 PM PDT 24
Peak memory 199744 kb
Host smart-f3ba76af-1daf-4dbd-a522-00b8e15f0837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941617430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.941617430
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3813395305
Short name T789
Test name
Test status
Simulation time 4977107331 ps
CPU time 7.29 seconds
Started Jul 15 04:30:21 PM PDT 24
Finished Jul 15 04:30:29 PM PDT 24
Peak memory 195812 kb
Host smart-9b7ee19a-3cd8-41e0-8131-a001789a5cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813395305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3813395305
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1685976746
Short name T23
Test name
Test status
Simulation time 230173181 ps
CPU time 0.86 seconds
Started Jul 15 04:30:28 PM PDT 24
Finished Jul 15 04:30:31 PM PDT 24
Peak memory 218196 kb
Host smart-0e81b8a4-99b4-4541-874b-e35c023cdeac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685976746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1685976746
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1496357479
Short name T478
Test name
Test status
Simulation time 514381133 ps
CPU time 1.75 seconds
Started Jul 15 04:30:29 PM PDT 24
Finished Jul 15 04:30:33 PM PDT 24
Peak memory 199128 kb
Host smart-4d95bce2-c11b-4f63-95ac-4bee3fdbdb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496357479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1496357479
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1595894241
Short name T560
Test name
Test status
Simulation time 290392760800 ps
CPU time 409.52 seconds
Started Jul 15 04:30:25 PM PDT 24
Finished Jul 15 04:37:16 PM PDT 24
Peak memory 199820 kb
Host smart-c8c31c10-64fd-43cc-ab20-adfd872f24a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595894241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1595894241
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1724024462
Short name T725
Test name
Test status
Simulation time 12371359089 ps
CPU time 36.42 seconds
Started Jul 15 04:30:20 PM PDT 24
Finished Jul 15 04:30:58 PM PDT 24
Peak memory 199488 kb
Host smart-34a6b6f3-d9a1-4b7c-88df-ff70b598241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724024462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1724024462
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3980234171
Short name T568
Test name
Test status
Simulation time 37035604657 ps
CPU time 9.51 seconds
Started Jul 15 04:30:21 PM PDT 24
Finished Jul 15 04:30:32 PM PDT 24
Peak memory 199648 kb
Host smart-964771cb-5011-47f4-a1b0-16be62d3ed6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980234171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3980234171
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3745996196
Short name T314
Test name
Test status
Simulation time 17766280 ps
CPU time 0.56 seconds
Started Jul 15 04:31:41 PM PDT 24
Finished Jul 15 04:31:43 PM PDT 24
Peak memory 195052 kb
Host smart-a27d65ac-a50e-4626-9ea7-b018fa0a2353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745996196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3745996196
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3136355520
Short name T397
Test name
Test status
Simulation time 58398103410 ps
CPU time 23.88 seconds
Started Jul 15 04:31:33 PM PDT 24
Finished Jul 15 04:31:58 PM PDT 24
Peak memory 199648 kb
Host smart-f349b338-a61a-44e6-b646-4146addeb0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136355520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3136355520
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2725784467
Short name T115
Test name
Test status
Simulation time 231063664133 ps
CPU time 374.95 seconds
Started Jul 15 04:31:36 PM PDT 24
Finished Jul 15 04:37:51 PM PDT 24
Peak memory 199696 kb
Host smart-d135fb6a-436d-4158-b6ad-d2451f0ace85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725784467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2725784467
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3716198784
Short name T1147
Test name
Test status
Simulation time 119008937332 ps
CPU time 45.53 seconds
Started Jul 15 04:31:37 PM PDT 24
Finished Jul 15 04:32:23 PM PDT 24
Peak memory 199676 kb
Host smart-94e89017-bdef-4cbb-a004-455661b6e949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716198784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3716198784
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3527426402
Short name T999
Test name
Test status
Simulation time 49496042168 ps
CPU time 76.99 seconds
Started Jul 15 04:31:44 PM PDT 24
Finished Jul 15 04:33:02 PM PDT 24
Peak memory 199544 kb
Host smart-9f36a4b4-75d9-4b7e-b5b9-172d4411a5fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527426402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3527426402
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3016633200
Short name T468
Test name
Test status
Simulation time 85152265166 ps
CPU time 394.75 seconds
Started Jul 15 04:31:40 PM PDT 24
Finished Jul 15 04:38:16 PM PDT 24
Peak memory 199684 kb
Host smart-6c9b2f60-ed11-42c7-838e-320333795e31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3016633200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3016633200
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2095538839
Short name T517
Test name
Test status
Simulation time 4489677222 ps
CPU time 7.47 seconds
Started Jul 15 04:31:42 PM PDT 24
Finished Jul 15 04:31:51 PM PDT 24
Peak memory 197460 kb
Host smart-12e650cf-be04-44ba-9854-e48420882e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095538839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2095538839
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1633994234
Short name T259
Test name
Test status
Simulation time 40602480678 ps
CPU time 65.77 seconds
Started Jul 15 04:31:39 PM PDT 24
Finished Jul 15 04:32:45 PM PDT 24
Peak memory 199728 kb
Host smart-3b5b82db-4920-4ab9-9484-b811fb8d0f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633994234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1633994234
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3406834019
Short name T1115
Test name
Test status
Simulation time 13500751847 ps
CPU time 170.93 seconds
Started Jul 15 04:31:40 PM PDT 24
Finished Jul 15 04:34:32 PM PDT 24
Peak memory 199836 kb
Host smart-ae11b662-17cc-48e8-b6fe-a076ffbb718c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3406834019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3406834019
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2023258224
Short name T340
Test name
Test status
Simulation time 1584644859 ps
CPU time 8.73 seconds
Started Jul 15 04:31:36 PM PDT 24
Finished Jul 15 04:31:45 PM PDT 24
Peak memory 197976 kb
Host smart-e1730053-0898-45fe-8881-1f20661a060d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023258224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2023258224
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3725812842
Short name T750
Test name
Test status
Simulation time 47638284311 ps
CPU time 16.88 seconds
Started Jul 15 04:31:42 PM PDT 24
Finished Jul 15 04:32:00 PM PDT 24
Peak memory 199636 kb
Host smart-88dbce20-2e9f-49d9-a6e8-196ca1c8c42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725812842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3725812842
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2601301604
Short name T544
Test name
Test status
Simulation time 6479759487 ps
CPU time 8.77 seconds
Started Jul 15 04:31:39 PM PDT 24
Finished Jul 15 04:31:48 PM PDT 24
Peak memory 195632 kb
Host smart-4fc9dee9-05c1-4f1f-9751-9914fc0fc71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601301604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2601301604
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1808942750
Short name T489
Test name
Test status
Simulation time 279405882 ps
CPU time 1.06 seconds
Started Jul 15 04:31:34 PM PDT 24
Finished Jul 15 04:31:36 PM PDT 24
Peak memory 198288 kb
Host smart-af7ce8f2-757b-4d06-94a1-560fee77bcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808942750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1808942750
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.665787907
Short name T492
Test name
Test status
Simulation time 175100498750 ps
CPU time 384.05 seconds
Started Jul 15 04:31:40 PM PDT 24
Finished Jul 15 04:38:05 PM PDT 24
Peak memory 199732 kb
Host smart-27de07bf-5225-420a-bcf2-0bc44830ae59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665787907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.665787907
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1394825898
Short name T511
Test name
Test status
Simulation time 6926356750 ps
CPU time 8.84 seconds
Started Jul 15 04:31:40 PM PDT 24
Finished Jul 15 04:31:50 PM PDT 24
Peak memory 199528 kb
Host smart-64470c36-0954-4435-8ed5-018c123b92f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394825898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1394825898
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.873872361
Short name T964
Test name
Test status
Simulation time 102608656776 ps
CPU time 87.16 seconds
Started Jul 15 04:31:36 PM PDT 24
Finished Jul 15 04:33:04 PM PDT 24
Peak memory 199700 kb
Host smart-81afdd3d-8301-4b16-8f27-d18425a1259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873872361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.873872361
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.60671454
Short name T926
Test name
Test status
Simulation time 9391017651 ps
CPU time 17.92 seconds
Started Jul 15 04:34:40 PM PDT 24
Finished Jul 15 04:34:59 PM PDT 24
Peak memory 199700 kb
Host smart-af962335-33dc-4c97-ad8c-ab0584cb8cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60671454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.60671454
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.125710557
Short name T506
Test name
Test status
Simulation time 16566186508 ps
CPU time 30.44 seconds
Started Jul 15 04:34:40 PM PDT 24
Finished Jul 15 04:35:12 PM PDT 24
Peak memory 199812 kb
Host smart-207ec5fd-8129-445b-9f57-e169e238e0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125710557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.125710557
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.145716442
Short name T171
Test name
Test status
Simulation time 77897550927 ps
CPU time 20.16 seconds
Started Jul 15 04:34:39 PM PDT 24
Finished Jul 15 04:35:00 PM PDT 24
Peak memory 199724 kb
Host smart-a43d9a0a-6560-4be0-a1a8-80c9d078a2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145716442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.145716442
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3523505558
Short name T456
Test name
Test status
Simulation time 16560876941 ps
CPU time 24.26 seconds
Started Jul 15 04:34:42 PM PDT 24
Finished Jul 15 04:35:07 PM PDT 24
Peak memory 199428 kb
Host smart-3e7e8db7-183a-4643-b89c-1392cff4e56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523505558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3523505558
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.653436273
Short name T1139
Test name
Test status
Simulation time 10985096309 ps
CPU time 14.73 seconds
Started Jul 15 04:34:39 PM PDT 24
Finished Jul 15 04:34:55 PM PDT 24
Peak memory 199468 kb
Host smart-7f07c265-c2eb-4b26-92c5-8fc19922a0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653436273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.653436273
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3563208078
Short name T940
Test name
Test status
Simulation time 64129372359 ps
CPU time 50.61 seconds
Started Jul 15 04:34:41 PM PDT 24
Finished Jul 15 04:35:32 PM PDT 24
Peak memory 199800 kb
Host smart-b1b3afff-1593-49e5-b58b-06a63e18a32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563208078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3563208078
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.24509870
Short name T172
Test name
Test status
Simulation time 48844998239 ps
CPU time 22.61 seconds
Started Jul 15 04:34:39 PM PDT 24
Finished Jul 15 04:35:03 PM PDT 24
Peak memory 199720 kb
Host smart-468e89af-8cb2-40a9-b422-9ffd39ffac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24509870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.24509870
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1215464449
Short name T550
Test name
Test status
Simulation time 36560297514 ps
CPU time 34.07 seconds
Started Jul 15 04:34:39 PM PDT 24
Finished Jul 15 04:35:13 PM PDT 24
Peak memory 199772 kb
Host smart-ea3792c3-fff7-485e-aef4-d150c2f7a350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215464449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1215464449
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1394567493
Short name T182
Test name
Test status
Simulation time 16494051734 ps
CPU time 7.4 seconds
Started Jul 15 04:34:50 PM PDT 24
Finished Jul 15 04:34:58 PM PDT 24
Peak memory 199784 kb
Host smart-e4b76a3a-273e-41a5-9653-9276e4bf126f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394567493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1394567493
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1996981407
Short name T938
Test name
Test status
Simulation time 28768452 ps
CPU time 0.61 seconds
Started Jul 15 04:31:41 PM PDT 24
Finished Jul 15 04:31:43 PM PDT 24
Peak memory 195108 kb
Host smart-b7e161d3-b5d3-4cdb-b407-cd7688cb278b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996981407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1996981407
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3283348087
Short name T840
Test name
Test status
Simulation time 26920037900 ps
CPU time 41.03 seconds
Started Jul 15 04:31:42 PM PDT 24
Finished Jul 15 04:32:24 PM PDT 24
Peak memory 199692 kb
Host smart-fd180145-dc55-413a-8ccc-e483ec63e701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283348087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3283348087
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2278999654
Short name T719
Test name
Test status
Simulation time 19920194624 ps
CPU time 15.53 seconds
Started Jul 15 04:31:41 PM PDT 24
Finished Jul 15 04:31:58 PM PDT 24
Peak memory 198172 kb
Host smart-6866c362-a1da-497a-8421-dce61a1eb1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278999654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2278999654
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2973742486
Short name T617
Test name
Test status
Simulation time 44117381880 ps
CPU time 24.15 seconds
Started Jul 15 04:31:42 PM PDT 24
Finished Jul 15 04:32:07 PM PDT 24
Peak memory 199596 kb
Host smart-c4633956-ce4f-40fe-a6a0-741c8b397a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973742486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2973742486
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3938321800
Short name T786
Test name
Test status
Simulation time 31229665581 ps
CPU time 5.92 seconds
Started Jul 15 04:31:41 PM PDT 24
Finished Jul 15 04:31:48 PM PDT 24
Peak memory 199604 kb
Host smart-f226d4a0-4d5b-4688-aa95-c3aa6d05841a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938321800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3938321800
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3212718567
Short name T585
Test name
Test status
Simulation time 216376595202 ps
CPU time 573.3 seconds
Started Jul 15 04:31:41 PM PDT 24
Finished Jul 15 04:41:16 PM PDT 24
Peak memory 199644 kb
Host smart-8661e9d0-cd58-482c-842c-008965708181
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3212718567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3212718567
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3467805642
Short name T996
Test name
Test status
Simulation time 2836303295 ps
CPU time 4.65 seconds
Started Jul 15 04:31:40 PM PDT 24
Finished Jul 15 04:31:45 PM PDT 24
Peak memory 195540 kb
Host smart-34f9fabb-081f-4838-b5d0-5558a7268a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467805642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3467805642
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3130912497
Short name T579
Test name
Test status
Simulation time 135798934686 ps
CPU time 51.25 seconds
Started Jul 15 04:31:39 PM PDT 24
Finished Jul 15 04:32:31 PM PDT 24
Peak memory 199952 kb
Host smart-654ca8ed-a253-4f90-871a-969cac326b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130912497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3130912497
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3854834767
Short name T787
Test name
Test status
Simulation time 7788931435 ps
CPU time 164.9 seconds
Started Jul 15 04:31:44 PM PDT 24
Finished Jul 15 04:34:30 PM PDT 24
Peak memory 199792 kb
Host smart-4a8f5fea-aa19-4d09-a14f-faad7585dcb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854834767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3854834767
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3460280690
Short name T813
Test name
Test status
Simulation time 5190804949 ps
CPU time 46.67 seconds
Started Jul 15 04:31:42 PM PDT 24
Finished Jul 15 04:32:30 PM PDT 24
Peak memory 197964 kb
Host smart-36c0271e-9b1a-43d2-8f40-ae0ea5d6fdff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460280690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3460280690
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1717322584
Short name T633
Test name
Test status
Simulation time 73881956490 ps
CPU time 93.8 seconds
Started Jul 15 04:31:40 PM PDT 24
Finished Jul 15 04:33:14 PM PDT 24
Peak memory 199704 kb
Host smart-48f38a3d-816e-4213-b0fe-58288984569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717322584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1717322584
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2259253112
Short name T528
Test name
Test status
Simulation time 31973483022 ps
CPU time 8.48 seconds
Started Jul 15 04:31:42 PM PDT 24
Finished Jul 15 04:31:52 PM PDT 24
Peak memory 195816 kb
Host smart-530ba5e1-5108-417a-bca9-b40e2c254473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259253112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2259253112
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3572543103
Short name T994
Test name
Test status
Simulation time 5678278283 ps
CPU time 18.95 seconds
Started Jul 15 04:31:39 PM PDT 24
Finished Jul 15 04:31:58 PM PDT 24
Peak memory 199728 kb
Host smart-7af1f3bd-23f4-444c-8344-fb56c92bf5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572543103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3572543103
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.394632028
Short name T273
Test name
Test status
Simulation time 75315825666 ps
CPU time 59.97 seconds
Started Jul 15 04:31:44 PM PDT 24
Finished Jul 15 04:32:45 PM PDT 24
Peak memory 199704 kb
Host smart-2f58b6d6-66af-4280-8046-79c7af964249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394632028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.394632028
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.408199960
Short name T1038
Test name
Test status
Simulation time 64847400022 ps
CPU time 282.08 seconds
Started Jul 15 04:31:41 PM PDT 24
Finished Jul 15 04:36:24 PM PDT 24
Peak memory 212956 kb
Host smart-b0f9f273-c095-4536-8ccc-3daeadcc00ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408199960 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.408199960
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2051420065
Short name T1007
Test name
Test status
Simulation time 6439931232 ps
CPU time 44.15 seconds
Started Jul 15 04:31:42 PM PDT 24
Finished Jul 15 04:32:27 PM PDT 24
Peak memory 199228 kb
Host smart-b7c7a6d0-d049-425b-9d17-18e267a34c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051420065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2051420065
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2712635038
Short name T1124
Test name
Test status
Simulation time 44281955818 ps
CPU time 98.56 seconds
Started Jul 15 04:31:41 PM PDT 24
Finished Jul 15 04:33:20 PM PDT 24
Peak memory 199672 kb
Host smart-f51eacc1-1587-4052-a6a3-ebdce543b506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712635038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2712635038
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1294441684
Short name T454
Test name
Test status
Simulation time 25224221581 ps
CPU time 41.24 seconds
Started Jul 15 04:34:48 PM PDT 24
Finished Jul 15 04:35:30 PM PDT 24
Peak memory 199628 kb
Host smart-182a0047-590e-4f8d-b2f3-79fcb7f83c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294441684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1294441684
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3142736617
Short name T189
Test name
Test status
Simulation time 40719698770 ps
CPU time 19.85 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:35:08 PM PDT 24
Peak memory 200104 kb
Host smart-67d6d8d2-6e83-414a-a9f3-7349ce29b6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142736617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3142736617
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2882742184
Short name T91
Test name
Test status
Simulation time 13404752717 ps
CPU time 19.65 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:35:08 PM PDT 24
Peak memory 199632 kb
Host smart-65f3e129-39fd-437a-a35d-660d7b6b6315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882742184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2882742184
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.481976505
Short name T756
Test name
Test status
Simulation time 73724932862 ps
CPU time 31.66 seconds
Started Jul 15 04:34:46 PM PDT 24
Finished Jul 15 04:35:18 PM PDT 24
Peak memory 199616 kb
Host smart-4139dcab-9ced-4de4-992d-2ab751114fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481976505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.481976505
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2016516604
Short name T1040
Test name
Test status
Simulation time 33598567324 ps
CPU time 14.41 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:35:03 PM PDT 24
Peak memory 199820 kb
Host smart-97edb91a-f6c5-4c14-bdff-f0fb6f29ab0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016516604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2016516604
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1304397042
Short name T138
Test name
Test status
Simulation time 66913049998 ps
CPU time 74.26 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:36:02 PM PDT 24
Peak memory 199688 kb
Host smart-1cf4dff7-434d-4c7c-959e-e71af2491f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304397042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1304397042
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2998032063
Short name T1176
Test name
Test status
Simulation time 29257670716 ps
CPU time 44.67 seconds
Started Jul 15 04:34:48 PM PDT 24
Finished Jul 15 04:35:34 PM PDT 24
Peak memory 199796 kb
Host smart-1646a718-90fa-4c21-a91e-19701a672d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998032063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2998032063
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1677982088
Short name T536
Test name
Test status
Simulation time 18748483946 ps
CPU time 30.19 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:35:18 PM PDT 24
Peak memory 199204 kb
Host smart-adb682b9-abc6-480f-a410-5f744cfdb126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677982088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1677982088
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1421354644
Short name T214
Test name
Test status
Simulation time 175086409624 ps
CPU time 68.98 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:35:57 PM PDT 24
Peak memory 199736 kb
Host smart-8cf1b2a0-b678-460d-896a-559395f1c10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421354644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1421354644
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2580626558
Short name T203
Test name
Test status
Simulation time 31609009448 ps
CPU time 13.81 seconds
Started Jul 15 04:34:51 PM PDT 24
Finished Jul 15 04:35:06 PM PDT 24
Peak memory 199872 kb
Host smart-95fd8225-0d13-47de-bbde-e649e27da9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580626558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2580626558
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2227781540
Short name T930
Test name
Test status
Simulation time 44864761 ps
CPU time 0.54 seconds
Started Jul 15 04:31:49 PM PDT 24
Finished Jul 15 04:31:51 PM PDT 24
Peak memory 195396 kb
Host smart-5b4dc9b7-91ce-454d-8c43-e624003d868a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227781540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2227781540
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3022604169
Short name T1023
Test name
Test status
Simulation time 49864526672 ps
CPU time 54.89 seconds
Started Jul 15 04:31:46 PM PDT 24
Finished Jul 15 04:32:42 PM PDT 24
Peak memory 199724 kb
Host smart-ed040109-50b2-4c44-9d20-9a8cfd18f1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022604169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3022604169
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.855267001
Short name T396
Test name
Test status
Simulation time 45215111576 ps
CPU time 62.72 seconds
Started Jul 15 04:31:49 PM PDT 24
Finished Jul 15 04:32:53 PM PDT 24
Peak memory 199700 kb
Host smart-f5a31d01-5064-4da2-a80f-603e081391c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855267001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.855267001
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3619074256
Short name T330
Test name
Test status
Simulation time 136467820052 ps
CPU time 44.17 seconds
Started Jul 15 04:31:49 PM PDT 24
Finished Jul 15 04:32:34 PM PDT 24
Peak memory 199756 kb
Host smart-8eaefb43-6de3-4ce7-924e-de5703fce9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619074256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3619074256
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1957412353
Short name T945
Test name
Test status
Simulation time 266664111206 ps
CPU time 467 seconds
Started Jul 15 04:31:47 PM PDT 24
Finished Jul 15 04:39:34 PM PDT 24
Peak memory 199708 kb
Host smart-e943afa1-8adb-4874-9a77-7d5c45b22ddc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957412353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1957412353
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2521486219
Short name T543
Test name
Test status
Simulation time 227181427023 ps
CPU time 156.25 seconds
Started Jul 15 04:31:49 PM PDT 24
Finished Jul 15 04:34:25 PM PDT 24
Peak memory 199736 kb
Host smart-8cd96d8f-9b37-4ff8-b69a-19f4df9b583c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521486219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2521486219
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3295289711
Short name T1033
Test name
Test status
Simulation time 4904722320 ps
CPU time 2.91 seconds
Started Jul 15 04:31:48 PM PDT 24
Finished Jul 15 04:31:51 PM PDT 24
Peak memory 198172 kb
Host smart-2f906ff0-9adf-4239-9af6-a13a0b5d1b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295289711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3295289711
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2352944470
Short name T509
Test name
Test status
Simulation time 190982836973 ps
CPU time 24.47 seconds
Started Jul 15 04:31:46 PM PDT 24
Finished Jul 15 04:32:11 PM PDT 24
Peak memory 208064 kb
Host smart-238dda4a-a625-401a-99f7-3555b277bef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352944470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2352944470
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.4088538458
Short name T605
Test name
Test status
Simulation time 32511318848 ps
CPU time 164.97 seconds
Started Jul 15 04:31:45 PM PDT 24
Finished Jul 15 04:34:31 PM PDT 24
Peak memory 199792 kb
Host smart-4ac058b6-4732-47b4-8f39-5ccff7ee4a65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4088538458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.4088538458
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2020419440
Short name T785
Test name
Test status
Simulation time 3277577564 ps
CPU time 17.59 seconds
Started Jul 15 04:31:46 PM PDT 24
Finished Jul 15 04:32:04 PM PDT 24
Peak memory 198932 kb
Host smart-69bb34bc-06cc-4641-9f9f-201a832cfccc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020419440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2020419440
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3216203253
Short name T594
Test name
Test status
Simulation time 57568398473 ps
CPU time 80.83 seconds
Started Jul 15 04:31:47 PM PDT 24
Finished Jul 15 04:33:09 PM PDT 24
Peak memory 199700 kb
Host smart-a4e14608-622c-4c4c-a01c-b0fca6aa2cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216203253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3216203253
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3766563282
Short name T861
Test name
Test status
Simulation time 2002270140 ps
CPU time 2.03 seconds
Started Jul 15 04:31:47 PM PDT 24
Finished Jul 15 04:31:50 PM PDT 24
Peak memory 195156 kb
Host smart-1b509179-81e3-426f-933a-8ba9904ce703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766563282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3766563282
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.900349962
Short name T95
Test name
Test status
Simulation time 890315102 ps
CPU time 3.17 seconds
Started Jul 15 04:31:42 PM PDT 24
Finished Jul 15 04:31:46 PM PDT 24
Peak memory 199664 kb
Host smart-ac651bd8-b7fb-448e-b4c7-18bfa5107674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900349962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.900349962
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.87251007
Short name T46
Test name
Test status
Simulation time 192688539472 ps
CPU time 285.7 seconds
Started Jul 15 04:31:51 PM PDT 24
Finished Jul 15 04:36:37 PM PDT 24
Peak memory 199664 kb
Host smart-d57f247e-752e-4da0-8071-cbb5b16abdc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87251007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.87251007
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1838209656
Short name T658
Test name
Test status
Simulation time 5995289323 ps
CPU time 76.24 seconds
Started Jul 15 04:31:53 PM PDT 24
Finished Jul 15 04:33:09 PM PDT 24
Peak memory 215832 kb
Host smart-99c89e03-781b-43d1-a6b2-87b20060fe1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838209656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1838209656
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2735771950
Short name T720
Test name
Test status
Simulation time 7127794234 ps
CPU time 19.72 seconds
Started Jul 15 04:31:49 PM PDT 24
Finished Jul 15 04:32:10 PM PDT 24
Peak memory 199644 kb
Host smart-368795b8-5d80-4573-9422-3ca681028242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735771950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2735771950
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1554162161
Short name T836
Test name
Test status
Simulation time 154538312311 ps
CPU time 57.29 seconds
Started Jul 15 04:31:49 PM PDT 24
Finished Jul 15 04:32:47 PM PDT 24
Peak memory 199656 kb
Host smart-93357116-313e-4f2a-8d01-89d06a1bf483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554162161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1554162161
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1396234868
Short name T1075
Test name
Test status
Simulation time 89808572925 ps
CPU time 62.31 seconds
Started Jul 15 04:34:46 PM PDT 24
Finished Jul 15 04:35:49 PM PDT 24
Peak memory 199736 kb
Host smart-b5910cb7-adf0-4826-934a-b915e0605b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396234868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1396234868
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.123779015
Short name T855
Test name
Test status
Simulation time 36318257587 ps
CPU time 28.28 seconds
Started Jul 15 04:34:49 PM PDT 24
Finished Jul 15 04:35:18 PM PDT 24
Peak memory 199560 kb
Host smart-9fdb46e0-57ce-43a6-b927-dd028968a16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123779015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.123779015
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.349948263
Short name T638
Test name
Test status
Simulation time 96519495112 ps
CPU time 145.59 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:37:14 PM PDT 24
Peak memory 199696 kb
Host smart-0f7254c8-a147-4b5f-b538-b0d6ab972e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349948263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.349948263
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1972544422
Short name T175
Test name
Test status
Simulation time 112632055876 ps
CPU time 90.08 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:36:18 PM PDT 24
Peak memory 199792 kb
Host smart-2832551e-e823-4f63-a5c3-9ee059851426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972544422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1972544422
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.4042547814
Short name T191
Test name
Test status
Simulation time 34934478809 ps
CPU time 148.29 seconds
Started Jul 15 04:34:48 PM PDT 24
Finished Jul 15 04:37:17 PM PDT 24
Peak memory 199756 kb
Host smart-67d70232-c420-4503-9186-2118fdb75dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042547814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.4042547814
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.373242039
Short name T686
Test name
Test status
Simulation time 46056388352 ps
CPU time 42.24 seconds
Started Jul 15 04:34:45 PM PDT 24
Finished Jul 15 04:35:28 PM PDT 24
Peak memory 199732 kb
Host smart-d8ae5a12-39ad-46a0-8895-511c3baadc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373242039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.373242039
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1748377848
Short name T838
Test name
Test status
Simulation time 35003158816 ps
CPU time 27.35 seconds
Started Jul 15 04:34:46 PM PDT 24
Finished Jul 15 04:35:15 PM PDT 24
Peak memory 199704 kb
Host smart-c8df4bc3-112a-4f51-8366-bd2dfa38efcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748377848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1748377848
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2221803210
Short name T92
Test name
Test status
Simulation time 61221067106 ps
CPU time 13.05 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:35:02 PM PDT 24
Peak memory 199748 kb
Host smart-03f6f4ea-42a7-4ebf-ab93-6d3dae0995d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221803210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2221803210
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1605893744
Short name T246
Test name
Test status
Simulation time 14387044888 ps
CPU time 13.15 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:35:01 PM PDT 24
Peak memory 199768 kb
Host smart-5486ce28-66fc-4277-bec3-8f0710448dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605893744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1605893744
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2822039229
Short name T305
Test name
Test status
Simulation time 103628816759 ps
CPU time 189.21 seconds
Started Jul 15 04:34:46 PM PDT 24
Finished Jul 15 04:37:56 PM PDT 24
Peak memory 199720 kb
Host smart-9fa81cf9-97d4-491e-a7ce-efda5b33ac72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822039229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2822039229
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1190354690
Short name T820
Test name
Test status
Simulation time 12312449 ps
CPU time 0.57 seconds
Started Jul 15 04:31:54 PM PDT 24
Finished Jul 15 04:31:55 PM PDT 24
Peak memory 194728 kb
Host smart-8cac9e0b-05b8-4561-b18e-6972c76aae6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190354690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1190354690
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3922125078
Short name T119
Test name
Test status
Simulation time 391958399602 ps
CPU time 370.22 seconds
Started Jul 15 04:31:49 PM PDT 24
Finished Jul 15 04:38:00 PM PDT 24
Peak memory 199732 kb
Host smart-1ddd82f2-5f8a-48b1-ab4e-722bf4a98290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922125078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3922125078
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2022508179
Short name T933
Test name
Test status
Simulation time 44818953895 ps
CPU time 35.27 seconds
Started Jul 15 04:31:51 PM PDT 24
Finished Jul 15 04:32:27 PM PDT 24
Peak memory 199448 kb
Host smart-c4c34fae-e6b3-48bb-bb24-114bcc42cf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022508179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2022508179
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2781705295
Short name T525
Test name
Test status
Simulation time 84499211991 ps
CPU time 133.8 seconds
Started Jul 15 04:31:46 PM PDT 24
Finished Jul 15 04:34:01 PM PDT 24
Peak memory 199672 kb
Host smart-a2330af6-1503-4200-813a-fde88cc70d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781705295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2781705295
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.590644778
Short name T997
Test name
Test status
Simulation time 49157758442 ps
CPU time 67.87 seconds
Started Jul 15 04:31:45 PM PDT 24
Finished Jul 15 04:32:54 PM PDT 24
Peak memory 199612 kb
Host smart-974cb8e7-a8cd-48c0-8db8-7b17f48fc13f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590644778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.590644778
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3309525560
Short name T280
Test name
Test status
Simulation time 120936559228 ps
CPU time 1383.22 seconds
Started Jul 15 04:31:47 PM PDT 24
Finished Jul 15 04:54:51 PM PDT 24
Peak memory 199796 kb
Host smart-0d64b499-ccbc-4fc7-b475-be1fc5e56e83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309525560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3309525560
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1907688088
Short name T1163
Test name
Test status
Simulation time 9192485718 ps
CPU time 18.28 seconds
Started Jul 15 04:31:49 PM PDT 24
Finished Jul 15 04:32:09 PM PDT 24
Peak memory 199344 kb
Host smart-4559eace-6e79-410e-8085-1acead775fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907688088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1907688088
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.31768468
Short name T615
Test name
Test status
Simulation time 52709106089 ps
CPU time 20.33 seconds
Started Jul 15 04:31:48 PM PDT 24
Finished Jul 15 04:32:09 PM PDT 24
Peak memory 198808 kb
Host smart-e7e54cc7-58a3-420a-95bb-594c5a54b19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31768468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.31768468
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1613357926
Short name T583
Test name
Test status
Simulation time 18790472288 ps
CPU time 486.2 seconds
Started Jul 15 04:31:49 PM PDT 24
Finished Jul 15 04:39:56 PM PDT 24
Peak memory 199800 kb
Host smart-f879c982-2a19-4ef2-9d7d-bf8ae0849198
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1613357926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1613357926
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.770703294
Short name T369
Test name
Test status
Simulation time 2026054303 ps
CPU time 2.53 seconds
Started Jul 15 04:31:48 PM PDT 24
Finished Jul 15 04:31:51 PM PDT 24
Peak memory 198932 kb
Host smart-8d1a96ba-973a-403b-8e97-445a4e983003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=770703294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.770703294
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1536773357
Short name T907
Test name
Test status
Simulation time 22976508019 ps
CPU time 37.23 seconds
Started Jul 15 04:31:47 PM PDT 24
Finished Jul 15 04:32:25 PM PDT 24
Peak memory 199680 kb
Host smart-b9816410-e03e-4f05-8154-8b9dc0fe4a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536773357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1536773357
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2524641285
Short name T547
Test name
Test status
Simulation time 5306914101 ps
CPU time 4.28 seconds
Started Jul 15 04:31:49 PM PDT 24
Finished Jul 15 04:31:54 PM PDT 24
Peak memory 196064 kb
Host smart-48b65848-4b55-4c3f-a171-4608dd9c14c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524641285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2524641285
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1181063257
Short name T871
Test name
Test status
Simulation time 945037135 ps
CPU time 0.97 seconds
Started Jul 15 04:31:47 PM PDT 24
Finished Jul 15 04:31:49 PM PDT 24
Peak memory 198044 kb
Host smart-dadfdeb2-e3bc-4bcc-bf61-9c5b0674832b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181063257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1181063257
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2616839876
Short name T678
Test name
Test status
Simulation time 182296779577 ps
CPU time 1733.55 seconds
Started Jul 15 04:31:53 PM PDT 24
Finished Jul 15 05:00:48 PM PDT 24
Peak memory 199692 kb
Host smart-ae404d0c-db00-4801-aed7-9940f4287371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616839876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2616839876
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2316557803
Short name T490
Test name
Test status
Simulation time 1017934620 ps
CPU time 3.46 seconds
Started Jul 15 04:31:49 PM PDT 24
Finished Jul 15 04:31:53 PM PDT 24
Peak memory 198324 kb
Host smart-06b45ebc-029d-425a-b966-2e66a44262b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316557803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2316557803
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3787327804
Short name T914
Test name
Test status
Simulation time 24587020216 ps
CPU time 23.5 seconds
Started Jul 15 04:31:47 PM PDT 24
Finished Jul 15 04:32:11 PM PDT 24
Peak memory 199756 kb
Host smart-6401effa-9dba-44e9-8526-40801a1c874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787327804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3787327804
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.10508795
Short name T388
Test name
Test status
Simulation time 24217745622 ps
CPU time 18.64 seconds
Started Jul 15 04:34:48 PM PDT 24
Finished Jul 15 04:35:07 PM PDT 24
Peak memory 199772 kb
Host smart-44d4268f-0c04-4297-892a-a22780597c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10508795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.10508795
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.795869262
Short name T984
Test name
Test status
Simulation time 13893033153 ps
CPU time 24.39 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:35:12 PM PDT 24
Peak memory 199736 kb
Host smart-1e3a63c5-953e-42f4-904f-d4467d26ccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795869262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.795869262
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2405466807
Short name T184
Test name
Test status
Simulation time 18252861494 ps
CPU time 21.1 seconds
Started Jul 15 04:34:46 PM PDT 24
Finished Jul 15 04:35:08 PM PDT 24
Peak memory 199728 kb
Host smart-10463d5a-eb92-484c-86e5-e6d4691c4712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405466807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2405466807
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.294198842
Short name T739
Test name
Test status
Simulation time 33557259804 ps
CPU time 23.05 seconds
Started Jul 15 04:34:47 PM PDT 24
Finished Jul 15 04:35:11 PM PDT 24
Peak memory 199800 kb
Host smart-e9517e58-bca2-49be-bba6-5807945a466f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294198842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.294198842
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.4200245221
Short name T308
Test name
Test status
Simulation time 90293232264 ps
CPU time 130.83 seconds
Started Jul 15 04:34:57 PM PDT 24
Finished Jul 15 04:37:08 PM PDT 24
Peak memory 199748 kb
Host smart-6f9c1310-0e0b-4e3e-be20-fa20ff97fdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200245221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.4200245221
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.726281107
Short name T967
Test name
Test status
Simulation time 142385133830 ps
CPU time 200.31 seconds
Started Jul 15 04:35:01 PM PDT 24
Finished Jul 15 04:38:22 PM PDT 24
Peak memory 199768 kb
Host smart-aa3005ab-a998-450e-84f3-560d9c732746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726281107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.726281107
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2004198593
Short name T679
Test name
Test status
Simulation time 90711254129 ps
CPU time 124.91 seconds
Started Jul 15 04:34:58 PM PDT 24
Finished Jul 15 04:37:04 PM PDT 24
Peak memory 199728 kb
Host smart-c468fbb5-63f2-4296-87a2-132d78c5d862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004198593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2004198593
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1812295472
Short name T955
Test name
Test status
Simulation time 264812802890 ps
CPU time 161.74 seconds
Started Jul 15 04:34:56 PM PDT 24
Finished Jul 15 04:37:39 PM PDT 24
Peak memory 199712 kb
Host smart-cca8fd21-2e6b-462d-abe3-ae4b47b3011e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812295472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1812295472
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1282361962
Short name T878
Test name
Test status
Simulation time 19543317789 ps
CPU time 24.92 seconds
Started Jul 15 04:34:57 PM PDT 24
Finished Jul 15 04:35:23 PM PDT 24
Peak memory 199612 kb
Host smart-c6869d92-49c6-4080-ac92-f884e1ff0517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282361962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1282361962
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.856985899
Short name T675
Test name
Test status
Simulation time 40048000685 ps
CPU time 31.52 seconds
Started Jul 15 04:34:56 PM PDT 24
Finished Jul 15 04:35:29 PM PDT 24
Peak memory 199792 kb
Host smart-25caa10f-76fd-455b-8628-70fae7af0df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856985899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.856985899
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3782261513
Short name T1106
Test name
Test status
Simulation time 63498390 ps
CPU time 0.51 seconds
Started Jul 15 04:31:56 PM PDT 24
Finished Jul 15 04:31:57 PM PDT 24
Peak memory 194536 kb
Host smart-df1a1c9c-b9a5-43db-9e05-39dd4f38d471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782261513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3782261513
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.4267984432
Short name T288
Test name
Test status
Simulation time 74365339343 ps
CPU time 105.95 seconds
Started Jul 15 04:31:58 PM PDT 24
Finished Jul 15 04:33:45 PM PDT 24
Peak memory 199712 kb
Host smart-1c2b039f-e74d-47c2-9a2a-3b27414b6d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267984432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.4267984432
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.89497430
Short name T403
Test name
Test status
Simulation time 16238764925 ps
CPU time 7.23 seconds
Started Jul 15 04:31:56 PM PDT 24
Finished Jul 15 04:32:04 PM PDT 24
Peak memory 199692 kb
Host smart-b739890a-775f-4c7a-bdd2-75937d78e11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89497430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.89497430
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2176399511
Short name T1022
Test name
Test status
Simulation time 25875409935 ps
CPU time 11.71 seconds
Started Jul 15 04:31:52 PM PDT 24
Finished Jul 15 04:32:05 PM PDT 24
Peak memory 199712 kb
Host smart-d5a25ed6-a06f-49e2-9b14-c9b423c9ad14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176399511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2176399511
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1348413007
Short name T40
Test name
Test status
Simulation time 3492738712 ps
CPU time 3.64 seconds
Started Jul 15 04:31:54 PM PDT 24
Finished Jul 15 04:31:58 PM PDT 24
Peak memory 196800 kb
Host smart-08848064-837c-4b49-b989-113b5666934f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348413007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1348413007
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3796408747
Short name T1102
Test name
Test status
Simulation time 68793953072 ps
CPU time 204.31 seconds
Started Jul 15 04:31:55 PM PDT 24
Finished Jul 15 04:35:20 PM PDT 24
Peak memory 199628 kb
Host smart-a3faaf63-ee42-492f-8f93-f1788b8740ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796408747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3796408747
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1360694843
Short name T527
Test name
Test status
Simulation time 1123079049 ps
CPU time 1.62 seconds
Started Jul 15 04:31:54 PM PDT 24
Finished Jul 15 04:31:56 PM PDT 24
Peak memory 198396 kb
Host smart-1fa887a3-22c2-4e65-86a6-a4ba6ce20941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360694843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1360694843
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2027464640
Short name T1031
Test name
Test status
Simulation time 140706299391 ps
CPU time 127.27 seconds
Started Jul 15 04:31:56 PM PDT 24
Finished Jul 15 04:34:04 PM PDT 24
Peak memory 208152 kb
Host smart-53a553e6-e9a6-4b81-9dc7-8d7ccace90be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027464640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2027464640
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.4267747585
Short name T448
Test name
Test status
Simulation time 24848072850 ps
CPU time 377.33 seconds
Started Jul 15 04:31:54 PM PDT 24
Finished Jul 15 04:38:12 PM PDT 24
Peak memory 199808 kb
Host smart-fff61895-d1ae-40d9-b9e4-2f0e600b7f55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267747585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.4267747585
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2872958939
Short name T1045
Test name
Test status
Simulation time 4966931174 ps
CPU time 8.82 seconds
Started Jul 15 04:31:54 PM PDT 24
Finished Jul 15 04:32:04 PM PDT 24
Peak memory 199016 kb
Host smart-5f8ccdb4-ce8b-4813-9cb2-212e6b1dc8b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872958939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2872958939
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3278041407
Short name T414
Test name
Test status
Simulation time 88211362392 ps
CPU time 160.86 seconds
Started Jul 15 04:31:55 PM PDT 24
Finished Jul 15 04:34:37 PM PDT 24
Peak memory 199796 kb
Host smart-2b0ef67b-fd27-4ab4-b919-33212f257460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278041407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3278041407
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1015422536
Short name T793
Test name
Test status
Simulation time 5201610979 ps
CPU time 7.71 seconds
Started Jul 15 04:31:52 PM PDT 24
Finished Jul 15 04:32:00 PM PDT 24
Peak memory 196516 kb
Host smart-34bbdb59-6221-41f1-9c83-c502a9c8f5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015422536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1015422536
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3765033859
Short name T323
Test name
Test status
Simulation time 5675867650 ps
CPU time 6.48 seconds
Started Jul 15 04:31:55 PM PDT 24
Finished Jul 15 04:32:02 PM PDT 24
Peak memory 199604 kb
Host smart-65ce7be1-c848-4fae-9643-6f797b09e4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765033859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3765033859
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2884048587
Short name T521
Test name
Test status
Simulation time 310874148344 ps
CPU time 364.29 seconds
Started Jul 15 04:31:53 PM PDT 24
Finished Jul 15 04:37:58 PM PDT 24
Peak memory 199664 kb
Host smart-2cd49685-dd9e-4a2b-b1ca-cc88a76a210d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884048587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2884048587
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1299287590
Short name T903
Test name
Test status
Simulation time 196585109814 ps
CPU time 444.04 seconds
Started Jul 15 04:31:57 PM PDT 24
Finished Jul 15 04:39:22 PM PDT 24
Peak memory 216216 kb
Host smart-990e5e8b-1451-48a4-9d97-c9c37d4100d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299287590 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1299287590
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2162023637
Short name T931
Test name
Test status
Simulation time 521736742 ps
CPU time 1.74 seconds
Started Jul 15 04:31:57 PM PDT 24
Finished Jul 15 04:31:59 PM PDT 24
Peak memory 198268 kb
Host smart-eb69c3f4-38ca-42ea-bc03-b48d61bdb72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162023637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2162023637
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.691242668
Short name T1170
Test name
Test status
Simulation time 14669772949 ps
CPU time 12.61 seconds
Started Jul 15 04:31:54 PM PDT 24
Finished Jul 15 04:32:07 PM PDT 24
Peak memory 199696 kb
Host smart-3832d865-c139-4902-a4b1-e834d6aa242b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691242668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.691242668
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2869417874
Short name T932
Test name
Test status
Simulation time 13496790546 ps
CPU time 22.47 seconds
Started Jul 15 04:34:56 PM PDT 24
Finished Jul 15 04:35:19 PM PDT 24
Peak memory 199484 kb
Host smart-2a9541fa-5ae4-497a-87a8-f37ad67d24ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869417874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2869417874
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1301209491
Short name T683
Test name
Test status
Simulation time 149782264668 ps
CPU time 104.07 seconds
Started Jul 15 04:35:00 PM PDT 24
Finished Jul 15 04:36:45 PM PDT 24
Peak memory 199732 kb
Host smart-703449db-acef-4533-98e6-8edd1aba0f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301209491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1301209491
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1003807642
Short name T732
Test name
Test status
Simulation time 105707111949 ps
CPU time 43.65 seconds
Started Jul 15 04:34:57 PM PDT 24
Finished Jul 15 04:35:42 PM PDT 24
Peak memory 199732 kb
Host smart-861f2b8d-053a-4fb0-b96d-541910d476a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003807642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1003807642
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2476395174
Short name T562
Test name
Test status
Simulation time 129026857059 ps
CPU time 49.4 seconds
Started Jul 15 04:34:58 PM PDT 24
Finished Jul 15 04:35:48 PM PDT 24
Peak memory 199700 kb
Host smart-e45b76c5-3848-4fc8-b034-fd5ede365df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476395174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2476395174
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3336039192
Short name T676
Test name
Test status
Simulation time 185448841077 ps
CPU time 42.25 seconds
Started Jul 15 04:34:57 PM PDT 24
Finished Jul 15 04:35:41 PM PDT 24
Peak memory 199672 kb
Host smart-64960626-471a-4520-8168-b0ce465c106f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336039192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3336039192
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2820457833
Short name T934
Test name
Test status
Simulation time 91952334702 ps
CPU time 176.55 seconds
Started Jul 15 04:34:56 PM PDT 24
Finished Jul 15 04:37:54 PM PDT 24
Peak memory 199748 kb
Host smart-f8d4e07d-32f7-4496-883a-a9e7b500fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820457833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2820457833
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2855992747
Short name T1151
Test name
Test status
Simulation time 40520006671 ps
CPU time 20.46 seconds
Started Jul 15 04:35:00 PM PDT 24
Finished Jul 15 04:35:21 PM PDT 24
Peak memory 199704 kb
Host smart-8eacb2d3-d8f4-4f2d-9635-ffc37b94b66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855992747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2855992747
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.429209391
Short name T193
Test name
Test status
Simulation time 18618086562 ps
CPU time 29.14 seconds
Started Jul 15 04:34:56 PM PDT 24
Finished Jul 15 04:35:26 PM PDT 24
Peak memory 199712 kb
Host smart-51c3371c-6125-48ad-a3ee-80ae638073d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429209391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.429209391
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.163350227
Short name T636
Test name
Test status
Simulation time 32193788 ps
CPU time 0.55 seconds
Started Jul 15 04:32:01 PM PDT 24
Finished Jul 15 04:32:02 PM PDT 24
Peak memory 195068 kb
Host smart-aaa21ad0-f7b5-40ed-8e38-e264c553efe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163350227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.163350227
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3319353347
Short name T249
Test name
Test status
Simulation time 127148260977 ps
CPU time 176.35 seconds
Started Jul 15 04:31:55 PM PDT 24
Finished Jul 15 04:34:52 PM PDT 24
Peak memory 199672 kb
Host smart-9dd28709-f73e-4c4b-8070-1cf70c212591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319353347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3319353347
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.121910698
Short name T476
Test name
Test status
Simulation time 128213690545 ps
CPU time 13.86 seconds
Started Jul 15 04:32:01 PM PDT 24
Finished Jul 15 04:32:16 PM PDT 24
Peak memory 199712 kb
Host smart-42d43061-1f84-41b0-9073-51e6c359054b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121910698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.121910698
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3812858615
Short name T310
Test name
Test status
Simulation time 126507613138 ps
CPU time 100.31 seconds
Started Jul 15 04:32:01 PM PDT 24
Finished Jul 15 04:33:42 PM PDT 24
Peak memory 199796 kb
Host smart-0b2405e1-bf74-486e-bee1-b77c8cfcc0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812858615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3812858615
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3919633480
Short name T901
Test name
Test status
Simulation time 76425221381 ps
CPU time 106.27 seconds
Started Jul 15 04:32:01 PM PDT 24
Finished Jul 15 04:33:48 PM PDT 24
Peak memory 199736 kb
Host smart-6416799b-c9e8-4f6a-9b36-82b27c64278d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919633480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3919633480
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1220709613
Short name T1012
Test name
Test status
Simulation time 40353125510 ps
CPU time 159.3 seconds
Started Jul 15 04:32:10 PM PDT 24
Finished Jul 15 04:34:52 PM PDT 24
Peak memory 199684 kb
Host smart-0db238e8-16a5-4543-8529-383995bc5be6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220709613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1220709613
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3330908111
Short name T780
Test name
Test status
Simulation time 7382166432 ps
CPU time 7.37 seconds
Started Jul 15 04:32:10 PM PDT 24
Finished Jul 15 04:32:20 PM PDT 24
Peak memory 197400 kb
Host smart-eb0a3013-9bef-4bdf-9806-595b3065ad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330908111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3330908111
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1264341129
Short name T886
Test name
Test status
Simulation time 104944784526 ps
CPU time 46.2 seconds
Started Jul 15 04:32:10 PM PDT 24
Finished Jul 15 04:32:59 PM PDT 24
Peak memory 198936 kb
Host smart-c4190cad-eea5-4a53-9b4a-39f806b46707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264341129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1264341129
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1722946571
Short name T726
Test name
Test status
Simulation time 14721241765 ps
CPU time 93.74 seconds
Started Jul 15 04:32:01 PM PDT 24
Finished Jul 15 04:33:35 PM PDT 24
Peak memory 199852 kb
Host smart-2879edc8-e2fd-41cd-96de-ca9e0e9a50ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722946571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1722946571
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.586750273
Short name T950
Test name
Test status
Simulation time 2764085176 ps
CPU time 5.82 seconds
Started Jul 15 04:32:02 PM PDT 24
Finished Jul 15 04:32:08 PM PDT 24
Peak memory 198248 kb
Host smart-ee57005a-dbb8-4495-b8ba-f98827f43a49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586750273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.586750273
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.739652891
Short name T957
Test name
Test status
Simulation time 29785526412 ps
CPU time 47.49 seconds
Started Jul 15 04:32:03 PM PDT 24
Finished Jul 15 04:32:50 PM PDT 24
Peak memory 199740 kb
Host smart-c80390aa-f380-442f-a855-5f290e7bb0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739652891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.739652891
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.4081334749
Short name T514
Test name
Test status
Simulation time 4568242857 ps
CPU time 2.22 seconds
Started Jul 15 04:32:03 PM PDT 24
Finished Jul 15 04:32:06 PM PDT 24
Peak memory 196184 kb
Host smart-af47e2e6-6961-49dd-95ec-c67801c3955a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081334749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.4081334749
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.4094049696
Short name T93
Test name
Test status
Simulation time 511053186 ps
CPU time 2.06 seconds
Started Jul 15 04:31:56 PM PDT 24
Finished Jul 15 04:31:59 PM PDT 24
Peak memory 199700 kb
Host smart-a474d196-e9c8-41ce-9326-937b6bec9427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094049696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.4094049696
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3715195035
Short name T697
Test name
Test status
Simulation time 313302397793 ps
CPU time 1062.54 seconds
Started Jul 15 04:32:02 PM PDT 24
Finished Jul 15 04:49:45 PM PDT 24
Peak memory 230748 kb
Host smart-f83dd71c-5b34-4244-8af4-1c94b475d77a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715195035 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3715195035
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.999647887
Short name T457
Test name
Test status
Simulation time 615319866 ps
CPU time 1.67 seconds
Started Jul 15 04:32:01 PM PDT 24
Finished Jul 15 04:32:04 PM PDT 24
Peak memory 197616 kb
Host smart-3b951f7c-186c-49dd-888f-511585615084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999647887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.999647887
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.108527321
Short name T682
Test name
Test status
Simulation time 78371476389 ps
CPU time 44.68 seconds
Started Jul 15 04:31:55 PM PDT 24
Finished Jul 15 04:32:40 PM PDT 24
Peak memory 199652 kb
Host smart-9da74016-6900-4070-89fd-8842846cc04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108527321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.108527321
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.790043270
Short name T1000
Test name
Test status
Simulation time 80617808099 ps
CPU time 86.67 seconds
Started Jul 15 04:34:58 PM PDT 24
Finished Jul 15 04:36:25 PM PDT 24
Peak memory 199660 kb
Host smart-1bdc5912-487c-4866-9e09-dc04d17109cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790043270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.790043270
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2937375312
Short name T426
Test name
Test status
Simulation time 13187910749 ps
CPU time 22.54 seconds
Started Jul 15 04:34:58 PM PDT 24
Finished Jul 15 04:35:22 PM PDT 24
Peak memory 199680 kb
Host smart-54bd7e15-0020-429d-8bf7-efe67a45f15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937375312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2937375312
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.863231281
Short name T841
Test name
Test status
Simulation time 73883020525 ps
CPU time 105.56 seconds
Started Jul 15 04:34:58 PM PDT 24
Finished Jul 15 04:36:44 PM PDT 24
Peak memory 199748 kb
Host smart-2cca0fee-f2fc-4da1-b8af-ef043e033e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863231281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.863231281
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.4005172769
Short name T510
Test name
Test status
Simulation time 8430453523 ps
CPU time 4.58 seconds
Started Jul 15 04:34:56 PM PDT 24
Finished Jul 15 04:35:01 PM PDT 24
Peak memory 199724 kb
Host smart-08960d33-1329-4c87-8b2c-7b47c7927ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005172769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.4005172769
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2212667485
Short name T194
Test name
Test status
Simulation time 10338394153 ps
CPU time 18.45 seconds
Started Jul 15 04:34:57 PM PDT 24
Finished Jul 15 04:35:17 PM PDT 24
Peak memory 199692 kb
Host smart-113a5d23-993e-4130-bf27-fc20fa23f63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212667485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2212667485
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.212271735
Short name T1046
Test name
Test status
Simulation time 63594450852 ps
CPU time 56.58 seconds
Started Jul 15 04:35:21 PM PDT 24
Finished Jul 15 04:36:19 PM PDT 24
Peak memory 199848 kb
Host smart-9a3032e6-c507-49be-b5bd-bc4f42cf2693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212271735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.212271735
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2793507320
Short name T1126
Test name
Test status
Simulation time 91819058965 ps
CPU time 30.72 seconds
Started Jul 15 04:35:09 PM PDT 24
Finished Jul 15 04:35:41 PM PDT 24
Peak memory 199708 kb
Host smart-67f3b229-a98f-43a1-9658-c1e60d160fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793507320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2793507320
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.948794471
Short name T219
Test name
Test status
Simulation time 218400974393 ps
CPU time 97.54 seconds
Started Jul 15 04:35:12 PM PDT 24
Finished Jul 15 04:36:51 PM PDT 24
Peak memory 199680 kb
Host smart-76098e94-9c85-480e-8aad-3c21f54cad3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948794471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.948794471
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2909092347
Short name T205
Test name
Test status
Simulation time 136059585233 ps
CPU time 48.86 seconds
Started Jul 15 04:35:09 PM PDT 24
Finished Jul 15 04:35:59 PM PDT 24
Peak memory 199736 kb
Host smart-05b5d09d-9d49-4be8-87ca-cdf4133cbc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909092347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2909092347
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.567454016
Short name T580
Test name
Test status
Simulation time 12017390 ps
CPU time 0.57 seconds
Started Jul 15 04:32:07 PM PDT 24
Finished Jul 15 04:32:09 PM PDT 24
Peak memory 194988 kb
Host smart-305a623a-6ada-4255-917f-12bd4e929478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567454016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.567454016
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1653171504
Short name T62
Test name
Test status
Simulation time 27548535618 ps
CPU time 22.37 seconds
Started Jul 15 04:32:01 PM PDT 24
Finished Jul 15 04:32:23 PM PDT 24
Peak memory 199696 kb
Host smart-a77e3e35-2154-4cef-801c-473568c1fa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653171504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1653171504
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2022559512
Short name T118
Test name
Test status
Simulation time 28588000339 ps
CPU time 49.59 seconds
Started Jul 15 04:32:07 PM PDT 24
Finished Jul 15 04:32:58 PM PDT 24
Peak memory 199760 kb
Host smart-1e053cb9-7109-42cc-bc62-6ff9be6d4437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022559512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2022559512
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2371981853
Short name T389
Test name
Test status
Simulation time 283243018756 ps
CPU time 28.29 seconds
Started Jul 15 04:32:10 PM PDT 24
Finished Jul 15 04:32:41 PM PDT 24
Peak memory 199728 kb
Host smart-1066d0c0-db2c-45c8-9225-3f48c08e4dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371981853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2371981853
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2652261874
Short name T968
Test name
Test status
Simulation time 31405554575 ps
CPU time 15.98 seconds
Started Jul 15 04:32:04 PM PDT 24
Finished Jul 15 04:32:20 PM PDT 24
Peak memory 199488 kb
Host smart-8ec91ba0-28f8-4bd0-b652-39c2e1ee49ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652261874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2652261874
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2861626984
Short name T747
Test name
Test status
Simulation time 107588888368 ps
CPU time 269.67 seconds
Started Jul 15 04:32:07 PM PDT 24
Finished Jul 15 04:36:38 PM PDT 24
Peak memory 199680 kb
Host smart-94bce21f-fcd9-4d09-a98f-44b310443b3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861626984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2861626984
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.674999889
Short name T350
Test name
Test status
Simulation time 10275058655 ps
CPU time 19.03 seconds
Started Jul 15 04:32:07 PM PDT 24
Finished Jul 15 04:32:28 PM PDT 24
Peak memory 198544 kb
Host smart-375bd35e-b62e-4dfd-9943-804c0f30ac28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674999889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.674999889
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1761813147
Short name T974
Test name
Test status
Simulation time 42346115523 ps
CPU time 32.27 seconds
Started Jul 15 04:32:01 PM PDT 24
Finished Jul 15 04:32:34 PM PDT 24
Peak memory 199324 kb
Host smart-0ca152b8-ab37-46f4-837a-b9dee2df7c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761813147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1761813147
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1238202622
Short name T309
Test name
Test status
Simulation time 31149193502 ps
CPU time 1584.81 seconds
Started Jul 15 04:32:08 PM PDT 24
Finished Jul 15 04:58:35 PM PDT 24
Peak memory 199792 kb
Host smart-02c230da-d0b2-41ba-81de-1df20e5b1621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1238202622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1238202622
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3969790860
Short name T913
Test name
Test status
Simulation time 4745215776 ps
CPU time 35.32 seconds
Started Jul 15 04:32:08 PM PDT 24
Finished Jul 15 04:32:45 PM PDT 24
Peak memory 197964 kb
Host smart-2d89270a-cb0e-4859-8930-eedaec202f15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969790860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3969790860
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3618247194
Short name T1005
Test name
Test status
Simulation time 104753610260 ps
CPU time 253.53 seconds
Started Jul 15 04:32:04 PM PDT 24
Finished Jul 15 04:36:18 PM PDT 24
Peak memory 199620 kb
Host smart-aad9d592-9e13-41eb-9dc0-4bc824a1a7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618247194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3618247194
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1239500189
Short name T1173
Test name
Test status
Simulation time 5946995367 ps
CPU time 5.41 seconds
Started Jul 15 04:32:02 PM PDT 24
Finished Jul 15 04:32:08 PM PDT 24
Peak memory 196220 kb
Host smart-384dfab0-aa12-4379-8ee5-53300debdb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239500189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1239500189
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2912986113
Short name T487
Test name
Test status
Simulation time 5515070556 ps
CPU time 7.37 seconds
Started Jul 15 04:32:10 PM PDT 24
Finished Jul 15 04:32:20 PM PDT 24
Peak memory 199652 kb
Host smart-5397dbca-d970-4b51-9ad2-7fa59c71d1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912986113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2912986113
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1060400631
Short name T801
Test name
Test status
Simulation time 291444623801 ps
CPU time 214.26 seconds
Started Jul 15 04:32:08 PM PDT 24
Finished Jul 15 04:35:43 PM PDT 24
Peak memory 199692 kb
Host smart-8346ece5-206f-48e8-b4be-8659f7076e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060400631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1060400631
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2610473295
Short name T925
Test name
Test status
Simulation time 39705499079 ps
CPU time 245.35 seconds
Started Jul 15 04:32:10 PM PDT 24
Finished Jul 15 04:36:17 PM PDT 24
Peak memory 216440 kb
Host smart-c22ec2eb-a374-4ac1-a6c5-4f8e9d8ccd0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610473295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2610473295
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.479044318
Short name T1003
Test name
Test status
Simulation time 2614983278 ps
CPU time 1.48 seconds
Started Jul 15 04:32:08 PM PDT 24
Finished Jul 15 04:32:12 PM PDT 24
Peak memory 198144 kb
Host smart-f963d074-ba37-4885-aeea-da4dbdccd6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479044318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.479044318
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2181988895
Short name T830
Test name
Test status
Simulation time 21761742538 ps
CPU time 30.25 seconds
Started Jul 15 04:32:10 PM PDT 24
Finished Jul 15 04:32:43 PM PDT 24
Peak memory 199396 kb
Host smart-ebdaedbc-2cd8-434f-bb68-53bf60783a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181988895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2181988895
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.226623049
Short name T215
Test name
Test status
Simulation time 98485125892 ps
CPU time 32.35 seconds
Started Jul 15 04:35:09 PM PDT 24
Finished Jul 15 04:35:43 PM PDT 24
Peak memory 199768 kb
Host smart-7f2b94e9-dc11-4ecf-927f-27d4d3d84160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226623049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.226623049
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2742294230
Short name T301
Test name
Test status
Simulation time 116492305838 ps
CPU time 91.9 seconds
Started Jul 15 04:35:09 PM PDT 24
Finished Jul 15 04:36:42 PM PDT 24
Peak memory 199732 kb
Host smart-230fa418-d897-43f0-b6e6-878f8b70f016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742294230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2742294230
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2328421947
Short name T240
Test name
Test status
Simulation time 125293571120 ps
CPU time 83.39 seconds
Started Jul 15 04:35:11 PM PDT 24
Finished Jul 15 04:36:35 PM PDT 24
Peak memory 199724 kb
Host smart-c27738cb-a344-4582-b6c2-76c80b946197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328421947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2328421947
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3448686793
Short name T771
Test name
Test status
Simulation time 38090198017 ps
CPU time 14.27 seconds
Started Jul 15 04:35:09 PM PDT 24
Finished Jul 15 04:35:25 PM PDT 24
Peak memory 199760 kb
Host smart-0278f9f8-f130-43ea-b5dc-a59c84846cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448686793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3448686793
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3844438105
Short name T1082
Test name
Test status
Simulation time 92962808565 ps
CPU time 134.75 seconds
Started Jul 15 04:35:08 PM PDT 24
Finished Jul 15 04:37:24 PM PDT 24
Peak memory 199732 kb
Host smart-255becda-b71b-4af7-a37f-c9255b27a054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844438105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3844438105
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.747398453
Short name T453
Test name
Test status
Simulation time 26930445505 ps
CPU time 15.76 seconds
Started Jul 15 04:35:12 PM PDT 24
Finished Jul 15 04:35:29 PM PDT 24
Peak memory 199796 kb
Host smart-241e1eb0-a13c-42c9-8a38-27a192bd1e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747398453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.747398453
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1368081751
Short name T217
Test name
Test status
Simulation time 71842864271 ps
CPU time 186.5 seconds
Started Jul 15 04:35:10 PM PDT 24
Finished Jul 15 04:38:18 PM PDT 24
Peak memory 199832 kb
Host smart-8714c47e-dde5-452c-a8b1-88a9df9ab91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368081751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1368081751
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2856217975
Short name T727
Test name
Test status
Simulation time 250212332719 ps
CPU time 37.16 seconds
Started Jul 15 04:35:15 PM PDT 24
Finished Jul 15 04:35:53 PM PDT 24
Peak memory 199672 kb
Host smart-eb21f6eb-0776-489e-ac1a-09723464e777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856217975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2856217975
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1047883449
Short name T163
Test name
Test status
Simulation time 75153607673 ps
CPU time 41.01 seconds
Started Jul 15 04:35:11 PM PDT 24
Finished Jul 15 04:35:53 PM PDT 24
Peak memory 199680 kb
Host smart-2a39d9fe-6072-4fd3-84e4-dc6551f3d8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047883449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1047883449
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2832365368
Short name T326
Test name
Test status
Simulation time 17884393 ps
CPU time 0.52 seconds
Started Jul 15 04:32:08 PM PDT 24
Finished Jul 15 04:32:10 PM PDT 24
Peak memory 194600 kb
Host smart-3d6f9ace-703c-4b17-b6f3-16c2bbb457ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832365368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2832365368
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1081239622
Short name T416
Test name
Test status
Simulation time 111115191397 ps
CPU time 154.04 seconds
Started Jul 15 04:32:08 PM PDT 24
Finished Jul 15 04:34:43 PM PDT 24
Peak memory 199668 kb
Host smart-16d06fa3-c9f7-4a6b-9c3f-90561ebb5c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081239622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1081239622
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2981222864
Short name T665
Test name
Test status
Simulation time 38806308093 ps
CPU time 34.27 seconds
Started Jul 15 04:32:06 PM PDT 24
Finished Jul 15 04:32:42 PM PDT 24
Peak memory 199640 kb
Host smart-3a518cfe-0213-44cd-9cb1-45b2dbb0f797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981222864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2981222864
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1768388843
Short name T166
Test name
Test status
Simulation time 10403751321 ps
CPU time 18.66 seconds
Started Jul 15 04:32:09 PM PDT 24
Finished Jul 15 04:32:30 PM PDT 24
Peak memory 199788 kb
Host smart-cb11c478-66e9-47a9-8d72-ee3dc872676a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768388843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1768388843
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3762085287
Short name T472
Test name
Test status
Simulation time 6677599042 ps
CPU time 4.24 seconds
Started Jul 15 04:32:08 PM PDT 24
Finished Jul 15 04:32:14 PM PDT 24
Peak memory 195964 kb
Host smart-749d10b5-87c7-4885-b6ac-18322fd54cb3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762085287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3762085287
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.76235428
Short name T721
Test name
Test status
Simulation time 82566517319 ps
CPU time 650.24 seconds
Started Jul 15 04:32:08 PM PDT 24
Finished Jul 15 04:43:01 PM PDT 24
Peak memory 199796 kb
Host smart-bebb16af-d61d-44a5-a0dc-ee1e02e46c49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76235428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.76235428
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2751483854
Short name T715
Test name
Test status
Simulation time 10145000394 ps
CPU time 6.52 seconds
Started Jul 15 04:32:07 PM PDT 24
Finished Jul 15 04:32:14 PM PDT 24
Peak memory 198220 kb
Host smart-d3b97f00-0e3f-4946-a7ec-5c567b3ecf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751483854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2751483854
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2338199353
Short name T1138
Test name
Test status
Simulation time 20256649681 ps
CPU time 33.2 seconds
Started Jul 15 04:32:09 PM PDT 24
Finished Jul 15 04:32:45 PM PDT 24
Peak memory 199960 kb
Host smart-f500606e-ce0b-478a-977e-96ac1774497a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338199353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2338199353
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1872309493
Short name T601
Test name
Test status
Simulation time 21766701102 ps
CPU time 941.78 seconds
Started Jul 15 04:32:12 PM PDT 24
Finished Jul 15 04:47:55 PM PDT 24
Peak memory 199684 kb
Host smart-6937b059-2fb4-474f-b4f3-133f3eaa6207
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872309493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1872309493
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.2145209328
Short name T408
Test name
Test status
Simulation time 5678415467 ps
CPU time 23.53 seconds
Started Jul 15 04:32:09 PM PDT 24
Finished Jul 15 04:32:34 PM PDT 24
Peak memory 197600 kb
Host smart-9b8a1ba7-e506-4be6-a4b0-75a6498a6b49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145209328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2145209328
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.4191480584
Short name T432
Test name
Test status
Simulation time 2683414042 ps
CPU time 5.15 seconds
Started Jul 15 04:32:10 PM PDT 24
Finished Jul 15 04:32:18 PM PDT 24
Peak memory 195572 kb
Host smart-a0bc9c52-d268-4e68-a335-65d1542179eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191480584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.4191480584
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.544953411
Short name T270
Test name
Test status
Simulation time 861978055 ps
CPU time 1.91 seconds
Started Jul 15 04:32:10 PM PDT 24
Finished Jul 15 04:32:14 PM PDT 24
Peak memory 198556 kb
Host smart-9fb2084c-f8d1-4cc0-8a45-1683a2640f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544953411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.544953411
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.4170293729
Short name T127
Test name
Test status
Simulation time 157320952109 ps
CPU time 264.32 seconds
Started Jul 15 04:32:14 PM PDT 24
Finished Jul 15 04:36:39 PM PDT 24
Peak memory 208092 kb
Host smart-34b399fa-16fd-4b74-8ec9-9deda6f2b151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170293729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.4170293729
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3485598115
Short name T292
Test name
Test status
Simulation time 53046720413 ps
CPU time 337.63 seconds
Started Jul 15 04:32:08 PM PDT 24
Finished Jul 15 04:37:48 PM PDT 24
Peak memory 215520 kb
Host smart-b8e654fd-f4a3-4fa4-a8ae-c2a8b297e905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485598115 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3485598115
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2617889771
Short name T773
Test name
Test status
Simulation time 996533190 ps
CPU time 1.91 seconds
Started Jul 15 04:32:09 PM PDT 24
Finished Jul 15 04:32:13 PM PDT 24
Peak memory 198160 kb
Host smart-2c7056ae-be69-416d-b2a4-572566f3f428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617889771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2617889771
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.237673186
Short name T322
Test name
Test status
Simulation time 98755497366 ps
CPU time 12.76 seconds
Started Jul 15 04:32:08 PM PDT 24
Finished Jul 15 04:32:22 PM PDT 24
Peak memory 199700 kb
Host smart-ee840ea9-514e-471f-a7d0-35708af2ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237673186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.237673186
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3934733095
Short name T706
Test name
Test status
Simulation time 42141506438 ps
CPU time 75.79 seconds
Started Jul 15 04:35:09 PM PDT 24
Finished Jul 15 04:36:26 PM PDT 24
Peak memory 199764 kb
Host smart-f2ba16ca-4b2a-4653-93cc-bedfca71f785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934733095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3934733095
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2397241921
Short name T929
Test name
Test status
Simulation time 65456683610 ps
CPU time 96.14 seconds
Started Jul 15 04:35:11 PM PDT 24
Finished Jul 15 04:36:48 PM PDT 24
Peak memory 199768 kb
Host smart-d556404c-a22e-4cf1-a01c-981440f9ee34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397241921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2397241921
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1519224834
Short name T438
Test name
Test status
Simulation time 43771146638 ps
CPU time 27.52 seconds
Started Jul 15 04:35:08 PM PDT 24
Finished Jul 15 04:35:37 PM PDT 24
Peak memory 199728 kb
Host smart-17fae08e-1110-4a74-a5c8-b294fd061d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519224834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1519224834
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3051728197
Short name T430
Test name
Test status
Simulation time 193356043989 ps
CPU time 73.3 seconds
Started Jul 15 04:35:09 PM PDT 24
Finished Jul 15 04:36:24 PM PDT 24
Peak memory 199700 kb
Host smart-94bffc63-5522-481b-bdfe-daaa9c7a7349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051728197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3051728197
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3588472426
Short name T496
Test name
Test status
Simulation time 96674318625 ps
CPU time 38.62 seconds
Started Jul 15 04:35:09 PM PDT 24
Finished Jul 15 04:35:48 PM PDT 24
Peak memory 199800 kb
Host smart-8facaae5-417d-490d-952d-e52ea913434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588472426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3588472426
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1717175530
Short name T858
Test name
Test status
Simulation time 18261439519 ps
CPU time 25.07 seconds
Started Jul 15 04:35:11 PM PDT 24
Finished Jul 15 04:35:37 PM PDT 24
Peak memory 199764 kb
Host smart-18fa2813-644f-4614-98d0-b31a37ebabb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717175530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1717175530
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2227412786
Short name T495
Test name
Test status
Simulation time 17152467914 ps
CPU time 33.52 seconds
Started Jul 15 04:35:12 PM PDT 24
Finished Jul 15 04:35:47 PM PDT 24
Peak memory 199828 kb
Host smart-ac9dc287-c7ab-46d1-9904-ae4e7c86f0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227412786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2227412786
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2823721215
Short name T155
Test name
Test status
Simulation time 26164387810 ps
CPU time 38.13 seconds
Started Jul 15 04:35:12 PM PDT 24
Finished Jul 15 04:35:51 PM PDT 24
Peak memory 199640 kb
Host smart-b1a48525-6cc6-49c1-9b3c-8ebf61792ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823721215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2823721215
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.4219986126
Short name T1020
Test name
Test status
Simulation time 33463541564 ps
CPU time 39.31 seconds
Started Jul 15 04:35:14 PM PDT 24
Finished Jul 15 04:35:53 PM PDT 24
Peak memory 199772 kb
Host smart-54ce7aa3-506a-424e-ad57-5e1ca193b956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219986126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.4219986126
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1778724931
Short name T666
Test name
Test status
Simulation time 11338954 ps
CPU time 0.51 seconds
Started Jul 15 04:32:15 PM PDT 24
Finished Jul 15 04:32:16 PM PDT 24
Peak memory 194060 kb
Host smart-c3aa8232-2b9c-4d23-87f5-4966ca63260d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778724931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1778724931
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3449040383
Short name T610
Test name
Test status
Simulation time 59282676803 ps
CPU time 108.39 seconds
Started Jul 15 04:32:07 PM PDT 24
Finished Jul 15 04:33:57 PM PDT 24
Peak memory 199656 kb
Host smart-da25c262-4a51-4fca-8353-d8d5f8e1036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449040383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3449040383
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1905972718
Short name T63
Test name
Test status
Simulation time 45022004262 ps
CPU time 37.65 seconds
Started Jul 15 04:32:09 PM PDT 24
Finished Jul 15 04:32:49 PM PDT 24
Peak memory 199784 kb
Host smart-7fb52eef-4abc-494f-ad55-9f22e10129ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905972718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1905972718
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2202018778
Short name T942
Test name
Test status
Simulation time 14672334630 ps
CPU time 11.24 seconds
Started Jul 15 04:32:07 PM PDT 24
Finished Jul 15 04:32:20 PM PDT 24
Peak memory 198704 kb
Host smart-5ec1a768-d1fe-4fd7-b0f2-1ab3e795fba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202018778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2202018778
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2401831594
Short name T279
Test name
Test status
Simulation time 56200550469 ps
CPU time 72.78 seconds
Started Jul 15 04:32:07 PM PDT 24
Finished Jul 15 04:33:22 PM PDT 24
Peak memory 199432 kb
Host smart-c093cae3-fb74-4be4-b257-476ac5c898ef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401831594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2401831594
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1653233443
Short name T928
Test name
Test status
Simulation time 45291710120 ps
CPU time 241.94 seconds
Started Jul 15 04:32:16 PM PDT 24
Finished Jul 15 04:36:19 PM PDT 24
Peak memory 199668 kb
Host smart-05873448-5b64-494b-96d9-c4746d4bdd6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653233443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1653233443
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.365581112
Short name T620
Test name
Test status
Simulation time 7029573463 ps
CPU time 13.15 seconds
Started Jul 15 04:32:08 PM PDT 24
Finished Jul 15 04:32:23 PM PDT 24
Peak memory 198272 kb
Host smart-5d2453c2-dcf3-436d-9715-3973c59b340b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365581112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.365581112
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.622998411
Short name T110
Test name
Test status
Simulation time 149690508731 ps
CPU time 70.98 seconds
Started Jul 15 04:32:12 PM PDT 24
Finished Jul 15 04:33:24 PM PDT 24
Peak memory 208160 kb
Host smart-32e4ac8d-19a8-4f47-bb1b-a3ba00cfbfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622998411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.622998411
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3177798691
Short name T446
Test name
Test status
Simulation time 15996860856 ps
CPU time 813.41 seconds
Started Jul 15 04:32:16 PM PDT 24
Finished Jul 15 04:45:50 PM PDT 24
Peak memory 199836 kb
Host smart-f4ac4616-f236-496e-b239-c94145f7605b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177798691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3177798691
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3972602881
Short name T339
Test name
Test status
Simulation time 6314491757 ps
CPU time 12.27 seconds
Started Jul 15 04:32:09 PM PDT 24
Finished Jul 15 04:32:23 PM PDT 24
Peak memory 197988 kb
Host smart-2d5081f6-b850-42ce-bcad-e5b44c1f8574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3972602881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3972602881
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1193928797
Short name T483
Test name
Test status
Simulation time 100750642818 ps
CPU time 69.16 seconds
Started Jul 15 04:32:10 PM PDT 24
Finished Jul 15 04:33:21 PM PDT 24
Peak memory 199648 kb
Host smart-af0966bc-dc59-4bc6-a3d1-41c92764caed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193928797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1193928797
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3517191796
Short name T332
Test name
Test status
Simulation time 618650767 ps
CPU time 0.84 seconds
Started Jul 15 04:32:06 PM PDT 24
Finished Jul 15 04:32:08 PM PDT 24
Peak memory 195128 kb
Host smart-e4903031-1651-41a0-b1fd-3bed4ca671ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517191796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3517191796
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.673349615
Short name T654
Test name
Test status
Simulation time 912330822 ps
CPU time 1.32 seconds
Started Jul 15 04:32:06 PM PDT 24
Finished Jul 15 04:32:09 PM PDT 24
Peak memory 198464 kb
Host smart-dc797be7-ede2-4f7a-803a-d9dced5eea43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673349615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.673349615
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2972920644
Short name T488
Test name
Test status
Simulation time 684122715462 ps
CPU time 161.04 seconds
Started Jul 15 04:32:16 PM PDT 24
Finished Jul 15 04:34:58 PM PDT 24
Peak memory 199740 kb
Host smart-38e5fc62-bfd3-4835-bbba-ae4edbde1a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972920644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2972920644
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.290809697
Short name T508
Test name
Test status
Simulation time 68070432206 ps
CPU time 1044.21 seconds
Started Jul 15 04:32:17 PM PDT 24
Finished Jul 15 04:49:43 PM PDT 24
Peak memory 216528 kb
Host smart-a0a2b6bb-3a54-460e-80cc-64aef22eb47c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290809697 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.290809697
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1443559642
Short name T828
Test name
Test status
Simulation time 6629393178 ps
CPU time 12.36 seconds
Started Jul 15 04:32:14 PM PDT 24
Finished Jul 15 04:32:27 PM PDT 24
Peak memory 199048 kb
Host smart-608b9902-6a9b-4332-b07c-73aeed20766e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443559642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1443559642
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.339693579
Short name T894
Test name
Test status
Simulation time 53194965584 ps
CPU time 84.97 seconds
Started Jul 15 04:32:09 PM PDT 24
Finished Jul 15 04:33:37 PM PDT 24
Peak memory 199824 kb
Host smart-6b40d866-7d11-40d1-af97-5c1ba78256cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339693579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.339693579
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3145391348
Short name T606
Test name
Test status
Simulation time 22145496908 ps
CPU time 29 seconds
Started Jul 15 04:35:08 PM PDT 24
Finished Jul 15 04:35:38 PM PDT 24
Peak memory 199816 kb
Host smart-7f54ee98-7811-49c9-8b82-03dc182273db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145391348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3145391348
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.4251390718
Short name T970
Test name
Test status
Simulation time 16615375474 ps
CPU time 31.03 seconds
Started Jul 15 04:35:17 PM PDT 24
Finished Jul 15 04:35:48 PM PDT 24
Peak memory 199696 kb
Host smart-00cae114-7af9-4cf8-b213-d9367c15f5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251390718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4251390718
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2272604320
Short name T268
Test name
Test status
Simulation time 23673425872 ps
CPU time 34.29 seconds
Started Jul 15 04:35:21 PM PDT 24
Finished Jul 15 04:35:56 PM PDT 24
Peak memory 199696 kb
Host smart-02dfed87-e96f-4066-934f-dc7d1bde464b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272604320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2272604320
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1060832968
Short name T992
Test name
Test status
Simulation time 34043780559 ps
CPU time 61.68 seconds
Started Jul 15 04:35:19 PM PDT 24
Finished Jul 15 04:36:21 PM PDT 24
Peak memory 199716 kb
Host smart-241d9265-b0d8-47dc-9913-70d15e283d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060832968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1060832968
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1123200997
Short name T1078
Test name
Test status
Simulation time 125845267384 ps
CPU time 29.55 seconds
Started Jul 15 04:35:19 PM PDT 24
Finished Jul 15 04:35:49 PM PDT 24
Peak memory 199676 kb
Host smart-a653298d-bed6-4ec3-a394-c1aa683a3aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123200997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1123200997
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3177720776
Short name T167
Test name
Test status
Simulation time 4721406722 ps
CPU time 7.5 seconds
Started Jul 15 04:35:22 PM PDT 24
Finished Jul 15 04:35:30 PM PDT 24
Peak memory 199788 kb
Host smart-c0914ae6-f3e6-4952-87db-25bd49012d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177720776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3177720776
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2378648504
Short name T179
Test name
Test status
Simulation time 34091089929 ps
CPU time 31.18 seconds
Started Jul 15 04:35:19 PM PDT 24
Finished Jul 15 04:35:52 PM PDT 24
Peak memory 199708 kb
Host smart-709ba1f2-5b61-4b49-a69e-88c47256603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378648504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2378648504
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3417293416
Short name T943
Test name
Test status
Simulation time 30522373641 ps
CPU time 43.3 seconds
Started Jul 15 04:35:20 PM PDT 24
Finished Jul 15 04:36:04 PM PDT 24
Peak memory 199736 kb
Host smart-3d81a3ef-51ab-430f-b562-187135347440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417293416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3417293416
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.526394998
Short name T687
Test name
Test status
Simulation time 8676130702 ps
CPU time 15.9 seconds
Started Jul 15 04:35:20 PM PDT 24
Finished Jul 15 04:35:37 PM PDT 24
Peak memory 199732 kb
Host smart-b00f1e24-15ac-45f2-a404-764959796626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526394998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.526394998
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.337641820
Short name T581
Test name
Test status
Simulation time 15471738 ps
CPU time 0.56 seconds
Started Jul 15 04:32:21 PM PDT 24
Finished Jul 15 04:32:23 PM PDT 24
Peak memory 195056 kb
Host smart-286a340f-33a0-4591-841e-bf377619277d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337641820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.337641820
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1769844834
Short name T877
Test name
Test status
Simulation time 131632854029 ps
CPU time 131.23 seconds
Started Jul 15 04:32:16 PM PDT 24
Finished Jul 15 04:34:28 PM PDT 24
Peak memory 199608 kb
Host smart-44244568-16e7-41fc-9fbf-48794639d8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769844834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1769844834
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1844586363
Short name T283
Test name
Test status
Simulation time 175372639090 ps
CPU time 82.41 seconds
Started Jul 15 04:32:17 PM PDT 24
Finished Jul 15 04:33:41 PM PDT 24
Peak memory 199784 kb
Host smart-b5ac8cd0-c91f-422c-b8f7-a24d7641f972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844586363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1844586363
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1320518422
Short name T1068
Test name
Test status
Simulation time 175505330519 ps
CPU time 21.91 seconds
Started Jul 15 04:32:16 PM PDT 24
Finished Jul 15 04:32:38 PM PDT 24
Peak memory 199800 kb
Host smart-84a72e1d-204c-466b-8908-aea2825dd7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320518422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1320518422
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.160038385
Short name T844
Test name
Test status
Simulation time 311501242465 ps
CPU time 503.64 seconds
Started Jul 15 04:32:17 PM PDT 24
Finished Jul 15 04:40:41 PM PDT 24
Peak memory 199008 kb
Host smart-5fd33ba0-0afe-4832-aeba-0f178e31f9ac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160038385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.160038385
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.407621859
Short name T32
Test name
Test status
Simulation time 45088497547 ps
CPU time 292.28 seconds
Started Jul 15 04:32:19 PM PDT 24
Finished Jul 15 04:37:12 PM PDT 24
Peak memory 199664 kb
Host smart-852001d1-a391-4222-90a0-69b64b59ceaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=407621859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.407621859
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.435709146
Short name T596
Test name
Test status
Simulation time 1392158750 ps
CPU time 1.55 seconds
Started Jul 15 04:32:17 PM PDT 24
Finished Jul 15 04:32:20 PM PDT 24
Peak memory 198288 kb
Host smart-993829ef-c8f8-42f1-8349-6f3489b87aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435709146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.435709146
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2376429261
Short name T806
Test name
Test status
Simulation time 50153496453 ps
CPU time 43.77 seconds
Started Jul 15 04:32:17 PM PDT 24
Finished Jul 15 04:33:02 PM PDT 24
Peak memory 199292 kb
Host smart-54f4dd72-4193-4e1f-82be-a667fc764ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376429261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2376429261
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.4087529992
Short name T667
Test name
Test status
Simulation time 24372851323 ps
CPU time 1121.67 seconds
Started Jul 15 04:32:19 PM PDT 24
Finished Jul 15 04:51:02 PM PDT 24
Peak memory 199712 kb
Host smart-7bd662a5-c1d2-459b-b41a-297260740946
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087529992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.4087529992
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3846125984
Short name T380
Test name
Test status
Simulation time 2845278669 ps
CPU time 4.93 seconds
Started Jul 15 04:32:17 PM PDT 24
Finished Jul 15 04:32:23 PM PDT 24
Peak memory 197860 kb
Host smart-c83e65d9-a70c-485a-8f90-c14da9ab9676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3846125984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3846125984
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2948265185
Short name T156
Test name
Test status
Simulation time 268101533865 ps
CPU time 79.15 seconds
Started Jul 15 04:32:17 PM PDT 24
Finished Jul 15 04:33:37 PM PDT 24
Peak memory 199788 kb
Host smart-5959673e-2437-4578-a6ec-d121f0fe5586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948265185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2948265185
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.4004886335
Short name T1073
Test name
Test status
Simulation time 63224970297 ps
CPU time 23.72 seconds
Started Jul 15 04:32:18 PM PDT 24
Finished Jul 15 04:32:43 PM PDT 24
Peak memory 195976 kb
Host smart-64890f39-19f9-4612-9cc4-4f2886c89da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004886335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.4004886335
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2132134883
Short name T737
Test name
Test status
Simulation time 653055990 ps
CPU time 2.4 seconds
Started Jul 15 04:32:16 PM PDT 24
Finished Jul 15 04:32:19 PM PDT 24
Peak memory 199632 kb
Host smart-a2a4b26d-e580-4157-bd7d-fca9260171d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132134883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2132134883
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3210891025
Short name T904
Test name
Test status
Simulation time 68412422066 ps
CPU time 429.42 seconds
Started Jul 15 04:32:19 PM PDT 24
Finished Jul 15 04:39:29 PM PDT 24
Peak memory 216236 kb
Host smart-c025a7d5-30e6-4ae0-8a1c-a023cdf482e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210891025 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3210891025
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.587609886
Short name T906
Test name
Test status
Simulation time 6684259176 ps
CPU time 21.77 seconds
Started Jul 15 04:32:18 PM PDT 24
Finished Jul 15 04:32:41 PM PDT 24
Peak memory 199176 kb
Host smart-d9846dee-5a9e-49e0-91a3-023e71f71e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587609886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.587609886
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.13619510
Short name T643
Test name
Test status
Simulation time 190723010560 ps
CPU time 21.18 seconds
Started Jul 15 04:32:16 PM PDT 24
Finished Jul 15 04:32:38 PM PDT 24
Peak memory 199800 kb
Host smart-a3d04c6a-f347-4dff-8ee9-4bfe48af03f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13619510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.13619510
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.354203853
Short name T1120
Test name
Test status
Simulation time 119782281221 ps
CPU time 49.94 seconds
Started Jul 15 04:35:21 PM PDT 24
Finished Jul 15 04:36:12 PM PDT 24
Peak memory 199688 kb
Host smart-9db878ec-70da-4e11-8be7-98a22fff121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354203853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.354203853
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.4143167293
Short name T173
Test name
Test status
Simulation time 60825148720 ps
CPU time 84.75 seconds
Started Jul 15 04:35:18 PM PDT 24
Finished Jul 15 04:36:44 PM PDT 24
Peak memory 199624 kb
Host smart-c245f86f-144b-4502-8393-29eda8ff5985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143167293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.4143167293
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.4242426079
Short name T539
Test name
Test status
Simulation time 39537375804 ps
CPU time 17.86 seconds
Started Jul 15 04:35:19 PM PDT 24
Finished Jul 15 04:35:38 PM PDT 24
Peak memory 199724 kb
Host smart-90ee16a2-b45e-4d17-a5a5-00c66ce89399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242426079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4242426079
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.4178024360
Short name T188
Test name
Test status
Simulation time 27238349257 ps
CPU time 24.07 seconds
Started Jul 15 04:35:36 PM PDT 24
Finished Jul 15 04:36:00 PM PDT 24
Peak memory 199716 kb
Host smart-bcb9cbae-8269-43f2-acc4-b9c54916c788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178024360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.4178024360
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3364739067
Short name T1015
Test name
Test status
Simulation time 55507137188 ps
CPU time 164.82 seconds
Started Jul 15 04:35:18 PM PDT 24
Finished Jul 15 04:38:04 PM PDT 24
Peak memory 199732 kb
Host smart-59509c4b-4e06-4a94-9ec6-02600b46607b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364739067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3364739067
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3415205301
Short name T784
Test name
Test status
Simulation time 21462453742 ps
CPU time 29.62 seconds
Started Jul 15 04:35:20 PM PDT 24
Finished Jul 15 04:35:50 PM PDT 24
Peak memory 198616 kb
Host smart-3350470c-0467-46e4-964d-0e165236e947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415205301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3415205301
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.41234804
Short name T764
Test name
Test status
Simulation time 114122806650 ps
CPU time 195.9 seconds
Started Jul 15 04:35:19 PM PDT 24
Finished Jul 15 04:38:36 PM PDT 24
Peak memory 199844 kb
Host smart-4d4364c2-9513-4b5a-ba2a-65a93b301885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41234804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.41234804
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2947833421
Short name T845
Test name
Test status
Simulation time 11919195257 ps
CPU time 19.18 seconds
Started Jul 15 04:35:19 PM PDT 24
Finished Jul 15 04:35:39 PM PDT 24
Peak memory 199704 kb
Host smart-9d07a023-db69-47a3-8d81-2f30b6eb33f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947833421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2947833421
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3591084706
Short name T26
Test name
Test status
Simulation time 192268456341 ps
CPU time 363.39 seconds
Started Jul 15 04:35:18 PM PDT 24
Finished Jul 15 04:41:23 PM PDT 24
Peak memory 199704 kb
Host smart-b8d81157-a770-492a-93ca-2fffc2c73c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591084706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3591084706
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3259297064
Short name T199
Test name
Test status
Simulation time 61842622398 ps
CPU time 95.4 seconds
Started Jul 15 04:35:19 PM PDT 24
Finished Jul 15 04:36:55 PM PDT 24
Peak memory 199860 kb
Host smart-9ffb58e2-d2e8-4cda-b72a-3ec498845e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259297064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3259297064
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1359842858
Short name T783
Test name
Test status
Simulation time 35795944 ps
CPU time 0.53 seconds
Started Jul 15 04:30:30 PM PDT 24
Finished Jul 15 04:30:32 PM PDT 24
Peak memory 195376 kb
Host smart-e342d261-9c9d-45e2-bf4d-aaaf771b09ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359842858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1359842858
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.266170640
Short name T59
Test name
Test status
Simulation time 26355671251 ps
CPU time 41.24 seconds
Started Jul 15 04:30:27 PM PDT 24
Finished Jul 15 04:31:10 PM PDT 24
Peak memory 199652 kb
Host smart-e634d794-ed9d-4978-9267-5a5af20b74c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266170640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.266170640
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2564665915
Short name T1044
Test name
Test status
Simulation time 44013676244 ps
CPU time 68.51 seconds
Started Jul 15 04:30:51 PM PDT 24
Finished Jul 15 04:32:01 PM PDT 24
Peak memory 199740 kb
Host smart-2c88fc5a-ffbb-4217-ae61-3ce51cfb4fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564665915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2564665915
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2807849940
Short name T317
Test name
Test status
Simulation time 1152771051 ps
CPU time 2.87 seconds
Started Jul 15 04:30:24 PM PDT 24
Finished Jul 15 04:30:29 PM PDT 24
Peak memory 198940 kb
Host smart-8ba9015a-6d3d-4d6f-8876-ae87a218d8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807849940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2807849940
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3990064727
Short name T16
Test name
Test status
Simulation time 28594104955 ps
CPU time 32.96 seconds
Started Jul 15 04:30:29 PM PDT 24
Finished Jul 15 04:31:04 PM PDT 24
Peak memory 198184 kb
Host smart-3f4252c3-bde9-4748-908f-b7df545e83cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990064727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3990064727
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1968849678
Short name T1032
Test name
Test status
Simulation time 66456744581 ps
CPU time 138.33 seconds
Started Jul 15 04:30:29 PM PDT 24
Finished Jul 15 04:32:50 PM PDT 24
Peak memory 199712 kb
Host smart-e7431d88-4497-476a-9e08-91fe11f40419
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1968849678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1968849678
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1758236048
Short name T799
Test name
Test status
Simulation time 6315739036 ps
CPU time 8.89 seconds
Started Jul 15 04:30:26 PM PDT 24
Finished Jul 15 04:30:37 PM PDT 24
Peak memory 197904 kb
Host smart-efe1b14a-546f-421e-914f-f35836b189fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758236048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1758236048
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.4197055108
Short name T867
Test name
Test status
Simulation time 90503635017 ps
CPU time 139.24 seconds
Started Jul 15 04:30:34 PM PDT 24
Finished Jul 15 04:32:54 PM PDT 24
Peak memory 200072 kb
Host smart-1b4eeea1-c512-4900-8571-24d1d2403453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197055108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.4197055108
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.407198128
Short name T1069
Test name
Test status
Simulation time 6935012375 ps
CPU time 127.48 seconds
Started Jul 15 04:30:21 PM PDT 24
Finished Jul 15 04:32:30 PM PDT 24
Peak memory 199644 kb
Host smart-63f72fa2-8451-4260-88ce-d712e753a337
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=407198128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.407198128
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.103070041
Short name T1004
Test name
Test status
Simulation time 2853110039 ps
CPU time 7.61 seconds
Started Jul 15 04:30:21 PM PDT 24
Finished Jul 15 04:30:30 PM PDT 24
Peak memory 197620 kb
Host smart-6b442ef3-fe2b-4712-9e46-e1db25ac30e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103070041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.103070041
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.394968698
Short name T755
Test name
Test status
Simulation time 59628993645 ps
CPU time 54.12 seconds
Started Jul 15 04:30:25 PM PDT 24
Finished Jul 15 04:31:21 PM PDT 24
Peak memory 199628 kb
Host smart-71801d02-87b9-4354-bb12-69b69cf14367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394968698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.394968698
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.360607622
Short name T238
Test name
Test status
Simulation time 6686998471 ps
CPU time 3.18 seconds
Started Jul 15 04:30:26 PM PDT 24
Finished Jul 15 04:30:31 PM PDT 24
Peak memory 195924 kb
Host smart-b7758724-8261-4598-a63f-3e12094a6317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360607622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.360607622
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.549314600
Short name T89
Test name
Test status
Simulation time 66201055 ps
CPU time 0.88 seconds
Started Jul 15 04:30:26 PM PDT 24
Finished Jul 15 04:30:29 PM PDT 24
Peak memory 218056 kb
Host smart-5fe379b7-7934-45f1-8a73-e655c630cca7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549314600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.549314600
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2773156442
Short name T567
Test name
Test status
Simulation time 459313314 ps
CPU time 1.11 seconds
Started Jul 15 04:30:33 PM PDT 24
Finished Jul 15 04:30:35 PM PDT 24
Peak memory 198368 kb
Host smart-47c30422-d5bd-4269-ae3d-c090930acd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773156442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2773156442
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2481877928
Short name T412
Test name
Test status
Simulation time 343544118058 ps
CPU time 1464.29 seconds
Started Jul 15 04:30:24 PM PDT 24
Finished Jul 15 04:54:50 PM PDT 24
Peak memory 199692 kb
Host smart-51df9e95-2057-4e2a-b34e-e41b64f546b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481877928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2481877928
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2064863693
Short name T30
Test name
Test status
Simulation time 20889210639 ps
CPU time 123.38 seconds
Started Jul 15 04:30:39 PM PDT 24
Finished Jul 15 04:32:44 PM PDT 24
Peak memory 208300 kb
Host smart-f187fdda-14a1-4f48-9621-400e3227da3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064863693 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2064863693
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3546123949
Short name T39
Test name
Test status
Simulation time 6820607280 ps
CPU time 12 seconds
Started Jul 15 04:30:33 PM PDT 24
Finished Jul 15 04:30:46 PM PDT 24
Peak memory 199132 kb
Host smart-e1a36e4a-1104-4da3-b695-45520edbaca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546123949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3546123949
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.170566933
Short name T401
Test name
Test status
Simulation time 39853754302 ps
CPU time 78.88 seconds
Started Jul 15 04:30:31 PM PDT 24
Finished Jul 15 04:31:52 PM PDT 24
Peak memory 199784 kb
Host smart-42d0a540-c4b8-4648-8cdf-f7bbb24fc116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170566933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.170566933
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.522351937
Short name T919
Test name
Test status
Simulation time 20399871 ps
CPU time 0.54 seconds
Started Jul 15 04:32:21 PM PDT 24
Finished Jul 15 04:32:22 PM PDT 24
Peak memory 194080 kb
Host smart-cb2a7b55-ede6-4bb4-b0ad-2623ce28a5a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522351937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.522351937
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2435559803
Short name T328
Test name
Test status
Simulation time 47858312013 ps
CPU time 65.34 seconds
Started Jul 15 04:32:23 PM PDT 24
Finished Jul 15 04:33:30 PM PDT 24
Peak memory 199660 kb
Host smart-7cfa896d-b02e-48cc-9ec9-d58a2d73917a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435559803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2435559803
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.4040868116
Short name T1042
Test name
Test status
Simulation time 20205615913 ps
CPU time 27.49 seconds
Started Jul 15 04:32:22 PM PDT 24
Finished Jul 15 04:32:51 PM PDT 24
Peak memory 199624 kb
Host smart-4e891f86-cd0d-444b-b859-99d4ce009a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040868116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4040868116
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_intr.3395254118
Short name T253
Test name
Test status
Simulation time 27707220501 ps
CPU time 39.17 seconds
Started Jul 15 04:32:21 PM PDT 24
Finished Jul 15 04:33:02 PM PDT 24
Peak memory 199724 kb
Host smart-939cc1ed-3ed1-4a51-b98c-152212c15d6c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395254118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3395254118
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2662922464
Short name T1016
Test name
Test status
Simulation time 65123594670 ps
CPU time 586.28 seconds
Started Jul 15 04:32:33 PM PDT 24
Finished Jul 15 04:42:20 PM PDT 24
Peak memory 200012 kb
Host smart-28ad6c64-1537-4260-8f03-c10f120dd120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662922464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2662922464
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.4026143403
Short name T960
Test name
Test status
Simulation time 10817006404 ps
CPU time 9.13 seconds
Started Jul 15 04:32:22 PM PDT 24
Finished Jul 15 04:32:33 PM PDT 24
Peak memory 199832 kb
Host smart-274e3fa1-4241-460c-9b75-7859dae61324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026143403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.4026143403
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3168870179
Short name T1049
Test name
Test status
Simulation time 16152853284 ps
CPU time 28.31 seconds
Started Jul 15 04:32:22 PM PDT 24
Finished Jul 15 04:32:52 PM PDT 24
Peak memory 199948 kb
Host smart-a6cd0152-9164-4391-bebd-b6fd320828da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168870179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3168870179
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.135071879
Short name T336
Test name
Test status
Simulation time 7762929590 ps
CPU time 68.47 seconds
Started Jul 15 04:32:21 PM PDT 24
Finished Jul 15 04:33:30 PM PDT 24
Peak memory 199736 kb
Host smart-a9f9ff5a-c3db-4375-a318-af50e8423179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135071879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.135071879
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.472381731
Short name T374
Test name
Test status
Simulation time 4455048616 ps
CPU time 2.9 seconds
Started Jul 15 04:32:22 PM PDT 24
Finished Jul 15 04:32:26 PM PDT 24
Peak memory 197996 kb
Host smart-ddb2ffdc-b0a6-401a-98bf-1ae65abf2fe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=472381731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.472381731
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.344242665
Short name T804
Test name
Test status
Simulation time 17796268320 ps
CPU time 39.72 seconds
Started Jul 15 04:32:22 PM PDT 24
Finished Jul 15 04:33:03 PM PDT 24
Peak memory 199756 kb
Host smart-e9e933e4-d938-4c69-890d-65d354455c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344242665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.344242665
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2103207633
Short name T1169
Test name
Test status
Simulation time 4906128092 ps
CPU time 7.45 seconds
Started Jul 15 04:32:21 PM PDT 24
Finished Jul 15 04:32:30 PM PDT 24
Peak memory 195984 kb
Host smart-01f68ac2-18c2-4470-9f7e-71ca3c42d15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103207633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2103207633
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2831890449
Short name T1145
Test name
Test status
Simulation time 6071228735 ps
CPU time 38.86 seconds
Started Jul 15 04:32:22 PM PDT 24
Finished Jul 15 04:33:02 PM PDT 24
Peak memory 199520 kb
Host smart-d66c19ed-04e1-4092-9cdc-1bc43a973790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831890449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2831890449
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1560706016
Short name T1059
Test name
Test status
Simulation time 114409221674 ps
CPU time 123.87 seconds
Started Jul 15 04:32:21 PM PDT 24
Finished Jul 15 04:34:26 PM PDT 24
Peak memory 199752 kb
Host smart-80039036-ae7b-4022-9987-0f2b2f99d186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560706016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1560706016
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.85207534
Short name T52
Test name
Test status
Simulation time 44632218415 ps
CPU time 485.71 seconds
Started Jul 15 04:32:21 PM PDT 24
Finished Jul 15 04:40:28 PM PDT 24
Peak memory 216308 kb
Host smart-e8155f8a-e268-45a2-a3ff-208c280358cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85207534 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.85207534
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3082702987
Short name T409
Test name
Test status
Simulation time 1514715861 ps
CPU time 1.58 seconds
Started Jul 15 04:32:23 PM PDT 24
Finished Jul 15 04:32:26 PM PDT 24
Peak memory 198536 kb
Host smart-28eb5a56-0689-4610-a722-94b0da4f11dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082702987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3082702987
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.416605500
Short name T1029
Test name
Test status
Simulation time 17822779898 ps
CPU time 7.48 seconds
Started Jul 15 04:32:23 PM PDT 24
Finished Jul 15 04:32:32 PM PDT 24
Peak memory 198904 kb
Host smart-352a1ee2-1b73-48c5-98b5-3135ed9aac05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416605500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.416605500
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.330873017
Short name T381
Test name
Test status
Simulation time 25608514 ps
CPU time 0.53 seconds
Started Jul 15 04:32:38 PM PDT 24
Finished Jul 15 04:32:40 PM PDT 24
Peak memory 193640 kb
Host smart-03f44b10-6f0d-4afb-ac88-a982c0441dac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330873017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.330873017
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.933859118
Short name T835
Test name
Test status
Simulation time 47475621822 ps
CPU time 18.57 seconds
Started Jul 15 04:32:24 PM PDT 24
Finished Jul 15 04:32:43 PM PDT 24
Peak memory 199712 kb
Host smart-4fb39904-eab5-4892-bc3a-cae7be2a2b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933859118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.933859118
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1003668979
Short name T652
Test name
Test status
Simulation time 55499805952 ps
CPU time 49.37 seconds
Started Jul 15 04:32:22 PM PDT 24
Finished Jul 15 04:33:12 PM PDT 24
Peak memory 199764 kb
Host smart-d6682a64-5808-42d6-9f9f-db45332ac58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003668979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1003668979
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.478456900
Short name T1099
Test name
Test status
Simulation time 22310647985 ps
CPU time 18.41 seconds
Started Jul 15 04:32:22 PM PDT 24
Finished Jul 15 04:32:41 PM PDT 24
Peak memory 199500 kb
Host smart-03c9a060-dd35-4c3e-9c57-fba7d85c9013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478456900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.478456900
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2348875539
Short name T299
Test name
Test status
Simulation time 80620853060 ps
CPU time 68.07 seconds
Started Jul 15 04:32:25 PM PDT 24
Finished Jul 15 04:33:34 PM PDT 24
Peak memory 200080 kb
Host smart-450f81ef-6a6d-4b28-8db4-1e29dd20b485
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348875539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2348875539
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1606404791
Short name T772
Test name
Test status
Simulation time 197321422099 ps
CPU time 102.32 seconds
Started Jul 15 04:32:28 PM PDT 24
Finished Jul 15 04:34:12 PM PDT 24
Peak memory 199792 kb
Host smart-21e9d0a3-f1ba-4254-a4d6-6a4e06bcc0e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606404791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1606404791
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.4257015595
Short name T1161
Test name
Test status
Simulation time 10251220561 ps
CPU time 22.39 seconds
Started Jul 15 04:32:30 PM PDT 24
Finished Jul 15 04:32:54 PM PDT 24
Peak memory 199700 kb
Host smart-bf704977-36c5-44c2-84d4-3650d69b0260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257015595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.4257015595
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1427472224
Short name T485
Test name
Test status
Simulation time 78533259130 ps
CPU time 30.21 seconds
Started Jul 15 04:32:20 PM PDT 24
Finished Jul 15 04:32:51 PM PDT 24
Peak memory 199900 kb
Host smart-e3cc2238-55d1-4d1d-9a42-1877c96ba630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427472224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1427472224
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3907923893
Short name T622
Test name
Test status
Simulation time 17736593743 ps
CPU time 891.39 seconds
Started Jul 15 04:32:31 PM PDT 24
Finished Jul 15 04:47:24 PM PDT 24
Peak memory 199720 kb
Host smart-6462e951-93bd-4600-b63a-db37db3f3341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3907923893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3907923893
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2286391367
Short name T529
Test name
Test status
Simulation time 5876778833 ps
CPU time 23.97 seconds
Started Jul 15 04:32:22 PM PDT 24
Finished Jul 15 04:32:47 PM PDT 24
Peak memory 198920 kb
Host smart-d3d72446-ee55-492d-9547-8b67c2a8d52d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286391367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2286391367
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3587550169
Short name T467
Test name
Test status
Simulation time 24464538094 ps
CPU time 32.55 seconds
Started Jul 15 04:32:29 PM PDT 24
Finished Jul 15 04:33:03 PM PDT 24
Peak memory 199468 kb
Host smart-1fcc251f-2d2e-47ac-8308-a9e970b11a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587550169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3587550169
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.4223533600
Short name T546
Test name
Test status
Simulation time 39467434559 ps
CPU time 13.88 seconds
Started Jul 15 04:32:30 PM PDT 24
Finished Jul 15 04:32:45 PM PDT 24
Peak memory 195464 kb
Host smart-36377b62-f051-4c81-86c9-53fed28581c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223533600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4223533600
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2285222349
Short name T331
Test name
Test status
Simulation time 267283339 ps
CPU time 1.81 seconds
Started Jul 15 04:32:24 PM PDT 24
Finished Jul 15 04:32:27 PM PDT 24
Peak memory 198256 kb
Host smart-1eb38883-64ba-47ac-91f6-900f5afa13e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285222349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2285222349
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1681241363
Short name T748
Test name
Test status
Simulation time 9131384222 ps
CPU time 8.83 seconds
Started Jul 15 04:32:29 PM PDT 24
Finished Jul 15 04:32:39 PM PDT 24
Peak memory 199448 kb
Host smart-e4c41bbd-282f-4132-8fd3-84d2645ccfe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681241363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1681241363
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.327863337
Short name T1050
Test name
Test status
Simulation time 161549335851 ps
CPU time 589.18 seconds
Started Jul 15 04:32:29 PM PDT 24
Finished Jul 15 04:42:20 PM PDT 24
Peak memory 229848 kb
Host smart-ea509413-89b2-4e18-9fe7-7ca749fc3317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327863337 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.327863337
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1533610307
Short name T690
Test name
Test status
Simulation time 681037277 ps
CPU time 1.36 seconds
Started Jul 15 04:32:29 PM PDT 24
Finished Jul 15 04:32:31 PM PDT 24
Peak memory 198180 kb
Host smart-1383d72f-33b0-4e7c-90c7-7f7dabed9236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533610307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1533610307
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.799153091
Short name T1153
Test name
Test status
Simulation time 43999623489 ps
CPU time 99.28 seconds
Started Jul 15 04:32:22 PM PDT 24
Finished Jul 15 04:34:03 PM PDT 24
Peak memory 199652 kb
Host smart-2ee309b3-6e4c-4f04-960f-eb92ef1031d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799153091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.799153091
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.4112404963
Short name T699
Test name
Test status
Simulation time 24373723 ps
CPU time 0.57 seconds
Started Jul 15 04:32:38 PM PDT 24
Finished Jul 15 04:32:40 PM PDT 24
Peak memory 195120 kb
Host smart-5621e2b2-152f-4f49-a209-e9ab7578b1ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112404963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.4112404963
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1075533252
Short name T589
Test name
Test status
Simulation time 153622191496 ps
CPU time 68.46 seconds
Started Jul 15 04:32:28 PM PDT 24
Finished Jul 15 04:33:38 PM PDT 24
Peak memory 199612 kb
Host smart-b998ee13-791f-4e2f-a725-6e2f2c326645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075533252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1075533252
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3314378192
Short name T762
Test name
Test status
Simulation time 12532213259 ps
CPU time 16.58 seconds
Started Jul 15 04:32:28 PM PDT 24
Finished Jul 15 04:32:46 PM PDT 24
Peak memory 199680 kb
Host smart-891e0296-60d8-477d-ab4d-356193aee861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314378192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3314378192
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2723671254
Short name T149
Test name
Test status
Simulation time 59393117683 ps
CPU time 26.11 seconds
Started Jul 15 04:32:31 PM PDT 24
Finished Jul 15 04:32:58 PM PDT 24
Peak memory 199792 kb
Host smart-febde8bc-339b-4edf-9d2e-41b3b8a7131e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723671254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2723671254
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3349755831
Short name T502
Test name
Test status
Simulation time 40954519971 ps
CPU time 19.36 seconds
Started Jul 15 04:32:30 PM PDT 24
Finished Jul 15 04:32:51 PM PDT 24
Peak memory 199776 kb
Host smart-ddd931cf-dff6-46e4-8e21-46ba73b1041e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349755831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3349755831
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1298684785
Short name T402
Test name
Test status
Simulation time 103623115061 ps
CPU time 524.13 seconds
Started Jul 15 04:32:28 PM PDT 24
Finished Jul 15 04:41:13 PM PDT 24
Peak memory 199656 kb
Host smart-a4bded59-4226-45d5-9e29-68fdf100afde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1298684785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1298684785
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2895031556
Short name T603
Test name
Test status
Simulation time 4281472666 ps
CPU time 5.13 seconds
Started Jul 15 04:32:27 PM PDT 24
Finished Jul 15 04:32:33 PM PDT 24
Peak memory 198868 kb
Host smart-c69e071d-c637-496b-a260-f8909ff8f74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895031556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2895031556
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.923559040
Short name T863
Test name
Test status
Simulation time 107792694113 ps
CPU time 55.92 seconds
Started Jul 15 04:32:29 PM PDT 24
Finished Jul 15 04:33:26 PM PDT 24
Peak memory 199868 kb
Host smart-a526f608-0dcf-4d61-81e9-398be9a61a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923559040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.923559040
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3166414056
Short name T856
Test name
Test status
Simulation time 11318134399 ps
CPU time 120.89 seconds
Started Jul 15 04:32:29 PM PDT 24
Finished Jul 15 04:34:32 PM PDT 24
Peak memory 199724 kb
Host smart-1230c6a4-3b5c-43ad-bd7a-ef1a2011fd60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166414056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3166414056
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3604778022
Short name T660
Test name
Test status
Simulation time 3157803517 ps
CPU time 18.84 seconds
Started Jul 15 04:32:30 PM PDT 24
Finished Jul 15 04:32:51 PM PDT 24
Peak memory 198064 kb
Host smart-f2b34fc7-7638-4d58-b935-e88e30e4f5ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604778022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3604778022
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3422085511
Short name T634
Test name
Test status
Simulation time 54257006687 ps
CPU time 87.48 seconds
Started Jul 15 04:32:38 PM PDT 24
Finished Jul 15 04:34:07 PM PDT 24
Peak memory 199792 kb
Host smart-96eac327-568d-444d-bbe2-fba2c6feb6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422085511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3422085511
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2823781906
Short name T393
Test name
Test status
Simulation time 5065476642 ps
CPU time 5.24 seconds
Started Jul 15 04:32:28 PM PDT 24
Finished Jul 15 04:32:34 PM PDT 24
Peak memory 196656 kb
Host smart-760eb4f1-04ca-4b61-ad24-9b8a98050278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823781906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2823781906
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.158927647
Short name T569
Test name
Test status
Simulation time 5447039360 ps
CPU time 13 seconds
Started Jul 15 04:32:29 PM PDT 24
Finished Jul 15 04:32:44 PM PDT 24
Peak memory 199672 kb
Host smart-7281955a-5d5e-4f6f-8329-3e57a2c806d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158927647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.158927647
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.736716297
Short name T659
Test name
Test status
Simulation time 194712555116 ps
CPU time 587.52 seconds
Started Jul 15 04:32:28 PM PDT 24
Finished Jul 15 04:42:17 PM PDT 24
Peak memory 208160 kb
Host smart-44899911-2f36-48d8-92f2-063f90f0328d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736716297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.736716297
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1572670716
Short name T692
Test name
Test status
Simulation time 80620867417 ps
CPU time 698.86 seconds
Started Jul 15 04:32:29 PM PDT 24
Finished Jul 15 04:44:10 PM PDT 24
Peak memory 216288 kb
Host smart-62184042-7aff-4d4d-925b-f4de9a7985e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572670716 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1572670716
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.66832307
Short name T319
Test name
Test status
Simulation time 5190943192 ps
CPU time 2.08 seconds
Started Jul 15 04:32:28 PM PDT 24
Finished Jul 15 04:32:31 PM PDT 24
Peak memory 198484 kb
Host smart-b9654bff-dc26-48d5-9978-edeed44327b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66832307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.66832307
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2556792520
Short name T260
Test name
Test status
Simulation time 35818491544 ps
CPU time 8.23 seconds
Started Jul 15 04:32:29 PM PDT 24
Finished Jul 15 04:32:38 PM PDT 24
Peak memory 199732 kb
Host smart-6531e873-46a1-4767-879a-ced9adfcd0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556792520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2556792520
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.179557554
Short name T335
Test name
Test status
Simulation time 48376355 ps
CPU time 0.53 seconds
Started Jul 15 04:32:36 PM PDT 24
Finished Jul 15 04:32:37 PM PDT 24
Peak memory 195368 kb
Host smart-5c091b69-928b-48f2-8d75-07d130ad2fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179557554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.179557554
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1689892068
Short name T37
Test name
Test status
Simulation time 39561888158 ps
CPU time 25.41 seconds
Started Jul 15 04:32:30 PM PDT 24
Finished Jul 15 04:32:57 PM PDT 24
Peak memory 199828 kb
Host smart-9544e9b9-d636-4b21-a8dd-729365680fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689892068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1689892068
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1716489137
Short name T920
Test name
Test status
Simulation time 55695366829 ps
CPU time 27.38 seconds
Started Jul 15 04:32:31 PM PDT 24
Finished Jul 15 04:33:00 PM PDT 24
Peak memory 199500 kb
Host smart-8578c7c2-611e-4c55-9e1a-8b6b502ead04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716489137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1716489137
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.858049857
Short name T158
Test name
Test status
Simulation time 145686268932 ps
CPU time 44.91 seconds
Started Jul 15 04:32:37 PM PDT 24
Finished Jul 15 04:33:23 PM PDT 24
Peak memory 199800 kb
Host smart-a25fa196-987d-4078-a30f-47cf8485635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858049857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.858049857
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3404768241
Short name T387
Test name
Test status
Simulation time 205136473544 ps
CPU time 61.42 seconds
Started Jul 15 04:32:37 PM PDT 24
Finished Jul 15 04:33:39 PM PDT 24
Peak memory 199808 kb
Host smart-4ef16108-6b66-4dc9-8aeb-946f058b9d87
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404768241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3404768241
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2797589918
Short name T379
Test name
Test status
Simulation time 201272147444 ps
CPU time 251.75 seconds
Started Jul 15 04:32:37 PM PDT 24
Finished Jul 15 04:36:51 PM PDT 24
Peak memory 200012 kb
Host smart-5ad96683-338b-424f-a680-fbf502d9bd82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2797589918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2797589918
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.551916338
Short name T987
Test name
Test status
Simulation time 3348039985 ps
CPU time 8.2 seconds
Started Jul 15 04:32:36 PM PDT 24
Finished Jul 15 04:32:45 PM PDT 24
Peak memory 199580 kb
Host smart-9a6f34f5-1041-487b-896c-b518b25bb945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551916338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.551916338
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3822132765
Short name T1122
Test name
Test status
Simulation time 8984979521 ps
CPU time 15.89 seconds
Started Jul 15 04:32:40 PM PDT 24
Finished Jul 15 04:32:58 PM PDT 24
Peak memory 197680 kb
Host smart-ac3c5b9b-74d8-4765-809c-2cfb5f018f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822132765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3822132765
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.714810787
Short name T365
Test name
Test status
Simulation time 20589352459 ps
CPU time 40.16 seconds
Started Jul 15 04:32:36 PM PDT 24
Finished Jul 15 04:33:17 PM PDT 24
Peak memory 199728 kb
Host smart-7b6c769c-95aa-4d40-8ad7-508e110f4996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=714810787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.714810787
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3321203628
Short name T329
Test name
Test status
Simulation time 2623637246 ps
CPU time 5.01 seconds
Started Jul 15 04:32:53 PM PDT 24
Finished Jul 15 04:32:59 PM PDT 24
Peak memory 197912 kb
Host smart-83638ead-5002-41e5-a82d-096e46d04ead
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3321203628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3321203628
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.840919753
Short name T673
Test name
Test status
Simulation time 55929002457 ps
CPU time 18.79 seconds
Started Jul 15 04:32:39 PM PDT 24
Finished Jul 15 04:32:59 PM PDT 24
Peak memory 199724 kb
Host smart-e46495d6-e794-4d2a-aede-e986ae7fb703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840919753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.840919753
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3555954555
Short name T572
Test name
Test status
Simulation time 4986160174 ps
CPU time 1.88 seconds
Started Jul 15 04:32:36 PM PDT 24
Finished Jul 15 04:32:39 PM PDT 24
Peak memory 195892 kb
Host smart-264352d5-c4f9-4706-a3cc-8bc198597f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555954555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3555954555
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2990116023
Short name T767
Test name
Test status
Simulation time 659978784 ps
CPU time 2.38 seconds
Started Jul 15 04:32:38 PM PDT 24
Finished Jul 15 04:32:42 PM PDT 24
Peak memory 199280 kb
Host smart-a8c38e8a-d96d-44a9-a42b-46f2841233c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990116023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2990116023
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3067777863
Short name T385
Test name
Test status
Simulation time 7192736069 ps
CPU time 11.14 seconds
Started Jul 15 04:32:40 PM PDT 24
Finished Jul 15 04:32:52 PM PDT 24
Peak memory 199432 kb
Host smart-43a6f0ed-5cda-4b72-a641-5044d503dc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067777863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3067777863
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.4282430994
Short name T1025
Test name
Test status
Simulation time 97596117116 ps
CPU time 40.91 seconds
Started Jul 15 04:32:29 PM PDT 24
Finished Jul 15 04:33:12 PM PDT 24
Peak memory 199660 kb
Host smart-f3617704-7938-41db-bfee-394aadf08e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282430994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.4282430994
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.439351209
Short name T760
Test name
Test status
Simulation time 23892128 ps
CPU time 0.54 seconds
Started Jul 15 04:32:43 PM PDT 24
Finished Jul 15 04:32:45 PM PDT 24
Peak memory 195080 kb
Host smart-984bf533-90a4-4585-b39c-8920885e6f0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439351209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.439351209
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.564704977
Short name T759
Test name
Test status
Simulation time 157291505727 ps
CPU time 63.88 seconds
Started Jul 15 04:32:40 PM PDT 24
Finished Jul 15 04:33:45 PM PDT 24
Peak memory 199660 kb
Host smart-45796735-e94d-45b9-bc8f-1733698066d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564704977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.564704977
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1701545150
Short name T989
Test name
Test status
Simulation time 16832455204 ps
CPU time 26.47 seconds
Started Jul 15 04:32:40 PM PDT 24
Finished Jul 15 04:33:07 PM PDT 24
Peak memory 199532 kb
Host smart-ab7a4d00-15b8-4dbb-9f6d-8550f046d83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701545150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1701545150
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.272587609
Short name T991
Test name
Test status
Simulation time 21718339962 ps
CPU time 31.66 seconds
Started Jul 15 04:32:37 PM PDT 24
Finished Jul 15 04:33:10 PM PDT 24
Peak memory 199796 kb
Host smart-7d113ee9-9c6d-4f2b-adbd-33bfb69749e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272587609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.272587609
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.4236808349
Short name T471
Test name
Test status
Simulation time 61058135467 ps
CPU time 106.38 seconds
Started Jul 15 04:32:38 PM PDT 24
Finished Jul 15 04:34:26 PM PDT 24
Peak memory 199800 kb
Host smart-28a41be2-1eb6-4a09-817a-774fc4bcafcb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236808349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.4236808349
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3502837132
Short name T321
Test name
Test status
Simulation time 80471833846 ps
CPU time 319.81 seconds
Started Jul 15 04:32:43 PM PDT 24
Finished Jul 15 04:38:04 PM PDT 24
Peak memory 199768 kb
Host smart-a9f6c2aa-d907-48de-a139-d80ead272515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502837132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3502837132
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1510402991
Short name T1061
Test name
Test status
Simulation time 8111131039 ps
CPU time 6.61 seconds
Started Jul 15 04:32:37 PM PDT 24
Finished Jul 15 04:32:44 PM PDT 24
Peak memory 199664 kb
Host smart-cba565d0-1e5b-4f8c-b65f-e173d0724be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510402991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1510402991
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2269821669
Short name T318
Test name
Test status
Simulation time 48378381332 ps
CPU time 21.4 seconds
Started Jul 15 04:32:36 PM PDT 24
Finished Jul 15 04:32:59 PM PDT 24
Peak memory 198296 kb
Host smart-056b86c1-0f9d-4047-bd57-f14a82fb4dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269821669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2269821669
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.864900844
Short name T277
Test name
Test status
Simulation time 19931703415 ps
CPU time 247.63 seconds
Started Jul 15 04:32:46 PM PDT 24
Finished Jul 15 04:36:56 PM PDT 24
Peak memory 199816 kb
Host smart-1511a3b3-2527-41e7-b55a-4dd94bb24483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864900844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.864900844
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.872570893
Short name T337
Test name
Test status
Simulation time 4566979238 ps
CPU time 9.59 seconds
Started Jul 15 04:32:35 PM PDT 24
Finished Jul 15 04:32:45 PM PDT 24
Peak memory 197928 kb
Host smart-01298d52-4303-4943-aa84-43bd710e69c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872570893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.872570893
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.891607763
Short name T924
Test name
Test status
Simulation time 15276993134 ps
CPU time 22.8 seconds
Started Jul 15 04:32:37 PM PDT 24
Finished Jul 15 04:33:01 PM PDT 24
Peak memory 199736 kb
Host smart-36122569-6dea-454c-b8a5-fa5c292a36bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891607763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.891607763
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.143049458
Short name T809
Test name
Test status
Simulation time 4517325668 ps
CPU time 2.53 seconds
Started Jul 15 04:32:38 PM PDT 24
Finished Jul 15 04:32:42 PM PDT 24
Peak memory 196224 kb
Host smart-328601ad-dd5c-44a6-a261-2c557ca70652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143049458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.143049458
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3070639873
Short name T590
Test name
Test status
Simulation time 113932997 ps
CPU time 0.84 seconds
Started Jul 15 04:32:37 PM PDT 24
Finished Jul 15 04:32:40 PM PDT 24
Peak memory 196784 kb
Host smart-3c8997b4-747b-4159-b52f-3f5b4a736f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070639873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3070639873
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.632409812
Short name T1095
Test name
Test status
Simulation time 239725926659 ps
CPU time 1107.31 seconds
Started Jul 15 04:32:44 PM PDT 24
Finished Jul 15 04:51:14 PM PDT 24
Peak memory 199648 kb
Host smart-1d45a578-a223-40d5-bae3-77e571be50be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632409812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.632409812
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2599754248
Short name T195
Test name
Test status
Simulation time 352239103664 ps
CPU time 1114.28 seconds
Started Jul 15 04:32:43 PM PDT 24
Finished Jul 15 04:51:18 PM PDT 24
Peak memory 225740 kb
Host smart-225f26e9-007f-4b77-8072-f60b1f6249d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599754248 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2599754248
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2753981217
Short name T535
Test name
Test status
Simulation time 2139636891 ps
CPU time 3.65 seconds
Started Jul 15 04:32:37 PM PDT 24
Finished Jul 15 04:32:42 PM PDT 24
Peak memory 199000 kb
Host smart-e4f2954d-8a0a-4e60-97c2-2280c5262002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753981217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2753981217
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.410071660
Short name T698
Test name
Test status
Simulation time 157100017090 ps
CPU time 85.55 seconds
Started Jul 15 04:32:37 PM PDT 24
Finished Jul 15 04:34:04 PM PDT 24
Peak memory 199764 kb
Host smart-be81d84a-d312-422b-b331-bef78cf3e0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410071660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.410071660
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2188164624
Short name T1142
Test name
Test status
Simulation time 10601719 ps
CPU time 0.53 seconds
Started Jul 15 04:32:43 PM PDT 24
Finished Jul 15 04:32:45 PM PDT 24
Peak memory 194060 kb
Host smart-aa170948-0e14-4402-a48c-fab534bf3add
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188164624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2188164624
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2849918925
Short name T988
Test name
Test status
Simulation time 99863330516 ps
CPU time 84.8 seconds
Started Jul 15 04:32:45 PM PDT 24
Finished Jul 15 04:34:11 PM PDT 24
Peak memory 199656 kb
Host smart-e1e4b909-8cc4-4ed7-9e31-c90941a4240a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849918925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2849918925
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3875114355
Short name T531
Test name
Test status
Simulation time 45115153476 ps
CPU time 68.75 seconds
Started Jul 15 04:32:44 PM PDT 24
Finished Jul 15 04:33:55 PM PDT 24
Peak memory 199740 kb
Host smart-b0f9d6c8-fca7-4c5a-a294-e67f0b70f056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875114355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3875114355
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1642977614
Short name T275
Test name
Test status
Simulation time 21045881154 ps
CPU time 17.75 seconds
Started Jul 15 04:32:45 PM PDT 24
Finished Jul 15 04:33:05 PM PDT 24
Peak memory 199696 kb
Host smart-9be6ca6b-9f5e-49cb-9f99-4134c9a3d05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642977614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1642977614
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1776472816
Short name T442
Test name
Test status
Simulation time 229198791437 ps
CPU time 103.19 seconds
Started Jul 15 04:32:45 PM PDT 24
Finished Jul 15 04:34:30 PM PDT 24
Peak memory 198512 kb
Host smart-f020db9a-0830-4ac9-8e5c-f981a1e3af57
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776472816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1776472816
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3370282008
Short name T1030
Test name
Test status
Simulation time 84339725770 ps
CPU time 683.15 seconds
Started Jul 15 04:32:44 PM PDT 24
Finished Jul 15 04:44:08 PM PDT 24
Peak memory 199768 kb
Host smart-1c689a07-a4cb-4527-ae5a-3dff079631ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370282008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3370282008
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.778441631
Short name T1100
Test name
Test status
Simulation time 5808243129 ps
CPU time 5.11 seconds
Started Jul 15 04:32:46 PM PDT 24
Finished Jul 15 04:32:53 PM PDT 24
Peak memory 199532 kb
Host smart-8199c373-d471-4d42-b578-a5cb350544ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778441631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.778441631
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2766032652
Short name T827
Test name
Test status
Simulation time 139007726664 ps
CPU time 89.55 seconds
Started Jul 15 04:32:46 PM PDT 24
Finished Jul 15 04:34:17 PM PDT 24
Peak memory 199960 kb
Host smart-550ac459-d72b-4474-b74d-81f0fe030813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766032652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2766032652
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.624464141
Short name T650
Test name
Test status
Simulation time 16191129910 ps
CPU time 216.64 seconds
Started Jul 15 04:32:45 PM PDT 24
Finished Jul 15 04:36:24 PM PDT 24
Peak memory 199728 kb
Host smart-aefbfef8-ecc8-41b9-9697-e32ebac5c9d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=624464141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.624464141
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3232958254
Short name T534
Test name
Test status
Simulation time 4672103675 ps
CPU time 20.06 seconds
Started Jul 15 04:32:42 PM PDT 24
Finished Jul 15 04:33:03 PM PDT 24
Peak memory 197644 kb
Host smart-5546d1c6-adbd-46bf-b08f-3b974d3d82e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3232958254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3232958254
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2039323886
Short name T140
Test name
Test status
Simulation time 132552719454 ps
CPU time 56.2 seconds
Started Jul 15 04:32:44 PM PDT 24
Finished Jul 15 04:33:41 PM PDT 24
Peak memory 199840 kb
Host smart-e07b3600-8d35-4a59-b2cc-3398085cef98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039323886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2039323886
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1017052370
Short name T981
Test name
Test status
Simulation time 2739214551 ps
CPU time 1.95 seconds
Started Jul 15 04:32:45 PM PDT 24
Finished Jul 15 04:32:49 PM PDT 24
Peak memory 196264 kb
Host smart-b9e70104-2b87-4e06-b114-908c29d31d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017052370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1017052370
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.4067963731
Short name T608
Test name
Test status
Simulation time 727234022 ps
CPU time 1.52 seconds
Started Jul 15 04:32:43 PM PDT 24
Finished Jul 15 04:32:45 PM PDT 24
Peak memory 197956 kb
Host smart-53b4b85e-f965-4721-9a01-8e0ca6d4a04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067963731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.4067963731
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3923807911
Short name T470
Test name
Test status
Simulation time 186310811039 ps
CPU time 295.78 seconds
Started Jul 15 04:32:43 PM PDT 24
Finished Jul 15 04:37:39 PM PDT 24
Peak memory 199696 kb
Host smart-f4b7730b-f8e1-4853-88ad-58d670ad0741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923807911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3923807911
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.353627059
Short name T102
Test name
Test status
Simulation time 74487578644 ps
CPU time 244.08 seconds
Started Jul 15 04:32:43 PM PDT 24
Finished Jul 15 04:36:48 PM PDT 24
Peak memory 215932 kb
Host smart-685aaa40-f910-4c0a-965e-f8d322db2d18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353627059 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.353627059
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3754882604
Short name T1162
Test name
Test status
Simulation time 1356392387 ps
CPU time 1.78 seconds
Started Jul 15 04:32:44 PM PDT 24
Finished Jul 15 04:32:48 PM PDT 24
Peak memory 198452 kb
Host smart-7cc14c10-5bde-44cb-b4bd-cb4ad2db8d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754882604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3754882604
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3549205607
Short name T341
Test name
Test status
Simulation time 100005686945 ps
CPU time 148.44 seconds
Started Jul 15 04:32:45 PM PDT 24
Finished Jul 15 04:35:15 PM PDT 24
Peak memory 199736 kb
Host smart-7a1a3033-5dbf-41c2-8687-6d6f187e7e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549205607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3549205607
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.143487683
Short name T358
Test name
Test status
Simulation time 28876327 ps
CPU time 0.53 seconds
Started Jul 15 04:32:56 PM PDT 24
Finished Jul 15 04:32:57 PM PDT 24
Peak memory 194056 kb
Host smart-24e54ec1-8eec-4c52-a89e-6756e0d3c6cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143487683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.143487683
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2253307753
Short name T425
Test name
Test status
Simulation time 164509841776 ps
CPU time 244.29 seconds
Started Jul 15 04:33:06 PM PDT 24
Finished Jul 15 04:37:12 PM PDT 24
Peak memory 199644 kb
Host smart-2a605931-3160-4e46-b609-1aac59232311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253307753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2253307753
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.544693414
Short name T954
Test name
Test status
Simulation time 23274451740 ps
CPU time 10.05 seconds
Started Jul 15 04:32:46 PM PDT 24
Finished Jul 15 04:32:58 PM PDT 24
Peak memory 199696 kb
Host smart-04d21d63-48e5-402d-bb7c-2534c555849c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544693414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.544693414
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4249460116
Short name T211
Test name
Test status
Simulation time 72988846735 ps
CPU time 32.18 seconds
Started Jul 15 04:32:52 PM PDT 24
Finished Jul 15 04:33:26 PM PDT 24
Peak memory 199704 kb
Host smart-3e19bc28-ffa6-4311-956c-6eec96568fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249460116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4249460116
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.510749891
Short name T860
Test name
Test status
Simulation time 49152550763 ps
CPU time 27.89 seconds
Started Jul 15 04:32:51 PM PDT 24
Finished Jul 15 04:33:20 PM PDT 24
Peak memory 199256 kb
Host smart-678f1113-e5fb-4abb-a4d1-7d6cc6707bf9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510749891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.510749891
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.14277297
Short name T297
Test name
Test status
Simulation time 92020937782 ps
CPU time 445.99 seconds
Started Jul 15 04:32:52 PM PDT 24
Finished Jul 15 04:40:19 PM PDT 24
Peak memory 199700 kb
Host smart-31e34459-9ba2-4e4f-885c-86bbfef1de81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14277297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.14277297
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3836399070
Short name T713
Test name
Test status
Simulation time 87344177 ps
CPU time 0.67 seconds
Started Jul 15 04:32:53 PM PDT 24
Finished Jul 15 04:32:55 PM PDT 24
Peak memory 195764 kb
Host smart-9ebd833e-9af3-45c3-aabc-be74f44b8f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836399070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3836399070
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.973149727
Short name T60
Test name
Test status
Simulation time 103887664899 ps
CPU time 42.09 seconds
Started Jul 15 04:32:51 PM PDT 24
Finished Jul 15 04:33:34 PM PDT 24
Peak memory 199416 kb
Host smart-3d1a0a31-4a32-4230-abbb-56e143211bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973149727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.973149727
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3341065917
Short name T623
Test name
Test status
Simulation time 2720136223 ps
CPU time 138.53 seconds
Started Jul 15 04:32:51 PM PDT 24
Finished Jul 15 04:35:11 PM PDT 24
Peak memory 199796 kb
Host smart-0cad8979-434f-4344-a032-4c89be477d6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3341065917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3341065917
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1013306527
Short name T549
Test name
Test status
Simulation time 6690001057 ps
CPU time 3.24 seconds
Started Jul 15 04:32:50 PM PDT 24
Finished Jul 15 04:32:54 PM PDT 24
Peak memory 198720 kb
Host smart-e42ef56a-eead-477a-a039-855cf862f9f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1013306527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1013306527
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.274871165
Short name T702
Test name
Test status
Simulation time 61787284306 ps
CPU time 161.39 seconds
Started Jul 15 04:32:52 PM PDT 24
Finished Jul 15 04:35:34 PM PDT 24
Peak memory 199720 kb
Host smart-ce5b286d-5234-4ee7-a343-c82f1755bed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274871165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.274871165
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2148187452
Short name T491
Test name
Test status
Simulation time 4229387898 ps
CPU time 1.23 seconds
Started Jul 15 04:32:49 PM PDT 24
Finished Jul 15 04:32:51 PM PDT 24
Peak memory 196088 kb
Host smart-998fe270-45b2-4faa-b6d0-6d65cbb60bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148187452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2148187452
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.534612168
Short name T795
Test name
Test status
Simulation time 650022374 ps
CPU time 2.26 seconds
Started Jul 15 04:32:44 PM PDT 24
Finished Jul 15 04:32:47 PM PDT 24
Peak memory 199100 kb
Host smart-69e95c8c-77ba-4960-a927-190c6487db34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534612168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.534612168
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.940627875
Short name T545
Test name
Test status
Simulation time 93054886814 ps
CPU time 100.58 seconds
Started Jul 15 04:32:54 PM PDT 24
Finished Jul 15 04:34:35 PM PDT 24
Peak memory 199720 kb
Host smart-bd201162-8d1a-42be-ac73-3b4baccd4fbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940627875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.940627875
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2688421731
Short name T157
Test name
Test status
Simulation time 201344443514 ps
CPU time 301.66 seconds
Started Jul 15 04:32:50 PM PDT 24
Finished Jul 15 04:37:53 PM PDT 24
Peak memory 216296 kb
Host smart-6e60fba6-a182-4c61-bdb7-8b5c4c9699a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688421731 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2688421731
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2944791865
Short name T952
Test name
Test status
Simulation time 645917445 ps
CPU time 2.15 seconds
Started Jul 15 04:32:52 PM PDT 24
Finished Jul 15 04:32:55 PM PDT 24
Peak memory 198388 kb
Host smart-4121cb11-3283-4e35-9595-238a52d0c72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944791865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2944791865
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1639494727
Short name T390
Test name
Test status
Simulation time 38205699108 ps
CPU time 27.48 seconds
Started Jul 15 04:32:45 PM PDT 24
Finished Jul 15 04:33:14 PM PDT 24
Peak memory 199660 kb
Host smart-cae79a89-6ab2-4c50-a961-6a7d2ebbbd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639494727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1639494727
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1562962771
Short name T520
Test name
Test status
Simulation time 42594647 ps
CPU time 0.54 seconds
Started Jul 15 04:32:53 PM PDT 24
Finished Jul 15 04:32:54 PM PDT 24
Peak memory 194544 kb
Host smart-6afb8642-4d2d-472a-8658-9c25b1dd690c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562962771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1562962771
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1980700847
Short name T876
Test name
Test status
Simulation time 99689504354 ps
CPU time 171.07 seconds
Started Jul 15 04:33:58 PM PDT 24
Finished Jul 15 04:36:51 PM PDT 24
Peak memory 198872 kb
Host smart-018c8a7a-d560-4c66-ad24-74506b668896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980700847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1980700847
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3517788815
Short name T700
Test name
Test status
Simulation time 25354895774 ps
CPU time 45.86 seconds
Started Jul 15 04:32:52 PM PDT 24
Finished Jul 15 04:33:39 PM PDT 24
Peak memory 199736 kb
Host smart-472fefbb-3d99-4470-a512-0963c364516b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517788815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3517788815
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3124848778
Short name T749
Test name
Test status
Simulation time 32266907938 ps
CPU time 22.03 seconds
Started Jul 15 04:32:50 PM PDT 24
Finished Jul 15 04:33:13 PM PDT 24
Peak memory 199780 kb
Host smart-be0ce369-503a-4417-922e-b9bf9dbbb634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124848778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3124848778
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.4244770519
Short name T368
Test name
Test status
Simulation time 44080182945 ps
CPU time 40.79 seconds
Started Jul 15 04:32:55 PM PDT 24
Finished Jul 15 04:33:37 PM PDT 24
Peak memory 199696 kb
Host smart-531d3e2c-408a-4ca8-baef-1cb7969a7348
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244770519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.4244770519
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.117161397
Short name T449
Test name
Test status
Simulation time 316927020196 ps
CPU time 475.59 seconds
Started Jul 15 04:32:53 PM PDT 24
Finished Jul 15 04:40:49 PM PDT 24
Peak memory 200080 kb
Host smart-8a5938fb-bd29-4b26-be88-37ff026cc3ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117161397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.117161397
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1550590025
Short name T1130
Test name
Test status
Simulation time 7266544453 ps
CPU time 5.57 seconds
Started Jul 15 04:32:52 PM PDT 24
Finished Jul 15 04:32:59 PM PDT 24
Peak memory 199492 kb
Host smart-0777ad76-ad96-47dc-bb68-b0cad49eae7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550590025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1550590025
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3801748541
Short name T895
Test name
Test status
Simulation time 29978453168 ps
CPU time 51.55 seconds
Started Jul 15 04:32:56 PM PDT 24
Finished Jul 15 04:33:48 PM PDT 24
Peak memory 199968 kb
Host smart-604ea05c-79b3-4c40-bed6-a55b75894bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801748541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3801748541
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1556236827
Short name T648
Test name
Test status
Simulation time 7151774130 ps
CPU time 315.65 seconds
Started Jul 15 04:32:53 PM PDT 24
Finished Jul 15 04:38:10 PM PDT 24
Peak memory 199724 kb
Host smart-102bfec7-acf7-4557-b11a-df62ca214afa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1556236827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1556236827
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2290251971
Short name T570
Test name
Test status
Simulation time 5041749213 ps
CPU time 37.02 seconds
Started Jul 15 04:32:53 PM PDT 24
Finished Jul 15 04:33:31 PM PDT 24
Peak memory 198040 kb
Host smart-befdfa2e-b17d-4acf-8ee4-b9746e44a62e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290251971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2290251971
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1646335651
Short name T587
Test name
Test status
Simulation time 101573007055 ps
CPU time 10.53 seconds
Started Jul 15 04:32:53 PM PDT 24
Finished Jul 15 04:33:04 PM PDT 24
Peak memory 199768 kb
Host smart-a7ee9e93-fb87-42a3-9c3c-65139a2cb400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646335651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1646335651
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3616037910
Short name T1013
Test name
Test status
Simulation time 4064686040 ps
CPU time 2.07 seconds
Started Jul 15 04:32:51 PM PDT 24
Finished Jul 15 04:32:54 PM PDT 24
Peak memory 195908 kb
Host smart-c446a7f2-d1e0-45c7-8a8c-c8574fc23755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616037910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3616037910
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.851603137
Short name T705
Test name
Test status
Simulation time 319479315 ps
CPU time 1.29 seconds
Started Jul 15 04:32:53 PM PDT 24
Finished Jul 15 04:32:56 PM PDT 24
Peak memory 198232 kb
Host smart-fa49457c-be8f-490c-aeb6-ceb41324de42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851603137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.851603137
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2444604512
Short name T1109
Test name
Test status
Simulation time 444455736541 ps
CPU time 2881.75 seconds
Started Jul 15 04:32:56 PM PDT 24
Finished Jul 15 05:20:59 PM PDT 24
Peak memory 199672 kb
Host smart-69b4e3e9-5e59-473b-a8cb-34e3f565ad93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444604512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2444604512
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3315336486
Short name T551
Test name
Test status
Simulation time 55563728692 ps
CPU time 641.75 seconds
Started Jul 15 04:32:53 PM PDT 24
Finished Jul 15 04:43:36 PM PDT 24
Peak memory 224660 kb
Host smart-c5cdce14-b83b-43bc-991d-724b223b67a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315336486 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3315336486
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1966475350
Short name T1027
Test name
Test status
Simulation time 2508897385 ps
CPU time 1.84 seconds
Started Jul 15 04:32:51 PM PDT 24
Finished Jul 15 04:32:54 PM PDT 24
Peak memory 198352 kb
Host smart-c4d57a0a-f913-4c15-8c8a-4b99272229b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966475350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1966475350
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.769978776
Short name T427
Test name
Test status
Simulation time 83392521378 ps
CPU time 68.74 seconds
Started Jul 15 04:32:52 PM PDT 24
Finished Jul 15 04:34:02 PM PDT 24
Peak memory 200004 kb
Host smart-3e0988fc-c537-4a6f-8ce5-486740bc66c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769978776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.769978776
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.4266571111
Short name T866
Test name
Test status
Simulation time 29281755 ps
CPU time 0.52 seconds
Started Jul 15 04:32:59 PM PDT 24
Finished Jul 15 04:33:01 PM PDT 24
Peak memory 194012 kb
Host smart-80900fc1-2f73-440a-8b81-ae9763d2865c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266571111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.4266571111
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1785294238
Short name T1154
Test name
Test status
Simulation time 109913975460 ps
CPU time 159.41 seconds
Started Jul 15 04:32:59 PM PDT 24
Finished Jul 15 04:35:40 PM PDT 24
Peak memory 199712 kb
Host smart-b5d52999-f907-4d6b-bc5a-a39723b73985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785294238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1785294238
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3409972484
Short name T1140
Test name
Test status
Simulation time 1723186058 ps
CPU time 1.93 seconds
Started Jul 15 04:33:00 PM PDT 24
Finished Jul 15 04:33:05 PM PDT 24
Peak memory 197384 kb
Host smart-d77cf0e6-499e-4b21-8671-c62d00765c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409972484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3409972484
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.524316707
Short name T128
Test name
Test status
Simulation time 25521633325 ps
CPU time 42.1 seconds
Started Jul 15 04:33:04 PM PDT 24
Finished Jul 15 04:33:48 PM PDT 24
Peak memory 199836 kb
Host smart-180a141e-a0fd-41c9-a658-29cfe0b556e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524316707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.524316707
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.4151120559
Short name T12
Test name
Test status
Simulation time 9163758386 ps
CPU time 14.22 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:33:18 PM PDT 24
Peak memory 197476 kb
Host smart-b316f2fd-e00a-455d-8a72-ace1fdd8e7bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151120559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.4151120559
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.4252606558
Short name T810
Test name
Test status
Simulation time 138771640236 ps
CPU time 481.95 seconds
Started Jul 15 04:33:03 PM PDT 24
Finished Jul 15 04:41:07 PM PDT 24
Peak memory 199644 kb
Host smart-776c91fe-1814-4252-924b-80a6ff920625
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252606558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.4252606558
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3840814440
Short name T891
Test name
Test status
Simulation time 7227645531 ps
CPU time 9.07 seconds
Started Jul 15 04:32:58 PM PDT 24
Finished Jul 15 04:33:08 PM PDT 24
Peak memory 198188 kb
Host smart-925fb4cb-05f1-4a3f-8e87-e8caf6efb7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840814440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3840814440
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1611127225
Short name T226
Test name
Test status
Simulation time 230447355891 ps
CPU time 73.2 seconds
Started Jul 15 04:33:05 PM PDT 24
Finished Jul 15 04:34:19 PM PDT 24
Peak memory 199544 kb
Host smart-f3ee231b-39be-4fc4-aaad-f15917ec18b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611127225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1611127225
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1493173334
Short name T1108
Test name
Test status
Simulation time 13526393908 ps
CPU time 672.99 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:44:18 PM PDT 24
Peak memory 199748 kb
Host smart-001e9399-d822-4e92-b6ff-6c3ab273319f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493173334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1493173334
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.4046918921
Short name T57
Test name
Test status
Simulation time 6758242571 ps
CPU time 15.71 seconds
Started Jul 15 04:33:08 PM PDT 24
Finished Jul 15 04:33:25 PM PDT 24
Peak memory 198868 kb
Host smart-b2075b65-7679-4ab0-9336-07763f4232b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046918921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4046918921
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1110095623
Short name T234
Test name
Test status
Simulation time 115727827601 ps
CPU time 162.7 seconds
Started Jul 15 04:33:03 PM PDT 24
Finished Jul 15 04:35:48 PM PDT 24
Peak memory 199832 kb
Host smart-bef6057d-305d-4673-850d-1d999759f317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110095623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1110095623
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.357210252
Short name T371
Test name
Test status
Simulation time 5592273282 ps
CPU time 3.06 seconds
Started Jul 15 04:33:00 PM PDT 24
Finished Jul 15 04:33:04 PM PDT 24
Peak memory 195816 kb
Host smart-debb9f57-fb66-4a53-affc-8f9bcea512f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357210252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.357210252
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1331472152
Short name T348
Test name
Test status
Simulation time 459857168 ps
CPU time 1.24 seconds
Started Jul 15 04:32:59 PM PDT 24
Finished Jul 15 04:33:01 PM PDT 24
Peak memory 198112 kb
Host smart-f7304e0d-3e76-4499-a4fa-fe86ea13db80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331472152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1331472152
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1759009546
Short name T108
Test name
Test status
Simulation time 72573451985 ps
CPU time 105.24 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:34:49 PM PDT 24
Peak memory 199760 kb
Host smart-d7a3f79d-e4a6-4c6f-8166-4716187fb5e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759009546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1759009546
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3704192624
Short name T1070
Test name
Test status
Simulation time 121010703965 ps
CPU time 465.35 seconds
Started Jul 15 04:33:02 PM PDT 24
Finished Jul 15 04:40:50 PM PDT 24
Peak memory 216140 kb
Host smart-e1e734a9-4c26-45fd-8b6e-70bbc0561cf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704192624 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3704192624
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3455723663
Short name T1084
Test name
Test status
Simulation time 1085510053 ps
CPU time 1.77 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:33:06 PM PDT 24
Peak memory 198536 kb
Host smart-ab91075a-502b-40a3-a169-d4ee5817f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455723663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3455723663
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3066536671
Short name T874
Test name
Test status
Simulation time 95617772869 ps
CPU time 146.94 seconds
Started Jul 15 04:33:00 PM PDT 24
Finished Jul 15 04:35:30 PM PDT 24
Peak memory 199768 kb
Host smart-a5ae7735-7712-4e64-a817-7ec83dc41ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066536671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3066536671
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.161085209
Short name T814
Test name
Test status
Simulation time 55029158 ps
CPU time 0.56 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:33:05 PM PDT 24
Peak memory 194060 kb
Host smart-b959d409-ebca-4393-a06f-21d9728925df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161085209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.161085209
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3861637260
Short name T58
Test name
Test status
Simulation time 67667173903 ps
CPU time 28.55 seconds
Started Jul 15 04:32:59 PM PDT 24
Finished Jul 15 04:33:30 PM PDT 24
Peak memory 199728 kb
Host smart-e9580dc8-027c-4a0f-9a90-de044aacbdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861637260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3861637260
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1298783085
Short name T289
Test name
Test status
Simulation time 53152407625 ps
CPU time 39.02 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:33:44 PM PDT 24
Peak memory 199612 kb
Host smart-2d5458f6-e114-487b-842f-18ddcb4f7b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298783085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1298783085
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.2681163257
Short name T851
Test name
Test status
Simulation time 357420675788 ps
CPU time 480.95 seconds
Started Jul 15 04:33:05 PM PDT 24
Finished Jul 15 04:41:07 PM PDT 24
Peak memory 198104 kb
Host smart-57312f05-593e-4b72-8c43-34a0c8094aaa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681163257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2681163257
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1820015788
Short name T998
Test name
Test status
Simulation time 60337178794 ps
CPU time 462.47 seconds
Started Jul 15 04:33:00 PM PDT 24
Finished Jul 15 04:40:44 PM PDT 24
Peak memory 199720 kb
Host smart-869afae8-5052-41b8-b570-b86fd1a4d12e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820015788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1820015788
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.885423279
Short name T966
Test name
Test status
Simulation time 4445852123 ps
CPU time 3.63 seconds
Started Jul 15 04:33:03 PM PDT 24
Finished Jul 15 04:33:09 PM PDT 24
Peak memory 197940 kb
Host smart-36d981be-35f0-44ce-9213-d327a4650401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885423279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.885423279
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3807613636
Short name T1111
Test name
Test status
Simulation time 59169041326 ps
CPU time 82.6 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:34:26 PM PDT 24
Peak memory 199968 kb
Host smart-c8267a04-40a5-4bbf-8af5-d2bbcfd186cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807613636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3807613636
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2066255707
Short name T899
Test name
Test status
Simulation time 8292445575 ps
CPU time 445.46 seconds
Started Jul 15 04:33:02 PM PDT 24
Finished Jul 15 04:40:30 PM PDT 24
Peak memory 199780 kb
Host smart-3688e889-09ad-4a78-8ffe-e089948f5f3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2066255707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2066255707
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2970009938
Short name T361
Test name
Test status
Simulation time 1593823636 ps
CPU time 4.59 seconds
Started Jul 15 04:33:00 PM PDT 24
Finished Jul 15 04:33:07 PM PDT 24
Peak memory 198416 kb
Host smart-226a14c0-a050-4b53-8ca5-e7597746782e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970009938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2970009938
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.202560456
Short name T664
Test name
Test status
Simulation time 20041656843 ps
CPU time 30.26 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:33:34 PM PDT 24
Peak memory 199776 kb
Host smart-f986ea6b-1d54-4a8e-ba4b-41b9de995425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202560456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.202560456
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2312213544
Short name T1116
Test name
Test status
Simulation time 1541681554 ps
CPU time 1.92 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:33:06 PM PDT 24
Peak memory 195340 kb
Host smart-c9c1b691-fe64-42e6-a47e-6cd753e257c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312213544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2312213544
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3234641083
Short name T951
Test name
Test status
Simulation time 314985518 ps
CPU time 1.38 seconds
Started Jul 15 04:33:02 PM PDT 24
Finished Jul 15 04:33:06 PM PDT 24
Peak memory 198424 kb
Host smart-0fa7d243-9367-4228-830c-309bb3b1910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234641083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3234641083
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3332988328
Short name T1052
Test name
Test status
Simulation time 245731879580 ps
CPU time 813.16 seconds
Started Jul 15 04:33:02 PM PDT 24
Finished Jul 15 04:46:38 PM PDT 24
Peak memory 208052 kb
Host smart-5a0ce115-b4b4-46f4-97b4-19bb837260ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332988328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3332988328
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1148080805
Short name T607
Test name
Test status
Simulation time 68224342171 ps
CPU time 416.01 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:40:00 PM PDT 24
Peak memory 215648 kb
Host smart-7a3cd5d1-884b-49b2-a005-e6e506d72ce8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148080805 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1148080805
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1057102374
Short name T736
Test name
Test status
Simulation time 856950465 ps
CPU time 2.36 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:33:07 PM PDT 24
Peak memory 199100 kb
Host smart-31a0a0da-b500-45a0-8cd9-6b58738ca4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057102374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1057102374
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1676871377
Short name T1062
Test name
Test status
Simulation time 13534508383 ps
CPU time 14.89 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:33:19 PM PDT 24
Peak memory 199688 kb
Host smart-2682c14c-ad65-46d5-a2c7-e5bd1ae880cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676871377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1676871377
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2959516572
Short name T469
Test name
Test status
Simulation time 41038290 ps
CPU time 0.53 seconds
Started Jul 15 04:30:26 PM PDT 24
Finished Jul 15 04:30:28 PM PDT 24
Peak memory 195364 kb
Host smart-4defec5f-9020-4c32-b4f8-d94bfd209f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959516572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2959516572
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.837797129
Short name T865
Test name
Test status
Simulation time 69475026273 ps
CPU time 29.36 seconds
Started Jul 15 04:30:28 PM PDT 24
Finished Jul 15 04:30:59 PM PDT 24
Peak memory 199752 kb
Host smart-8799b9cf-3843-4740-bf34-ba4764b39e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837797129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.837797129
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2208693267
Short name T613
Test name
Test status
Simulation time 13421073499 ps
CPU time 22.91 seconds
Started Jul 15 04:30:35 PM PDT 24
Finished Jul 15 04:30:59 PM PDT 24
Peak memory 199504 kb
Host smart-41b16500-04ee-4d9e-a86d-b5ccc0603fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208693267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2208693267
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.376028193
Short name T364
Test name
Test status
Simulation time 72553348099 ps
CPU time 28.57 seconds
Started Jul 15 04:30:29 PM PDT 24
Finished Jul 15 04:30:59 PM PDT 24
Peak memory 199712 kb
Host smart-9069d9d9-476e-47aa-a06c-571ebbcd6e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376028193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.376028193
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.845207464
Short name T621
Test name
Test status
Simulation time 16949496878 ps
CPU time 17.22 seconds
Started Jul 15 04:30:27 PM PDT 24
Finished Jul 15 04:30:45 PM PDT 24
Peak memory 199772 kb
Host smart-7883aa51-98f5-4e61-aaea-fc478f74254d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845207464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.845207464
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3075986051
Short name T1117
Test name
Test status
Simulation time 83577605364 ps
CPU time 533.11 seconds
Started Jul 15 04:30:29 PM PDT 24
Finished Jul 15 04:39:24 PM PDT 24
Peak memory 199732 kb
Host smart-c8b80246-f847-430e-8703-fa8a67e81913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075986051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3075986051
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1802772070
Short name T359
Test name
Test status
Simulation time 39777649 ps
CPU time 0.6 seconds
Started Jul 15 04:30:34 PM PDT 24
Finished Jul 15 04:30:35 PM PDT 24
Peak memory 195468 kb
Host smart-76bb1dd6-b3a3-455c-8f96-0e9dbb13bfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802772070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1802772070
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.641533034
Short name T677
Test name
Test status
Simulation time 5248504118 ps
CPU time 4.77 seconds
Started Jul 15 04:30:27 PM PDT 24
Finished Jul 15 04:30:33 PM PDT 24
Peak memory 196548 kb
Host smart-e6ab30f9-494a-489c-b3d2-15994a417788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641533034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.641533034
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2280179073
Short name T862
Test name
Test status
Simulation time 19510037224 ps
CPU time 209.05 seconds
Started Jul 15 04:30:28 PM PDT 24
Finished Jul 15 04:34:00 PM PDT 24
Peak memory 199768 kb
Host smart-e138f761-db1e-44d9-895c-7937f9cc8f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280179073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2280179073
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1547784614
Short name T983
Test name
Test status
Simulation time 1693647505 ps
CPU time 4.88 seconds
Started Jul 15 04:30:37 PM PDT 24
Finished Jul 15 04:30:44 PM PDT 24
Peak memory 197940 kb
Host smart-a480c214-8411-4fda-815e-416bc273967c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547784614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1547784614
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2204681216
Short name T1006
Test name
Test status
Simulation time 100123531363 ps
CPU time 41.34 seconds
Started Jul 15 04:30:36 PM PDT 24
Finished Jul 15 04:31:19 PM PDT 24
Peak memory 199668 kb
Host smart-190e0ca1-90d9-48a9-aca7-096bf0a16e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204681216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2204681216
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1940316795
Short name T439
Test name
Test status
Simulation time 26149403243 ps
CPU time 14.92 seconds
Started Jul 15 04:30:30 PM PDT 24
Finished Jul 15 04:30:47 PM PDT 24
Peak memory 196152 kb
Host smart-39001ea9-7eef-46e1-b92a-12b1a37fc952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940316795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1940316795
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3959239792
Short name T88
Test name
Test status
Simulation time 112937500 ps
CPU time 0.79 seconds
Started Jul 15 04:30:32 PM PDT 24
Finished Jul 15 04:30:35 PM PDT 24
Peak memory 218172 kb
Host smart-a7172681-1c53-4750-b6dd-7d5241908e22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959239792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3959239792
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1188455556
Short name T399
Test name
Test status
Simulation time 5812626036 ps
CPU time 8.98 seconds
Started Jul 15 04:30:34 PM PDT 24
Finished Jul 15 04:30:44 PM PDT 24
Peak memory 199600 kb
Host smart-d330c24d-c39c-4be5-af07-387920e986b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188455556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1188455556
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3135770301
Short name T1072
Test name
Test status
Simulation time 114496793845 ps
CPU time 512.06 seconds
Started Jul 15 04:30:26 PM PDT 24
Finished Jul 15 04:39:00 PM PDT 24
Peak memory 199672 kb
Host smart-b8106398-455d-4251-b426-c775cd10e732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135770301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3135770301
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.88553767
Short name T436
Test name
Test status
Simulation time 47385138605 ps
CPU time 554.58 seconds
Started Jul 15 04:30:33 PM PDT 24
Finished Jul 15 04:39:49 PM PDT 24
Peak memory 228120 kb
Host smart-1e54b99a-e189-4d36-9b48-6c6415caa94b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88553767 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.88553767
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1797059696
Short name T956
Test name
Test status
Simulation time 1947447106 ps
CPU time 2.14 seconds
Started Jul 15 04:30:49 PM PDT 24
Finished Jul 15 04:30:52 PM PDT 24
Peak memory 198452 kb
Host smart-8d0164b0-f3d3-45d6-a303-6d19f8589979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797059696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1797059696
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.4196244673
Short name T235
Test name
Test status
Simulation time 87906507444 ps
CPU time 216.09 seconds
Started Jul 15 04:30:23 PM PDT 24
Finished Jul 15 04:34:00 PM PDT 24
Peak memory 199788 kb
Host smart-65202d92-6041-46e7-94c8-62ceb480e51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196244673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.4196244673
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.913584797
Short name T383
Test name
Test status
Simulation time 13705678 ps
CPU time 0.56 seconds
Started Jul 15 04:33:07 PM PDT 24
Finished Jul 15 04:33:09 PM PDT 24
Peak memory 195084 kb
Host smart-c325ddca-0e0f-4106-a660-2bcdf6bcfc68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913584797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.913584797
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3353623315
Short name T1
Test name
Test status
Simulation time 92881337090 ps
CPU time 18.54 seconds
Started Jul 15 04:33:00 PM PDT 24
Finished Jul 15 04:33:22 PM PDT 24
Peak memory 199780 kb
Host smart-6714d50c-3ed4-4c47-9843-b2ab838e33b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353623315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3353623315
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.319363451
Short name T604
Test name
Test status
Simulation time 126833467565 ps
CPU time 25.91 seconds
Started Jul 15 04:33:00 PM PDT 24
Finished Jul 15 04:33:29 PM PDT 24
Peak memory 199788 kb
Host smart-c2fcf6c0-2e1e-4d75-abaf-e010e1f08cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319363451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.319363451
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3357681806
Short name T723
Test name
Test status
Simulation time 73544564952 ps
CPU time 103.47 seconds
Started Jul 15 04:33:03 PM PDT 24
Finished Jul 15 04:34:49 PM PDT 24
Peak memory 199808 kb
Host smart-3f592606-3bfa-4a29-95ab-9d982bccb146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357681806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3357681806
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2821494458
Short name T482
Test name
Test status
Simulation time 123356381010 ps
CPU time 389.25 seconds
Started Jul 15 04:33:12 PM PDT 24
Finished Jul 15 04:39:42 PM PDT 24
Peak memory 199728 kb
Host smart-fc5b8092-1ed0-4545-a74c-8ab4b1494e86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821494458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2821494458
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3346250112
Short name T316
Test name
Test status
Simulation time 6133651377 ps
CPU time 3.43 seconds
Started Jul 15 04:33:07 PM PDT 24
Finished Jul 15 04:33:12 PM PDT 24
Peak memory 199392 kb
Host smart-8771fdc6-418d-4e23-9bb0-ca35f0b7c796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346250112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3346250112
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.3600727165
Short name T1175
Test name
Test status
Simulation time 10391204049 ps
CPU time 11.75 seconds
Started Jul 15 04:34:26 PM PDT 24
Finished Jul 15 04:34:39 PM PDT 24
Peak memory 198164 kb
Host smart-2abd8f44-631b-4e73-aa9f-2df5cc967054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600727165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3600727165
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.751646529
Short name T1066
Test name
Test status
Simulation time 15725202644 ps
CPU time 966.9 seconds
Started Jul 15 04:33:13 PM PDT 24
Finished Jul 15 04:49:21 PM PDT 24
Peak memory 199740 kb
Host smart-2ab165e0-ec32-4cf9-9e7f-f5e9c4da4dca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=751646529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.751646529
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3233175051
Short name T982
Test name
Test status
Simulation time 2751788979 ps
CPU time 4.32 seconds
Started Jul 15 04:33:03 PM PDT 24
Finished Jul 15 04:33:10 PM PDT 24
Peak memory 198016 kb
Host smart-194aaba2-9d78-40a8-8213-078f12c8d4ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233175051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3233175051
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.4069857221
Short name T742
Test name
Test status
Simulation time 64263679656 ps
CPU time 25.9 seconds
Started Jul 15 04:33:13 PM PDT 24
Finished Jul 15 04:33:40 PM PDT 24
Peak memory 199536 kb
Host smart-32a3ee02-8d4f-4053-8aca-0e0a0a14d44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069857221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.4069857221
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.571832991
Short name T980
Test name
Test status
Simulation time 1417301495 ps
CPU time 2.8 seconds
Started Jul 15 04:33:08 PM PDT 24
Finished Jul 15 04:33:12 PM PDT 24
Peak memory 195124 kb
Host smart-2cf3d1c0-012a-4455-95da-2bd1a77090a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571832991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.571832991
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3743774675
Short name T360
Test name
Test status
Simulation time 528906852 ps
CPU time 1.28 seconds
Started Jul 15 04:33:01 PM PDT 24
Finished Jul 15 04:33:06 PM PDT 24
Peak memory 198340 kb
Host smart-fd918a59-acd8-490e-85bc-68bc32dd9122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743774675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3743774675
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2515166496
Short name T109
Test name
Test status
Simulation time 353343655881 ps
CPU time 230.36 seconds
Started Jul 15 04:33:07 PM PDT 24
Finished Jul 15 04:36:59 PM PDT 24
Peak memory 215696 kb
Host smart-afa9f15f-c7dd-40e6-88be-e4618a4a2722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515166496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2515166496
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.4160514595
Short name T868
Test name
Test status
Simulation time 223194660985 ps
CPU time 354.76 seconds
Started Jul 15 04:34:26 PM PDT 24
Finished Jul 15 04:40:23 PM PDT 24
Peak memory 216032 kb
Host smart-52920377-a024-4371-b8ad-0dfd6955a7e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160514595 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.4160514595
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3602069997
Short name T285
Test name
Test status
Simulation time 7618720064 ps
CPU time 8.67 seconds
Started Jul 15 04:33:10 PM PDT 24
Finished Jul 15 04:33:20 PM PDT 24
Peak memory 199648 kb
Host smart-1605e14e-1e62-4f4a-a7e7-6573274de82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602069997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3602069997
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.692835260
Short name T1094
Test name
Test status
Simulation time 36988248734 ps
CPU time 24.07 seconds
Started Jul 15 04:33:00 PM PDT 24
Finished Jul 15 04:33:27 PM PDT 24
Peak memory 199696 kb
Host smart-fc344bf7-3984-4524-8315-8ca0c1582757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692835260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.692835260
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.4140130611
Short name T504
Test name
Test status
Simulation time 12374761 ps
CPU time 0.58 seconds
Started Jul 15 04:33:15 PM PDT 24
Finished Jul 15 04:33:17 PM PDT 24
Peak memory 194076 kb
Host smart-a294b077-486f-4356-9212-07df7efcc9ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140130611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4140130611
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2943569181
Short name T1118
Test name
Test status
Simulation time 53981051107 ps
CPU time 47.03 seconds
Started Jul 15 04:33:12 PM PDT 24
Finished Jul 15 04:34:00 PM PDT 24
Peak memory 199696 kb
Host smart-0cba6ec2-76dd-4e37-a7f9-84d6b00e3669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943569181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2943569181
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.657575939
Short name T36
Test name
Test status
Simulation time 100216635713 ps
CPU time 38.58 seconds
Started Jul 15 04:34:27 PM PDT 24
Finished Jul 15 04:35:07 PM PDT 24
Peak memory 199308 kb
Host smart-ee8c3d61-36b7-4553-841d-9bb752b18715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657575939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.657575939
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2244436892
Short name T892
Test name
Test status
Simulation time 105223275846 ps
CPU time 70.52 seconds
Started Jul 15 04:33:09 PM PDT 24
Finished Jul 15 04:34:21 PM PDT 24
Peak memory 199668 kb
Host smart-16ae3fb7-20a1-4565-93ec-c193d5fec249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244436892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2244436892
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1671117669
Short name T731
Test name
Test status
Simulation time 18736213957 ps
CPU time 29.84 seconds
Started Jul 15 04:34:26 PM PDT 24
Finished Jul 15 04:34:58 PM PDT 24
Peak memory 199492 kb
Host smart-8a94ef9c-16bf-4f5e-82ff-b364f7e3376b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671117669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1671117669
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3502531564
Short name T593
Test name
Test status
Simulation time 37862799722 ps
CPU time 275.61 seconds
Started Jul 15 04:33:14 PM PDT 24
Finished Jul 15 04:37:51 PM PDT 24
Peak memory 199672 kb
Host smart-17bf9d13-47f1-4b3c-a870-214b37406f60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502531564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3502531564
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.237838690
Short name T1121
Test name
Test status
Simulation time 10061086461 ps
CPU time 5.34 seconds
Started Jul 15 04:34:26 PM PDT 24
Finished Jul 15 04:34:33 PM PDT 24
Peak memory 198988 kb
Host smart-e2e80ce3-3f0b-496c-9aa1-ce300f9dd424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237838690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.237838690
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1565838554
Short name T653
Test name
Test status
Simulation time 95213281417 ps
CPU time 107.14 seconds
Started Jul 15 04:33:08 PM PDT 24
Finished Jul 15 04:34:56 PM PDT 24
Peak memory 208068 kb
Host smart-890eb75b-2d44-47be-89d7-9536a4aa2f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565838554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1565838554
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1247619582
Short name T1087
Test name
Test status
Simulation time 3513364375 ps
CPU time 51.08 seconds
Started Jul 15 04:33:09 PM PDT 24
Finished Jul 15 04:34:01 PM PDT 24
Peak memory 199792 kb
Host smart-d5cda233-0d67-42b7-8c36-4007e72df913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247619582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1247619582
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3093587427
Short name T563
Test name
Test status
Simulation time 4734428314 ps
CPU time 42.18 seconds
Started Jul 15 04:34:27 PM PDT 24
Finished Jul 15 04:35:11 PM PDT 24
Peak memory 197724 kb
Host smart-f06b1b9c-7918-4cd5-89d7-69b96fd5f015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3093587427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3093587427
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1707050462
Short name T287
Test name
Test status
Simulation time 123258787412 ps
CPU time 45.03 seconds
Started Jul 15 04:33:10 PM PDT 24
Finished Jul 15 04:33:56 PM PDT 24
Peak memory 199760 kb
Host smart-70fc55ad-a8a5-41dc-8289-352c39f8a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707050462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1707050462
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1351953099
Short name T410
Test name
Test status
Simulation time 2621931879 ps
CPU time 2.54 seconds
Started Jul 15 04:33:08 PM PDT 24
Finished Jul 15 04:33:12 PM PDT 24
Peak memory 195756 kb
Host smart-d0e9df7d-fe16-4a66-977e-6a8f03193989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351953099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1351953099
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.818815680
Short name T1144
Test name
Test status
Simulation time 5348696249 ps
CPU time 7.65 seconds
Started Jul 15 04:33:12 PM PDT 24
Finished Jul 15 04:33:20 PM PDT 24
Peak memory 198920 kb
Host smart-5e335a27-a87f-42c9-8f14-54909fd68d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818815680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.818815680
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3728923915
Short name T918
Test name
Test status
Simulation time 121724409565 ps
CPU time 130.9 seconds
Started Jul 15 04:33:14 PM PDT 24
Finished Jul 15 04:35:26 PM PDT 24
Peak memory 215416 kb
Host smart-3ffce3e9-fd31-4e47-91b1-1f3a1ed12291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728923915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3728923915
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.901847365
Short name T597
Test name
Test status
Simulation time 55991336749 ps
CPU time 663.27 seconds
Started Jul 15 04:33:14 PM PDT 24
Finished Jul 15 04:44:18 PM PDT 24
Peak memory 216264 kb
Host smart-6aeaf171-add1-4667-a9af-dc340ad2bd03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901847365 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.901847365
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1026560970
Short name T431
Test name
Test status
Simulation time 7971505451 ps
CPU time 10.96 seconds
Started Jul 15 04:33:07 PM PDT 24
Finished Jul 15 04:33:19 PM PDT 24
Peak memory 199616 kb
Host smart-eb5d850e-4db8-4bb1-b989-d36e55f358c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026560970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1026560970
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1746186079
Short name T474
Test name
Test status
Simulation time 7946902876 ps
CPU time 13.09 seconds
Started Jul 15 04:33:11 PM PDT 24
Finished Jul 15 04:33:25 PM PDT 24
Peak memory 197716 kb
Host smart-781ae19f-2f5a-4122-b53c-126e173c97ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746186079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1746186079
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1048665155
Short name T939
Test name
Test status
Simulation time 29007886 ps
CPU time 0.53 seconds
Started Jul 15 04:33:13 PM PDT 24
Finished Jul 15 04:33:14 PM PDT 24
Peak memory 195204 kb
Host smart-074a57ed-45c3-4eb6-a0bb-7e706369764f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048665155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1048665155
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3459445134
Short name T1156
Test name
Test status
Simulation time 104316135664 ps
CPU time 152.65 seconds
Started Jul 15 04:33:15 PM PDT 24
Finished Jul 15 04:35:48 PM PDT 24
Peak memory 199868 kb
Host smart-a7a23e1a-259f-4bc6-b612-3a5cfc7906ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459445134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3459445134
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.157046182
Short name T1057
Test name
Test status
Simulation time 13086136696 ps
CPU time 16.42 seconds
Started Jul 15 04:33:14 PM PDT 24
Finished Jul 15 04:33:31 PM PDT 24
Peak memory 199772 kb
Host smart-6e28ce7e-00a1-48a3-acbd-3a5b32df4b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157046182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.157046182
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.315377300
Short name T132
Test name
Test status
Simulation time 30801383241 ps
CPU time 9.94 seconds
Started Jul 15 04:33:14 PM PDT 24
Finished Jul 15 04:33:25 PM PDT 24
Peak memory 199744 kb
Host smart-41b67c49-b754-4ad2-a694-23257c3a02bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315377300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.315377300
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.86850959
Short name T573
Test name
Test status
Simulation time 194787688198 ps
CPU time 97.15 seconds
Started Jul 15 04:33:14 PM PDT 24
Finished Jul 15 04:34:53 PM PDT 24
Peak memory 199672 kb
Host smart-e59a721e-4b23-4a4a-b1bd-53366f7259ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86850959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.86850959
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4232886545
Short name T598
Test name
Test status
Simulation time 51785109517 ps
CPU time 58.75 seconds
Started Jul 15 04:33:13 PM PDT 24
Finished Jul 15 04:34:12 PM PDT 24
Peak memory 199764 kb
Host smart-2ffee8fe-c768-4912-a3cb-4a67ab3208c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4232886545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4232886545
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3025291038
Short name T542
Test name
Test status
Simulation time 5790275175 ps
CPU time 10.8 seconds
Started Jul 15 04:33:13 PM PDT 24
Finished Jul 15 04:33:25 PM PDT 24
Peak memory 199440 kb
Host smart-8ccfcc65-c166-4af4-a52e-f55a71ae3417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025291038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3025291038
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1610184807
Short name T247
Test name
Test status
Simulation time 45322972666 ps
CPU time 31.98 seconds
Started Jul 15 04:33:12 PM PDT 24
Finished Jul 15 04:33:45 PM PDT 24
Peak memory 198640 kb
Host smart-8a3ca7e5-0b69-4ed6-94b1-e121455a5a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610184807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1610184807
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3682104526
Short name T237
Test name
Test status
Simulation time 24433752413 ps
CPU time 322.5 seconds
Started Jul 15 04:33:14 PM PDT 24
Finished Jul 15 04:38:37 PM PDT 24
Peak memory 199720 kb
Host smart-9552bc91-7acd-4f3a-82d6-15ad171e03e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682104526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3682104526
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1665359418
Short name T391
Test name
Test status
Simulation time 5769136681 ps
CPU time 14.15 seconds
Started Jul 15 04:33:14 PM PDT 24
Finished Jul 15 04:33:29 PM PDT 24
Peak memory 197928 kb
Host smart-dc7df34d-fa5f-48e6-a329-a45ea0dab7f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1665359418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1665359418
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.873379758
Short name T1055
Test name
Test status
Simulation time 53007902869 ps
CPU time 39.5 seconds
Started Jul 15 04:33:15 PM PDT 24
Finished Jul 15 04:33:56 PM PDT 24
Peak memory 199588 kb
Host smart-45eae57b-601d-4f3c-a682-70fd7be59653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873379758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.873379758
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.615575806
Short name T507
Test name
Test status
Simulation time 1783986175 ps
CPU time 2.08 seconds
Started Jul 15 04:33:15 PM PDT 24
Finished Jul 15 04:33:18 PM PDT 24
Peak memory 195184 kb
Host smart-a48eeb9a-f8e8-406d-bd46-e2d36ba89d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615575806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.615575806
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1355938610
Short name T802
Test name
Test status
Simulation time 472079218 ps
CPU time 1.15 seconds
Started Jul 15 04:33:14 PM PDT 24
Finished Jul 15 04:33:16 PM PDT 24
Peak memory 198092 kb
Host smart-7755dda9-ff30-4654-84c9-b783d5f35d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355938610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1355938610
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.708700655
Short name T1097
Test name
Test status
Simulation time 41440656120 ps
CPU time 712.45 seconds
Started Jul 15 04:33:14 PM PDT 24
Finished Jul 15 04:45:07 PM PDT 24
Peak memory 216316 kb
Host smart-3a116e44-df69-46f3-b714-4c2e6bd42ef8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708700655 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.708700655
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.887193016
Short name T600
Test name
Test status
Simulation time 496592273 ps
CPU time 1.19 seconds
Started Jul 15 04:33:15 PM PDT 24
Finished Jul 15 04:33:17 PM PDT 24
Peak memory 198608 kb
Host smart-53df1191-0023-4620-97de-cfbde48c5232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887193016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.887193016
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3580492224
Short name T1051
Test name
Test status
Simulation time 6105040074 ps
CPU time 10.3 seconds
Started Jul 15 04:33:13 PM PDT 24
Finished Jul 15 04:33:25 PM PDT 24
Peak memory 197048 kb
Host smart-2c057f23-1e28-4efc-96b8-a0cab59ea63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580492224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3580492224
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.578185469
Short name T740
Test name
Test status
Simulation time 45912498 ps
CPU time 0.54 seconds
Started Jul 15 04:33:21 PM PDT 24
Finished Jul 15 04:33:23 PM PDT 24
Peak memory 194060 kb
Host smart-69225969-43a2-40c7-8426-45375ef4635f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578185469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.578185469
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3293774282
Short name T703
Test name
Test status
Simulation time 276291667979 ps
CPU time 640.35 seconds
Started Jul 15 04:34:27 PM PDT 24
Finished Jul 15 04:45:09 PM PDT 24
Peak memory 199484 kb
Host smart-5edef0f1-f070-4ee4-a42b-d4963c945c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293774282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3293774282
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2378812102
Short name T295
Test name
Test status
Simulation time 51993986529 ps
CPU time 56.25 seconds
Started Jul 15 04:33:21 PM PDT 24
Finished Jul 15 04:34:18 PM PDT 24
Peak memory 199784 kb
Host smart-e67608e1-b446-453c-8127-c047ca9a5025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378812102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2378812102
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.318556052
Short name T519
Test name
Test status
Simulation time 62222530793 ps
CPU time 39.03 seconds
Started Jul 15 04:33:37 PM PDT 24
Finished Jul 15 04:34:16 PM PDT 24
Peak memory 199680 kb
Host smart-73b8b8f7-3b86-4a92-8643-95871b90bb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318556052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.318556052
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1755978744
Short name T889
Test name
Test status
Simulation time 8590605877 ps
CPU time 4.38 seconds
Started Jul 15 04:33:22 PM PDT 24
Finished Jul 15 04:33:28 PM PDT 24
Peak memory 199668 kb
Host smart-90793d29-e821-438d-a3ad-f8f1e6218000
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755978744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1755978744
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2027699854
Short name T1135
Test name
Test status
Simulation time 32041328776 ps
CPU time 124.41 seconds
Started Jul 15 04:33:24 PM PDT 24
Finished Jul 15 04:35:30 PM PDT 24
Peak memory 199632 kb
Host smart-ce6ee0cd-141d-4796-a8e6-d13f87aa8741
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2027699854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2027699854
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3687664693
Short name T460
Test name
Test status
Simulation time 10489328674 ps
CPU time 7.8 seconds
Started Jul 15 04:33:24 PM PDT 24
Finished Jul 15 04:33:34 PM PDT 24
Peak memory 199160 kb
Host smart-005b8cfb-975e-4ce7-9ff0-d6c8ee4ea145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687664693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3687664693
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2016788272
Short name T922
Test name
Test status
Simulation time 226124754832 ps
CPU time 59.39 seconds
Started Jul 15 04:34:27 PM PDT 24
Finished Jul 15 04:35:28 PM PDT 24
Peak memory 199768 kb
Host smart-be47b77e-7c25-4272-a796-a5de5b12f21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016788272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2016788272
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3196715740
Short name T233
Test name
Test status
Simulation time 7127776894 ps
CPU time 383.81 seconds
Started Jul 15 04:33:32 PM PDT 24
Finished Jul 15 04:39:57 PM PDT 24
Peak memory 199104 kb
Host smart-bf1d49af-ebbb-4c1b-88c4-344d81c5d5bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3196715740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3196715740
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.326443639
Short name T646
Test name
Test status
Simulation time 7316122773 ps
CPU time 15.08 seconds
Started Jul 15 04:33:23 PM PDT 24
Finished Jul 15 04:33:40 PM PDT 24
Peak memory 197728 kb
Host smart-db0d2c26-35a0-4f48-ab36-a35d271a819f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=326443639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.326443639
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1311561526
Short name T244
Test name
Test status
Simulation time 61628822452 ps
CPU time 122.21 seconds
Started Jul 15 04:34:27 PM PDT 24
Finished Jul 15 04:36:31 PM PDT 24
Peak memory 199492 kb
Host smart-54359288-9a87-41aa-bf25-2f08aaa131fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311561526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1311561526
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.498042714
Short name T1035
Test name
Test status
Simulation time 3276742328 ps
CPU time 2.73 seconds
Started Jul 15 04:33:19 PM PDT 24
Finished Jul 15 04:33:23 PM PDT 24
Peak memory 196328 kb
Host smart-76dd506e-4993-4208-b616-267be5976d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498042714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.498042714
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1396948208
Short name T315
Test name
Test status
Simulation time 297652313 ps
CPU time 1.18 seconds
Started Jul 15 04:33:23 PM PDT 24
Finished Jul 15 04:33:25 PM PDT 24
Peak memory 198096 kb
Host smart-a103c57b-6617-4097-b440-d89876f720ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396948208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1396948208
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.4140902584
Short name T466
Test name
Test status
Simulation time 579015935982 ps
CPU time 870.99 seconds
Started Jul 15 04:33:23 PM PDT 24
Finished Jul 15 04:47:56 PM PDT 24
Peak memory 216496 kb
Host smart-659361e7-18cf-47d8-b908-c3e1ebd67148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140902584 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.4140902584
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.836083931
Short name T893
Test name
Test status
Simulation time 1001562528 ps
CPU time 2.45 seconds
Started Jul 15 04:33:23 PM PDT 24
Finished Jul 15 04:33:26 PM PDT 24
Peak memory 198792 kb
Host smart-61bd0842-7a40-494d-8df8-0741086d1741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836083931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.836083931
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2534640684
Short name T530
Test name
Test status
Simulation time 476716050108 ps
CPU time 71.88 seconds
Started Jul 15 04:33:24 PM PDT 24
Finished Jul 15 04:34:38 PM PDT 24
Peak memory 199732 kb
Host smart-e2987e9e-f801-4503-9c81-3842e9237f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534640684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2534640684
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2647772354
Short name T411
Test name
Test status
Simulation time 12674773 ps
CPU time 0.54 seconds
Started Jul 15 04:33:23 PM PDT 24
Finished Jul 15 04:33:25 PM PDT 24
Peak memory 195052 kb
Host smart-9043e8fe-1f85-4b05-b72c-e3ad12d4a835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647772354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2647772354
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3607698203
Short name T38
Test name
Test status
Simulation time 277580747474 ps
CPU time 454.91 seconds
Started Jul 15 04:33:22 PM PDT 24
Finished Jul 15 04:40:58 PM PDT 24
Peak memory 199648 kb
Host smart-4813a152-8832-4508-baa5-b6313f389418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607698203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3607698203
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3852905540
Short name T428
Test name
Test status
Simulation time 169636376210 ps
CPU time 237.96 seconds
Started Jul 15 04:33:32 PM PDT 24
Finished Jul 15 04:37:31 PM PDT 24
Peak memory 199040 kb
Host smart-7860a30f-9776-4a61-9d90-e73aec53686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852905540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3852905540
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1760485199
Short name T642
Test name
Test status
Simulation time 153707211255 ps
CPU time 48.09 seconds
Started Jul 15 04:33:32 PM PDT 24
Finished Jul 15 04:34:21 PM PDT 24
Peak memory 199784 kb
Host smart-0734092d-b757-4444-97fb-93bb9d8e4a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760485199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1760485199
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1140141148
Short name T1148
Test name
Test status
Simulation time 27074635197 ps
CPU time 18.28 seconds
Started Jul 15 04:33:21 PM PDT 24
Finished Jul 15 04:33:40 PM PDT 24
Peak memory 199760 kb
Host smart-29b8f12a-d5bc-46a8-aa26-fa8ac995edb9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140141148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1140141148
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1752068743
Short name T254
Test name
Test status
Simulation time 104321291555 ps
CPU time 761.06 seconds
Started Jul 15 04:33:21 PM PDT 24
Finished Jul 15 04:46:02 PM PDT 24
Peak memory 199656 kb
Host smart-624e88fa-b95d-4d35-bb6b-602789045a92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1752068743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1752068743
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1192893722
Short name T1127
Test name
Test status
Simulation time 384546016 ps
CPU time 1.12 seconds
Started Jul 15 04:33:22 PM PDT 24
Finished Jul 15 04:33:25 PM PDT 24
Peak memory 195820 kb
Host smart-e5979f79-bd39-4f40-b68d-d0deb92c208d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192893722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1192893722
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3169294941
Short name T971
Test name
Test status
Simulation time 239648313751 ps
CPU time 76.98 seconds
Started Jul 15 04:33:22 PM PDT 24
Finished Jul 15 04:34:40 PM PDT 24
Peak memory 199908 kb
Host smart-2718d550-518b-43a4-b400-7713f1ff5e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169294941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3169294941
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3643467010
Short name T239
Test name
Test status
Simulation time 3948191875 ps
CPU time 144.05 seconds
Started Jul 15 04:33:32 PM PDT 24
Finished Jul 15 04:35:57 PM PDT 24
Peak memory 199800 kb
Host smart-ebd69243-849b-4a8e-a425-a190fd653aa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643467010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3643467010
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.794508553
Short name T356
Test name
Test status
Simulation time 5562239584 ps
CPU time 22.21 seconds
Started Jul 15 04:34:27 PM PDT 24
Finished Jul 15 04:34:51 PM PDT 24
Peak memory 197728 kb
Host smart-8375938b-33ed-4f71-8eed-466758d82a95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794508553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.794508553
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1751261676
Short name T902
Test name
Test status
Simulation time 61527774190 ps
CPU time 95.61 seconds
Started Jul 15 04:33:22 PM PDT 24
Finished Jul 15 04:34:59 PM PDT 24
Peak memory 199612 kb
Host smart-124a2e86-d181-40cc-8675-6442d42e2bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751261676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1751261676
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3469081247
Short name T1093
Test name
Test status
Simulation time 1836477209 ps
CPU time 1.4 seconds
Started Jul 15 04:33:24 PM PDT 24
Finished Jul 15 04:33:27 PM PDT 24
Peak memory 195160 kb
Host smart-59f736d2-3444-4050-a8d3-3f671b7e6b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469081247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3469081247
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1748300491
Short name T782
Test name
Test status
Simulation time 898483128 ps
CPU time 2.06 seconds
Started Jul 15 04:33:23 PM PDT 24
Finished Jul 15 04:33:26 PM PDT 24
Peak memory 199172 kb
Host smart-73e13290-54d9-42bf-8718-85a544f4cf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748300491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1748300491
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.15780811
Short name T668
Test name
Test status
Simulation time 307543814900 ps
CPU time 1170.67 seconds
Started Jul 15 04:33:22 PM PDT 24
Finished Jul 15 04:52:54 PM PDT 24
Peak memory 199652 kb
Host smart-11b5182d-828f-4e3e-a446-cceba6cf5627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15780811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.15780811
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3230020628
Short name T533
Test name
Test status
Simulation time 26674782958 ps
CPU time 400.89 seconds
Started Jul 15 04:33:24 PM PDT 24
Finished Jul 15 04:40:06 PM PDT 24
Peak memory 215380 kb
Host smart-a32225a3-5251-43d2-9a61-acfa65520537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230020628 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3230020628
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1350487640
Short name T376
Test name
Test status
Simulation time 1063516996 ps
CPU time 3.06 seconds
Started Jul 15 04:33:28 PM PDT 24
Finished Jul 15 04:33:31 PM PDT 24
Peak memory 198668 kb
Host smart-ed3f7c90-b468-4309-85ca-16a2c00b42e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350487640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1350487640
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2000297359
Short name T639
Test name
Test status
Simulation time 99775497168 ps
CPU time 205.64 seconds
Started Jul 15 04:33:32 PM PDT 24
Finished Jul 15 04:36:59 PM PDT 24
Peak memory 199692 kb
Host smart-1a272377-9047-4842-9972-5b095527bfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000297359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2000297359
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3263328384
Short name T19
Test name
Test status
Simulation time 22215228 ps
CPU time 0.52 seconds
Started Jul 15 04:33:27 PM PDT 24
Finished Jul 15 04:33:29 PM PDT 24
Peak memory 195460 kb
Host smart-07dd88f0-320c-4b0a-bf2a-c4e0c7890b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263328384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3263328384
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.4083052588
Short name T429
Test name
Test status
Simulation time 45147251228 ps
CPU time 85.4 seconds
Started Jul 15 04:33:21 PM PDT 24
Finished Jul 15 04:34:47 PM PDT 24
Peak memory 199660 kb
Host smart-d8574b27-adba-492c-9fa1-1e5bc63bc9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083052588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.4083052588
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3260486447
Short name T465
Test name
Test status
Simulation time 162957792404 ps
CPU time 264.2 seconds
Started Jul 15 04:33:22 PM PDT 24
Finished Jul 15 04:37:48 PM PDT 24
Peak memory 199772 kb
Host smart-34cb610b-153a-4ede-9f74-0c9074a8ab8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260486447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3260486447
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1558380624
Short name T684
Test name
Test status
Simulation time 14242447257 ps
CPU time 23.81 seconds
Started Jul 15 04:33:24 PM PDT 24
Finished Jul 15 04:33:49 PM PDT 24
Peak memory 199772 kb
Host smart-4256b4f0-a9a8-491a-a1c0-3968b9b0336b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558380624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1558380624
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3651601642
Short name T1177
Test name
Test status
Simulation time 287743609688 ps
CPU time 192.9 seconds
Started Jul 15 04:33:28 PM PDT 24
Finished Jul 15 04:36:42 PM PDT 24
Peak memory 199648 kb
Host smart-a279e0e5-f873-47d6-8f99-d61e94de0746
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651601642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3651601642
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2138309739
Short name T599
Test name
Test status
Simulation time 86493049242 ps
CPU time 639.55 seconds
Started Jul 15 04:33:29 PM PDT 24
Finished Jul 15 04:44:10 PM PDT 24
Peak memory 199752 kb
Host smart-58771e21-ce21-4796-acde-3888ffb0f9b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138309739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2138309739
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3524771117
Short name T480
Test name
Test status
Simulation time 8756128818 ps
CPU time 19.89 seconds
Started Jul 15 04:33:30 PM PDT 24
Finished Jul 15 04:33:51 PM PDT 24
Peak memory 199188 kb
Host smart-ce4a6dac-1d37-4c0e-8693-ca5f3422f8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524771117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3524771117
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1401938294
Short name T873
Test name
Test status
Simulation time 59540502749 ps
CPU time 94.43 seconds
Started Jul 15 04:33:29 PM PDT 24
Finished Jul 15 04:35:05 PM PDT 24
Peak memory 199876 kb
Host smart-279e6afa-f89b-43f8-9e66-ea4a3adc162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401938294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1401938294
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1154560803
Short name T537
Test name
Test status
Simulation time 10729673970 ps
CPU time 549.19 seconds
Started Jul 15 04:33:28 PM PDT 24
Finished Jul 15 04:42:39 PM PDT 24
Peak memory 199752 kb
Host smart-d6ce0eb0-e07c-4dc8-a2fa-d7cbc31bf8dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1154560803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1154560803
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.77075923
Short name T3
Test name
Test status
Simulation time 3819562853 ps
CPU time 33.04 seconds
Started Jul 15 04:33:28 PM PDT 24
Finished Jul 15 04:34:03 PM PDT 24
Peak memory 198112 kb
Host smart-85e0b8b1-448a-42e3-9e73-7eb2d560d325
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77075923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.77075923
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.4220061763
Short name T45
Test name
Test status
Simulation time 46464373694 ps
CPU time 28.16 seconds
Started Jul 15 04:33:28 PM PDT 24
Finished Jul 15 04:33:57 PM PDT 24
Peak memory 200036 kb
Host smart-99ccc1ab-0e6e-420b-b781-97aed6608d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220061763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.4220061763
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3858268399
Short name T817
Test name
Test status
Simulation time 3287359436 ps
CPU time 1.69 seconds
Started Jul 15 04:33:29 PM PDT 24
Finished Jul 15 04:33:32 PM PDT 24
Peak memory 196252 kb
Host smart-db5cb11d-d405-4115-bb4b-d435c301d132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858268399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3858268399
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.605333901
Short name T859
Test name
Test status
Simulation time 920274017 ps
CPU time 1.78 seconds
Started Jul 15 04:33:23 PM PDT 24
Finished Jul 15 04:33:26 PM PDT 24
Peak memory 199396 kb
Host smart-63217f04-b5fd-4c33-909d-f06c8c5aa604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605333901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.605333901
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1204182533
Short name T641
Test name
Test status
Simulation time 252641332911 ps
CPU time 119.34 seconds
Started Jul 15 04:33:28 PM PDT 24
Finished Jul 15 04:35:29 PM PDT 24
Peak memory 216136 kb
Host smart-f948e39f-9543-4b99-999a-c07739adfc82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204182533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1204182533
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2744178927
Short name T1164
Test name
Test status
Simulation time 80870554505 ps
CPU time 417.2 seconds
Started Jul 15 04:33:30 PM PDT 24
Finished Jul 15 04:40:28 PM PDT 24
Peak memory 216440 kb
Host smart-fa68de1e-33ee-4557-8f3a-9dc7f92f8f0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744178927 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2744178927
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3875623469
Short name T880
Test name
Test status
Simulation time 2351871360 ps
CPU time 2.22 seconds
Started Jul 15 04:33:28 PM PDT 24
Finished Jul 15 04:33:32 PM PDT 24
Peak memory 198700 kb
Host smart-25adf42b-621f-452e-9664-0c78d3f073e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875623469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3875623469
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2968736390
Short name T362
Test name
Test status
Simulation time 7040091708 ps
CPU time 4.5 seconds
Started Jul 15 04:33:23 PM PDT 24
Finished Jul 15 04:33:29 PM PDT 24
Peak memory 199652 kb
Host smart-a75e9ce6-1396-4105-8dd3-20ca7463e92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968736390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2968736390
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.4020156050
Short name T975
Test name
Test status
Simulation time 21666142 ps
CPU time 0.53 seconds
Started Jul 15 04:33:27 PM PDT 24
Finished Jul 15 04:33:28 PM PDT 24
Peak memory 194340 kb
Host smart-7a9dcebb-110c-40df-84bd-72544928aa6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020156050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4020156050
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.4084703183
Short name T710
Test name
Test status
Simulation time 24799750592 ps
CPU time 9.51 seconds
Started Jul 15 04:33:29 PM PDT 24
Finished Jul 15 04:33:40 PM PDT 24
Peak memory 199732 kb
Host smart-ea2e9b6c-5d26-462c-aa8f-ebf5fb3f72d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084703183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.4084703183
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2370729228
Short name T141
Test name
Test status
Simulation time 154910085107 ps
CPU time 121.65 seconds
Started Jul 15 04:33:28 PM PDT 24
Finished Jul 15 04:35:30 PM PDT 24
Peak memory 199648 kb
Host smart-86a81e05-7444-4252-8a8d-c4722c8d6d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370729228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2370729228
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1759180801
Short name T210
Test name
Test status
Simulation time 34636888699 ps
CPU time 13.65 seconds
Started Jul 15 04:33:33 PM PDT 24
Finished Jul 15 04:33:47 PM PDT 24
Peak memory 199732 kb
Host smart-71a1400e-7edc-4d3b-8084-a9501523b155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759180801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1759180801
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2138678183
Short name T788
Test name
Test status
Simulation time 3650204838 ps
CPU time 6.17 seconds
Started Jul 15 04:33:31 PM PDT 24
Finished Jul 15 04:33:38 PM PDT 24
Peak memory 196284 kb
Host smart-c4bec7b4-a0fd-47ca-bbf8-8e8f0721a908
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138678183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2138678183
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3926251563
Short name T853
Test name
Test status
Simulation time 62434367469 ps
CPU time 363.31 seconds
Started Jul 15 04:33:27 PM PDT 24
Finished Jul 15 04:39:31 PM PDT 24
Peak memory 199664 kb
Host smart-93608cd5-f2b5-4a58-ae61-db8c340260ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926251563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3926251563
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.474462366
Short name T556
Test name
Test status
Simulation time 14647832826 ps
CPU time 8.32 seconds
Started Jul 15 04:33:31 PM PDT 24
Finished Jul 15 04:33:41 PM PDT 24
Peak memory 199684 kb
Host smart-f8f97a74-26d8-4efb-bcb4-7d8ba24d09c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474462366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.474462366
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1285011551
Short name T947
Test name
Test status
Simulation time 22930911542 ps
CPU time 9.08 seconds
Started Jul 15 04:33:31 PM PDT 24
Finished Jul 15 04:33:42 PM PDT 24
Peak memory 199748 kb
Host smart-443a0271-0e63-4827-bbd0-a1062c9b5acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285011551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1285011551
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2712814491
Short name T944
Test name
Test status
Simulation time 6615945432 ps
CPU time 314.46 seconds
Started Jul 15 04:33:29 PM PDT 24
Finished Jul 15 04:38:44 PM PDT 24
Peak memory 199776 kb
Host smart-cff52e2c-a0a9-46c3-a6fc-4c4221459050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712814491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2712814491
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1465295848
Short name T420
Test name
Test status
Simulation time 2343417910 ps
CPU time 3.54 seconds
Started Jul 15 04:33:28 PM PDT 24
Finished Jul 15 04:33:33 PM PDT 24
Peak memory 198348 kb
Host smart-d37c8f2b-fc07-4f93-b6a8-b20917d6a384
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1465295848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1465295848
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2795777499
Short name T1047
Test name
Test status
Simulation time 55146408094 ps
CPU time 42.69 seconds
Started Jul 15 04:33:28 PM PDT 24
Finished Jul 15 04:34:11 PM PDT 24
Peak memory 199632 kb
Host smart-43865f15-3b40-4885-8517-cfdfba2d4218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795777499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2795777499
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2537388079
Short name T707
Test name
Test status
Simulation time 6310769062 ps
CPU time 2.92 seconds
Started Jul 15 04:33:31 PM PDT 24
Finished Jul 15 04:33:35 PM PDT 24
Peak memory 196020 kb
Host smart-4d6bc8bd-e639-462f-b032-fbb9cfe817b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537388079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2537388079
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2538346379
Short name T248
Test name
Test status
Simulation time 5722431147 ps
CPU time 15 seconds
Started Jul 15 04:33:31 PM PDT 24
Finished Jul 15 04:33:48 PM PDT 24
Peak memory 199712 kb
Host smart-12e2204a-39e4-4ffa-889f-65d142c2fe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538346379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2538346379
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1649769492
Short name T1071
Test name
Test status
Simulation time 115968626659 ps
CPU time 74.33 seconds
Started Jul 15 04:33:30 PM PDT 24
Finished Jul 15 04:34:45 PM PDT 24
Peak memory 199688 kb
Host smart-a19a922d-0dbf-4f54-b354-7c917c79d663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649769492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1649769492
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.788249994
Short name T792
Test name
Test status
Simulation time 134523837300 ps
CPU time 1019.33 seconds
Started Jul 15 04:33:33 PM PDT 24
Finished Jul 15 04:50:33 PM PDT 24
Peak memory 216232 kb
Host smart-d1e3b203-9c40-48bb-8a5b-c6c59d2e07a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788249994 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.788249994
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.345440763
Short name T366
Test name
Test status
Simulation time 1091345621 ps
CPU time 3.04 seconds
Started Jul 15 04:33:28 PM PDT 24
Finished Jul 15 04:33:33 PM PDT 24
Peak memory 199116 kb
Host smart-8b994ae4-f594-44d4-8790-f01626139e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345440763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.345440763
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3367594931
Short name T1081
Test name
Test status
Simulation time 91635957888 ps
CPU time 102.7 seconds
Started Jul 15 04:33:29 PM PDT 24
Finished Jul 15 04:35:13 PM PDT 24
Peak memory 199700 kb
Host smart-277f239f-2d68-41ab-bd71-d8bd119eee8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367594931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3367594931
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.4027770993
Short name T949
Test name
Test status
Simulation time 29315736 ps
CPU time 0.56 seconds
Started Jul 15 04:33:38 PM PDT 24
Finished Jul 15 04:33:40 PM PDT 24
Peak memory 194672 kb
Host smart-cc582fb6-3283-467f-bdd2-4b798fb4ea86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027770993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.4027770993
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3823719235
Short name T803
Test name
Test status
Simulation time 38826621905 ps
CPU time 37.47 seconds
Started Jul 15 04:33:35 PM PDT 24
Finished Jul 15 04:34:13 PM PDT 24
Peak memory 199720 kb
Host smart-3394f853-9061-4ef2-9295-046b3f84e82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823719235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3823719235
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1715943801
Short name T831
Test name
Test status
Simulation time 32100917503 ps
CPU time 25.9 seconds
Started Jul 15 04:33:34 PM PDT 24
Finished Jul 15 04:34:01 PM PDT 24
Peak memory 199696 kb
Host smart-64776f12-d890-452b-a3bd-d9bc3408c7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715943801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1715943801
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2902033613
Short name T375
Test name
Test status
Simulation time 49441353919 ps
CPU time 11.6 seconds
Started Jul 15 04:33:35 PM PDT 24
Finished Jul 15 04:33:47 PM PDT 24
Peak memory 199148 kb
Host smart-dac1d18c-8ebe-4469-ab58-1b7aece5a11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902033613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2902033613
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1850988675
Short name T251
Test name
Test status
Simulation time 49034940122 ps
CPU time 30.72 seconds
Started Jul 15 04:33:40 PM PDT 24
Finished Jul 15 04:34:11 PM PDT 24
Peak memory 199680 kb
Host smart-a637fb88-e125-40f0-9770-53871c8840c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850988675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1850988675
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1688520881
Short name T338
Test name
Test status
Simulation time 143400498403 ps
CPU time 238.34 seconds
Started Jul 15 04:33:37 PM PDT 24
Finished Jul 15 04:37:37 PM PDT 24
Peak memory 199748 kb
Host smart-c5e7d1be-7614-496e-a19f-0f9ded3be78a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688520881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1688520881
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.4228927959
Short name T325
Test name
Test status
Simulation time 872880664 ps
CPU time 0.91 seconds
Started Jul 15 04:33:37 PM PDT 24
Finished Jul 15 04:33:39 PM PDT 24
Peak memory 195380 kb
Host smart-53fe2608-eada-4655-8ec0-432ca91a3a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228927959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.4228927959
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.4052616746
Short name T1021
Test name
Test status
Simulation time 23726422389 ps
CPU time 17.58 seconds
Started Jul 15 04:33:35 PM PDT 24
Finished Jul 15 04:33:54 PM PDT 24
Peak memory 197332 kb
Host smart-ed5436aa-03cb-4e6f-b718-ebb707da5389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052616746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.4052616746
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2838421617
Short name T256
Test name
Test status
Simulation time 16122319837 ps
CPU time 49.24 seconds
Started Jul 15 04:33:39 PM PDT 24
Finished Jul 15 04:34:29 PM PDT 24
Peak memory 199792 kb
Host smart-9b59d08a-7dcc-4e61-8004-395ff76372f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838421617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2838421617
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4280606862
Short name T386
Test name
Test status
Simulation time 4779915117 ps
CPU time 7.64 seconds
Started Jul 15 04:33:39 PM PDT 24
Finished Jul 15 04:33:47 PM PDT 24
Peak memory 198512 kb
Host smart-91cf9064-974e-4b01-bfdc-cf235025984c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280606862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4280606862
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2232823483
Short name T236
Test name
Test status
Simulation time 141517760482 ps
CPU time 35.12 seconds
Started Jul 15 04:33:35 PM PDT 24
Finished Jul 15 04:34:11 PM PDT 24
Peak memory 199700 kb
Host smart-ddd95418-d947-455f-b175-fe4e27aadfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232823483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2232823483
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3156822994
Short name T1063
Test name
Test status
Simulation time 1279367525 ps
CPU time 2.4 seconds
Started Jul 15 04:33:34 PM PDT 24
Finished Jul 15 04:33:38 PM PDT 24
Peak memory 195200 kb
Host smart-ad4140d0-0439-4c5e-bede-186aa478653c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156822994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3156822994
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3859404944
Short name T1024
Test name
Test status
Simulation time 244588507 ps
CPU time 1.36 seconds
Started Jul 15 04:33:33 PM PDT 24
Finished Jul 15 04:33:35 PM PDT 24
Peak memory 198132 kb
Host smart-3cc15617-cca7-4191-9cc4-2426d24006e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859404944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3859404944
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3886611592
Short name T113
Test name
Test status
Simulation time 163421113545 ps
CPU time 295.7 seconds
Started Jul 15 04:33:35 PM PDT 24
Finished Jul 15 04:38:32 PM PDT 24
Peak memory 199712 kb
Host smart-d9e377bc-3f0c-49ee-a64f-6a650f6dcb60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886611592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3886611592
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2816683714
Short name T101
Test name
Test status
Simulation time 86460218676 ps
CPU time 919.32 seconds
Started Jul 15 04:33:33 PM PDT 24
Finished Jul 15 04:48:54 PM PDT 24
Peak memory 224800 kb
Host smart-33cceabf-a4d8-4489-a8e5-0089578f7967
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816683714 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2816683714
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2332978461
Short name T1014
Test name
Test status
Simulation time 937132883 ps
CPU time 2.78 seconds
Started Jul 15 04:33:34 PM PDT 24
Finished Jul 15 04:33:38 PM PDT 24
Peak memory 199136 kb
Host smart-4beef2fe-8ff3-4577-ae0e-0142f9820f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332978461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2332978461
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1356375245
Short name T1172
Test name
Test status
Simulation time 470520701323 ps
CPU time 56.57 seconds
Started Jul 15 04:33:32 PM PDT 24
Finished Jul 15 04:34:30 PM PDT 24
Peak memory 199852 kb
Host smart-00c8f3a3-2406-4bd4-8093-d15dae12e1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356375245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1356375245
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1160883993
Short name T735
Test name
Test status
Simulation time 11525871 ps
CPU time 0.56 seconds
Started Jul 15 04:33:43 PM PDT 24
Finished Jul 15 04:33:44 PM PDT 24
Peak memory 195368 kb
Host smart-ed7d1d04-9b5f-49d3-9954-45471e4baa27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160883993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1160883993
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1632757157
Short name T1089
Test name
Test status
Simulation time 25047185266 ps
CPU time 27.07 seconds
Started Jul 15 04:33:35 PM PDT 24
Finished Jul 15 04:34:03 PM PDT 24
Peak memory 199612 kb
Host smart-3222be35-a9aa-443a-8715-07efb4290493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632757157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1632757157
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2770524121
Short name T565
Test name
Test status
Simulation time 16942323123 ps
CPU time 27.63 seconds
Started Jul 15 04:33:39 PM PDT 24
Finished Jul 15 04:34:07 PM PDT 24
Peak memory 199524 kb
Host smart-189396bc-ea9a-42fd-965e-154d24fd83ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770524121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2770524121
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.467993228
Short name T1010
Test name
Test status
Simulation time 31207573603 ps
CPU time 16.2 seconds
Started Jul 15 04:33:38 PM PDT 24
Finished Jul 15 04:33:55 PM PDT 24
Peak memory 199676 kb
Host smart-a60092c5-4268-49f7-bd13-a0d891ec64c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467993228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.467993228
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3151576974
Short name T282
Test name
Test status
Simulation time 11849987058 ps
CPU time 4.29 seconds
Started Jul 15 04:33:37 PM PDT 24
Finished Jul 15 04:33:42 PM PDT 24
Peak memory 199540 kb
Host smart-e1916d18-3495-43a9-91ec-b0ff26e162da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151576974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3151576974
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.370003816
Short name T887
Test name
Test status
Simulation time 85649644444 ps
CPU time 749.97 seconds
Started Jul 15 04:33:43 PM PDT 24
Finished Jul 15 04:46:15 PM PDT 24
Peak memory 199836 kb
Host smart-5aa3dfcd-b5be-44b1-b06a-4019e93aaff7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370003816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.370003816
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.4128492431
Short name T657
Test name
Test status
Simulation time 6906669699 ps
CPU time 7.34 seconds
Started Jul 15 04:33:43 PM PDT 24
Finished Jul 15 04:33:52 PM PDT 24
Peak memory 198724 kb
Host smart-d2a5b4ba-333f-4565-acc6-05f599bb4cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128492431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.4128492431
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3425796871
Short name T881
Test name
Test status
Simulation time 88600501038 ps
CPU time 130.42 seconds
Started Jul 15 04:33:35 PM PDT 24
Finished Jul 15 04:35:47 PM PDT 24
Peak memory 198888 kb
Host smart-a1c5d4dc-96aa-42af-b1b9-3bfd3a80a38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425796871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3425796871
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.4204769001
Short name T1053
Test name
Test status
Simulation time 4723559622 ps
CPU time 174.25 seconds
Started Jul 15 04:33:42 PM PDT 24
Finished Jul 15 04:36:37 PM PDT 24
Peak memory 199716 kb
Host smart-c918224a-83cb-48e2-b385-ea1e0eab3758
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204769001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.4204769001
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.399070786
Short name T437
Test name
Test status
Simulation time 7661626625 ps
CPU time 11.05 seconds
Started Jul 15 04:33:39 PM PDT 24
Finished Jul 15 04:33:51 PM PDT 24
Peak memory 198632 kb
Host smart-4ab120b8-b54e-47fb-bae2-209987f3c820
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399070786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.399070786
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2911057848
Short name T367
Test name
Test status
Simulation time 90328568994 ps
CPU time 128.04 seconds
Started Jul 15 04:33:40 PM PDT 24
Finished Jul 15 04:35:49 PM PDT 24
Peak memory 199756 kb
Host smart-f07da16a-862d-4485-86a2-85e571417018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911057848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2911057848
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2525381472
Short name T753
Test name
Test status
Simulation time 2751482013 ps
CPU time 2.72 seconds
Started Jul 15 04:33:36 PM PDT 24
Finished Jul 15 04:33:40 PM PDT 24
Peak memory 195568 kb
Host smart-1a627501-a441-4de6-9562-5c20577bdb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525381472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2525381472
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.529404245
Short name T882
Test name
Test status
Simulation time 5476962008 ps
CPU time 7.23 seconds
Started Jul 15 04:33:36 PM PDT 24
Finished Jul 15 04:33:44 PM PDT 24
Peak memory 199492 kb
Host smart-edd36599-f806-45b5-a5bd-8472c99e7985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529404245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.529404245
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3247297718
Short name T209
Test name
Test status
Simulation time 286051568087 ps
CPU time 488.49 seconds
Started Jul 15 04:33:47 PM PDT 24
Finished Jul 15 04:41:56 PM PDT 24
Peak memory 208204 kb
Host smart-72d73fe2-e136-4f90-abb7-4f01bb153950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247297718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3247297718
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2218477714
Short name T1112
Test name
Test status
Simulation time 26050385544 ps
CPU time 561.38 seconds
Started Jul 15 04:33:44 PM PDT 24
Finished Jul 15 04:43:07 PM PDT 24
Peak memory 215852 kb
Host smart-1b4a9c82-a5b5-4e26-b24b-c1ef1852d365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218477714 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2218477714
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.237873797
Short name T826
Test name
Test status
Simulation time 815973083 ps
CPU time 2.7 seconds
Started Jul 15 04:33:39 PM PDT 24
Finished Jul 15 04:33:43 PM PDT 24
Peak memory 198288 kb
Host smart-5e2c66f4-5717-422e-9eaa-7e1e50441e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237873797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.237873797
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3175571401
Short name T540
Test name
Test status
Simulation time 11431582360 ps
CPU time 16.65 seconds
Started Jul 15 04:33:36 PM PDT 24
Finished Jul 15 04:33:53 PM PDT 24
Peak memory 197652 kb
Host smart-21784417-0b2e-4363-85d2-4795f23b053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175571401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3175571401
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1669753926
Short name T342
Test name
Test status
Simulation time 15071564 ps
CPU time 0.55 seconds
Started Jul 15 04:33:47 PM PDT 24
Finished Jul 15 04:33:49 PM PDT 24
Peak memory 195144 kb
Host smart-bf2dbb4a-7d30-463d-9107-92667fd79069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669753926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1669753926
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2971950000
Short name T462
Test name
Test status
Simulation time 133962455815 ps
CPU time 119.78 seconds
Started Jul 15 04:33:42 PM PDT 24
Finished Jul 15 04:35:42 PM PDT 24
Peak memory 199696 kb
Host smart-7d0d2c59-26af-4d45-a928-fa8f7e7159e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971950000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2971950000
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.202776589
Short name T592
Test name
Test status
Simulation time 27006413620 ps
CPU time 11.79 seconds
Started Jul 15 04:33:41 PM PDT 24
Finished Jul 15 04:33:54 PM PDT 24
Peak memory 199572 kb
Host smart-99c733a2-4316-4cab-b9b2-57277f5b5780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202776589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.202776589
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3640808239
Short name T170
Test name
Test status
Simulation time 143458710098 ps
CPU time 57.83 seconds
Started Jul 15 04:33:47 PM PDT 24
Finished Jul 15 04:34:46 PM PDT 24
Peak memory 199368 kb
Host smart-768218d2-30d2-4970-a06a-4b6f5cd4cbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640808239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3640808239
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2834567257
Short name T433
Test name
Test status
Simulation time 24576366115 ps
CPU time 15.12 seconds
Started Jul 15 04:33:45 PM PDT 24
Finished Jul 15 04:34:02 PM PDT 24
Peak memory 199728 kb
Host smart-38174f62-1c29-4ffe-b373-14c503cccc5f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834567257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2834567257
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3606981269
Short name T709
Test name
Test status
Simulation time 111446446230 ps
CPU time 238.58 seconds
Started Jul 15 04:33:43 PM PDT 24
Finished Jul 15 04:37:43 PM PDT 24
Peak memory 199748 kb
Host smart-995604b2-766e-476e-97a5-ae8025a39021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3606981269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3606981269
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1192696926
Short name T378
Test name
Test status
Simulation time 1376030629 ps
CPU time 1.14 seconds
Started Jul 15 04:33:43 PM PDT 24
Finished Jul 15 04:33:45 PM PDT 24
Peak memory 195156 kb
Host smart-eb61a4a3-46fe-4dd1-ba93-ab745cffdebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192696926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1192696926
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2376894057
Short name T548
Test name
Test status
Simulation time 123684322619 ps
CPU time 149.94 seconds
Started Jul 15 04:33:44 PM PDT 24
Finished Jul 15 04:36:15 PM PDT 24
Peak memory 199836 kb
Host smart-b3c169a7-d9d7-49e2-937d-0e3ddf447c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376894057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2376894057
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.2425609305
Short name T811
Test name
Test status
Simulation time 7082245910 ps
CPU time 188.04 seconds
Started Jul 15 04:33:47 PM PDT 24
Finished Jul 15 04:36:57 PM PDT 24
Peak memory 199720 kb
Host smart-42867372-3c3f-4b84-9446-994d3a343b3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425609305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2425609305
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1755746061
Short name T936
Test name
Test status
Simulation time 4450062063 ps
CPU time 31.9 seconds
Started Jul 15 04:33:44 PM PDT 24
Finished Jul 15 04:34:17 PM PDT 24
Peak memory 198620 kb
Host smart-e30c823d-e638-4ac5-8626-033e27888527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755746061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1755746061
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.4124480049
Short name T123
Test name
Test status
Simulation time 83746976465 ps
CPU time 33.84 seconds
Started Jul 15 04:33:42 PM PDT 24
Finished Jul 15 04:34:16 PM PDT 24
Peak memory 199700 kb
Host smart-296fe5a4-35eb-4b6a-b018-ad42ff27b72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124480049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.4124480049
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2527085685
Short name T852
Test name
Test status
Simulation time 3614541119 ps
CPU time 1.79 seconds
Started Jul 15 04:33:43 PM PDT 24
Finished Jul 15 04:33:46 PM PDT 24
Peak memory 195744 kb
Host smart-07a6f0f0-1ca6-4a5e-ad04-4000755ced9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527085685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2527085685
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3533590880
Short name T651
Test name
Test status
Simulation time 314908830 ps
CPU time 1.4 seconds
Started Jul 15 04:33:42 PM PDT 24
Finished Jul 15 04:33:44 PM PDT 24
Peak memory 199644 kb
Host smart-706c656a-da37-4d1e-b625-c77bd99e8f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533590880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3533590880
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3615812505
Short name T993
Test name
Test status
Simulation time 266967288782 ps
CPU time 144.61 seconds
Started Jul 15 04:33:45 PM PDT 24
Finished Jul 15 04:36:11 PM PDT 24
Peak memory 216040 kb
Host smart-45268e12-762d-44d8-a2a1-08e57d80bfee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615812505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3615812505
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.97031342
Short name T290
Test name
Test status
Simulation time 63155866932 ps
CPU time 309.75 seconds
Started Jul 15 04:33:44 PM PDT 24
Finished Jul 15 04:38:55 PM PDT 24
Peak memory 216172 kb
Host smart-ab3d0e0f-a2a1-449a-a581-16c39ec4b020
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97031342 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.97031342
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3934372228
Short name T559
Test name
Test status
Simulation time 1429015204 ps
CPU time 1.34 seconds
Started Jul 15 04:33:41 PM PDT 24
Finished Jul 15 04:33:43 PM PDT 24
Peak memory 197764 kb
Host smart-27a38ea0-3add-46f2-8c7d-36676a9e6783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934372228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3934372228
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1840415442
Short name T512
Test name
Test status
Simulation time 4475267533 ps
CPU time 7.01 seconds
Started Jul 15 04:33:43 PM PDT 24
Finished Jul 15 04:33:51 PM PDT 24
Peak memory 196412 kb
Host smart-ff4e816a-4d17-410e-b40c-530de412b937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840415442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1840415442
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.715460997
Short name T1060
Test name
Test status
Simulation time 36321969 ps
CPU time 0.53 seconds
Started Jul 15 04:30:46 PM PDT 24
Finished Jul 15 04:30:48 PM PDT 24
Peak memory 195168 kb
Host smart-0789c849-a8b8-4251-9581-e9bd70e6961d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715460997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.715460997
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2300287160
Short name T757
Test name
Test status
Simulation time 45924259162 ps
CPU time 37.99 seconds
Started Jul 15 04:30:30 PM PDT 24
Finished Jul 15 04:31:10 PM PDT 24
Peak memory 199648 kb
Host smart-b5dff5c2-c1a0-4b63-a676-22a3edd58420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300287160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2300287160
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.382108969
Short name T977
Test name
Test status
Simulation time 43120396361 ps
CPU time 62.81 seconds
Started Jul 15 04:30:24 PM PDT 24
Finished Jul 15 04:31:28 PM PDT 24
Peak memory 199640 kb
Host smart-28f96755-0545-4dac-90d2-3d511ff99ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382108969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.382108969
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2195546953
Short name T523
Test name
Test status
Simulation time 70471105637 ps
CPU time 31.64 seconds
Started Jul 15 04:30:36 PM PDT 24
Finished Jul 15 04:31:09 PM PDT 24
Peak memory 199720 kb
Host smart-710ad810-3b95-4a65-8d8d-996eca53505e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195546953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2195546953
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.990235682
Short name T571
Test name
Test status
Simulation time 264390946157 ps
CPU time 108.82 seconds
Started Jul 15 04:30:29 PM PDT 24
Finished Jul 15 04:32:20 PM PDT 24
Peak memory 199772 kb
Host smart-dd322197-43f3-4def-a731-c305b69d8ae3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990235682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.990235682
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2664768479
Short name T1039
Test name
Test status
Simulation time 293429616385 ps
CPU time 217.01 seconds
Started Jul 15 04:30:37 PM PDT 24
Finished Jul 15 04:34:15 PM PDT 24
Peak memory 199672 kb
Host smart-ffafcd36-eff4-4f84-8fa9-d2b3d3655b90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2664768479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2664768479
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.4013501320
Short name T334
Test name
Test status
Simulation time 4179708192 ps
CPU time 5.02 seconds
Started Jul 15 04:30:37 PM PDT 24
Finished Jul 15 04:30:44 PM PDT 24
Peak memory 199460 kb
Host smart-2e50383c-ca9d-41d8-9a7c-78ea5d682904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013501320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.4013501320
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.913822908
Short name T647
Test name
Test status
Simulation time 26990968560 ps
CPU time 47.56 seconds
Started Jul 15 04:30:37 PM PDT 24
Finished Jul 15 04:31:27 PM PDT 24
Peak memory 199960 kb
Host smart-97e3579f-d7aa-4cce-8c8a-dc7e532b3f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913822908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.913822908
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.343965246
Short name T262
Test name
Test status
Simulation time 13671351482 ps
CPU time 162.89 seconds
Started Jul 15 04:30:39 PM PDT 24
Finished Jul 15 04:33:23 PM PDT 24
Peak memory 199700 kb
Host smart-911a3485-d2b2-4fe9-ba50-e6ec1807d941
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=343965246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.343965246
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1219487539
Short name T313
Test name
Test status
Simulation time 2419325243 ps
CPU time 14.97 seconds
Started Jul 15 04:30:28 PM PDT 24
Finished Jul 15 04:30:46 PM PDT 24
Peak memory 197888 kb
Host smart-07f399af-3602-4b90-aa50-11bb1d7d15c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219487539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1219487539
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1829367026
Short name T758
Test name
Test status
Simulation time 64578718176 ps
CPU time 120.87 seconds
Started Jul 15 04:30:36 PM PDT 24
Finished Jul 15 04:32:38 PM PDT 24
Peak memory 199804 kb
Host smart-d9da3076-b9a1-471c-b8ae-23b0c9a1686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829367026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1829367026
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3521485729
Short name T347
Test name
Test status
Simulation time 42402976338 ps
CPU time 54.61 seconds
Started Jul 15 04:30:36 PM PDT 24
Finished Jul 15 04:31:32 PM PDT 24
Peak memory 195528 kb
Host smart-67af52be-e6eb-4044-bee3-8ab80b547992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521485729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3521485729
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2724518631
Short name T552
Test name
Test status
Simulation time 552051246 ps
CPU time 1.64 seconds
Started Jul 15 04:30:35 PM PDT 24
Finished Jul 15 04:30:38 PM PDT 24
Peak memory 197944 kb
Host smart-a2ae37f8-ee26-4180-a99b-07588768d606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724518631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2724518631
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3368771681
Short name T415
Test name
Test status
Simulation time 358891472061 ps
CPU time 433.76 seconds
Started Jul 15 04:30:30 PM PDT 24
Finished Jul 15 04:37:46 PM PDT 24
Peak memory 199584 kb
Host smart-38cfa5e7-9b93-4f2b-a545-a47e0299415d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368771681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3368771681
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3671754880
Short name T49
Test name
Test status
Simulation time 382240285267 ps
CPU time 1143.23 seconds
Started Jul 15 04:30:42 PM PDT 24
Finished Jul 15 04:49:47 PM PDT 24
Peak memory 224744 kb
Host smart-ac10c96a-874e-4b7e-bbbf-0425e44efa1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671754880 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3671754880
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1899203974
Short name T1009
Test name
Test status
Simulation time 1300258421 ps
CPU time 2.09 seconds
Started Jul 15 04:30:40 PM PDT 24
Finished Jul 15 04:30:44 PM PDT 24
Peak memory 198672 kb
Host smart-57f4ea6e-e6dc-4bf4-8c42-8083330aa02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899203974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1899203974
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.23623451
Short name T500
Test name
Test status
Simulation time 93338330366 ps
CPU time 36.03 seconds
Started Jul 15 04:33:44 PM PDT 24
Finished Jul 15 04:34:21 PM PDT 24
Peak memory 199760 kb
Host smart-34eb2c11-a38b-47e5-95c8-b28fe920ac3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23623451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.23623451
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1304006567
Short name T423
Test name
Test status
Simulation time 175401362306 ps
CPU time 1715.94 seconds
Started Jul 15 04:33:47 PM PDT 24
Finished Jul 15 05:02:23 PM PDT 24
Peak memory 229568 kb
Host smart-3e5f63f6-cc82-41e5-800d-1fc9afaaf0f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304006567 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1304006567
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.645541393
Short name T47
Test name
Test status
Simulation time 155384022184 ps
CPU time 887.96 seconds
Started Jul 15 04:33:45 PM PDT 24
Finished Jul 15 04:48:35 PM PDT 24
Peak memory 226684 kb
Host smart-e9fbffb3-37d5-4bc8-bd3f-2214e0ad3b0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645541393 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.645541393
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2177608558
Short name T1026
Test name
Test status
Simulation time 42274516146 ps
CPU time 17 seconds
Started Jul 15 04:33:45 PM PDT 24
Finished Jul 15 04:34:03 PM PDT 24
Peak memory 199584 kb
Host smart-5cb29999-6c25-4555-a9d1-81c30cce5182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177608558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2177608558
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.658373467
Short name T1129
Test name
Test status
Simulation time 66314290275 ps
CPU time 438.07 seconds
Started Jul 15 04:33:47 PM PDT 24
Finished Jul 15 04:41:06 PM PDT 24
Peak memory 215496 kb
Host smart-26433aa7-3793-499d-8d86-49ec8a6bad9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658373467 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.658373467
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.457143022
Short name T135
Test name
Test status
Simulation time 11641295297 ps
CPU time 18.26 seconds
Started Jul 15 04:33:47 PM PDT 24
Finished Jul 15 04:34:07 PM PDT 24
Peak memory 199772 kb
Host smart-854dafc1-3ca2-4531-8523-2bf28b41b744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457143022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.457143022
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1524145481
Short name T105
Test name
Test status
Simulation time 20667477913 ps
CPU time 171.83 seconds
Started Jul 15 04:33:44 PM PDT 24
Finished Jul 15 04:36:38 PM PDT 24
Peak memory 216416 kb
Host smart-a4aaafb8-6887-4a19-9444-65b387d1f1a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524145481 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1524145481
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.676032420
Short name T224
Test name
Test status
Simulation time 50272451488 ps
CPU time 72.24 seconds
Started Jul 15 04:33:44 PM PDT 24
Finished Jul 15 04:34:57 PM PDT 24
Peak memory 199760 kb
Host smart-e9c0bfb3-4380-4d41-aaa9-3e868dc21c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676032420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.676032420
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.573289865
Short name T497
Test name
Test status
Simulation time 35736822903 ps
CPU time 594.03 seconds
Started Jul 15 04:33:45 PM PDT 24
Finished Jul 15 04:43:41 PM PDT 24
Peak memory 216484 kb
Host smart-bcbc989b-43f9-4bfa-bfe8-0b91eea260ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573289865 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.573289865
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1093353587
Short name T121
Test name
Test status
Simulation time 91287470286 ps
CPU time 135.83 seconds
Started Jul 15 04:33:44 PM PDT 24
Finished Jul 15 04:36:01 PM PDT 24
Peak memory 199724 kb
Host smart-30ae2928-6278-4060-92f8-7d63e315625b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093353587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1093353587
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.967802337
Short name T627
Test name
Test status
Simulation time 15231129699 ps
CPU time 194.99 seconds
Started Jul 15 04:33:45 PM PDT 24
Finished Jul 15 04:37:01 PM PDT 24
Peak memory 216236 kb
Host smart-9eae37b5-d964-4de5-bc4d-175d78411d37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967802337 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.967802337
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2724974742
Short name T142
Test name
Test status
Simulation time 141769125841 ps
CPU time 57.45 seconds
Started Jul 15 04:33:52 PM PDT 24
Finished Jul 15 04:34:50 PM PDT 24
Peak memory 199700 kb
Host smart-c4d4eae1-03d3-4e4a-a250-1286d05d71c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724974742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2724974742
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.143213926
Short name T961
Test name
Test status
Simulation time 180214798098 ps
CPU time 1237.48 seconds
Started Jul 15 04:33:50 PM PDT 24
Finished Jul 15 04:54:28 PM PDT 24
Peak memory 215968 kb
Host smart-49b8897d-4f2d-4072-9897-256f13750c02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143213926 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.143213926
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1735565863
Short name T879
Test name
Test status
Simulation time 192186105920 ps
CPU time 16.05 seconds
Started Jul 15 04:33:52 PM PDT 24
Finished Jul 15 04:34:09 PM PDT 24
Peak memory 199676 kb
Host smart-dc9ca367-1da5-48ef-a020-e6df60cc0e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735565863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1735565863
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3618922516
Short name T281
Test name
Test status
Simulation time 14105455713 ps
CPU time 466.39 seconds
Started Jul 15 04:33:49 PM PDT 24
Finished Jul 15 04:41:36 PM PDT 24
Peak memory 215480 kb
Host smart-70ae36a8-ea26-4db8-a034-96d689223305
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618922516 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3618922516
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1698073026
Short name T825
Test name
Test status
Simulation time 14117900173 ps
CPU time 18.57 seconds
Started Jul 15 04:33:50 PM PDT 24
Finished Jul 15 04:34:09 PM PDT 24
Peak memory 199756 kb
Host smart-afce7620-dd5c-4573-a31c-5f821dd7e5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698073026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1698073026
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.577979661
Short name T90
Test name
Test status
Simulation time 121103345258 ps
CPU time 208.04 seconds
Started Jul 15 04:33:54 PM PDT 24
Finished Jul 15 04:37:23 PM PDT 24
Peak memory 199796 kb
Host smart-8edb0ecc-1e88-48b3-8d0d-dcfa0c32e99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577979661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.577979661
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2143070308
Short name T14
Test name
Test status
Simulation time 36224371143 ps
CPU time 363.11 seconds
Started Jul 15 04:33:50 PM PDT 24
Finished Jul 15 04:39:53 PM PDT 24
Peak memory 215656 kb
Host smart-448751e7-24b2-4b6a-acc2-cce024e6bd3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143070308 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2143070308
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2228350477
Short name T976
Test name
Test status
Simulation time 15266762 ps
CPU time 0.6 seconds
Started Jul 15 04:30:38 PM PDT 24
Finished Jul 15 04:30:40 PM PDT 24
Peak memory 195164 kb
Host smart-51fae247-4648-4521-b5e9-6155bbed707a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228350477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2228350477
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1796160299
Short name T133
Test name
Test status
Simulation time 126945637801 ps
CPU time 46.37 seconds
Started Jul 15 04:30:39 PM PDT 24
Finished Jul 15 04:31:27 PM PDT 24
Peak memory 199792 kb
Host smart-ecd05da7-6547-4c43-afc4-71f5190a07e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796160299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1796160299
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1512312415
Short name T447
Test name
Test status
Simulation time 24887737877 ps
CPU time 33.99 seconds
Started Jul 15 04:30:32 PM PDT 24
Finished Jul 15 04:31:08 PM PDT 24
Peak memory 199476 kb
Host smart-8a47ab05-1100-41c3-8240-d2fea1bfe3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512312415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1512312415
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1960995439
Short name T909
Test name
Test status
Simulation time 15436378315 ps
CPU time 24.64 seconds
Started Jul 15 04:30:29 PM PDT 24
Finished Jul 15 04:30:56 PM PDT 24
Peak memory 199728 kb
Host smart-e29ffddf-1b88-48d3-8d1b-df5335314695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960995439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1960995439
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2559328853
Short name T553
Test name
Test status
Simulation time 30223726133 ps
CPU time 16.21 seconds
Started Jul 15 04:30:41 PM PDT 24
Finished Jul 15 04:30:59 PM PDT 24
Peak memory 199588 kb
Host smart-5df5227e-8189-4fba-976e-65d6bf21ef23
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559328853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2559328853
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1837802230
Short name T229
Test name
Test status
Simulation time 113198939515 ps
CPU time 428.82 seconds
Started Jul 15 04:30:36 PM PDT 24
Finished Jul 15 04:37:47 PM PDT 24
Peak memory 199644 kb
Host smart-64f3f4cf-5be9-4b91-bc33-91d3f746cbb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1837802230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1837802230
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1481154262
Short name T908
Test name
Test status
Simulation time 2511082095 ps
CPU time 3.19 seconds
Started Jul 15 04:30:38 PM PDT 24
Finished Jul 15 04:30:43 PM PDT 24
Peak memory 198812 kb
Host smart-6ce7b731-cd87-4d7d-b98a-d71d0ef155e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481154262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1481154262
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3368355823
Short name T106
Test name
Test status
Simulation time 60740778258 ps
CPU time 97.86 seconds
Started Jul 15 04:30:43 PM PDT 24
Finished Jul 15 04:32:22 PM PDT 24
Peak memory 200016 kb
Host smart-5f7103cd-e5a5-4f9e-af81-e7a02a1b691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368355823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3368355823
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2412063936
Short name T1034
Test name
Test status
Simulation time 17926080220 ps
CPU time 250.78 seconds
Started Jul 15 04:30:47 PM PDT 24
Finished Jul 15 04:34:59 PM PDT 24
Peak memory 199748 kb
Host smart-3e4b3c9e-f6e1-4e07-8ab9-b338370453fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412063936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2412063936
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3787548733
Short name T1088
Test name
Test status
Simulation time 2418291968 ps
CPU time 18.12 seconds
Started Jul 15 04:30:38 PM PDT 24
Finished Jul 15 04:30:58 PM PDT 24
Peak memory 198012 kb
Host smart-77939929-43f6-406f-a949-d1f411ff4e06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787548733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3787548733
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3027231190
Short name T632
Test name
Test status
Simulation time 265656167750 ps
CPU time 361.31 seconds
Started Jul 15 04:30:47 PM PDT 24
Finished Jul 15 04:36:50 PM PDT 24
Peak memory 199688 kb
Host smart-944e7951-e600-4e34-95e2-08c77d2efa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027231190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3027231190
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3131461416
Short name T616
Test name
Test status
Simulation time 2980568920 ps
CPU time 5.59 seconds
Started Jul 15 04:30:38 PM PDT 24
Finished Jul 15 04:30:45 PM PDT 24
Peak memory 195692 kb
Host smart-bbfba553-8808-49f7-9677-c66f20457c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131461416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3131461416
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.612269124
Short name T819
Test name
Test status
Simulation time 5758686921 ps
CPU time 12.93 seconds
Started Jul 15 04:30:36 PM PDT 24
Finished Jul 15 04:30:50 PM PDT 24
Peak memory 199180 kb
Host smart-f06618ce-2e67-4393-a727-e95ec8c4b553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612269124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.612269124
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2172890623
Short name T619
Test name
Test status
Simulation time 363182343170 ps
CPU time 336.18 seconds
Started Jul 15 04:30:41 PM PDT 24
Finished Jul 15 04:36:19 PM PDT 24
Peak memory 199684 kb
Host smart-a8e97c2f-4836-4ed2-8bb8-11926e8f64c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172890623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2172890623
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1335537402
Short name T284
Test name
Test status
Simulation time 7972208962 ps
CPU time 11.19 seconds
Started Jul 15 04:30:40 PM PDT 24
Finished Jul 15 04:30:53 PM PDT 24
Peak memory 199116 kb
Host smart-66a5f25c-93a6-43a9-9f38-44c3d2eed18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335537402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1335537402
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1546381806
Short name T695
Test name
Test status
Simulation time 21762192783 ps
CPU time 33.45 seconds
Started Jul 15 04:30:40 PM PDT 24
Finished Jul 15 04:31:15 PM PDT 24
Peak memory 196896 kb
Host smart-7fc1c5ce-f23e-44b5-a930-e0992ed40f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546381806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1546381806
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1338214801
Short name T1096
Test name
Test status
Simulation time 178404361671 ps
CPU time 535.82 seconds
Started Jul 15 04:33:53 PM PDT 24
Finished Jul 15 04:42:50 PM PDT 24
Peak memory 228044 kb
Host smart-4008b8bc-52c2-4b89-8b29-95d7080f20c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338214801 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1338214801
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.4157564446
Short name T1119
Test name
Test status
Simulation time 20749737785 ps
CPU time 35.04 seconds
Started Jul 15 04:33:50 PM PDT 24
Finished Jul 15 04:34:25 PM PDT 24
Peak memory 199672 kb
Host smart-2d62fb0b-74c9-4099-a620-74ad7f07d007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157564446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4157564446
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1086486110
Short name T461
Test name
Test status
Simulation time 96265222175 ps
CPU time 936.57 seconds
Started Jul 15 04:33:52 PM PDT 24
Finished Jul 15 04:49:29 PM PDT 24
Peak memory 216432 kb
Host smart-d85b2593-4425-4693-b507-455f4ab36087
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086486110 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1086486110
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2509505873
Short name T645
Test name
Test status
Simulation time 96266324010 ps
CPU time 115.8 seconds
Started Jul 15 04:33:53 PM PDT 24
Finished Jul 15 04:35:50 PM PDT 24
Peak memory 199796 kb
Host smart-eb5f2205-0f36-48e4-a923-91f56ab7de23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509505873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2509505873
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3966387574
Short name T728
Test name
Test status
Simulation time 288402818671 ps
CPU time 269.19 seconds
Started Jul 15 04:33:51 PM PDT 24
Finished Jul 15 04:38:21 PM PDT 24
Peak memory 215384 kb
Host smart-da8e560e-6a8f-4012-aea4-31ab9ad39a2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966387574 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3966387574
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3234166707
Short name T777
Test name
Test status
Simulation time 50633924634 ps
CPU time 20.28 seconds
Started Jul 15 04:33:52 PM PDT 24
Finished Jul 15 04:34:13 PM PDT 24
Peak memory 199740 kb
Host smart-fadfdfc1-8798-447b-9f94-72d88dbe4ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234166707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3234166707
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1803638700
Short name T1054
Test name
Test status
Simulation time 397927403182 ps
CPU time 526.79 seconds
Started Jul 15 04:33:53 PM PDT 24
Finished Jul 15 04:42:40 PM PDT 24
Peak memory 216212 kb
Host smart-f9477e33-2291-4b37-8530-1afd950dddac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803638700 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1803638700
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.463484185
Short name T729
Test name
Test status
Simulation time 101520830768 ps
CPU time 71.24 seconds
Started Jul 15 04:33:51 PM PDT 24
Finished Jul 15 04:35:03 PM PDT 24
Peak memory 199716 kb
Host smart-5993e6a9-9ebf-4cc4-b713-5038ee82bc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463484185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.463484185
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.209044920
Short name T834
Test name
Test status
Simulation time 76944569340 ps
CPU time 547.85 seconds
Started Jul 15 04:33:50 PM PDT 24
Finished Jul 15 04:42:59 PM PDT 24
Peak memory 216224 kb
Host smart-c1edcc6e-0861-4c18-92db-22e3a860b276
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209044920 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.209044920
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.278546007
Short name T751
Test name
Test status
Simulation time 71020058670 ps
CPU time 1172.21 seconds
Started Jul 15 04:33:58 PM PDT 24
Finished Jul 15 04:53:31 PM PDT 24
Peak memory 224660 kb
Host smart-cea6ec35-df79-42a6-9eec-3b475b75f504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278546007 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.278546007
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.774533261
Short name T712
Test name
Test status
Simulation time 26340900859 ps
CPU time 44.15 seconds
Started Jul 15 04:33:57 PM PDT 24
Finished Jul 15 04:34:42 PM PDT 24
Peak memory 199856 kb
Host smart-bd98a4ba-33c6-4ccf-9c42-694247fe2add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774533261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.774533261
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.720547664
Short name T28
Test name
Test status
Simulation time 13469039487 ps
CPU time 107.08 seconds
Started Jul 15 04:34:00 PM PDT 24
Finished Jul 15 04:35:49 PM PDT 24
Peak memory 208340 kb
Host smart-40599127-2b23-4a5d-8e9e-7d0fab9c2bf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720547664 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.720547664
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3452347510
Short name T911
Test name
Test status
Simulation time 55561936809 ps
CPU time 38.68 seconds
Started Jul 15 04:33:56 PM PDT 24
Finished Jul 15 04:34:35 PM PDT 24
Peak memory 199408 kb
Host smart-4045fb2a-0055-4d8f-ba40-8c23c296ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452347510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3452347510
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1874890834
Short name T637
Test name
Test status
Simulation time 71101803413 ps
CPU time 423.07 seconds
Started Jul 15 04:34:01 PM PDT 24
Finished Jul 15 04:41:05 PM PDT 24
Peak memory 216504 kb
Host smart-228c4e17-f13a-450a-974d-8236c2eaf150
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874890834 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1874890834
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3478990989
Short name T421
Test name
Test status
Simulation time 22855680 ps
CPU time 0.58 seconds
Started Jul 15 04:30:37 PM PDT 24
Finished Jul 15 04:30:39 PM PDT 24
Peak memory 195060 kb
Host smart-505bfe94-7f2f-46fb-a014-0175d714d356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478990989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3478990989
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3047466472
Short name T765
Test name
Test status
Simulation time 72077511732 ps
CPU time 28.41 seconds
Started Jul 15 04:30:41 PM PDT 24
Finished Jul 15 04:31:11 PM PDT 24
Peak memory 199716 kb
Host smart-682fa636-8407-4535-87a2-a0669fc8ddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047466472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3047466472
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2250825853
Short name T1149
Test name
Test status
Simulation time 125454768659 ps
CPU time 61.01 seconds
Started Jul 15 04:30:41 PM PDT 24
Finished Jul 15 04:31:43 PM PDT 24
Peak memory 199704 kb
Host smart-c51e9c71-0437-4112-9bbd-8051da6d95ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250825853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2250825853
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1089039197
Short name T174
Test name
Test status
Simulation time 276575361449 ps
CPU time 56.2 seconds
Started Jul 15 04:30:42 PM PDT 24
Finished Jul 15 04:31:39 PM PDT 24
Peak memory 199880 kb
Host smart-ced7aa62-99dd-41d4-96e4-4d84c29cdcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089039197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1089039197
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2858520953
Short name T1110
Test name
Test status
Simulation time 55174394353 ps
CPU time 101.8 seconds
Started Jul 15 04:30:46 PM PDT 24
Finished Jul 15 04:32:29 PM PDT 24
Peak memory 199732 kb
Host smart-4b6acf38-653e-45f7-b4be-db98a9d4335a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858520953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2858520953
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1569013269
Short name T464
Test name
Test status
Simulation time 92674501546 ps
CPU time 723.75 seconds
Started Jul 15 04:30:37 PM PDT 24
Finished Jul 15 04:42:43 PM PDT 24
Peak memory 199640 kb
Host smart-f2ca59f7-b3ec-4be0-9d82-df17bceb40a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1569013269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1569013269
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1477791305
Short name T384
Test name
Test status
Simulation time 4196954825 ps
CPU time 11.35 seconds
Started Jul 15 04:30:47 PM PDT 24
Finished Jul 15 04:30:59 PM PDT 24
Peak memory 199696 kb
Host smart-f7c49666-ac17-434e-9cff-8fb15a8b1ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477791305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1477791305
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2169718836
Short name T538
Test name
Test status
Simulation time 146008254394 ps
CPU time 187.57 seconds
Started Jul 15 04:30:39 PM PDT 24
Finished Jul 15 04:33:48 PM PDT 24
Peak memory 200052 kb
Host smart-426112bc-a7de-4174-8522-b7bda536fb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169718836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2169718836
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.327662200
Short name T232
Test name
Test status
Simulation time 22914429727 ps
CPU time 852.51 seconds
Started Jul 15 04:30:37 PM PDT 24
Finished Jul 15 04:44:52 PM PDT 24
Peak memory 199688 kb
Host smart-73f19f32-92d2-4dd0-9683-ca3170857d4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=327662200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.327662200
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3737471811
Short name T1133
Test name
Test status
Simulation time 4424370608 ps
CPU time 34.13 seconds
Started Jul 15 04:30:38 PM PDT 24
Finished Jul 15 04:31:13 PM PDT 24
Peak memory 197960 kb
Host smart-74292df8-854b-4d74-ac7a-f3142313ae0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737471811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3737471811
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1652070359
Short name T555
Test name
Test status
Simulation time 43275369650 ps
CPU time 10.87 seconds
Started Jul 15 04:30:47 PM PDT 24
Finished Jul 15 04:30:59 PM PDT 24
Peak memory 199000 kb
Host smart-657e75ce-8a34-4b51-8cbb-f8024b775e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652070359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1652070359
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.831424303
Short name T463
Test name
Test status
Simulation time 45132795137 ps
CPU time 11.39 seconds
Started Jul 15 04:30:42 PM PDT 24
Finished Jul 15 04:30:54 PM PDT 24
Peak memory 195624 kb
Host smart-21a56a07-2259-472a-953f-fcff2f03d846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831424303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.831424303
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.134866610
Short name T250
Test name
Test status
Simulation time 489929867 ps
CPU time 2.06 seconds
Started Jul 15 04:30:37 PM PDT 24
Finished Jul 15 04:30:41 PM PDT 24
Peak memory 198168 kb
Host smart-c939fe68-1fac-47b9-8f22-bc46f896817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134866610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.134866610
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1114501852
Short name T921
Test name
Test status
Simulation time 324608719722 ps
CPU time 259.88 seconds
Started Jul 15 04:30:38 PM PDT 24
Finished Jul 15 04:35:00 PM PDT 24
Peak memory 216300 kb
Host smart-83ae3e6e-c7a3-4143-95ec-f97801f02bb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114501852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1114501852
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.716913291
Short name T688
Test name
Test status
Simulation time 15125380264 ps
CPU time 158.64 seconds
Started Jul 15 04:30:36 PM PDT 24
Finished Jul 15 04:33:16 PM PDT 24
Peak memory 215612 kb
Host smart-7709273d-17da-4b71-a8c0-cd53b7915de7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716913291 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.716913291
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2389782506
Short name T382
Test name
Test status
Simulation time 672094183 ps
CPU time 1.85 seconds
Started Jul 15 04:30:40 PM PDT 24
Finished Jul 15 04:30:43 PM PDT 24
Peak memory 198108 kb
Host smart-c0f220a2-d6b8-44e2-8124-922f5c00a0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389782506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2389782506
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3023438635
Short name T302
Test name
Test status
Simulation time 101488818234 ps
CPU time 9.44 seconds
Started Jul 15 04:30:46 PM PDT 24
Finished Jul 15 04:30:57 PM PDT 24
Peak memory 199428 kb
Host smart-5639de23-e6f9-4755-aec6-3100b543e789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023438635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3023438635
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1661830029
Short name T413
Test name
Test status
Simulation time 51595132510 ps
CPU time 17.5 seconds
Started Jul 15 04:34:00 PM PDT 24
Finished Jul 15 04:34:19 PM PDT 24
Peak memory 199776 kb
Host smart-7b0f01fc-6364-4c40-bb0f-5b29fd706dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661830029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1661830029
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3086571707
Short name T122
Test name
Test status
Simulation time 158477006668 ps
CPU time 542.34 seconds
Started Jul 15 04:33:58 PM PDT 24
Finished Jul 15 04:43:01 PM PDT 24
Peak memory 228468 kb
Host smart-6bf50197-662f-45a6-99ab-2a24a470c226
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086571707 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3086571707
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.979572755
Short name T124
Test name
Test status
Simulation time 86545245208 ps
CPU time 129.49 seconds
Started Jul 15 04:34:03 PM PDT 24
Finished Jul 15 04:36:13 PM PDT 24
Peak memory 199752 kb
Host smart-2b3263b1-ebcd-4e43-8253-7f21b10d62b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979572755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.979572755
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3762599549
Short name T1143
Test name
Test status
Simulation time 176088184018 ps
CPU time 626.43 seconds
Started Jul 15 04:34:01 PM PDT 24
Finished Jul 15 04:44:28 PM PDT 24
Peak memory 225908 kb
Host smart-63c7aaae-5488-4b7e-a960-745abf3388a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762599549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3762599549
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3015114740
Short name T541
Test name
Test status
Simulation time 29463285416 ps
CPU time 22.87 seconds
Started Jul 15 04:33:57 PM PDT 24
Finished Jul 15 04:34:20 PM PDT 24
Peak memory 199704 kb
Host smart-a391f75a-1e0f-48f5-923e-ad2cbee4c8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015114740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3015114740
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3979221944
Short name T1160
Test name
Test status
Simulation time 47901330352 ps
CPU time 694.74 seconds
Started Jul 15 04:33:57 PM PDT 24
Finished Jul 15 04:45:32 PM PDT 24
Peak memory 216292 kb
Host smart-752ac0b2-5f03-4df1-82d6-6d0431162170
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979221944 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3979221944
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.463417164
Short name T1080
Test name
Test status
Simulation time 25037968401 ps
CPU time 20.99 seconds
Started Jul 15 04:33:57 PM PDT 24
Finished Jul 15 04:34:18 PM PDT 24
Peak memory 199856 kb
Host smart-5a9b269a-5e51-40bc-ab51-5a2f3a0b1563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463417164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.463417164
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1295492771
Short name T54
Test name
Test status
Simulation time 146475888294 ps
CPU time 441.49 seconds
Started Jul 15 04:33:58 PM PDT 24
Finished Jul 15 04:41:21 PM PDT 24
Peak memory 216252 kb
Host smart-a0df855e-c080-4d4f-a00a-bc4659f46537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295492771 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1295492771
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.832921250
Short name T774
Test name
Test status
Simulation time 32035344772 ps
CPU time 11.35 seconds
Started Jul 15 04:33:59 PM PDT 24
Finished Jul 15 04:34:12 PM PDT 24
Peak memory 199716 kb
Host smart-e10e72d9-2ef9-43f6-aa8e-9bf455c8eb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832921250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.832921250
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1200120248
Short name T582
Test name
Test status
Simulation time 64531238507 ps
CPU time 772.52 seconds
Started Jul 15 04:33:59 PM PDT 24
Finished Jul 15 04:46:53 PM PDT 24
Peak memory 216300 kb
Host smart-1061c40a-2c7b-47bf-b5b6-122632a916bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200120248 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1200120248
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3867478875
Short name T662
Test name
Test status
Simulation time 101659128169 ps
CPU time 1092.34 seconds
Started Jul 15 04:33:57 PM PDT 24
Finished Jul 15 04:52:10 PM PDT 24
Peak memory 230216 kb
Host smart-b8359510-8937-4646-b2eb-6b4733e19ffd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867478875 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3867478875
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2406005504
Short name T222
Test name
Test status
Simulation time 52296489091 ps
CPU time 22.92 seconds
Started Jul 15 04:34:02 PM PDT 24
Finished Jul 15 04:34:27 PM PDT 24
Peak memory 199748 kb
Host smart-3ab2894b-7b5e-4ad3-a21b-489c67fc1ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406005504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2406005504
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3170330823
Short name T206
Test name
Test status
Simulation time 48302452803 ps
CPU time 40.29 seconds
Started Jul 15 04:34:02 PM PDT 24
Finished Jul 15 04:34:44 PM PDT 24
Peak memory 199772 kb
Host smart-19f7dfc7-0e8c-4576-9d12-e0ad7c46e01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170330823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3170330823
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2327907642
Short name T923
Test name
Test status
Simulation time 356001619778 ps
CPU time 319.52 seconds
Started Jul 15 04:34:02 PM PDT 24
Finished Jul 15 04:39:22 PM PDT 24
Peak memory 216240 kb
Host smart-930947ff-7b99-4851-aac5-93e0358c67de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327907642 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2327907642
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.231185893
Short name T670
Test name
Test status
Simulation time 10065327681 ps
CPU time 17.36 seconds
Started Jul 15 04:33:58 PM PDT 24
Finished Jul 15 04:34:17 PM PDT 24
Peak memory 199672 kb
Host smart-2a019cdd-dd3e-4ea4-86da-4cc6fb6803b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231185893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.231185893
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3318089870
Short name T55
Test name
Test status
Simulation time 84485155935 ps
CPU time 451.29 seconds
Started Jul 15 04:33:58 PM PDT 24
Finished Jul 15 04:41:30 PM PDT 24
Peak memory 216464 kb
Host smart-bb01330e-c18e-4418-a4f1-448a962a4741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318089870 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3318089870
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2077874483
Short name T274
Test name
Test status
Simulation time 71795187673 ps
CPU time 17.51 seconds
Started Jul 15 04:33:58 PM PDT 24
Finished Jul 15 04:34:16 PM PDT 24
Peak memory 199504 kb
Host smart-a0f69ec2-5326-4f7d-9751-312f8bf1898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077874483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2077874483
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1845561923
Short name T561
Test name
Test status
Simulation time 27234328306 ps
CPU time 148.47 seconds
Started Jul 15 04:34:09 PM PDT 24
Finished Jul 15 04:36:40 PM PDT 24
Peak memory 216428 kb
Host smart-79bfbab5-d72d-4391-8c00-6adfdebab0df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845561923 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1845561923
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1865027943
Short name T21
Test name
Test status
Simulation time 15543447 ps
CPU time 0.53 seconds
Started Jul 15 04:30:49 PM PDT 24
Finished Jul 15 04:30:50 PM PDT 24
Peak memory 195352 kb
Host smart-c782c89a-e19c-4ae8-84a7-e4b874c2e4ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865027943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1865027943
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.863073155
Short name T896
Test name
Test status
Simulation time 97625438787 ps
CPU time 13.14 seconds
Started Jul 15 04:30:41 PM PDT 24
Finished Jul 15 04:30:55 PM PDT 24
Peak memory 199668 kb
Host smart-92c90c96-7fb7-43c6-91a5-58079b5bd6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863073155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.863073155
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2478666639
Short name T1128
Test name
Test status
Simulation time 29188872859 ps
CPU time 25.26 seconds
Started Jul 15 04:30:46 PM PDT 24
Finished Jul 15 04:31:13 PM PDT 24
Peak memory 199760 kb
Host smart-c870aef6-a473-4d4d-8605-9c20f42d2dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478666639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2478666639
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3269162506
Short name T779
Test name
Test status
Simulation time 36392946253 ps
CPU time 17.78 seconds
Started Jul 15 04:30:44 PM PDT 24
Finished Jul 15 04:31:03 PM PDT 24
Peak memory 199692 kb
Host smart-2bb73a61-743b-4502-862d-348653400bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269162506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3269162506
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2490597616
Short name T400
Test name
Test status
Simulation time 16234998635 ps
CPU time 25.91 seconds
Started Jul 15 04:30:43 PM PDT 24
Finished Jul 15 04:31:09 PM PDT 24
Peak memory 199476 kb
Host smart-36d8bd96-fb24-4d3e-ac35-db40ffecc9e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490597616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2490597616
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1612354088
Short name T554
Test name
Test status
Simulation time 95452397950 ps
CPU time 463.22 seconds
Started Jul 15 04:30:54 PM PDT 24
Finished Jul 15 04:38:39 PM PDT 24
Peak memory 200068 kb
Host smart-8dd6043e-35c3-46e9-a52f-7b3a2e7e8fa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1612354088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1612354088
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.165561690
Short name T566
Test name
Test status
Simulation time 3894212323 ps
CPU time 1.16 seconds
Started Jul 15 04:30:44 PM PDT 24
Finished Jul 15 04:30:47 PM PDT 24
Peak memory 198180 kb
Host smart-0ab25806-6125-4928-a003-0d49dbafde45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165561690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.165561690
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2735163558
Short name T1056
Test name
Test status
Simulation time 61976907850 ps
CPU time 100.97 seconds
Started Jul 15 04:30:51 PM PDT 24
Finished Jul 15 04:32:34 PM PDT 24
Peak memory 199840 kb
Host smart-3289f8a1-f6db-4d7f-8ab1-859de2f66292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735163558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2735163558
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1798095215
Short name T351
Test name
Test status
Simulation time 17014230104 ps
CPU time 196.79 seconds
Started Jul 15 04:30:45 PM PDT 24
Finished Jul 15 04:34:03 PM PDT 24
Peak memory 199792 kb
Host smart-0b04931a-99a3-4e65-b02f-d6c61e212dfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1798095215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1798095215
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1649078187
Short name T1104
Test name
Test status
Simulation time 4529959040 ps
CPU time 34.96 seconds
Started Jul 15 04:30:46 PM PDT 24
Finished Jul 15 04:31:22 PM PDT 24
Peak memory 199016 kb
Host smart-34dbbc6c-740c-4b69-b60d-1e1e39838784
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649078187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1649078187
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2859594996
Short name T129
Test name
Test status
Simulation time 54314491132 ps
CPU time 77.14 seconds
Started Jul 15 04:30:45 PM PDT 24
Finished Jul 15 04:32:04 PM PDT 24
Peak memory 199680 kb
Host smart-2f7e24f7-163a-4ed7-8f64-97eb8536f1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859594996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2859594996
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1302155924
Short name T255
Test name
Test status
Simulation time 1491567018 ps
CPU time 1.25 seconds
Started Jul 15 04:30:45 PM PDT 24
Finished Jul 15 04:30:48 PM PDT 24
Peak memory 195244 kb
Host smart-2ecd6fd3-a914-44e3-9b10-c10c27254e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302155924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1302155924
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.25181941
Short name T34
Test name
Test status
Simulation time 5912620225 ps
CPU time 7.94 seconds
Started Jul 15 04:30:40 PM PDT 24
Finished Jul 15 04:30:49 PM PDT 24
Peak memory 199648 kb
Host smart-739c1590-a151-46a6-ae26-bd555d6ecaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25181941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.25181941
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.733420842
Short name T1036
Test name
Test status
Simulation time 52904683906 ps
CPU time 87.32 seconds
Started Jul 15 04:30:50 PM PDT 24
Finished Jul 15 04:32:19 PM PDT 24
Peak memory 199620 kb
Host smart-e07c2b7d-8b4b-46e1-a98d-9998a0d509c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733420842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.733420842
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1986840171
Short name T515
Test name
Test status
Simulation time 622075972871 ps
CPU time 758.78 seconds
Started Jul 15 04:30:48 PM PDT 24
Finished Jul 15 04:43:28 PM PDT 24
Peak memory 231000 kb
Host smart-63f4535b-18d5-4f15-8aa6-2611fe6e96c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986840171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1986840171
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3562546906
Short name T505
Test name
Test status
Simulation time 2137956495 ps
CPU time 2.18 seconds
Started Jul 15 04:30:50 PM PDT 24
Finished Jul 15 04:30:53 PM PDT 24
Peak memory 198900 kb
Host smart-e1cc9b64-3149-4cf3-999a-88796b9d5a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562546906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3562546906
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2427955793
Short name T278
Test name
Test status
Simulation time 70464144148 ps
CPU time 18.83 seconds
Started Jul 15 04:30:49 PM PDT 24
Finished Jul 15 04:31:09 PM PDT 24
Peak memory 199352 kb
Host smart-af509d2a-06da-4439-8bbe-6e7617a62003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427955793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2427955793
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3423920434
Short name T1178
Test name
Test status
Simulation time 36478124411 ps
CPU time 16.23 seconds
Started Jul 15 04:34:08 PM PDT 24
Finished Jul 15 04:34:27 PM PDT 24
Peak memory 199660 kb
Host smart-64b0299a-db67-410e-9ef3-ee8d451e00a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423920434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3423920434
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1883911411
Short name T134
Test name
Test status
Simulation time 60906307455 ps
CPU time 899.76 seconds
Started Jul 15 04:34:06 PM PDT 24
Finished Jul 15 04:49:08 PM PDT 24
Peak memory 216340 kb
Host smart-460aa826-b18f-4717-ba25-7992bb1f6a74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883911411 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1883911411
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.588071377
Short name T443
Test name
Test status
Simulation time 12649471600 ps
CPU time 26.37 seconds
Started Jul 15 04:34:08 PM PDT 24
Finished Jul 15 04:34:37 PM PDT 24
Peak memory 199752 kb
Host smart-0c0fbd7d-9440-45ad-b141-1487fc5edc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588071377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.588071377
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2054610958
Short name T13
Test name
Test status
Simulation time 18125062107 ps
CPU time 149.01 seconds
Started Jul 15 04:34:05 PM PDT 24
Finished Jul 15 04:36:36 PM PDT 24
Peak memory 199960 kb
Host smart-0e8f9f77-60b2-44fc-8acb-02b5011d9c98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054610958 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2054610958
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.4276293995
Short name T656
Test name
Test status
Simulation time 64650734876 ps
CPU time 137.75 seconds
Started Jul 15 04:34:07 PM PDT 24
Finished Jul 15 04:36:28 PM PDT 24
Peak memory 199808 kb
Host smart-4036a24f-80e2-4a6b-bdae-c7ffb6fc7720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276293995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.4276293995
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1485637911
Short name T51
Test name
Test status
Simulation time 111647312218 ps
CPU time 275.43 seconds
Started Jul 15 04:34:07 PM PDT 24
Finished Jul 15 04:38:45 PM PDT 24
Peak memory 216436 kb
Host smart-4f6f9225-a79f-4fd4-b08a-0b1b24d6f7a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485637911 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1485637911
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2749985987
Short name T435
Test name
Test status
Simulation time 11347526547 ps
CPU time 21.38 seconds
Started Jul 15 04:34:05 PM PDT 24
Finished Jul 15 04:34:30 PM PDT 24
Peak memory 199756 kb
Host smart-ce580b3a-c50b-469f-aeb6-ef93649e961f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749985987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2749985987
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.69403955
Short name T671
Test name
Test status
Simulation time 67671663681 ps
CPU time 444.43 seconds
Started Jul 15 04:34:08 PM PDT 24
Finished Jul 15 04:41:35 PM PDT 24
Peak memory 216420 kb
Host smart-6996e1b5-8698-4a6f-bc0b-f459f8481ef1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69403955 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.69403955
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1016494130
Short name T1079
Test name
Test status
Simulation time 57921361918 ps
CPU time 60.68 seconds
Started Jul 15 04:34:05 PM PDT 24
Finished Jul 15 04:35:09 PM PDT 24
Peak memory 199732 kb
Host smart-61243cc3-d50e-4c28-9adc-130bcd2ab51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016494130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1016494130
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.4052951387
Short name T50
Test name
Test status
Simulation time 58076176729 ps
CPU time 273.93 seconds
Started Jul 15 04:34:06 PM PDT 24
Finished Jul 15 04:38:43 PM PDT 24
Peak memory 216408 kb
Host smart-9ada95e2-53b5-4352-95ad-78c3cda0318f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052951387 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.4052951387
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3672858776
Short name T398
Test name
Test status
Simulation time 12159115418 ps
CPU time 19.63 seconds
Started Jul 15 04:34:08 PM PDT 24
Finished Jul 15 04:34:30 PM PDT 24
Peak memory 199596 kb
Host smart-5aad4d65-a952-4a3e-a9b3-09e0c91a5727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672858776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3672858776
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2139906194
Short name T978
Test name
Test status
Simulation time 60274540101 ps
CPU time 214.2 seconds
Started Jul 15 04:34:08 PM PDT 24
Finished Jul 15 04:37:45 PM PDT 24
Peak memory 208392 kb
Host smart-a3cbe800-2657-44ca-90f5-c84f6f1a2e0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139906194 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2139906194
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.4029157944
Short name T404
Test name
Test status
Simulation time 30355276231 ps
CPU time 24 seconds
Started Jul 15 04:34:05 PM PDT 24
Finished Jul 15 04:34:32 PM PDT 24
Peak memory 199764 kb
Host smart-6745dca7-ff92-44e5-ae07-b4fde882691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029157944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.4029157944
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.235127060
Short name T609
Test name
Test status
Simulation time 90805011525 ps
CPU time 459.84 seconds
Started Jul 15 04:34:07 PM PDT 24
Finished Jul 15 04:41:50 PM PDT 24
Peak memory 224576 kb
Host smart-d2207812-b254-4ffc-9614-fd8f42ffd0ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235127060 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.235127060
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.472399852
Short name T1083
Test name
Test status
Simulation time 19607292154 ps
CPU time 37.29 seconds
Started Jul 15 04:34:06 PM PDT 24
Finished Jul 15 04:34:46 PM PDT 24
Peak memory 199612 kb
Host smart-9cc8d2bd-109c-492b-8cd4-acff974667e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472399852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.472399852
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3402982671
Short name T839
Test name
Test status
Simulation time 76736754711 ps
CPU time 836.26 seconds
Started Jul 15 04:34:06 PM PDT 24
Finished Jul 15 04:48:05 PM PDT 24
Peak memory 216324 kb
Host smart-72e2c79b-0e7b-43f4-875d-fd482e93732b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402982671 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3402982671
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1842138541
Short name T663
Test name
Test status
Simulation time 77481723164 ps
CPU time 26.96 seconds
Started Jul 15 04:34:05 PM PDT 24
Finished Jul 15 04:34:35 PM PDT 24
Peak memory 199848 kb
Host smart-e07de2cd-31dd-4e15-8979-b26ae245e562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842138541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1842138541
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2180959497
Short name T1074
Test name
Test status
Simulation time 39976785547 ps
CPU time 384.99 seconds
Started Jul 15 04:34:06 PM PDT 24
Finished Jul 15 04:40:34 PM PDT 24
Peak memory 215824 kb
Host smart-08d0d687-5597-4fe0-a0d1-4673d040803e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180959497 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2180959497
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.144583901
Short name T147
Test name
Test status
Simulation time 77177036586 ps
CPU time 61 seconds
Started Jul 15 04:34:05 PM PDT 24
Finished Jul 15 04:35:09 PM PDT 24
Peak memory 199796 kb
Host smart-7f91c268-a9d6-40ae-bac1-c9d7706a4100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144583901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.144583901
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3911735038
Short name T17
Test name
Test status
Simulation time 41797085552 ps
CPU time 448.46 seconds
Started Jul 15 04:34:08 PM PDT 24
Finished Jul 15 04:41:39 PM PDT 24
Peak memory 216468 kb
Host smart-c66688cf-0f91-4d2c-b6ad-3d86510712a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911735038 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3911735038
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3280762379
Short name T518
Test name
Test status
Simulation time 18355431 ps
CPU time 0.52 seconds
Started Jul 15 04:30:50 PM PDT 24
Finished Jul 15 04:30:51 PM PDT 24
Peak memory 194668 kb
Host smart-2bc16724-cc6e-458b-b59a-75fd859b54fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280762379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3280762379
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3552629814
Short name T131
Test name
Test status
Simulation time 17643953192 ps
CPU time 15.59 seconds
Started Jul 15 04:30:45 PM PDT 24
Finished Jul 15 04:31:02 PM PDT 24
Peak memory 199612 kb
Host smart-4fec3ad3-2ab8-4edb-ab5e-ca61d164db96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552629814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3552629814
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2707419292
Short name T1001
Test name
Test status
Simulation time 196865843318 ps
CPU time 160.41 seconds
Started Jul 15 04:30:50 PM PDT 24
Finished Jul 15 04:33:31 PM PDT 24
Peak memory 199696 kb
Host smart-ccb83432-4e53-4ac5-9dd4-128fd42ef465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707419292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2707419292
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_intr.428777179
Short name T1085
Test name
Test status
Simulation time 10520655076 ps
CPU time 16.44 seconds
Started Jul 15 04:30:49 PM PDT 24
Finished Jul 15 04:31:06 PM PDT 24
Peak memory 196596 kb
Host smart-f339ccfe-1c28-4c48-a8f7-fa478298dbdb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428777179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.428777179
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.373617949
Short name T681
Test name
Test status
Simulation time 91124999075 ps
CPU time 209.77 seconds
Started Jul 15 04:30:44 PM PDT 24
Finished Jul 15 04:34:15 PM PDT 24
Peak memory 199688 kb
Host smart-51504895-6b73-4a87-9862-b9adb99c3955
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373617949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.373617949
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1689870306
Short name T614
Test name
Test status
Simulation time 2869020948 ps
CPU time 2.77 seconds
Started Jul 15 04:30:48 PM PDT 24
Finished Jul 15 04:30:52 PM PDT 24
Peak memory 195988 kb
Host smart-83dee84a-c989-42e9-a5da-28ec7719696b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689870306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1689870306
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.24083452
Short name T304
Test name
Test status
Simulation time 28039776450 ps
CPU time 43.66 seconds
Started Jul 15 04:30:44 PM PDT 24
Finished Jul 15 04:31:29 PM PDT 24
Peak memory 199948 kb
Host smart-d369adcc-511a-44d5-aa5f-eebcfd37fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24083452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.24083452
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.196484530
Short name T231
Test name
Test status
Simulation time 7455276492 ps
CPU time 353.95 seconds
Started Jul 15 04:30:48 PM PDT 24
Finished Jul 15 04:36:43 PM PDT 24
Peak memory 199628 kb
Host smart-bcc9eac8-b276-423b-a582-d3b264204309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=196484530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.196484530
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1606608863
Short name T444
Test name
Test status
Simulation time 6379542356 ps
CPU time 7.33 seconds
Started Jul 15 04:30:50 PM PDT 24
Finished Jul 15 04:30:59 PM PDT 24
Peak memory 198724 kb
Host smart-01d761ac-102e-4c73-8a32-8d55d20ec602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606608863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1606608863
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1254137488
Short name T602
Test name
Test status
Simulation time 89929448534 ps
CPU time 156.8 seconds
Started Jul 15 04:30:45 PM PDT 24
Finished Jul 15 04:33:23 PM PDT 24
Peak memory 199744 kb
Host smart-67c17b93-1722-4ccf-a4e5-1d1efd39fb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254137488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1254137488
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3317980522
Short name T343
Test name
Test status
Simulation time 35123768377 ps
CPU time 53.55 seconds
Started Jul 15 04:30:49 PM PDT 24
Finished Jul 15 04:31:43 PM PDT 24
Peak memory 196108 kb
Host smart-c47714fa-bcfa-450a-b39e-864d8efb89d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317980522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3317980522
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1521125068
Short name T837
Test name
Test status
Simulation time 5543077106 ps
CPU time 14.71 seconds
Started Jul 15 04:30:49 PM PDT 24
Finished Jul 15 04:31:04 PM PDT 24
Peak memory 199568 kb
Host smart-701bb487-057c-4777-994a-63b486f9b3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521125068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1521125068
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.4065853566
Short name T843
Test name
Test status
Simulation time 58559394502 ps
CPU time 127.23 seconds
Started Jul 15 04:30:44 PM PDT 24
Finished Jul 15 04:32:52 PM PDT 24
Peak memory 199752 kb
Host smart-58da3ad1-5db7-45de-9474-f8e6faa8de6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065853566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4065853566
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.230722300
Short name T870
Test name
Test status
Simulation time 188247030286 ps
CPU time 944.45 seconds
Started Jul 15 04:30:44 PM PDT 24
Finished Jul 15 04:46:30 PM PDT 24
Peak memory 225972 kb
Host smart-fd2f9473-75a0-4a4d-b229-e15eddb59968
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230722300 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.230722300
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3853800912
Short name T846
Test name
Test status
Simulation time 1092132606 ps
CPU time 1.86 seconds
Started Jul 15 04:30:46 PM PDT 24
Finished Jul 15 04:30:49 PM PDT 24
Peak memory 198436 kb
Host smart-abdc6fee-a2ef-4cff-b95e-0b6300efc159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853800912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3853800912
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.429958896
Short name T905
Test name
Test status
Simulation time 42471959363 ps
CPU time 91.75 seconds
Started Jul 15 04:30:46 PM PDT 24
Finished Jul 15 04:32:19 PM PDT 24
Peak memory 199764 kb
Host smart-3c74e0bf-c6e7-4239-a0d4-360359a566d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429958896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.429958896
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2438013683
Short name T312
Test name
Test status
Simulation time 76474156265 ps
CPU time 56.44 seconds
Started Jul 15 04:34:05 PM PDT 24
Finished Jul 15 04:35:04 PM PDT 24
Peak memory 199724 kb
Host smart-6dec5a4f-d14b-46b7-8961-ce21eb4432ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438013683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2438013683
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3410626041
Short name T768
Test name
Test status
Simulation time 310721582969 ps
CPU time 993.73 seconds
Started Jul 15 04:34:08 PM PDT 24
Finished Jul 15 04:50:45 PM PDT 24
Peak memory 224680 kb
Host smart-09ec755b-6a08-49fb-b027-80b633360c15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410626041 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3410626041
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2394595189
Short name T198
Test name
Test status
Simulation time 187548689892 ps
CPU time 17.9 seconds
Started Jul 15 04:34:07 PM PDT 24
Finished Jul 15 04:34:28 PM PDT 24
Peak memory 199824 kb
Host smart-fa079487-e3e5-451c-bc34-1a83527d7a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394595189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2394595189
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.728263076
Short name T875
Test name
Test status
Simulation time 148417401486 ps
CPU time 654.77 seconds
Started Jul 15 04:34:05 PM PDT 24
Finished Jul 15 04:45:03 PM PDT 24
Peak memory 215108 kb
Host smart-fc763ea4-147a-4464-9c59-bd3821cae681
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728263076 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.728263076
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.246868616
Short name T1171
Test name
Test status
Simulation time 31733975631 ps
CPU time 323.49 seconds
Started Jul 15 04:34:06 PM PDT 24
Finished Jul 15 04:39:33 PM PDT 24
Peak memory 216492 kb
Host smart-bb01450b-0b7f-4ee4-a579-de9f4e336230
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246868616 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.246868616
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.46671071
Short name T145
Test name
Test status
Simulation time 32257149574 ps
CPU time 24.23 seconds
Started Jul 15 04:34:04 PM PDT 24
Finished Jul 15 04:34:30 PM PDT 24
Peak memory 199752 kb
Host smart-0959cc72-44b9-4f61-a471-a70becfaf203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46671071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.46671071
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3792657829
Short name T701
Test name
Test status
Simulation time 50110594267 ps
CPU time 33.49 seconds
Started Jul 15 04:34:03 PM PDT 24
Finished Jul 15 04:34:38 PM PDT 24
Peak memory 199640 kb
Host smart-3f99ab34-5e51-4afd-b100-9755e3aab42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792657829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3792657829
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.4079471859
Short name T745
Test name
Test status
Simulation time 92422046865 ps
CPU time 1056.65 seconds
Started Jul 15 04:34:05 PM PDT 24
Finished Jul 15 04:51:44 PM PDT 24
Peak memory 220400 kb
Host smart-d6dbb5e8-0526-499c-a128-6e9aa56d6f72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079471859 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.4079471859
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2181254521
Short name T306
Test name
Test status
Simulation time 16217933769 ps
CPU time 26.7 seconds
Started Jul 15 04:34:06 PM PDT 24
Finished Jul 15 04:34:36 PM PDT 24
Peak memory 199508 kb
Host smart-9b1c2a42-b41f-4d8a-bb3c-17e1fe5c621e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181254521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2181254521
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2790283292
Short name T293
Test name
Test status
Simulation time 61724865021 ps
CPU time 298.93 seconds
Started Jul 15 04:34:08 PM PDT 24
Finished Jul 15 04:39:09 PM PDT 24
Peak memory 216236 kb
Host smart-a0e1dc4b-f433-400e-a4ba-b254012f68eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790283292 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2790283292
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3823865166
Short name T303
Test name
Test status
Simulation time 77384442273 ps
CPU time 20.68 seconds
Started Jul 15 04:34:06 PM PDT 24
Finished Jul 15 04:34:30 PM PDT 24
Peak memory 199772 kb
Host smart-99b1a703-cdd8-453b-8147-21a653ccc42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823865166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3823865166
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.76470655
Short name T743
Test name
Test status
Simulation time 42637380157 ps
CPU time 483.2 seconds
Started Jul 15 04:34:05 PM PDT 24
Finished Jul 15 04:42:11 PM PDT 24
Peak memory 216416 kb
Host smart-f61b08e8-f997-4dff-96b4-0a8464d1663b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76470655 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.76470655
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2456714469
Short name T1067
Test name
Test status
Simulation time 105305359846 ps
CPU time 71.44 seconds
Started Jul 15 04:34:07 PM PDT 24
Finished Jul 15 04:35:21 PM PDT 24
Peak memory 199660 kb
Host smart-381768e2-258e-4c89-9784-3a1941db4705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456714469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2456714469
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1950823121
Short name T577
Test name
Test status
Simulation time 30294178389 ps
CPU time 302.26 seconds
Started Jul 15 04:34:15 PM PDT 24
Finished Jul 15 04:39:19 PM PDT 24
Peak memory 208228 kb
Host smart-00012a0d-5bac-450c-932f-f4cbfba58adf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950823121 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1950823121
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2869604000
Short name T185
Test name
Test status
Simulation time 48682312128 ps
CPU time 17.49 seconds
Started Jul 15 04:34:12 PM PDT 24
Finished Jul 15 04:34:31 PM PDT 24
Peak memory 199608 kb
Host smart-9ab622f6-0769-45a6-8f3e-19f4ca97f789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869604000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2869604000
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.292437589
Short name T53
Test name
Test status
Simulation time 69687150178 ps
CPU time 742.13 seconds
Started Jul 15 04:34:13 PM PDT 24
Finished Jul 15 04:46:36 PM PDT 24
Peak memory 224660 kb
Host smart-f6bb325e-b0d3-487c-af65-8df6de984f2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292437589 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.292437589
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.656493049
Short name T815
Test name
Test status
Simulation time 25787981381 ps
CPU time 14.94 seconds
Started Jul 15 04:34:15 PM PDT 24
Finished Jul 15 04:34:32 PM PDT 24
Peak memory 199176 kb
Host smart-b4352de9-bd71-4f4c-ac7b-c776b1b99a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656493049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.656493049
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2074127342
Short name T770
Test name
Test status
Simulation time 28653093502 ps
CPU time 313.69 seconds
Started Jul 15 04:34:16 PM PDT 24
Finished Jul 15 04:39:31 PM PDT 24
Peak memory 216520 kb
Host smart-a4238b1d-f408-4efd-9586-aad76384b2fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074127342 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2074127342
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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