Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	109543	1			T2	20		T3	4		T4	1
all_values[1]	109543	1			T2	20		T3	4		T4	1
all_values[2]	109543	1			T2	20		T3	4		T4	1
all_values[3]	109543	1			T2	20		T3	4		T4	1
all_values[4]	109543	1			T2	20		T3	4		T4	1
all_values[5]	109543	1			T2	20		T3	4		T4	1
all_values[6]	109543	1			T2	20		T3	4		T4	1
all_values[7]	109543	1			T2	20		T3	4		T4	1
all_values[8]	109543	1			T2	20		T3	4		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

501537

1

T2

82

T3

10

T4

4

auto[1]

484350

1

T2

98

T3

26

T4

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

897301

1

T2

143

T3

30

T4

7

auto[1]

88586

1

T2

37

T3

6

T4

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	34898	1			T2	1		T5	4		T6	43
all_values[0]	auto[0]	auto[1]	23311	1			T2	2		T5	16		T6	8
all_values[0]	auto[1]	auto[0]	31508	1			T2	3		T5	19		T7	363
all_values[0]	auto[1]	auto[1]	19826	1			T2	14		T3	4		T4	1
all_values[1]	auto[0]	auto[0]	53122	1			T2	6		T5	42		T6	46
all_values[1]	auto[0]	auto[1]	1934	1			T6	5		T43	4		T14	6
all_values[1]	auto[1]	auto[0]	52819	1			T2	14		T3	4		T4	1
all_values[1]	auto[1]	auto[1]	1668	1			T9	19		T13	13		T24	29
all_values[2]	auto[0]	auto[0]	48580	1			T2	11		T4	1		T5	50
all_values[2]	auto[0]	auto[1]	2870	1			T2	2		T5	6		T6	4
all_values[2]	auto[1]	auto[0]	55392	1			T2	3		T3	4		T5	4
all_values[2]	auto[1]	auto[1]	2701	1			T2	4		T5	1		T6	1
all_values[3]	auto[0]	auto[0]	58491	1			T2	14		T3	4		T5	19
all_values[3]	auto[0]	auto[1]	308	1			T11	1		T16	1		T32	1
all_values[3]	auto[1]	auto[0]	50425	1			T2	6		T4	1		T5	42
all_values[3]	auto[1]	auto[1]	319	1			T6	1		T13	1		T14	3
all_values[4]	auto[0]	auto[0]	57828	1			T2	10		T5	16		T6	6
all_values[4]	auto[0]	auto[1]	523	1			T13	1		T15	5		T16	4
all_values[4]	auto[1]	auto[0]	50689	1			T2	10		T3	4		T4	1
all_values[4]	auto[1]	auto[1]	503	1			T14	1		T32	4		T20	15
all_values[5]	auto[0]	auto[0]	56737	1			T2	20		T3	2		T4	1
all_values[5]	auto[0]	auto[1]	202	1			T14	3		T16	1		T93	1
all_values[5]	auto[1]	auto[0]	52439	1			T3	2		T5	13		T6	5
all_values[5]	auto[1]	auto[1]	165	1			T14	3		T32	1		T93	2
all_values[6]	auto[0]	auto[0]	57070	1			T2	10		T3	2		T4	1
all_values[6]	auto[0]	auto[1]	175	1			T14	1		T16	3		T93	1
all_values[6]	auto[1]	auto[0]	52081	1			T2	10		T3	2		T5	18
all_values[6]	auto[1]	auto[1]	217	1			T14	5		T32	3		T93	1
all_values[7]	auto[0]	auto[0]	51215	1			T2	1		T3	2		T5	36
all_values[7]	auto[0]	auto[1]	360	1			T16	2		T32	2		T93	6
all_values[7]	auto[1]	auto[0]	57625	1			T2	19		T3	2		T4	1
all_values[7]	auto[1]	auto[1]	343	1			T14	2		T18	1		T126	1
all_values[8]	auto[0]	auto[0]	38556	1			T2	3		T5	36		T7	285
all_values[8]	auto[0]	auto[1]	15357	1			T2	2		T4	1		T5	7
all_values[8]	auto[1]	auto[0]	37826	1			T2	2		T3	2		T5	1
all_values[8]	auto[1]	auto[1]	17804	1			T2	13		T3	2		T5	17