Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2347	1			T3	2		T4	15		T5	3
auto[BaudRate115200]	2073	1			T2	1		T3	1		T4	9
auto[BaudRate230400]	2077	1			T2	1		T4	12		T5	1
auto[BaudRate128Kbps]	2046	1			T3	1		T4	15		T5	2
auto[BaudRate256Kbps]	2243	1			T2	2		T4	6		T5	4
auto[BaudRate1Mbps]	1749	1			T2	1		T3	2		T4	3
auto[BaudRate1p5Mbps]	1272	1			T3	1		T5	2		T6	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1481	1			T4	60		T6	9		T18	10
freqs[25]	1260	1			T2	5		T10	9		T92	10
freqs[48]	460	1			T23	21		T260	18		T283	4
freqs[50]	752	1			T25	2		T17	7		T50	14
freqs[100]	1143	1			T13	2		T38	10		T131	6

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	255	1			T4	15		T6	2		T18	1
auto[BaudRate9600]	freqs[25]	239	1			T53	3		T55	1		T268	1
auto[BaudRate9600]	freqs[48]	70	1			T23	6		T283	1		T114	4
auto[BaudRate9600]	freqs[50]	105	1			T25	1		T17	7		T50	14
auto[BaudRate9600]	freqs[100]	185	1			T13	1		T131	1		T16	9
auto[BaudRate115200]	freqs[24]	217	1			T4	9		T18	1		T46	12
auto[BaudRate115200]	freqs[25]	171	1			T2	1		T10	1		T293	1
auto[BaudRate115200]	freqs[48]	65	1			T260	2		T283	1		T114	1
auto[BaudRate115200]	freqs[50]	123	1			T185	2		T117	1		T193	3
auto[BaudRate115200]	freqs[100]	169	1			T13	1		T38	1		T131	1
auto[BaudRate230400]	freqs[24]	227	1			T4	12		T18	2		T46	10
auto[BaudRate230400]	freqs[25]	197	1			T2	1		T10	1		T92	3
auto[BaudRate230400]	freqs[48]	67	1			T23	6		T260	6		T283	2
auto[BaudRate230400]	freqs[50]	90	1			T25	1		T185	2		T117	1
auto[BaudRate230400]	freqs[100]	172	1			T38	2		T16	5		T47	1
auto[BaudRate128Kbps]	freqs[24]	243	1			T4	15		T6	3		T18	1
auto[BaudRate128Kbps]	freqs[25]	214	1			T10	3		T92	4		T55	3
auto[BaudRate128Kbps]	freqs[48]	76	1			T260	1		T114	1		T296	1
auto[BaudRate128Kbps]	freqs[50]	137	1			T185	2		T117	1		T193	1
auto[BaudRate128Kbps]	freqs[100]	126	1			T38	2		T131	2		T16	3
auto[BaudRate256Kbps]	freqs[24]	209	1			T4	6		T6	2		T18	2
auto[BaudRate256Kbps]	freqs[25]	181	1			T2	2		T92	1		T53	1
auto[BaudRate256Kbps]	freqs[48]	72	1			T23	6		T260	2		T114	2
auto[BaudRate256Kbps]	freqs[50]	117	1			T185	2		T117	1		T193	1
auto[BaudRate256Kbps]	freqs[100]	182	1			T38	2		T131	2		T16	6
auto[BaudRate1Mbps]	freqs[24]	223	1			T4	3		T6	1		T18	3
auto[BaudRate1Mbps]	freqs[25]	186	1			T2	1		T10	2		T92	2
auto[BaudRate1Mbps]	freqs[48]	49	1			T260	2		T36	3		T317	1
auto[BaudRate1Mbps]	freqs[50]	76	1			T295	1		T117	1		T106	3
auto[BaudRate1Mbps]	freqs[100]	137	1			T38	1		T16	3		T136	3
auto[BaudRate1p5Mbps]	freqs[25]	72	1			T10	2		T53	2		T268	1
auto[BaudRate1p5Mbps]	freqs[48]	61	1			T23	3		T260	5		T114	1
auto[BaudRate1p5Mbps]	freqs[50]	104	1			T295	1		T117	3		T193	2
auto[BaudRate1p5Mbps]	freqs[100]	172	1			T38	2		T16	5		T47	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded