Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29156714	1			T2	17		T3	10		T4	8
all_levels[1]	192850	1			T3	2		T5	22		T7	134
all_levels[2]	2389	1			T2	1		T5	9		T9	4
all_levels[3]	1234	1			T5	2		T6	2		T24	8
all_levels[4]	798	1			T2	1		T5	1		T9	1
all_levels[5]	609	1			T43	2		T24	4		T38	1
all_levels[6]	485	1			T43	1		T24	2		T38	2
all_levels[7]	430	1			T5	2		T43	1		T24	5
all_levels[8]	329	1			T5	1		T24	1		T39	3
all_levels[9]	244	1			T2	1		T3	1		T24	3
all_levels[10]	237	1			T5	1		T43	1		T24	1
all_levels[11]	211	1			T5	1		T125	1		T44	1
all_levels[12]	213	1			T24	1		T125	1		T131	3
all_levels[13]	151	1			T6	3		T24	2		T38	1
all_levels[14]	137	1			T10	1		T24	1		T38	1
all_levels[15]	124	1			T43	1		T24	1		T125	3
all_levels[16]	136	1			T6	3		T11	1		T43	1
all_levels[17]	88	1			T11	1		T24	1		T44	1
all_levels[18]	98	1			T11	1		T43	1		T125	3
all_levels[19]	84	1			T24	1		T124	3		T126	1
all_levels[20]	86	1			T6	1		T24	1		T125	2
all_levels[21]	79	1			T9	1		T125	1		T16	1
all_levels[22]	61	1			T132	1		T53	2		T55	1
all_levels[23]	78	1			T125	1		T133	1		T134	1
all_levels[24]	58	1			T43	1		T44	1		T55	1
all_levels[25]	68	1			T92	1		T44	1		T135	1
all_levels[26]	55	1			T3	2		T43	1		T132	1
all_levels[27]	57	1			T43	1		T46	1		T136	2
all_levels[28]	52	1			T132	1		T131	1		T32	1
all_levels[29]	42	1			T44	2		T32	1		T116	1
all_levels[30]	36	1			T6	1		T137	1		T138	1
all_levels[31]	36	1			T11	3		T34	2		T139	1
all_levels[32]	28	1			T43	2		T125	2		T32	1
all_levels[33]	26	1			T6	1		T11	2		T43	1
all_levels[34]	33	1			T6	2		T43	1		T132	1
all_levels[35]	26	1			T32	1		T52	1		T137	1
all_levels[36]	19	1			T140	1		T141	1		T142	1
all_levels[37]	15	1			T143	1		T35	1		T128	1
all_levels[38]	24	1			T132	1		T144	3		T145	1
all_levels[39]	22	1			T46	1		T143	1		T139	1
all_levels[40]	23	1			T43	1		T146	1		T139	1
all_levels[41]	23	1			T46	1		T147	1		T148	1
all_levels[42]	13	1			T3	1		T149	1		T113	1
all_levels[43]	13	1			T137	2		T133	2		T150	1
all_levels[44]	17	1			T46	1		T35	1		T151	1
all_levels[45]	26	1			T43	1		T55	4		T152	1
all_levels[46]	10	1			T153	2		T154	1		T155	1
all_levels[47]	13	1			T152	1		T156	1		T157	1
all_levels[48]	18	1			T146	1		T158	1		T159	1
all_levels[49]	12	1			T160	1		T161	1		T162	1
all_levels[50]	16	1			T43	1		T143	1		T139	1
all_levels[51]	7	1			T32	1		T163	1		T164	1
all_levels[52]	13	1			T117	1		T165	1		T164	1
all_levels[53]	5	1			T9	1		T166	2		T167	1
all_levels[54]	14	1			T168	3		T169	1		T170	1
all_levels[55]	18	1			T6	1		T132	5		T171	2
all_levels[56]	7	1			T32	1		T120	1		T172	1
all_levels[57]	14	1			T150	2		T113	1		T173	1
all_levels[58]	11	1			T174	1		T113	1		T128	1
all_levels[59]	5	1			T175	1		T176	1		T177	1
all_levels[60]	7	1			T134	1		T178	3		T179	1
all_levels[61]	5	1			T180	1		T56	2		T181	1
all_levels[62]	7	1			T6	1		T182	1		T183	1
all_levels[63]	8	1			T152	1		T134	1		T184	2
all_levels[64]	89	1			T6	1		T134	1		T118	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29353908

1

T2

20

T3

9

T5

286

auto[1]

4948

1

T3

7

T4

8

T6

8

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[50] , all_levels[51]]	[auto[1]]	--	--	2
[all_levels[53]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29152271	1			T2	17		T3	5		T5	247
all_levels[0]	auto[1]	4443	1			T3	5		T4	8		T6	2
all_levels[1]	auto[0]	192766	1			T3	1		T5	22		T7	134
all_levels[1]	auto[1]	84	1			T3	1		T44	2		T53	3
all_levels[2]	auto[0]	2363	1			T2	1		T5	9		T9	4
all_levels[2]	auto[1]	26	1			T52	2		T55	2		T185	1
all_levels[3]	auto[0]	1209	1			T5	2		T6	1		T24	8
all_levels[3]	auto[1]	25	1			T6	1		T53	1		T186	5
all_levels[4]	auto[0]	772	1			T2	1		T5	1		T9	1
all_levels[4]	auto[1]	26	1			T52	1		T53	1		T187	1
all_levels[5]	auto[0]	589	1			T43	2		T24	4		T38	1
all_levels[5]	auto[1]	20	1			T188	1		T189	3		T163	1
all_levels[6]	auto[0]	469	1			T43	1		T24	2		T38	2
all_levels[6]	auto[1]	16	1			T190	2		T191	1		T192	1
all_levels[7]	auto[0]	407	1			T5	2		T43	1		T24	5
all_levels[7]	auto[1]	23	1			T52	1		T135	2		T193	1
all_levels[8]	auto[0]	309	1			T5	1		T24	1		T39	3
all_levels[8]	auto[1]	20	1			T46	2		T185	2		T137	1
all_levels[9]	auto[0]	230	1			T2	1		T3	1		T24	3
all_levels[9]	auto[1]	14	1			T194	2		T195	1		T196	2
all_levels[10]	auto[0]	223	1			T5	1		T43	1		T24	1
all_levels[10]	auto[1]	14	1			T148	4		T197	1		T198	2
all_levels[11]	auto[0]	197	1			T5	1		T125	1		T44	1
all_levels[11]	auto[1]	14	1			T175	1		T199	1		T200	1
all_levels[12]	auto[0]	200	1			T24	1		T125	1		T131	3
all_levels[12]	auto[1]	13	1			T55	2		T171	2		T201	1
all_levels[13]	auto[0]	139	1			T6	1		T24	2		T38	1
all_levels[13]	auto[1]	12	1			T6	2		T202	1		T203	1
all_levels[14]	auto[0]	124	1			T10	1		T24	1		T38	1
all_levels[14]	auto[1]	13	1			T40	1		T149	2		T204	1
all_levels[15]	auto[0]	119	1			T43	1		T24	1		T125	2
all_levels[15]	auto[1]	5	1			T125	1		T205	1		T206	2
all_levels[16]	auto[0]	123	1			T6	1		T11	1		T43	1
all_levels[16]	auto[1]	13	1			T6	2		T207	5		T202	1
all_levels[17]	auto[0]	79	1			T11	1		T24	1		T44	1
all_levels[17]	auto[1]	9	1			T208	3		T209	1		T210	1
all_levels[18]	auto[0]	89	1			T11	1		T43	1		T125	3
all_levels[18]	auto[1]	9	1			T211	1		T193	2		T148	1
all_levels[19]	auto[0]	78	1			T24	1		T124	3		T126	1
all_levels[19]	auto[1]	6	1			T212	1		T213	1		T214	1
all_levels[20]	auto[0]	77	1			T6	1		T24	1		T125	2
all_levels[20]	auto[1]	9	1			T215	2		T145	2		T216	3
all_levels[21]	auto[0]	73	1			T9	1		T125	1		T16	1
all_levels[21]	auto[1]	6	1			T198	1		T217	1		T218	1
all_levels[22]	auto[0]	58	1			T132	1		T53	1		T55	1
all_levels[22]	auto[1]	3	1			T53	1		T219	1		T220	1
all_levels[23]	auto[0]	63	1			T125	1		T133	1		T134	1
all_levels[23]	auto[1]	15	1			T221	1		T222	14		-	-
all_levels[24]	auto[0]	53	1			T43	1		T44	1		T55	1
all_levels[24]	auto[1]	5	1			T137	1		T75	1		T223	1
all_levels[25]	auto[0]	56	1			T92	1		T44	1		T135	1
all_levels[25]	auto[1]	12	1			T224	1		T219	1		T204	1
all_levels[26]	auto[0]	54	1			T3	1		T43	1		T132	1
all_levels[26]	auto[1]	1	1			T3	1		-	-		-	-
all_levels[27]	auto[0]	50	1			T43	1		T46	1		T136	1
all_levels[27]	auto[1]	7	1			T136	1		T56	3		T217	3
all_levels[28]	auto[0]	48	1			T132	1		T131	1		T32	1
all_levels[28]	auto[1]	4	1			T196	1		T225	2		T226	1
all_levels[29]	auto[0]	40	1			T44	1		T32	1		T116	1
all_levels[29]	auto[1]	2	1			T44	1		T227	1		-	-
all_levels[30]	auto[0]	34	1			T6	1		T137	1		T138	1
all_levels[30]	auto[1]	2	1			T228	1		T229	1		-	-
all_levels[31]	auto[0]	30	1			T11	1		T34	1		T139	1
all_levels[31]	auto[1]	6	1			T11	2		T34	1		T230	2
all_levels[32]	auto[0]	26	1			T43	2		T125	1		T32	1
all_levels[32]	auto[1]	2	1			T125	1		T231	1		-	-
all_levels[33]	auto[0]	25	1			T6	1		T11	1		T43	1
all_levels[33]	auto[1]	1	1			T11	1		-	-		-	-
all_levels[34]	auto[0]	29	1			T6	1		T43	1		T132	1
all_levels[34]	auto[1]	4	1			T6	1		T78	1		T129	1
all_levels[35]	auto[0]	25	1			T32	1		T52	1		T137	1
all_levels[35]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[36]	auto[0]	16	1			T140	1		T141	1		T142	1
all_levels[36]	auto[1]	3	1			T233	1		T234	1		T229	1
all_levels[37]	auto[0]	15	1			T143	1		T35	1		T128	1
all_levels[38]	auto[0]	21	1			T132	1		T144	1		T145	1
all_levels[38]	auto[1]	3	1			T144	2		T235	1		-	-
all_levels[39]	auto[0]	19	1			T46	1		T143	1		T139	1
all_levels[39]	auto[1]	3	1			T236	1		T237	1		T238	1
all_levels[40]	auto[0]	19	1			T43	1		T146	1		T139	1
all_levels[40]	auto[1]	4	1			T239	4		-	-		-	-
all_levels[41]	auto[0]	19	1			T46	1		T147	1		T148	1
all_levels[41]	auto[1]	4	1			T111	2		T240	1		T241	1
all_levels[42]	auto[0]	12	1			T3	1		T149	1		T113	1
all_levels[42]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[43]	auto[0]	10	1			T137	2		T133	1		T150	1
all_levels[43]	auto[1]	3	1			T133	1		T229	2		-	-
all_levels[44]	auto[0]	16	1			T46	1		T35	1		T151	1
all_levels[44]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[45]	auto[0]	18	1			T43	1		T55	1		T152	1
all_levels[45]	auto[1]	8	1			T55	3		T57	3		T243	1
all_levels[46]	auto[0]	7	1			T153	1		T154	1		T155	1
all_levels[46]	auto[1]	3	1			T153	1		T244	2		-	-
all_levels[47]	auto[0]	13	1			T152	1		T156	1		T157	1
all_levels[48]	auto[0]	17	1			T146	1		T158	1		T159	1
all_levels[48]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[49]	auto[0]	10	1			T160	1		T161	1		T162	1
all_levels[49]	auto[1]	2	1			T246	1		T247	1		-	-
all_levels[50]	auto[0]	16	1			T43	1		T143	1		T139	1
all_levels[51]	auto[0]	7	1			T32	1		T163	1		T164	1
all_levels[52]	auto[0]	12	1			T117	1		T165	1		T164	1
all_levels[52]	auto[1]	1	1			T248	1		-	-		-	-
all_levels[53]	auto[0]	5	1			T9	1		T166	2		T167	1
all_levels[54]	auto[0]	12	1			T168	1		T169	1		T170	1
all_levels[54]	auto[1]	2	1			T168	2		-	-		-	-
all_levels[55]	auto[0]	12	1			T6	1		T132	1		T171	1
all_levels[55]	auto[1]	6	1			T132	4		T171	1		T159	1
all_levels[56]	auto[0]	7	1			T32	1		T120	1		T172	1
all_levels[57]	auto[0]	12	1			T150	2		T113	1		T173	1
all_levels[57]	auto[1]	2	1			T249	2		-	-		-	-
all_levels[58]	auto[0]	8	1			T174	1		T113	1		T128	1
all_levels[58]	auto[1]	3	1			T250	3		-	-		-	-
all_levels[59]	auto[0]	5	1			T175	1		T176	1		T177	1
all_levels[60]	auto[0]	4	1			T134	1		T178	1		T179	1
all_levels[60]	auto[1]	3	1			T178	2		T251	1		-	-
all_levels[61]	auto[0]	5	1			T180	1		T56	2		T181	1
all_levels[62]	auto[0]	6	1			T6	1		T182	1		T183	1
all_levels[62]	auto[1]	1	1			T233	1		-	-		-	-
all_levels[63]	auto[0]	8	1			T152	1		T134	1		T184	2
all_levels[64]	auto[0]	80	1			T6	1		T134	1		T118	1
all_levels[64]	auto[1]	9	1			T252	1		T253	1		T254	1