Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	109543	1			T2	20		T3	4		T4	1
all_pins[1]	109543	1			T2	20		T3	4		T4	1
all_pins[2]	109543	1			T2	20		T3	4		T4	1
all_pins[3]	109543	1			T2	20		T3	4		T4	1
all_pins[4]	109543	1			T2	20		T3	4		T4	1
all_pins[5]	109543	1			T2	20		T3	4		T4	1
all_pins[6]	109543	1			T2	20		T3	4		T4	1
all_pins[7]	109543	1			T2	20		T3	4		T4	1
all_pins[8]	109543	1			T2	20		T3	4		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	941321	1			T2	144		T3	29		T4	8
values[0x1]	44566	1			T2	36		T3	7		T4	1
transitions[0x0=>0x1]	34698	1			T2	25		T3	5		T4	1
transitions[0x1=>0x0]	34488	1			T2	24		T3	4		T5	25

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	89622	1			T2	6		T5	39		T6	51
all_pins[0]	values[0x1]	19921	1			T2	14		T3	4		T4	1
all_pins[0]	transitions[0x0=>0x1]	19221	1			T2	14		T3	4		T4	1
all_pins[0]	transitions[0x1=>0x0]	966	1			T9	19		T13	13		T24	29
all_pins[1]	values[0x0]	107877	1			T2	20		T3	4		T4	1
all_pins[1]	values[0x1]	1666	1			T9	19		T13	13		T24	29
all_pins[1]	transitions[0x0=>0x1]	1564	1			T9	19		T13	13		T24	29
all_pins[1]	transitions[0x1=>0x0]	2669	1			T2	4		T5	1		T6	1
all_pins[2]	values[0x0]	106772	1			T2	16		T3	4		T4	1
all_pins[2]	values[0x1]	2771	1			T2	4		T5	1		T6	1
all_pins[2]	transitions[0x0=>0x1]	2706	1			T2	4		T5	1		T6	1
all_pins[2]	transitions[0x1=>0x0]	254	1			T6	1		T13	1		T14	2
all_pins[3]	values[0x0]	109224	1			T2	20		T3	4		T4	1
all_pins[3]	values[0x1]	319	1			T6	1		T13	1		T14	3
all_pins[3]	transitions[0x0=>0x1]	269	1			T6	1		T13	1		T14	2
all_pins[3]	transitions[0x1=>0x0]	453	1			T32	4		T20	15		T93	3
all_pins[4]	values[0x0]	109040	1			T2	20		T3	4		T4	1
all_pins[4]	values[0x1]	503	1			T14	1		T32	4		T20	15
all_pins[4]	transitions[0x0=>0x1]	446	1			T32	4		T20	12		T93	3
all_pins[4]	transitions[0x1=>0x0]	161	1			T14	2		T32	1		T20	1
all_pins[5]	values[0x0]	109325	1			T2	20		T3	4		T4	1
all_pins[5]	values[0x1]	218	1			T14	3		T32	1		T20	4
all_pins[5]	transitions[0x0=>0x1]	171	1			T14	2		T20	4		T93	2
all_pins[5]	transitions[0x1=>0x0]	879	1			T2	5		T3	1		T5	1
all_pins[6]	values[0x0]	108617	1			T2	15		T3	3		T4	1
all_pins[6]	values[0x1]	926	1			T2	5		T3	1		T5	1
all_pins[6]	transitions[0x0=>0x1]	862	1			T2	5		T3	1		T5	1
all_pins[6]	transitions[0x1=>0x0]	279	1			T18	1		T126	1		T34	1
all_pins[7]	values[0x0]	109200	1			T2	20		T3	4		T4	1
all_pins[7]	values[0x1]	343	1			T14	2		T18	1		T126	1
all_pins[7]	transitions[0x0=>0x1]	202	1			T14	2		T18	1		T126	1
all_pins[7]	transitions[0x1=>0x0]	17758	1			T2	13		T3	2		T5	17
all_pins[8]	values[0x0]	91644	1			T2	7		T3	2		T4	1
all_pins[8]	values[0x1]	17899	1			T2	13		T3	2		T5	17
all_pins[8]	transitions[0x0=>0x1]	9257	1			T2	2		T5	1		T6	7
all_pins[8]	transitions[0x1=>0x0]	11069	1			T2	2		T3	1		T5	6