Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5839910	1			T2	12		T3	4		T5	67
all_levels[1]	1306421	1			T2	2		T3	4		T5	94
all_levels[2]	286748	1			T2	2		T5	1		T7	4162
all_levels[3]	335608	1			T3	4		T7	4168		T8	4607
all_levels[4]	330363	1			T5	2		T6	3		T7	4157
all_levels[5]	334371	1			T3	3		T5	1		T7	4170
all_levels[6]	246034	1			T7	4136		T8	4589		T9	3
all_levels[7]	224834	1			T7	4171		T8	4600		T9	1
all_levels[8]	347286	1			T7	4164		T8	4604		T9	5
all_levels[9]	303821	1			T7	4173		T8	4600		T9	2
all_levels[10]	548341	1			T5	32		T7	4171		T8	4611
all_levels[11]	223496	1			T2	5		T5	11		T7	4159
all_levels[12]	203844	1			T5	61		T7	4169		T8	4568
all_levels[13]	374723	1			T5	2		T6	1		T7	4152
all_levels[14]	218341	1			T5	3		T7	4147		T8	4595
all_levels[15]	203094	1			T7	4166		T8	4587		T9	2
all_levels[16]	338170	1			T7	4159		T8	4557		T9	4
all_levels[17]	191218	1			T7	4171		T8	4592		T9	5
all_levels[18]	241802	1			T7	4175		T8	4545		T9	4
all_levels[19]	226286	1			T7	4145		T8	4594		T9	2
all_levels[20]	380056	1			T7	18899		T8	4601		T9	5
all_levels[21]	192419	1			T7	4142		T8	4600		T9	128
all_levels[22]	453595	1			T7	4175		T8	4461		T9	1
all_levels[23]	197827	1			T7	4152		T8	2625		T9	4
all_levels[24]	177964	1			T5	1		T6	3		T7	4169
all_levels[25]	181241	1			T5	1		T7	4173		T8	2633
all_levels[26]	290832	1			T5	3		T6	2		T7	4158
all_levels[27]	261910	1			T7	4164		T8	2615		T9	5
all_levels[28]	203227	1			T5	1		T7	4163		T8	2641
all_levels[29]	157429	1			T7	4168		T8	2638		T37	5
all_levels[30]	254254	1			T5	2		T7	56393		T8	52431
all_levels[31]	742518	1			T5	1		T7	5413		T8	3005
all_levels[32]	13540483	1			T5	4		T7	20227		T8	332821

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29353908

1

T2

20

T3

9

T5

286

auto[1]

4558

1

T2

1

T3

6

T5

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5837318	1			T2	12		T3	2		T5	67
all_levels[0]	auto[1]	2592	1			T3	2		T6	3		T9	1
all_levels[1]	auto[0]	1306106	1			T2	2		T3	3		T5	93
all_levels[1]	auto[1]	315	1			T3	1		T5	1		T6	1
all_levels[2]	auto[0]	286681	1			T2	2		T5	1		T7	4162
all_levels[2]	auto[1]	67	1			T40	2		T267	3		T194	1
all_levels[3]	auto[0]	335454	1			T3	3		T7	4168		T8	4607
all_levels[3]	auto[1]	154	1			T3	1		T40	1		T46	4
all_levels[4]	auto[0]	330321	1			T5	2		T6	1		T7	4157
all_levels[4]	auto[1]	42	1			T6	2		T42	2		T132	4
all_levels[5]	auto[0]	334346	1			T3	1		T5	1		T7	4170
all_levels[5]	auto[1]	25	1			T3	2		T46	1		T32	1
all_levels[6]	auto[0]	246002	1			T7	4136		T8	4589		T9	3
all_levels[6]	auto[1]	32	1			T37	1		T125	1		T132	1
all_levels[7]	auto[0]	224697	1			T7	4171		T8	4600		T9	1
all_levels[7]	auto[1]	137	1			T125	1		T281	3		T16	5
all_levels[8]	auto[0]	347251	1			T7	4164		T8	4604		T9	5
all_levels[8]	auto[1]	35	1			T78	1		T230	1		T310	1
all_levels[9]	auto[0]	303799	1			T7	4173		T8	4600		T9	2
all_levels[9]	auto[1]	22	1			T186	2		T81	1		T107	1
all_levels[10]	auto[0]	548311	1			T5	32		T7	4171		T8	4611
all_levels[10]	auto[1]	30	1			T9	1		T75	2		T149	1
all_levels[11]	auto[0]	223480	1			T2	4		T5	11		T7	4159
all_levels[11]	auto[1]	16	1			T2	1		T39	1		T44	1
all_levels[12]	auto[0]	203816	1			T5	61		T7	4169		T8	4568
all_levels[12]	auto[1]	28	1			T311	1		T216	4		T155	3
all_levels[13]	auto[0]	374691	1			T5	2		T6	1		T7	4152
all_levels[13]	auto[1]	32	1			T46	3		T136	1		T159	1
all_levels[14]	auto[0]	218316	1			T5	3		T7	4147		T8	4595
all_levels[14]	auto[1]	25	1			T44	1		T298	1		T319	1
all_levels[15]	auto[0]	202903	1			T7	4166		T8	4587		T9	2
all_levels[15]	auto[1]	191	1			T125	1		T93	1		T147	1
all_levels[16]	auto[0]	338152	1			T7	4159		T8	4557		T9	4
all_levels[16]	auto[1]	18	1			T81	1		T272	1		T230	2
all_levels[17]	auto[0]	191202	1			T7	4171		T8	4592		T9	5
all_levels[17]	auto[1]	16	1			T39	1		T194	1		T320	1
all_levels[18]	auto[0]	241768	1			T7	4175		T8	4545		T9	4
all_levels[18]	auto[1]	34	1			T39	1		T125	1		T281	1
all_levels[19]	auto[0]	226272	1			T7	4145		T8	4594		T9	2
all_levels[19]	auto[1]	14	1			T46	1		T201	2		T236	1
all_levels[20]	auto[0]	380043	1			T7	18899		T8	4601		T9	5
all_levels[20]	auto[1]	13	1			T48	1		T118	1		T223	1
all_levels[21]	auto[0]	192395	1			T7	4142		T8	4600		T9	128
all_levels[21]	auto[1]	24	1			T286	3		T201	1		T139	1
all_levels[22]	auto[0]	453578	1			T7	4175		T8	4461		T9	1
all_levels[22]	auto[1]	17	1			T321	1		T322	1		T200	1
all_levels[23]	auto[0]	197810	1			T7	4152		T8	2625		T9	4
all_levels[23]	auto[1]	17	1			T185	1		T191	1		T311	1
all_levels[24]	auto[0]	177951	1			T5	1		T6	2		T7	4169
all_levels[24]	auto[1]	13	1			T6	1		T191	1		T264	1
all_levels[25]	auto[0]	181224	1			T5	1		T7	4173		T8	2633
all_levels[25]	auto[1]	17	1			T10	1		T323	3		T149	2
all_levels[26]	auto[0]	290806	1			T5	3		T6	1		T7	4158
all_levels[26]	auto[1]	26	1			T6	1		T284	1		T76	1
all_levels[27]	auto[0]	261889	1			T7	4164		T8	2615		T9	5
all_levels[27]	auto[1]	21	1			T81	1		T213	1		T188	1
all_levels[28]	auto[0]	203213	1			T5	1		T7	4163		T8	2641
all_levels[28]	auto[1]	14	1			T281	1		T258	2		T305	1
all_levels[29]	auto[0]	157406	1			T7	4168		T8	2638		T37	5
all_levels[29]	auto[1]	23	1			T294	1		T57	1		T219	1
all_levels[30]	auto[0]	254226	1			T5	2		T7	56393		T8	52430
all_levels[30]	auto[1]	28	1			T8	1		T44	1		T135	2
all_levels[31]	auto[0]	742498	1			T5	1		T7	5413		T8	3005
all_levels[31]	auto[1]	20	1			T129	1		T221	6		T324	2
all_levels[32]	auto[0]	13539983	1			T5	4		T7	20227		T8	332821
all_levels[32]	auto[1]	500	1			T11	2		T43	1		T24	1