Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	798	1			T14	7		T16	4		T32	8
all_values[1]	798	1			T14	7		T16	4		T32	8
all_values[2]	798	1			T14	7		T16	4		T32	8
all_values[3]	798	1			T14	7		T16	4		T32	8
all_values[4]	798	1			T14	7		T16	4		T32	8
all_values[5]	798	1			T14	7		T16	4		T32	8
all_values[6]	798	1			T14	7		T16	4		T32	8
all_values[7]	798	1			T14	7		T16	4		T32	8
all_values[8]	798	1			T14	7		T16	4		T32	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3832

1

T14

28

T16

32

T32

38

auto[1]

3350

1

T14

35

T16

4

T32

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2356

1

T14

13

T16

13

T32

25

auto[1]

4826

1

T14

50

T16

23

T32

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4240

1

T14

34

T16

22

T32

42

auto[1]

2942

1

T14

29

T16

14

T32

30

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	267	1			T14	1		T16	4		T32	3
all_values[0]	auto[0]	auto[1]	auto[1]	216	1			T14	4		T32	2		T93	3
all_values[0]	auto[1]	auto[0]	auto[1]	169	1			T14	1		T32	2		T93	2
all_values[0]	auto[1]	auto[1]	auto[1]	146	1			T14	1		T32	1		T93	1
all_values[1]	auto[0]	auto[0]	auto[0]	241	1			T14	1		T16	2		T32	3
all_values[1]	auto[0]	auto[1]	auto[0]	225	1			T14	1		T32	1		T93	3
all_values[1]	auto[1]	auto[0]	auto[1]	186	1			T14	4		T16	2		T32	2
all_values[1]	auto[1]	auto[1]	auto[1]	146	1			T14	1		T32	2		T33	1
all_values[2]	auto[0]	auto[0]	auto[0]	160	1			T14	1		T32	2		T33	1
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T14	1		T16	1		T33	1
all_values[2]	auto[0]	auto[1]	auto[0]	159	1			T16	1		T32	3		T35	2
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T14	2		T32	1		T93	3
all_values[2]	auto[1]	auto[0]	auto[1]	162	1			T14	3		T16	2		T32	1
all_values[2]	auto[1]	auto[1]	auto[1]	149	1			T32	1		T93	4		T34	1
all_values[3]	auto[0]	auto[0]	auto[0]	168	1			T14	1		T32	1		T34	1
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T16	1		T33	2		T123	1
all_values[3]	auto[0]	auto[1]	auto[0]	136	1			T14	1		T16	1		T32	3
all_values[3]	auto[0]	auto[1]	auto[1]	83	1			T14	2		T32	1		T34	1
all_values[3]	auto[1]	auto[0]	auto[1]	177	1			T16	2		T32	3		T93	4
all_values[3]	auto[1]	auto[1]	auto[1]	154	1			T14	3		T93	1		T33	1
all_values[4]	auto[0]	auto[0]	auto[0]	172	1			T14	2		T16	3		T32	1
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T32	2		T35	2		T128	1
all_values[4]	auto[0]	auto[1]	auto[0]	148	1			T14	2		T16	1		T93	1
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T32	1		T93	2		T129	2
all_values[4]	auto[1]	auto[0]	auto[1]	150	1			T14	1		T32	2		T93	1
all_values[4]	auto[1]	auto[1]	auto[1]	178	1			T14	2		T32	2		T93	2
all_values[5]	auto[0]	auto[0]	auto[0]	175	1			T14	1		T16	3		T32	2
all_values[5]	auto[0]	auto[0]	auto[1]	92	1			T14	1		T93	2		T34	2
all_values[5]	auto[0]	auto[1]	auto[0]	140	1			T32	2		T93	3		T33	1
all_values[5]	auto[0]	auto[1]	auto[1]	74	1			T14	3		T123	1		T129	2
all_values[5]	auto[1]	auto[0]	auto[1]	183	1			T14	1		T16	1		T32	2
all_values[5]	auto[1]	auto[1]	auto[1]	134	1			T14	1		T32	2		T93	1
all_values[6]	auto[0]	auto[0]	auto[0]	144	1			T16	1		T32	2		T93	2
all_values[6]	auto[0]	auto[0]	auto[1]	75	1			T16	2		T33	1		T35	2
all_values[6]	auto[0]	auto[1]	auto[0]	145	1			T32	1		T93	2		T33	1
all_values[6]	auto[0]	auto[1]	auto[1]	97	1			T14	2		T32	2		T93	1
all_values[6]	auto[1]	auto[0]	auto[1]	180	1			T14	3		T16	1		T32	2
all_values[6]	auto[1]	auto[1]	auto[1]	157	1			T14	2		T32	1		T93	1
all_values[7]	auto[0]	auto[0]	auto[0]	193	1			T14	1		T16	1		T32	3
all_values[7]	auto[0]	auto[0]	auto[1]	71	1			T32	1		T93	2		T33	1
all_values[7]	auto[0]	auto[1]	auto[0]	150	1			T14	2		T32	1		T93	1
all_values[7]	auto[0]	auto[1]	auto[1]	60	1			T14	1		T34	1		T35	1
all_values[7]	auto[1]	auto[0]	auto[1]	195	1			T14	2		T16	3		T32	2
all_values[7]	auto[1]	auto[1]	auto[1]	129	1			T14	1		T32	1		T34	2
all_values[8]	auto[0]	auto[0]	auto[1]	253	1			T14	3		T33	1		T34	1
all_values[8]	auto[0]	auto[1]	auto[1]	198	1			T14	1		T16	1		T32	4
all_values[8]	auto[1]	auto[0]	auto[1]	188	1			T16	3		T32	2		T93	1
all_values[8]	auto[1]	auto[1]	auto[1]	159	1			T14	3		T32	2		T93	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal