Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total test records in report: 1315
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T1257 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2726535459 Jul 16 05:10:29 PM PDT 24 Jul 16 05:10:31 PM PDT 24 90564686 ps
T1258 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2000670831 Jul 16 05:10:23 PM PDT 24 Jul 16 05:10:25 PM PDT 24 18320617 ps
T1259 /workspace/coverage/cover_reg_top/3.uart_tl_errors.1240853436 Jul 16 05:09:52 PM PDT 24 Jul 16 05:09:55 PM PDT 24 147149956 ps
T1260 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2379568760 Jul 16 05:10:14 PM PDT 24 Jul 16 05:10:15 PM PDT 24 23185650 ps
T1261 /workspace/coverage/cover_reg_top/6.uart_csr_rw.893404815 Jul 16 05:09:52 PM PDT 24 Jul 16 05:09:53 PM PDT 24 59649390 ps
T70 /workspace/coverage/cover_reg_top/18.uart_csr_rw.1128248009 Jul 16 05:10:23 PM PDT 24 Jul 16 05:10:25 PM PDT 24 16300412 ps
T71 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1066816012 Jul 16 05:10:18 PM PDT 24 Jul 16 05:10:19 PM PDT 24 21817452 ps
T1262 /workspace/coverage/cover_reg_top/19.uart_csr_rw.3840395807 Jul 16 05:10:09 PM PDT 24 Jul 16 05:10:11 PM PDT 24 31151170 ps
T72 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.288013249 Jul 16 05:10:14 PM PDT 24 Jul 16 05:10:16 PM PDT 24 76246786 ps
T1263 /workspace/coverage/cover_reg_top/4.uart_intr_test.3694259248 Jul 16 05:09:56 PM PDT 24 Jul 16 05:09:57 PM PDT 24 39658325 ps
T1264 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1002197795 Jul 16 05:10:19 PM PDT 24 Jul 16 05:10:20 PM PDT 24 16186045 ps
T1265 /workspace/coverage/cover_reg_top/36.uart_intr_test.2878324096 Jul 16 05:10:20 PM PDT 24 Jul 16 05:10:21 PM PDT 24 21610732 ps
T1266 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3254581959 Jul 16 05:10:10 PM PDT 24 Jul 16 05:10:12 PM PDT 24 19426562 ps
T1267 /workspace/coverage/cover_reg_top/4.uart_tl_errors.718396235 Jul 16 05:09:53 PM PDT 24 Jul 16 05:09:57 PM PDT 24 218161534 ps
T103 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.451102609 Jul 16 05:09:49 PM PDT 24 Jul 16 05:09:51 PM PDT 24 95232843 ps
T1268 /workspace/coverage/cover_reg_top/1.uart_intr_test.3955862445 Jul 16 05:10:19 PM PDT 24 Jul 16 05:10:20 PM PDT 24 127788497 ps
T1269 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.131668208 Jul 16 05:10:09 PM PDT 24 Jul 16 05:10:11 PM PDT 24 27517158 ps
T1270 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1221903119 Jul 16 05:09:39 PM PDT 24 Jul 16 05:09:40 PM PDT 24 183617382 ps
T1271 /workspace/coverage/cover_reg_top/23.uart_intr_test.3276568324 Jul 16 05:10:25 PM PDT 24 Jul 16 05:10:27 PM PDT 24 43377930 ps
T1272 /workspace/coverage/cover_reg_top/2.uart_intr_test.1623190993 Jul 16 05:10:06 PM PDT 24 Jul 16 05:10:07 PM PDT 24 14674593 ps
T1273 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3158543966 Jul 16 05:10:09 PM PDT 24 Jul 16 05:10:11 PM PDT 24 39645478 ps
T1274 /workspace/coverage/cover_reg_top/13.uart_intr_test.98758922 Jul 16 05:10:22 PM PDT 24 Jul 16 05:10:23 PM PDT 24 28351298 ps
T1275 /workspace/coverage/cover_reg_top/13.uart_csr_rw.3115439828 Jul 16 05:10:07 PM PDT 24 Jul 16 05:10:09 PM PDT 24 17408362 ps
T1276 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3521473610 Jul 16 05:10:19 PM PDT 24 Jul 16 05:10:20 PM PDT 24 26893896 ps
T1277 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3005535355 Jul 16 05:09:54 PM PDT 24 Jul 16 05:09:55 PM PDT 24 145558475 ps
T1278 /workspace/coverage/cover_reg_top/24.uart_intr_test.2227758203 Jul 16 05:10:25 PM PDT 24 Jul 16 05:10:27 PM PDT 24 64995509 ps
T1279 /workspace/coverage/cover_reg_top/39.uart_intr_test.3928754124 Jul 16 05:10:23 PM PDT 24 Jul 16 05:10:24 PM PDT 24 25036477 ps
T1280 /workspace/coverage/cover_reg_top/0.uart_intr_test.4106217990 Jul 16 05:09:54 PM PDT 24 Jul 16 05:09:56 PM PDT 24 13554905 ps
T130 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4254325519 Jul 16 05:10:19 PM PDT 24 Jul 16 05:10:21 PM PDT 24 131014866 ps
T1281 /workspace/coverage/cover_reg_top/48.uart_intr_test.1922349988 Jul 16 05:10:26 PM PDT 24 Jul 16 05:10:28 PM PDT 24 13079234 ps
T1282 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4153296840 Jul 16 05:10:13 PM PDT 24 Jul 16 05:10:14 PM PDT 24 25823490 ps
T1283 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.883601491 Jul 16 05:10:17 PM PDT 24 Jul 16 05:10:20 PM PDT 24 214012756 ps
T1284 /workspace/coverage/cover_reg_top/30.uart_intr_test.115908017 Jul 16 05:10:28 PM PDT 24 Jul 16 05:10:30 PM PDT 24 15571786 ps
T1285 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1305612830 Jul 16 05:09:54 PM PDT 24 Jul 16 05:09:57 PM PDT 24 122877388 ps
T1286 /workspace/coverage/cover_reg_top/42.uart_intr_test.3295185722 Jul 16 05:10:21 PM PDT 24 Jul 16 05:10:22 PM PDT 24 45393405 ps
T1287 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3224591527 Jul 16 05:09:52 PM PDT 24 Jul 16 05:09:55 PM PDT 24 319299187 ps
T1288 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2926701630 Jul 16 05:09:45 PM PDT 24 Jul 16 05:09:46 PM PDT 24 28490450 ps
T1289 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2071899544 Jul 16 05:10:08 PM PDT 24 Jul 16 05:10:10 PM PDT 24 41050122 ps
T1290 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1663300280 Jul 16 05:10:05 PM PDT 24 Jul 16 05:10:06 PM PDT 24 40615798 ps
T1291 /workspace/coverage/cover_reg_top/12.uart_intr_test.836401584 Jul 16 05:10:09 PM PDT 24 Jul 16 05:10:11 PM PDT 24 47781577 ps
T1292 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1403041010 Jul 16 05:09:53 PM PDT 24 Jul 16 05:09:55 PM PDT 24 47332105 ps
T1293 /workspace/coverage/cover_reg_top/46.uart_intr_test.3529821540 Jul 16 05:10:23 PM PDT 24 Jul 16 05:10:25 PM PDT 24 45908135 ps
T1294 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3557721445 Jul 16 05:10:14 PM PDT 24 Jul 16 05:10:16 PM PDT 24 26675552 ps
T1295 /workspace/coverage/cover_reg_top/18.uart_intr_test.3972099950 Jul 16 05:10:30 PM PDT 24 Jul 16 05:10:31 PM PDT 24 195018936 ps
T1296 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1303736976 Jul 16 05:09:50 PM PDT 24 Jul 16 05:09:51 PM PDT 24 35918530 ps
T1297 /workspace/coverage/cover_reg_top/11.uart_intr_test.3375960400 Jul 16 05:10:08 PM PDT 24 Jul 16 05:10:10 PM PDT 24 44987292 ps
T1298 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2795686292 Jul 16 05:10:10 PM PDT 24 Jul 16 05:10:12 PM PDT 24 24642279 ps
T1299 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3026280784 Jul 16 05:10:04 PM PDT 24 Jul 16 05:10:05 PM PDT 24 268913661 ps
T1300 /workspace/coverage/cover_reg_top/11.uart_csr_rw.106897845 Jul 16 05:10:07 PM PDT 24 Jul 16 05:10:09 PM PDT 24 41147786 ps
T1301 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3947428000 Jul 16 05:10:07 PM PDT 24 Jul 16 05:10:09 PM PDT 24 19721158 ps
T1302 /workspace/coverage/cover_reg_top/35.uart_intr_test.1231981785 Jul 16 05:10:23 PM PDT 24 Jul 16 05:10:24 PM PDT 24 17559552 ps
T1303 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.216033515 Jul 16 05:10:09 PM PDT 24 Jul 16 05:10:11 PM PDT 24 325354287 ps
T1304 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.44188577 Jul 16 05:09:54 PM PDT 24 Jul 16 05:09:56 PM PDT 24 36415926 ps
T1305 /workspace/coverage/cover_reg_top/32.uart_intr_test.3487022775 Jul 16 05:10:21 PM PDT 24 Jul 16 05:10:23 PM PDT 24 19155084 ps
T1306 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.8231590 Jul 16 05:10:29 PM PDT 24 Jul 16 05:10:31 PM PDT 24 60696831 ps
T1307 /workspace/coverage/cover_reg_top/20.uart_intr_test.1157500671 Jul 16 05:10:24 PM PDT 24 Jul 16 05:10:26 PM PDT 24 19605803 ps
T1308 /workspace/coverage/cover_reg_top/26.uart_intr_test.1423654202 Jul 16 05:10:22 PM PDT 24 Jul 16 05:10:23 PM PDT 24 59389801 ps
T1309 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.247651424 Jul 16 05:10:14 PM PDT 24 Jul 16 05:10:15 PM PDT 24 104335585 ps
T1310 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.132053177 Jul 16 05:10:17 PM PDT 24 Jul 16 05:10:18 PM PDT 24 49079225 ps
T1311 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2402720374 Jul 16 05:10:30 PM PDT 24 Jul 16 05:10:31 PM PDT 24 161980104 ps
T1312 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.143197960 Jul 16 05:10:16 PM PDT 24 Jul 16 05:10:17 PM PDT 24 75315425 ps
T1313 /workspace/coverage/cover_reg_top/5.uart_tl_errors.681151249 Jul 16 05:09:53 PM PDT 24 Jul 16 05:09:56 PM PDT 24 506737841 ps
T1314 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1882359441 Jul 16 05:10:14 PM PDT 24 Jul 16 05:10:16 PM PDT 24 16510682 ps
T73 /workspace/coverage/cover_reg_top/9.uart_csr_rw.1894459071 Jul 16 05:10:23 PM PDT 24 Jul 16 05:10:25 PM PDT 24 32703641 ps
T1315 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1068026632 Jul 16 05:09:52 PM PDT 24 Jul 16 05:09:54 PM PDT 24 67193942 ps

Test location /workspace/coverage/default/22.uart_tx_rx.3805977612
Short name T5
Test name
Test status
Simulation time 61598427478 ps
CPU time 54.08 seconds
Started Jul 16 04:57:13 PM PDT 24
Finished Jul 16 04:58:09 PM PDT 24
Peak memory 199864 kb
Host smart-a5b57d09-5308-40c0-8450-e4d981ff2925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805977612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3805977612
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3240367799
Short name T32
Test name
Test status
Simulation time 235367715199 ps
CPU time 743.71 seconds
Started Jul 16 04:59:07 PM PDT 24
Finished Jul 16 05:11:32 PM PDT 24
Peak memory 216324 kb
Host smart-c7673e24-7402-4402-bb32-1917aed446e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240367799 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3240367799
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.1985673605
Short name T46
Test name
Test status
Simulation time 263048956879 ps
CPU time 257.91 seconds
Started Jul 16 04:56:22 PM PDT 24
Finished Jul 16 05:00:41 PM PDT 24
Peak memory 199728 kb
Host smart-00584d44-aa55-409f-908d-302b824fbdd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985673605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1985673605
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.809481058
Short name T56
Test name
Test status
Simulation time 438342218940 ps
CPU time 825.66 seconds
Started Jul 16 04:58:45 PM PDT 24
Finished Jul 16 05:12:31 PM PDT 24
Peak memory 224612 kb
Host smart-47fb0e6f-4cc0-4221-8ed7-8eeb09ce21ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809481058 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.809481058
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3378374104
Short name T31
Test name
Test status
Simulation time 141667824538 ps
CPU time 1447.15 seconds
Started Jul 16 04:59:23 PM PDT 24
Finished Jul 16 05:23:31 PM PDT 24
Peak memory 224696 kb
Host smart-42370e6e-cfc9-4bdd-b665-a43b69f8106a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378374104 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3378374104
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all.4153255292
Short name T116
Test name
Test status
Simulation time 311641719116 ps
CPU time 1167.17 seconds
Started Jul 16 04:58:22 PM PDT 24
Finished Jul 16 05:17:50 PM PDT 24
Peak memory 208212 kb
Host smart-a1162f55-5691-482a-a112-6da1e5920ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153255292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.4153255292
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2228353496
Short name T11
Test name
Test status
Simulation time 78944965085 ps
CPU time 31.19 seconds
Started Jul 16 04:57:09 PM PDT 24
Finished Jul 16 04:57:41 PM PDT 24
Peak memory 199816 kb
Host smart-55b1b10c-5454-41ff-9afe-e472af4b6715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228353496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2228353496
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.452324764
Short name T12
Test name
Test status
Simulation time 37885550 ps
CPU time 0.79 seconds
Started Jul 16 04:56:29 PM PDT 24
Finished Jul 16 04:56:31 PM PDT 24
Peak memory 218192 kb
Host smart-23fc75d0-24cc-4821-8c36-78c6f674cc55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452324764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.452324764
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.945387172
Short name T35
Test name
Test status
Simulation time 289354460254 ps
CPU time 517.21 seconds
Started Jul 16 04:58:56 PM PDT 24
Finished Jul 16 05:07:34 PM PDT 24
Peak memory 216476 kb
Host smart-40b7cb3a-7dbc-408c-ad31-f17336853c1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945387172 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.945387172
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2696878560
Short name T194
Test name
Test status
Simulation time 316677060751 ps
CPU time 1553.93 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 05:23:06 PM PDT 24
Peak memory 224664 kb
Host smart-4f55a30d-259e-4c2f-8438-9f667f16c876
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696878560 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2696878560
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2985887369
Short name T9
Test name
Test status
Simulation time 178835111858 ps
CPU time 250.86 seconds
Started Jul 16 05:00:06 PM PDT 24
Finished Jul 16 05:04:17 PM PDT 24
Peak memory 199784 kb
Host smart-b02865dd-bdcf-4a84-b710-456452b32d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985887369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2985887369
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.4207484051
Short name T34
Test name
Test status
Simulation time 190341585031 ps
CPU time 264.12 seconds
Started Jul 16 04:59:29 PM PDT 24
Finished Jul 16 05:03:53 PM PDT 24
Peak memory 216472 kb
Host smart-cc589a4d-0f9a-47c8-953e-b4bb84e31d61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207484051 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.4207484051
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1299043585
Short name T36
Test name
Test status
Simulation time 94771287059 ps
CPU time 844.37 seconds
Started Jul 16 04:59:06 PM PDT 24
Finished Jul 16 05:13:11 PM PDT 24
Peak memory 216488 kb
Host smart-ac8762ae-c761-46e5-bb1d-ef73a75f6887
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299043585 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1299043585
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3124083458
Short name T137
Test name
Test status
Simulation time 85511307580 ps
CPU time 163.4 seconds
Started Jul 16 04:59:22 PM PDT 24
Finished Jul 16 05:02:06 PM PDT 24
Peak memory 199532 kb
Host smart-8f0df5cf-faa4-48f5-b2f8-a2fed04afae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124083458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3124083458
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3743402168
Short name T16
Test name
Test status
Simulation time 58179675067 ps
CPU time 984.16 seconds
Started Jul 16 04:57:15 PM PDT 24
Finished Jul 16 05:13:41 PM PDT 24
Peak memory 216384 kb
Host smart-27ad952e-bcc4-4560-9870-4a0d61a3a3f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743402168 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3743402168
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2867008350
Short name T191
Test name
Test status
Simulation time 156341222272 ps
CPU time 239.91 seconds
Started Jul 16 04:59:24 PM PDT 24
Finished Jul 16 05:03:25 PM PDT 24
Peak memory 199840 kb
Host smart-c667eae2-56c0-4287-8dbe-6e5a5ae1ff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867008350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2867008350
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.4026332216
Short name T97
Test name
Test status
Simulation time 327862521 ps
CPU time 1.41 seconds
Started Jul 16 05:09:53 PM PDT 24
Finished Jul 16 05:09:56 PM PDT 24
Peak memory 199996 kb
Host smart-fe1c0776-d137-44b1-9a69-09d2c63a8ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026332216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.4026332216
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2806467990
Short name T52
Test name
Test status
Simulation time 370200546103 ps
CPU time 48.77 seconds
Started Jul 16 05:00:18 PM PDT 24
Finished Jul 16 05:01:08 PM PDT 24
Peak memory 199648 kb
Host smart-84d0e0b1-91ec-4100-bc82-4fa583328b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806467990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2806467990
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2293949149
Short name T178
Test name
Test status
Simulation time 54672561553 ps
CPU time 22.17 seconds
Started Jul 16 04:59:42 PM PDT 24
Finished Jul 16 05:00:05 PM PDT 24
Peak memory 199844 kb
Host smart-6802b668-e4d3-438b-833e-48ebf94803db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293949149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2293949149
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2632719564
Short name T28
Test name
Test status
Simulation time 22012995 ps
CPU time 0.56 seconds
Started Jul 16 04:57:11 PM PDT 24
Finished Jul 16 04:57:13 PM PDT 24
Peak memory 195044 kb
Host smart-2defb53d-8f88-4f0b-b745-a35724271e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632719564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2632719564
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2504625237
Short name T125
Test name
Test status
Simulation time 52228560771 ps
CPU time 86.02 seconds
Started Jul 16 04:59:42 PM PDT 24
Finished Jul 16 05:01:09 PM PDT 24
Peak memory 199640 kb
Host smart-be9d2068-56aa-4d4c-9b13-6484bcae70a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504625237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2504625237
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.361709701
Short name T271
Test name
Test status
Simulation time 831518776977 ps
CPU time 730.68 seconds
Started Jul 16 04:59:20 PM PDT 24
Finished Jul 16 05:11:32 PM PDT 24
Peak memory 228216 kb
Host smart-a26acaeb-fcc7-4639-940b-44ec769e1e57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361709701 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.361709701
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2738982184
Short name T44
Test name
Test status
Simulation time 98945124450 ps
CPU time 151.31 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:03:04 PM PDT 24
Peak memory 200076 kb
Host smart-0085e9e1-405d-4227-a882-3b2e655f9658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738982184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2738982184
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2323437740
Short name T53
Test name
Test status
Simulation time 213465795820 ps
CPU time 88.18 seconds
Started Jul 16 04:59:55 PM PDT 24
Finished Jul 16 05:01:24 PM PDT 24
Peak memory 199656 kb
Host smart-231f6372-2b46-428b-b11d-fc88e2fbf8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323437740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2323437740
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3198163628
Short name T161
Test name
Test status
Simulation time 279959683075 ps
CPU time 413.7 seconds
Started Jul 16 04:58:00 PM PDT 24
Finished Jul 16 05:04:55 PM PDT 24
Peak memory 209488 kb
Host smart-b167fba2-f76c-4552-aea0-8bb4a3b982ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198163628 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3198163628
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.359562005
Short name T64
Test name
Test status
Simulation time 38307930 ps
CPU time 0.85 seconds
Started Jul 16 05:09:45 PM PDT 24
Finished Jul 16 05:09:46 PM PDT 24
Peak memory 197020 kb
Host smart-e0361ede-245d-440a-868e-179de9e487b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359562005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.359562005
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3188196953
Short name T89
Test name
Test status
Simulation time 74928253 ps
CPU time 0.59 seconds
Started Jul 16 05:10:11 PM PDT 24
Finished Jul 16 05:10:12 PM PDT 24
Peak memory 196112 kb
Host smart-a48dc40d-de1f-4a9a-bc00-4fabf37322af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188196953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3188196953
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2416492932
Short name T117
Test name
Test status
Simulation time 32095401374 ps
CPU time 31.84 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:57:19 PM PDT 24
Peak memory 199736 kb
Host smart-efe59660-a18d-430e-85b7-6b3f6641ead3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416492932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2416492932
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.332795818
Short name T6
Test name
Test status
Simulation time 129630778368 ps
CPU time 48.63 seconds
Started Jul 16 04:59:51 PM PDT 24
Finished Jul 16 05:00:40 PM PDT 24
Peak memory 199752 kb
Host smart-2e5d8a8a-ceb6-4269-8dde-93a04bbf019e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332795818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.332795818
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2362853143
Short name T201
Test name
Test status
Simulation time 129990129597 ps
CPU time 143.1 seconds
Started Jul 16 04:59:51 PM PDT 24
Finished Jul 16 05:02:14 PM PDT 24
Peak memory 199688 kb
Host smart-2e8e2b61-2dc6-445d-aa75-f70ac25fa0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362853143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2362853143
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1000257880
Short name T149
Test name
Test status
Simulation time 48598105425 ps
CPU time 66.42 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 04:59:09 PM PDT 24
Peak memory 199660 kb
Host smart-29befa4d-4f9a-4990-adb3-0df028c30eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000257880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1000257880
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1240604997
Short name T133
Test name
Test status
Simulation time 54720301466 ps
CPU time 44.62 seconds
Started Jul 16 04:59:33 PM PDT 24
Finished Jul 16 05:00:18 PM PDT 24
Peak memory 199784 kb
Host smart-80420b95-f17f-48e5-9467-1d2edf8a9fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240604997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1240604997
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3565976249
Short name T620
Test name
Test status
Simulation time 30134910861 ps
CPU time 49.33 seconds
Started Jul 16 05:00:07 PM PDT 24
Finished Jul 16 05:00:57 PM PDT 24
Peak memory 199940 kb
Host smart-5307b064-9209-41e2-8234-c0b0c855de65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565976249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3565976249
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2970179324
Short name T153
Test name
Test status
Simulation time 61942261196 ps
CPU time 108.91 seconds
Started Jul 16 04:59:57 PM PDT 24
Finished Jul 16 05:01:46 PM PDT 24
Peak memory 200084 kb
Host smart-7c9da1b8-c4e0-424d-a92b-2d248e5c6bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970179324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2970179324
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1533831127
Short name T100
Test name
Test status
Simulation time 163965084 ps
CPU time 1.29 seconds
Started Jul 16 05:10:10 PM PDT 24
Finished Jul 16 05:10:12 PM PDT 24
Peak memory 200100 kb
Host smart-c5cd9083-b799-4d6b-9d26-e09da0ac93b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533831127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1533831127
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2994967411
Short name T590
Test name
Test status
Simulation time 154638723268 ps
CPU time 127.26 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 05:00:36 PM PDT 24
Peak memory 199840 kb
Host smart-1e09cff8-2168-41af-97e6-71cca766775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994967411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2994967411
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3848013791
Short name T270
Test name
Test status
Simulation time 140250938577 ps
CPU time 139.76 seconds
Started Jul 16 04:57:16 PM PDT 24
Finished Jul 16 04:59:37 PM PDT 24
Peak memory 200104 kb
Host smart-c28333dc-0df6-4062-b664-820c4dbca090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848013791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3848013791
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2199054379
Short name T168
Test name
Test status
Simulation time 32954944874 ps
CPU time 29.06 seconds
Started Jul 16 04:59:41 PM PDT 24
Finished Jul 16 05:00:11 PM PDT 24
Peak memory 199796 kb
Host smart-6962cf0d-4116-41e8-bd19-a2e45ddd1d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199054379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2199054379
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1297409078
Short name T177
Test name
Test status
Simulation time 57634524567 ps
CPU time 94.94 seconds
Started Jul 16 04:59:55 PM PDT 24
Finished Jul 16 05:01:31 PM PDT 24
Peak memory 199760 kb
Host smart-5d8774e0-0cb2-4d8c-922c-d0e4cfc5a68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297409078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1297409078
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2736258581
Short name T233
Test name
Test status
Simulation time 34901876220 ps
CPU time 20.45 seconds
Started Jul 16 05:00:09 PM PDT 24
Finished Jul 16 05:00:30 PM PDT 24
Peak memory 199716 kb
Host smart-1c7c3954-ff88-45ab-a0d2-57d88f4b49ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736258581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2736258581
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.798574806
Short name T106
Test name
Test status
Simulation time 174038756857 ps
CPU time 794.97 seconds
Started Jul 16 04:58:00 PM PDT 24
Finished Jul 16 05:11:16 PM PDT 24
Peak memory 224772 kb
Host smart-c0cde2de-0347-4b97-8962-937cf2c3e751
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798574806 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.798574806
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all.3039536856
Short name T311
Test name
Test status
Simulation time 216465727259 ps
CPU time 328.93 seconds
Started Jul 16 04:59:04 PM PDT 24
Finished Jul 16 05:04:34 PM PDT 24
Peak memory 208096 kb
Host smart-2b60124f-73ea-4535-879c-1a1482ae394e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039536856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3039536856
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1290007603
Short name T306
Test name
Test status
Simulation time 247232343850 ps
CPU time 34.34 seconds
Started Jul 16 04:59:41 PM PDT 24
Finished Jul 16 05:00:16 PM PDT 24
Peak memory 199808 kb
Host smart-929a852e-ff11-481c-801f-149a84a4baac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290007603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1290007603
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2274568328
Short name T40
Test name
Test status
Simulation time 120308754669 ps
CPU time 194.46 seconds
Started Jul 16 04:59:41 PM PDT 24
Finished Jul 16 05:02:56 PM PDT 24
Peak memory 199720 kb
Host smart-4b428644-cd59-4855-824c-39551b76185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274568328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2274568328
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.61838297
Short name T198
Test name
Test status
Simulation time 184908666240 ps
CPU time 77.99 seconds
Started Jul 16 05:00:08 PM PDT 24
Finished Jul 16 05:01:27 PM PDT 24
Peak memory 199652 kb
Host smart-da6caa04-0765-471e-bbfd-71c94c67cb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61838297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.61838297
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.607122710
Short name T230
Test name
Test status
Simulation time 24530102857 ps
CPU time 42.14 seconds
Started Jul 16 04:59:18 PM PDT 24
Finished Jul 16 05:00:01 PM PDT 24
Peak memory 199704 kb
Host smart-817892ed-cce6-4f89-9b50-8ae1adf996d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607122710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.607122710
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.207271367
Short name T890
Test name
Test status
Simulation time 50109976757 ps
CPU time 70.6 seconds
Started Jul 16 04:59:40 PM PDT 24
Finished Jul 16 05:00:51 PM PDT 24
Peak memory 199756 kb
Host smart-10963692-239d-4573-83b2-c4b48e51208c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207271367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.207271367
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1802512287
Short name T911
Test name
Test status
Simulation time 23407882859 ps
CPU time 34.54 seconds
Started Jul 16 05:00:09 PM PDT 24
Finished Jul 16 05:00:44 PM PDT 24
Peak memory 199764 kb
Host smart-758cbd31-c6cd-480f-bb0a-245388a610d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802512287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1802512287
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.825137764
Short name T236
Test name
Test status
Simulation time 99762298585 ps
CPU time 301.65 seconds
Started Jul 16 05:00:08 PM PDT 24
Finished Jul 16 05:05:10 PM PDT 24
Peak memory 199796 kb
Host smart-ff2d6085-3489-4350-8d99-6c2c6e18385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825137764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.825137764
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.255027299
Short name T211
Test name
Test status
Simulation time 168533272302 ps
CPU time 185.46 seconds
Started Jul 16 05:00:18 PM PDT 24
Finished Jul 16 05:03:24 PM PDT 24
Peak memory 199748 kb
Host smart-cb4991c5-9d4e-44b5-9ad0-5aafac4207a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255027299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.255027299
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3493681238
Short name T192
Test name
Test status
Simulation time 27296246065 ps
CPU time 46.28 seconds
Started Jul 16 04:56:54 PM PDT 24
Finished Jul 16 04:57:41 PM PDT 24
Peak memory 199924 kb
Host smart-df3dc90e-7b13-4419-9cf2-4dd60d48d417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493681238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3493681238
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2503299901
Short name T196
Test name
Test status
Simulation time 32214112760 ps
CPU time 38.23 seconds
Started Jul 16 04:59:34 PM PDT 24
Finished Jul 16 05:00:13 PM PDT 24
Peak memory 199820 kb
Host smart-9e0530a7-043d-4180-a949-b8db446e70e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503299901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2503299901
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3079968444
Short name T55
Test name
Test status
Simulation time 62887896640 ps
CPU time 30.16 seconds
Started Jul 16 04:59:29 PM PDT 24
Finished Jul 16 05:00:00 PM PDT 24
Peak memory 199780 kb
Host smart-7f9c076b-8b08-4348-a5c5-0a0ad9eb8b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079968444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3079968444
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.379018576
Short name T1080
Test name
Test status
Simulation time 20800411991 ps
CPU time 31.86 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:57:23 PM PDT 24
Peak memory 199760 kb
Host smart-02c142bd-4311-42cb-b8de-89e086a3dbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379018576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.379018576
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2987502527
Short name T232
Test name
Test status
Simulation time 152369810349 ps
CPU time 75.9 seconds
Started Jul 16 04:59:41 PM PDT 24
Finished Jul 16 05:00:57 PM PDT 24
Peak memory 199504 kb
Host smart-c1ed1f11-4344-438c-8d51-05fd033f957c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987502527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2987502527
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1950972459
Short name T247
Test name
Test status
Simulation time 63239196467 ps
CPU time 12.07 seconds
Started Jul 16 04:59:41 PM PDT 24
Finished Jul 16 04:59:54 PM PDT 24
Peak memory 199856 kb
Host smart-e189f83b-cbab-44f0-adf6-321d6f3c1b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950972459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1950972459
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2858505173
Short name T244
Test name
Test status
Simulation time 142070131382 ps
CPU time 186.16 seconds
Started Jul 16 04:59:52 PM PDT 24
Finished Jul 16 05:02:58 PM PDT 24
Peak memory 199648 kb
Host smart-c8fe94bd-507e-46e6-80c8-f2563c6d20b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858505173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2858505173
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2193096715
Short name T159
Test name
Test status
Simulation time 109698143135 ps
CPU time 144.2 seconds
Started Jul 16 04:59:53 PM PDT 24
Finished Jul 16 05:02:18 PM PDT 24
Peak memory 199804 kb
Host smart-12e61a98-905a-48e9-b6fc-d66a7811aeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193096715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2193096715
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3964320139
Short name T235
Test name
Test status
Simulation time 102183176477 ps
CPU time 271.32 seconds
Started Jul 16 04:59:53 PM PDT 24
Finished Jul 16 05:04:24 PM PDT 24
Peak memory 199840 kb
Host smart-52d6f44c-b856-4134-92b8-26d19c867032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964320139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3964320139
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_noise_filter.4024313093
Short name T394
Test name
Test status
Simulation time 187755709510 ps
CPU time 69.54 seconds
Started Jul 16 04:57:08 PM PDT 24
Finished Jul 16 04:58:18 PM PDT 24
Peak memory 208084 kb
Host smart-8d0d7744-b6c7-4dda-82d1-04286bd04d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024313093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.4024313093
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1428377016
Short name T229
Test name
Test status
Simulation time 77603561498 ps
CPU time 29.91 seconds
Started Jul 16 04:59:53 PM PDT 24
Finished Jul 16 05:00:23 PM PDT 24
Peak memory 199748 kb
Host smart-ac38c177-899d-4f57-9d94-215dd1e0c32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428377016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1428377016
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3986489324
Short name T240
Test name
Test status
Simulation time 159433115824 ps
CPU time 72.38 seconds
Started Jul 16 04:59:58 PM PDT 24
Finished Jul 16 05:01:10 PM PDT 24
Peak memory 200084 kb
Host smart-dab3cc44-f7ea-4af6-8f34-38a097e084c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986489324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3986489324
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1877198672
Short name T250
Test name
Test status
Simulation time 63715132911 ps
CPU time 31.5 seconds
Started Jul 16 05:00:07 PM PDT 24
Finished Jul 16 05:00:39 PM PDT 24
Peak memory 199808 kb
Host smart-9a9a894c-d158-4306-afa8-61ce33d677cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877198672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1877198672
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1858614289
Short name T210
Test name
Test status
Simulation time 117095647054 ps
CPU time 177.84 seconds
Started Jul 16 05:00:06 PM PDT 24
Finished Jul 16 05:03:04 PM PDT 24
Peak memory 199856 kb
Host smart-2192d375-8b80-4836-b861-5d9541b2d115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858614289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1858614289
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2168691397
Short name T234
Test name
Test status
Simulation time 22011610631 ps
CPU time 23.6 seconds
Started Jul 16 05:00:07 PM PDT 24
Finished Jul 16 05:00:32 PM PDT 24
Peak memory 199680 kb
Host smart-db5c2683-5574-474f-9bcd-bdabe6ae423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168691397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2168691397
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1771518121
Short name T245
Test name
Test status
Simulation time 125532182327 ps
CPU time 179.74 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:03:33 PM PDT 24
Peak memory 199748 kb
Host smart-9f10619d-78f2-40f1-b88c-0c6d8999cb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771518121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1771518121
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1557842859
Short name T249
Test name
Test status
Simulation time 66202128844 ps
CPU time 25.84 seconds
Started Jul 16 05:00:31 PM PDT 24
Finished Jul 16 05:00:58 PM PDT 24
Peak memory 199756 kb
Host smart-6df9f12c-1a46-410e-9d3b-b2ec3a3ec339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557842859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1557842859
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.158872404
Short name T221
Test name
Test status
Simulation time 599333644168 ps
CPU time 1657.7 seconds
Started Jul 16 04:56:26 PM PDT 24
Finished Jul 16 05:24:05 PM PDT 24
Peak memory 226532 kb
Host smart-53572322-71af-476b-9a04-827d7283c49b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158872404 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.158872404
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3435585884
Short name T248
Test name
Test status
Simulation time 25114775089 ps
CPU time 19.7 seconds
Started Jul 16 04:59:20 PM PDT 24
Finished Jul 16 04:59:41 PM PDT 24
Peak memory 199856 kb
Host smart-916a7d10-7418-4ac4-beb5-2fa47b254d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435585884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3435585884
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2179655711
Short name T3
Test name
Test status
Simulation time 20438592294 ps
CPU time 10.46 seconds
Started Jul 16 04:59:24 PM PDT 24
Finished Jul 16 04:59:35 PM PDT 24
Peak memory 199428 kb
Host smart-aa833557-9515-4eff-b29d-650dc69d04d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179655711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2179655711
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1328179334
Short name T239
Test name
Test status
Simulation time 64509226500 ps
CPU time 105.95 seconds
Started Jul 16 04:59:24 PM PDT 24
Finished Jul 16 05:01:10 PM PDT 24
Peak memory 199728 kb
Host smart-793ed515-9646-4fbb-bbd1-2ba64defe6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328179334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1328179334
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.4035133635
Short name T242
Test name
Test status
Simulation time 19109455404 ps
CPU time 22.45 seconds
Started Jul 16 04:59:41 PM PDT 24
Finished Jul 16 05:00:04 PM PDT 24
Peak memory 199740 kb
Host smart-beece006-4099-4d3a-90dc-824ec044e7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035133635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.4035133635
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1305612830
Short name T1285
Test name
Test status
Simulation time 122877388 ps
CPU time 1.44 seconds
Started Jul 16 05:09:54 PM PDT 24
Finished Jul 16 05:09:57 PM PDT 24
Peak memory 198776 kb
Host smart-7a2e8666-89ba-4eb8-b6c3-297bb2c5a2d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305612830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1305612830
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3947428000
Short name T1301
Test name
Test status
Simulation time 19721158 ps
CPU time 0.59 seconds
Started Jul 16 05:10:07 PM PDT 24
Finished Jul 16 05:10:09 PM PDT 24
Peak memory 196132 kb
Host smart-43206ded-3a2d-4712-b44a-dae6d18652f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947428000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3947428000
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2906213685
Short name T1238
Test name
Test status
Simulation time 21091499 ps
CPU time 0.92 seconds
Started Jul 16 05:09:43 PM PDT 24
Finished Jul 16 05:09:44 PM PDT 24
Peak memory 200528 kb
Host smart-81164563-b247-4405-b517-be1e04d62d7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906213685 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2906213685
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.351588632
Short name T1232
Test name
Test status
Simulation time 17001187 ps
CPU time 0.64 seconds
Started Jul 16 05:09:54 PM PDT 24
Finished Jul 16 05:09:56 PM PDT 24
Peak memory 196112 kb
Host smart-a5407b24-36c8-4d93-9c6f-d6f799a7dacb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351588632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.351588632
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.4106217990
Short name T1280
Test name
Test status
Simulation time 13554905 ps
CPU time 0.63 seconds
Started Jul 16 05:09:54 PM PDT 24
Finished Jul 16 05:09:56 PM PDT 24
Peak memory 195064 kb
Host smart-36dc9c9e-a808-4218-8cfa-0a230eb151b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106217990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.4106217990
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2926701630
Short name T1288
Test name
Test status
Simulation time 28490450 ps
CPU time 0.76 seconds
Started Jul 16 05:09:45 PM PDT 24
Finished Jul 16 05:09:46 PM PDT 24
Peak memory 197804 kb
Host smart-3f429bba-8623-4435-926a-4b66bf70f9ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926701630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2926701630
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2076510399
Short name T1202
Test name
Test status
Simulation time 80181476 ps
CPU time 2.17 seconds
Started Jul 16 05:09:54 PM PDT 24
Finished Jul 16 05:09:58 PM PDT 24
Peak memory 200768 kb
Host smart-d51745c9-4f93-4b38-9a7b-0ea99628be2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076510399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2076510399
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1221903119
Short name T1270
Test name
Test status
Simulation time 183617382 ps
CPU time 0.97 seconds
Started Jul 16 05:09:39 PM PDT 24
Finished Jul 16 05:09:40 PM PDT 24
Peak memory 199728 kb
Host smart-ad2a19c9-bb02-4445-9c81-94b04ac40abf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221903119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1221903119
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.143197960
Short name T1312
Test name
Test status
Simulation time 75315425 ps
CPU time 0.65 seconds
Started Jul 16 05:10:16 PM PDT 24
Finished Jul 16 05:10:17 PM PDT 24
Peak memory 196048 kb
Host smart-a27f7092-1fef-42eb-ad58-0fc01f1dfcf9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143197960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.143197960
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.883601491
Short name T1283
Test name
Test status
Simulation time 214012756 ps
CPU time 2.24 seconds
Started Jul 16 05:10:17 PM PDT 24
Finished Jul 16 05:10:20 PM PDT 24
Peak memory 197912 kb
Host smart-fb10b0ff-0553-49ca-ae27-8427ad30cce1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883601491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.883601491
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3004925239
Short name T65
Test name
Test status
Simulation time 1062046132 ps
CPU time 1 seconds
Started Jul 16 05:09:52 PM PDT 24
Finished Jul 16 05:09:55 PM PDT 24
Peak memory 196032 kb
Host smart-a3e56678-a76b-4e71-9667-50f23c6ad31d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004925239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3004925239
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.137158109
Short name T1227
Test name
Test status
Simulation time 104232346 ps
CPU time 0.84 seconds
Started Jul 16 05:09:51 PM PDT 24
Finished Jul 16 05:09:53 PM PDT 24
Peak memory 200492 kb
Host smart-904ea7ae-81d7-41d7-817b-47c491f2e759
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137158109 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.137158109
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3375574294
Short name T67
Test name
Test status
Simulation time 19979382 ps
CPU time 0.65 seconds
Started Jul 16 05:10:07 PM PDT 24
Finished Jul 16 05:10:08 PM PDT 24
Peak memory 196276 kb
Host smart-a42cc0e0-f65e-466e-8bc4-265023ee4375
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375574294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3375574294
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3955862445
Short name T1268
Test name
Test status
Simulation time 127788497 ps
CPU time 0.58 seconds
Started Jul 16 05:10:19 PM PDT 24
Finished Jul 16 05:10:20 PM PDT 24
Peak memory 195100 kb
Host smart-b0a7cbd3-64f6-4d78-97cb-954c7db7584c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955862445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3955862445
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2560312225
Short name T1242
Test name
Test status
Simulation time 70051794 ps
CPU time 0.64 seconds
Started Jul 16 05:09:54 PM PDT 24
Finished Jul 16 05:09:55 PM PDT 24
Peak memory 196420 kb
Host smart-2d42f725-40ab-47f1-b9d6-b00e785f31cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560312225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2560312225
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3596387672
Short name T1213
Test name
Test status
Simulation time 973602222 ps
CPU time 1.68 seconds
Started Jul 16 05:10:16 PM PDT 24
Finished Jul 16 05:10:18 PM PDT 24
Peak memory 200672 kb
Host smart-c2ed212a-ba55-4394-bdf8-4edfd0163b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596387672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3596387672
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3026280784
Short name T1299
Test name
Test status
Simulation time 268913661 ps
CPU time 0.87 seconds
Started Jul 16 05:10:04 PM PDT 24
Finished Jul 16 05:10:05 PM PDT 24
Peak memory 200488 kb
Host smart-df614cf3-8ba8-4af9-8117-8c3746077285
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026280784 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3026280784
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1145225949
Short name T1216
Test name
Test status
Simulation time 43544094 ps
CPU time 0.64 seconds
Started Jul 16 05:10:07 PM PDT 24
Finished Jul 16 05:10:09 PM PDT 24
Peak memory 195048 kb
Host smart-13e045d5-e203-4b85-b391-c065e4ce03b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145225949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1145225949
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2000670831
Short name T1258
Test name
Test status
Simulation time 18320617 ps
CPU time 0.67 seconds
Started Jul 16 05:10:23 PM PDT 24
Finished Jul 16 05:10:25 PM PDT 24
Peak memory 195536 kb
Host smart-c3f3c018-d091-4433-83b1-f8db15cff977
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000670831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2000670831
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1221178021
Short name T1256
Test name
Test status
Simulation time 108041885 ps
CPU time 1.57 seconds
Started Jul 16 05:10:10 PM PDT 24
Finished Jul 16 05:10:12 PM PDT 24
Peak memory 200704 kb
Host smart-d5df6524-4d23-4891-8087-da7531d46181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221178021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1221178021
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2813589496
Short name T98
Test name
Test status
Simulation time 155808727 ps
CPU time 0.9 seconds
Started Jul 16 05:10:15 PM PDT 24
Finished Jul 16 05:10:16 PM PDT 24
Peak memory 199504 kb
Host smart-219cd75c-f3b6-4c0a-be06-f77b32465435
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813589496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2813589496
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.131668208
Short name T1269
Test name
Test status
Simulation time 27517158 ps
CPU time 0.72 seconds
Started Jul 16 05:10:09 PM PDT 24
Finished Jul 16 05:10:11 PM PDT 24
Peak memory 198116 kb
Host smart-5e08d60a-4c25-4d52-9cec-b97b3a1a93f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131668208 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.131668208
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.106897845
Short name T1300
Test name
Test status
Simulation time 41147786 ps
CPU time 0.62 seconds
Started Jul 16 05:10:07 PM PDT 24
Finished Jul 16 05:10:09 PM PDT 24
Peak memory 196216 kb
Host smart-05c14d6b-7cf3-4844-8bb7-61d75d1522f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106897845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.106897845
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3375960400
Short name T1297
Test name
Test status
Simulation time 44987292 ps
CPU time 0.6 seconds
Started Jul 16 05:10:08 PM PDT 24
Finished Jul 16 05:10:10 PM PDT 24
Peak memory 195112 kb
Host smart-bfd0cf5f-05d4-4693-abe2-8b0784752ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375960400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3375960400
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1383720976
Short name T88
Test name
Test status
Simulation time 72422268 ps
CPU time 0.62 seconds
Started Jul 16 05:10:29 PM PDT 24
Finished Jul 16 05:10:30 PM PDT 24
Peak memory 196544 kb
Host smart-31f08a0e-f82a-4fca-ba61-496fa6bfb905
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383720976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1383720976
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2334851430
Short name T1209
Test name
Test status
Simulation time 27203988 ps
CPU time 1.42 seconds
Started Jul 16 05:10:04 PM PDT 24
Finished Jul 16 05:10:06 PM PDT 24
Peak memory 200652 kb
Host smart-d96a71f9-b13d-4570-a56f-f586d6d46025
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334851430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2334851430
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.247651424
Short name T1309
Test name
Test status
Simulation time 104335585 ps
CPU time 0.94 seconds
Started Jul 16 05:10:14 PM PDT 24
Finished Jul 16 05:10:15 PM PDT 24
Peak memory 199320 kb
Host smart-a80e02b4-f1dc-49f8-a18a-87597b292ede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247651424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.247651424
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.823035115
Short name T1249
Test name
Test status
Simulation time 28799056 ps
CPU time 0.89 seconds
Started Jul 16 05:10:09 PM PDT 24
Finished Jul 16 05:10:11 PM PDT 24
Peak memory 200568 kb
Host smart-8d023d1e-5ed8-40a7-88c0-d3eaf13fbe6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823035115 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.823035115
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1010650286
Short name T1246
Test name
Test status
Simulation time 43314553 ps
CPU time 0.61 seconds
Started Jul 16 05:10:11 PM PDT 24
Finished Jul 16 05:10:13 PM PDT 24
Peak memory 196172 kb
Host smart-49be8c7e-4ad2-4059-a932-65e91bd1ce88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010650286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1010650286
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.836401584
Short name T1291
Test name
Test status
Simulation time 47781577 ps
CPU time 0.59 seconds
Started Jul 16 05:10:09 PM PDT 24
Finished Jul 16 05:10:11 PM PDT 24
Peak memory 195100 kb
Host smart-36d5432c-6030-4ec0-a719-40385965522c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836401584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.836401584
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2981715311
Short name T83
Test name
Test status
Simulation time 39389284 ps
CPU time 0.62 seconds
Started Jul 16 05:10:19 PM PDT 24
Finished Jul 16 05:10:20 PM PDT 24
Peak memory 196144 kb
Host smart-b4e9ac23-5607-41ee-a9a1-7be6a75632be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981715311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2981715311
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2292821337
Short name T1229
Test name
Test status
Simulation time 55844280 ps
CPU time 1.23 seconds
Started Jul 16 05:10:24 PM PDT 24
Finished Jul 16 05:10:26 PM PDT 24
Peak memory 200704 kb
Host smart-6e0b861e-d58b-41e0-9b1e-7cd9ec01ffb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292821337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2292821337
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.317032686
Short name T94
Test name
Test status
Simulation time 176874817 ps
CPU time 1.34 seconds
Started Jul 16 05:10:19 PM PDT 24
Finished Jul 16 05:10:21 PM PDT 24
Peak memory 199876 kb
Host smart-f3899922-1c64-4ae5-bcba-08430d1d6e9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317032686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.317032686
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2071899544
Short name T1289
Test name
Test status
Simulation time 41050122 ps
CPU time 0.79 seconds
Started Jul 16 05:10:08 PM PDT 24
Finished Jul 16 05:10:10 PM PDT 24
Peak memory 199332 kb
Host smart-aa515178-ed3b-420c-a328-60c34c611aa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071899544 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2071899544
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3115439828
Short name T1275
Test name
Test status
Simulation time 17408362 ps
CPU time 0.63 seconds
Started Jul 16 05:10:07 PM PDT 24
Finished Jul 16 05:10:09 PM PDT 24
Peak memory 196460 kb
Host smart-de059dbd-dfa8-4d52-a9f9-03afa804756c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115439828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3115439828
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.98758922
Short name T1274
Test name
Test status
Simulation time 28351298 ps
CPU time 0.56 seconds
Started Jul 16 05:10:22 PM PDT 24
Finished Jul 16 05:10:23 PM PDT 24
Peak memory 195080 kb
Host smart-ab6f8d55-2b3e-4716-bb50-aef600203223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98758922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.98758922
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3557721445
Short name T1294
Test name
Test status
Simulation time 26675552 ps
CPU time 0.72 seconds
Started Jul 16 05:10:14 PM PDT 24
Finished Jul 16 05:10:16 PM PDT 24
Peak memory 197576 kb
Host smart-a00488b1-9673-46e4-b64a-5c3ff82dddd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557721445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3557721445
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3715847007
Short name T1212
Test name
Test status
Simulation time 884066020 ps
CPU time 1.91 seconds
Started Jul 16 05:10:19 PM PDT 24
Finished Jul 16 05:10:21 PM PDT 24
Peak memory 200672 kb
Host smart-21929aad-2f54-49e7-a1d6-0ab67cdc9d82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715847007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3715847007
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1202536583
Short name T99
Test name
Test status
Simulation time 77168145 ps
CPU time 1.33 seconds
Started Jul 16 05:10:03 PM PDT 24
Finished Jul 16 05:10:05 PM PDT 24
Peak memory 200172 kb
Host smart-a60e2caa-3825-4e08-9af2-bc9451942443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202536583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1202536583
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3960948172
Short name T1183
Test name
Test status
Simulation time 33287443 ps
CPU time 0.69 seconds
Started Jul 16 05:10:05 PM PDT 24
Finished Jul 16 05:10:06 PM PDT 24
Peak memory 197892 kb
Host smart-4f3ec205-f25b-4e4b-b4c5-b6fcb4514620
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960948172 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3960948172
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1852757654
Short name T90
Test name
Test status
Simulation time 15295261 ps
CPU time 0.65 seconds
Started Jul 16 05:10:07 PM PDT 24
Finished Jul 16 05:10:09 PM PDT 24
Peak memory 196168 kb
Host smart-89e2e424-7724-4ec2-b67d-ffeb5bcb1ded
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852757654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1852757654
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.859958015
Short name T1223
Test name
Test status
Simulation time 36847741 ps
CPU time 0.57 seconds
Started Jul 16 05:10:06 PM PDT 24
Finished Jul 16 05:10:07 PM PDT 24
Peak memory 195076 kb
Host smart-64650e73-4d1d-47b3-80bc-dd8302f26bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859958015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.859958015
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.865260449
Short name T1225
Test name
Test status
Simulation time 46833816 ps
CPU time 0.64 seconds
Started Jul 16 05:10:18 PM PDT 24
Finished Jul 16 05:10:19 PM PDT 24
Peak memory 196360 kb
Host smart-088f5e54-c444-49b2-8f36-22c8c4983053
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865260449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.865260449
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1899021872
Short name T1220
Test name
Test status
Simulation time 208133125 ps
CPU time 1.38 seconds
Started Jul 16 05:10:09 PM PDT 24
Finished Jul 16 05:10:11 PM PDT 24
Peak memory 200716 kb
Host smart-43eb53de-4c76-4067-87cc-4ca3cb47167a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899021872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1899021872
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.248927527
Short name T1250
Test name
Test status
Simulation time 190061621 ps
CPU time 1.1 seconds
Started Jul 16 05:10:08 PM PDT 24
Finished Jul 16 05:10:10 PM PDT 24
Peak memory 199600 kb
Host smart-afb60bdc-341d-4dc0-b99c-ebe4a6248c53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248927527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.248927527
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3254581959
Short name T1266
Test name
Test status
Simulation time 19426562 ps
CPU time 0.75 seconds
Started Jul 16 05:10:10 PM PDT 24
Finished Jul 16 05:10:12 PM PDT 24
Peak memory 198704 kb
Host smart-a6ce7697-fab7-49bf-8ddd-388cd8e1b73b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254581959 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3254581959
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1066816012
Short name T71
Test name
Test status
Simulation time 21817452 ps
CPU time 0.61 seconds
Started Jul 16 05:10:18 PM PDT 24
Finished Jul 16 05:10:19 PM PDT 24
Peak memory 196140 kb
Host smart-8de252d5-3319-45d7-a75b-8d1efb14f82a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066816012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1066816012
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2765663895
Short name T1187
Test name
Test status
Simulation time 11926895 ps
CPU time 0.6 seconds
Started Jul 16 05:10:09 PM PDT 24
Finished Jul 16 05:10:11 PM PDT 24
Peak memory 195100 kb
Host smart-f55ea631-3c06-4062-8221-d1ac27606a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765663895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2765663895
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1520877751
Short name T1240
Test name
Test status
Simulation time 19256030 ps
CPU time 0.71 seconds
Started Jul 16 05:10:13 PM PDT 24
Finished Jul 16 05:10:14 PM PDT 24
Peak memory 195540 kb
Host smart-0f3e1d4b-0b6f-4174-ad61-014e09cde9ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520877751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1520877751
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.356054662
Short name T1185
Test name
Test status
Simulation time 45843622 ps
CPU time 1.28 seconds
Started Jul 16 05:10:19 PM PDT 24
Finished Jul 16 05:10:21 PM PDT 24
Peak memory 200660 kb
Host smart-d2600fe9-44d5-4af5-b28d-4c043c12e6a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356054662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.356054662
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4243085109
Short name T96
Test name
Test status
Simulation time 52083966 ps
CPU time 1.01 seconds
Started Jul 16 05:10:07 PM PDT 24
Finished Jul 16 05:10:09 PM PDT 24
Peak memory 199288 kb
Host smart-930b1c6f-d4a8-4617-933f-d7f034985b3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243085109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.4243085109
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2763713158
Short name T1224
Test name
Test status
Simulation time 19277499 ps
CPU time 0.68 seconds
Started Jul 16 05:10:22 PM PDT 24
Finished Jul 16 05:10:24 PM PDT 24
Peak memory 198460 kb
Host smart-deaa4626-16b1-4a38-b722-deeaf5329d35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763713158 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2763713158
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1194083887
Short name T1208
Test name
Test status
Simulation time 15269272 ps
CPU time 0.6 seconds
Started Jul 16 05:10:08 PM PDT 24
Finished Jul 16 05:10:09 PM PDT 24
Peak memory 196220 kb
Host smart-07b9651d-c89f-4341-96bd-785efbd1b855
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194083887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1194083887
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3627808247
Short name T1230
Test name
Test status
Simulation time 31253968 ps
CPU time 0.59 seconds
Started Jul 16 05:10:10 PM PDT 24
Finished Jul 16 05:10:12 PM PDT 24
Peak memory 195132 kb
Host smart-32f3939b-0954-4622-9193-d8dcfbf9a828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627808247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3627808247
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.126965145
Short name T85
Test name
Test status
Simulation time 12966764 ps
CPU time 0.63 seconds
Started Jul 16 05:10:29 PM PDT 24
Finished Jul 16 05:10:30 PM PDT 24
Peak memory 196344 kb
Host smart-39cde89a-5359-44c3-9b10-d554d388beb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126965145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.126965145
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2855524610
Short name T1236
Test name
Test status
Simulation time 77460590 ps
CPU time 1.05 seconds
Started Jul 16 05:10:12 PM PDT 24
Finished Jul 16 05:10:14 PM PDT 24
Peak memory 200540 kb
Host smart-82f0ec31-8907-4243-9155-a81f03bf5ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855524610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2855524610
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3918600113
Short name T95
Test name
Test status
Simulation time 144588334 ps
CPU time 0.91 seconds
Started Jul 16 05:10:05 PM PDT 24
Finished Jul 16 05:10:06 PM PDT 24
Peak memory 199568 kb
Host smart-c3f2a80f-a747-4b2d-b481-24d2972ba7ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918600113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3918600113
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1026374741
Short name T1201
Test name
Test status
Simulation time 81955798 ps
CPU time 0.96 seconds
Started Jul 16 05:10:16 PM PDT 24
Finished Jul 16 05:10:18 PM PDT 24
Peak memory 200500 kb
Host smart-9360a7b9-3cf1-432f-826a-d32c7d0ce6b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026374741 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1026374741
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3480200739
Short name T1195
Test name
Test status
Simulation time 25032413 ps
CPU time 0.61 seconds
Started Jul 16 05:10:13 PM PDT 24
Finished Jul 16 05:10:14 PM PDT 24
Peak memory 196188 kb
Host smart-a799fc08-fb90-424d-a008-fc8d19e78186
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480200739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3480200739
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.968132816
Short name T1197
Test name
Test status
Simulation time 184614819 ps
CPU time 0.58 seconds
Started Jul 16 05:10:08 PM PDT 24
Finished Jul 16 05:10:10 PM PDT 24
Peak memory 195000 kb
Host smart-8c70dcbb-080f-4906-a9e3-992f6c37bb41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968132816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.968132816
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4293504674
Short name T86
Test name
Test status
Simulation time 17968662 ps
CPU time 0.64 seconds
Started Jul 16 05:10:11 PM PDT 24
Finished Jul 16 05:10:13 PM PDT 24
Peak memory 196304 kb
Host smart-102324e2-7396-4b90-827c-1c423d5a121d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293504674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.4293504674
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.881661299
Short name T1192
Test name
Test status
Simulation time 105126584 ps
CPU time 2.58 seconds
Started Jul 16 05:10:07 PM PDT 24
Finished Jul 16 05:10:11 PM PDT 24
Peak memory 200752 kb
Host smart-96b2b4e4-f528-4d0f-8aab-31b41a5077b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881661299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.881661299
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4254325519
Short name T130
Test name
Test status
Simulation time 131014866 ps
CPU time 1.2 seconds
Started Jul 16 05:10:19 PM PDT 24
Finished Jul 16 05:10:21 PM PDT 24
Peak memory 199880 kb
Host smart-0bad6c3e-d9ac-4ea4-bc4b-7e1d8e7cc0c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254325519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.4254325519
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1002197795
Short name T1264
Test name
Test status
Simulation time 16186045 ps
CPU time 0.66 seconds
Started Jul 16 05:10:19 PM PDT 24
Finished Jul 16 05:10:20 PM PDT 24
Peak memory 197912 kb
Host smart-6520d15a-d12d-4ecb-8510-dfe797a6ed15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002197795 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1002197795
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1128248009
Short name T70
Test name
Test status
Simulation time 16300412 ps
CPU time 0.59 seconds
Started Jul 16 05:10:23 PM PDT 24
Finished Jul 16 05:10:25 PM PDT 24
Peak memory 196088 kb
Host smart-c1c6e92b-c7ad-4fc5-934c-4993e40933c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128248009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1128248009
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3972099950
Short name T1295
Test name
Test status
Simulation time 195018936 ps
CPU time 0.58 seconds
Started Jul 16 05:10:30 PM PDT 24
Finished Jul 16 05:10:31 PM PDT 24
Peak memory 195036 kb
Host smart-9ba8d781-4025-4a21-b393-63dc1d4fe52d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972099950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3972099950
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3158543966
Short name T1273
Test name
Test status
Simulation time 39645478 ps
CPU time 0.65 seconds
Started Jul 16 05:10:09 PM PDT 24
Finished Jul 16 05:10:11 PM PDT 24
Peak memory 197160 kb
Host smart-208ffbe1-312b-4ed3-8515-24f5c9607033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158543966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3158543966
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2630752553
Short name T1226
Test name
Test status
Simulation time 415093862 ps
CPU time 1.96 seconds
Started Jul 16 05:10:10 PM PDT 24
Finished Jul 16 05:10:13 PM PDT 24
Peak memory 200788 kb
Host smart-8ee885e7-d5ff-4fc8-89dc-ba9231ad2d9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630752553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2630752553
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.216033515
Short name T1303
Test name
Test status
Simulation time 325354287 ps
CPU time 1.38 seconds
Started Jul 16 05:10:09 PM PDT 24
Finished Jul 16 05:10:11 PM PDT 24
Peak memory 200080 kb
Host smart-4c6ea673-bb8c-446e-bc24-c6ccd9671401
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216033515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.216033515
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2907316457
Short name T1222
Test name
Test status
Simulation time 46325177 ps
CPU time 0.64 seconds
Started Jul 16 05:10:08 PM PDT 24
Finished Jul 16 05:10:09 PM PDT 24
Peak memory 198228 kb
Host smart-1e0718d9-c74c-4f4f-b587-30215220e574
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907316457 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2907316457
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3840395807
Short name T1262
Test name
Test status
Simulation time 31151170 ps
CPU time 0.69 seconds
Started Jul 16 05:10:09 PM PDT 24
Finished Jul 16 05:10:11 PM PDT 24
Peak memory 196476 kb
Host smart-e56db5fc-8642-4d73-be23-56e90e36c834
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840395807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3840395807
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1002421903
Short name T1206
Test name
Test status
Simulation time 13725569 ps
CPU time 0.56 seconds
Started Jul 16 05:10:11 PM PDT 24
Finished Jul 16 05:10:13 PM PDT 24
Peak memory 195048 kb
Host smart-e4884f5a-e0e3-4e23-81c0-011c43a27fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002421903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1002421903
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1558838664
Short name T1221
Test name
Test status
Simulation time 50809702 ps
CPU time 0.68 seconds
Started Jul 16 05:10:07 PM PDT 24
Finished Jul 16 05:10:08 PM PDT 24
Peak memory 196632 kb
Host smart-9ec3f4d1-19d1-4e06-9198-65b27978caca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558838664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1558838664
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3269149557
Short name T1214
Test name
Test status
Simulation time 85857477 ps
CPU time 1.96 seconds
Started Jul 16 05:10:10 PM PDT 24
Finished Jul 16 05:10:12 PM PDT 24
Peak memory 200828 kb
Host smart-c6835144-46e4-4e45-9969-0fe3aec860bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269149557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3269149557
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2203896082
Short name T102
Test name
Test status
Simulation time 110818108 ps
CPU time 1.37 seconds
Started Jul 16 05:10:22 PM PDT 24
Finished Jul 16 05:10:25 PM PDT 24
Peak memory 200000 kb
Host smart-192880d1-e6f8-481b-ba03-5c60dfec834f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203896082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2203896082
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.44188577
Short name T1304
Test name
Test status
Simulation time 36415926 ps
CPU time 0.67 seconds
Started Jul 16 05:09:54 PM PDT 24
Finished Jul 16 05:09:56 PM PDT 24
Peak memory 196280 kb
Host smart-41dd53a5-04cc-47a6-9e94-00af1d644e9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44188577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.44188577
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2128984109
Short name T1255
Test name
Test status
Simulation time 96438832 ps
CPU time 1.55 seconds
Started Jul 16 05:09:50 PM PDT 24
Finished Jul 16 05:09:52 PM PDT 24
Peak memory 198428 kb
Host smart-6485e31f-5dc7-43be-b344-e8c25aacf9b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128984109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2128984109
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2379568760
Short name T1260
Test name
Test status
Simulation time 23185650 ps
CPU time 0.6 seconds
Started Jul 16 05:10:14 PM PDT 24
Finished Jul 16 05:10:15 PM PDT 24
Peak memory 196004 kb
Host smart-90c786c5-9b2c-4bfd-b715-444663207aab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379568760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2379568760
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.226596297
Short name T1247
Test name
Test status
Simulation time 115940675 ps
CPU time 0.95 seconds
Started Jul 16 05:10:19 PM PDT 24
Finished Jul 16 05:10:20 PM PDT 24
Peak memory 200548 kb
Host smart-4b2a1fe1-b57f-445f-9b17-e318d833d353
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226596297 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.226596297
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1303736976
Short name T1296
Test name
Test status
Simulation time 35918530 ps
CPU time 0.63 seconds
Started Jul 16 05:09:50 PM PDT 24
Finished Jul 16 05:09:51 PM PDT 24
Peak memory 196308 kb
Host smart-325d1d9e-4043-477a-a01b-64fdef56b6c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303736976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1303736976
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1623190993
Short name T1272
Test name
Test status
Simulation time 14674593 ps
CPU time 0.58 seconds
Started Jul 16 05:10:06 PM PDT 24
Finished Jul 16 05:10:07 PM PDT 24
Peak memory 195152 kb
Host smart-7e746873-1b91-411d-9f7d-e352204b0068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623190993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1623190993
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3432480424
Short name T87
Test name
Test status
Simulation time 16882567 ps
CPU time 0.78 seconds
Started Jul 16 05:10:14 PM PDT 24
Finished Jul 16 05:10:16 PM PDT 24
Peak memory 197936 kb
Host smart-47537cca-0f21-47d1-b216-23213f712174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432480424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3432480424
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4101357008
Short name T1194
Test name
Test status
Simulation time 96151891 ps
CPU time 2.04 seconds
Started Jul 16 05:09:50 PM PDT 24
Finished Jul 16 05:09:52 PM PDT 24
Peak memory 201008 kb
Host smart-106ee0f3-3877-48b3-a246-3413f865d03b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101357008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4101357008
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2726535459
Short name T1257
Test name
Test status
Simulation time 90564686 ps
CPU time 0.93 seconds
Started Jul 16 05:10:29 PM PDT 24
Finished Jul 16 05:10:31 PM PDT 24
Peak memory 199528 kb
Host smart-10cc1977-5186-4aa7-a379-9fd7433c2136
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726535459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2726535459
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1157500671
Short name T1307
Test name
Test status
Simulation time 19605803 ps
CPU time 0.63 seconds
Started Jul 16 05:10:24 PM PDT 24
Finished Jul 16 05:10:26 PM PDT 24
Peak memory 195048 kb
Host smart-305804ad-1f40-4e2d-bbb7-bd9e5d718e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157500671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1157500671
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3717153456
Short name T1252
Test name
Test status
Simulation time 42666842 ps
CPU time 0.66 seconds
Started Jul 16 05:10:21 PM PDT 24
Finished Jul 16 05:10:22 PM PDT 24
Peak memory 195080 kb
Host smart-e5ad44b3-9e94-4c4c-8e52-7492220b3423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717153456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3717153456
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1705298683
Short name T1241
Test name
Test status
Simulation time 52221094 ps
CPU time 0.6 seconds
Started Jul 16 05:10:23 PM PDT 24
Finished Jul 16 05:10:24 PM PDT 24
Peak memory 195168 kb
Host smart-7bd9ef30-366b-4f87-81e3-9230629a4c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705298683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1705298683
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3276568324
Short name T1271
Test name
Test status
Simulation time 43377930 ps
CPU time 0.58 seconds
Started Jul 16 05:10:25 PM PDT 24
Finished Jul 16 05:10:27 PM PDT 24
Peak memory 195064 kb
Host smart-afed4b33-02e1-4f98-9461-641728ed73c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276568324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3276568324
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2227758203
Short name T1278
Test name
Test status
Simulation time 64995509 ps
CPU time 0.57 seconds
Started Jul 16 05:10:25 PM PDT 24
Finished Jul 16 05:10:27 PM PDT 24
Peak memory 195092 kb
Host smart-2b90fc5a-c426-46ee-ae7e-636d48b2c952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227758203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2227758203
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.826755173
Short name T1235
Test name
Test status
Simulation time 28871689 ps
CPU time 0.55 seconds
Started Jul 16 05:10:23 PM PDT 24
Finished Jul 16 05:10:24 PM PDT 24
Peak memory 195164 kb
Host smart-ce3cff6f-115c-47f8-b4bf-95856593aaf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826755173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.826755173
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1423654202
Short name T1308
Test name
Test status
Simulation time 59389801 ps
CPU time 0.6 seconds
Started Jul 16 05:10:22 PM PDT 24
Finished Jul 16 05:10:23 PM PDT 24
Peak memory 195112 kb
Host smart-cacf4bd2-7f14-47d2-b427-48f2c6ef2545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423654202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1423654202
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.160258475
Short name T1193
Test name
Test status
Simulation time 14472922 ps
CPU time 0.59 seconds
Started Jul 16 05:10:25 PM PDT 24
Finished Jul 16 05:10:27 PM PDT 24
Peak memory 194476 kb
Host smart-90db11b6-4a64-4221-b497-ed953bb219a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160258475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.160258475
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2846399971
Short name T1243
Test name
Test status
Simulation time 22832771 ps
CPU time 0.59 seconds
Started Jul 16 05:10:24 PM PDT 24
Finished Jul 16 05:10:26 PM PDT 24
Peak memory 195068 kb
Host smart-cd28d99e-de3f-423d-a3e0-354a192d1c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846399971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2846399971
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2078756904
Short name T1228
Test name
Test status
Simulation time 12258534 ps
CPU time 0.55 seconds
Started Jul 16 05:10:23 PM PDT 24
Finished Jul 16 05:10:24 PM PDT 24
Peak memory 195100 kb
Host smart-f2cd2226-1e6a-475c-84c2-ea5052a17124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078756904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2078756904
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3521473610
Short name T1276
Test name
Test status
Simulation time 26893896 ps
CPU time 0.77 seconds
Started Jul 16 05:10:19 PM PDT 24
Finished Jul 16 05:10:20 PM PDT 24
Peak memory 197232 kb
Host smart-19a427f0-7154-4cfb-9ed8-ac2ae043e848
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521473610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3521473610
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1676476876
Short name T66
Test name
Test status
Simulation time 48007824 ps
CPU time 1.37 seconds
Started Jul 16 05:10:06 PM PDT 24
Finished Jul 16 05:10:08 PM PDT 24
Peak memory 198388 kb
Host smart-f8aa9422-c510-4a34-807e-ab6c843ade2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676476876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1676476876
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.288013249
Short name T72
Test name
Test status
Simulation time 76246786 ps
CPU time 0.58 seconds
Started Jul 16 05:10:14 PM PDT 24
Finished Jul 16 05:10:16 PM PDT 24
Peak memory 196004 kb
Host smart-7e21aebd-b06e-47e8-b93e-0e93ccb1bf59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288013249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.288013249
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4262602336
Short name T1244
Test name
Test status
Simulation time 47408864 ps
CPU time 1.07 seconds
Started Jul 16 05:09:51 PM PDT 24
Finished Jul 16 05:09:53 PM PDT 24
Peak memory 200820 kb
Host smart-d0b785a8-0ac3-4909-bd39-c7066c48d2f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262602336 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.4262602336
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3005535355
Short name T1277
Test name
Test status
Simulation time 145558475 ps
CPU time 0.62 seconds
Started Jul 16 05:09:54 PM PDT 24
Finished Jul 16 05:09:55 PM PDT 24
Peak memory 196276 kb
Host smart-68373eef-959c-407c-a15a-d661106fa068
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005535355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3005535355
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.178679698
Short name T1215
Test name
Test status
Simulation time 14361592 ps
CPU time 0.6 seconds
Started Jul 16 05:09:53 PM PDT 24
Finished Jul 16 05:09:55 PM PDT 24
Peak memory 195180 kb
Host smart-3c716240-186d-4fc3-9117-b38ab2f12fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178679698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.178679698
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2795686292
Short name T1298
Test name
Test status
Simulation time 24642279 ps
CPU time 0.7 seconds
Started Jul 16 05:10:10 PM PDT 24
Finished Jul 16 05:10:12 PM PDT 24
Peak memory 197220 kb
Host smart-2a4bc690-b041-4a19-8b8e-a7eb66895773
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795686292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2795686292
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1240853436
Short name T1259
Test name
Test status
Simulation time 147149956 ps
CPU time 1.55 seconds
Started Jul 16 05:09:52 PM PDT 24
Finished Jul 16 05:09:55 PM PDT 24
Peak memory 200744 kb
Host smart-363f1692-6f6b-4b4a-aeec-9ae1bd66b48d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240853436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1240853436
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2402720374
Short name T1311
Test name
Test status
Simulation time 161980104 ps
CPU time 0.95 seconds
Started Jul 16 05:10:30 PM PDT 24
Finished Jul 16 05:10:31 PM PDT 24
Peak memory 199864 kb
Host smart-56da3fde-cc32-42ff-872c-7dae24d11582
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402720374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2402720374
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.115908017
Short name T1284
Test name
Test status
Simulation time 15571786 ps
CPU time 0.63 seconds
Started Jul 16 05:10:28 PM PDT 24
Finished Jul 16 05:10:30 PM PDT 24
Peak memory 195156 kb
Host smart-2528d0e4-424d-4c35-980e-4606f9f95da7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115908017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.115908017
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3897930435
Short name T1251
Test name
Test status
Simulation time 14820145 ps
CPU time 0.56 seconds
Started Jul 16 05:10:37 PM PDT 24
Finished Jul 16 05:10:38 PM PDT 24
Peak memory 195048 kb
Host smart-dff00577-247b-424a-be20-1c46bb271d51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897930435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3897930435
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3487022775
Short name T1305
Test name
Test status
Simulation time 19155084 ps
CPU time 0.63 seconds
Started Jul 16 05:10:21 PM PDT 24
Finished Jul 16 05:10:23 PM PDT 24
Peak memory 195100 kb
Host smart-71283a1b-5f4a-4235-9076-db378b93482a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487022775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3487022775
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2106241214
Short name T1204
Test name
Test status
Simulation time 19931969 ps
CPU time 0.61 seconds
Started Jul 16 05:10:22 PM PDT 24
Finished Jul 16 05:10:23 PM PDT 24
Peak memory 194976 kb
Host smart-143de371-1b0d-4ad1-91c2-d5dcb91b3e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106241214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2106241214
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.335612451
Short name T1234
Test name
Test status
Simulation time 13100246 ps
CPU time 0.59 seconds
Started Jul 16 05:10:25 PM PDT 24
Finished Jul 16 05:10:27 PM PDT 24
Peak memory 194492 kb
Host smart-77ee1929-5ddd-414e-9cb9-9d5408938127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335612451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.335612451
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1231981785
Short name T1302
Test name
Test status
Simulation time 17559552 ps
CPU time 0.59 seconds
Started Jul 16 05:10:23 PM PDT 24
Finished Jul 16 05:10:24 PM PDT 24
Peak memory 195092 kb
Host smart-aaf89022-49db-434d-bc4c-b80183a2a638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231981785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1231981785
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2878324096
Short name T1265
Test name
Test status
Simulation time 21610732 ps
CPU time 0.6 seconds
Started Jul 16 05:10:20 PM PDT 24
Finished Jul 16 05:10:21 PM PDT 24
Peak memory 195148 kb
Host smart-a1b42c8f-608e-4704-854a-207e5c037a60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878324096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2878324096
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1569445912
Short name T1233
Test name
Test status
Simulation time 37789561 ps
CPU time 0.56 seconds
Started Jul 16 05:10:25 PM PDT 24
Finished Jul 16 05:10:27 PM PDT 24
Peak memory 195108 kb
Host smart-7c4c9719-5c18-421b-b451-ad63be907897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569445912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1569445912
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3893424274
Short name T1211
Test name
Test status
Simulation time 38120304 ps
CPU time 0.56 seconds
Started Jul 16 05:10:19 PM PDT 24
Finished Jul 16 05:10:20 PM PDT 24
Peak memory 195144 kb
Host smart-80df756a-2090-4128-8917-77c337938445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893424274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3893424274
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3928754124
Short name T1279
Test name
Test status
Simulation time 25036477 ps
CPU time 0.58 seconds
Started Jul 16 05:10:23 PM PDT 24
Finished Jul 16 05:10:24 PM PDT 24
Peak memory 195096 kb
Host smart-4791bedf-80ab-4080-96e4-030fe15edd58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928754124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3928754124
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1403041010
Short name T1292
Test name
Test status
Simulation time 47332105 ps
CPU time 0.74 seconds
Started Jul 16 05:09:53 PM PDT 24
Finished Jul 16 05:09:55 PM PDT 24
Peak memory 197028 kb
Host smart-87c19eb5-7ae6-4f97-b8ed-bb7513b25fa4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403041010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1403041010
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3224591527
Short name T1287
Test name
Test status
Simulation time 319299187 ps
CPU time 1.39 seconds
Started Jul 16 05:09:52 PM PDT 24
Finished Jul 16 05:09:55 PM PDT 24
Peak memory 198420 kb
Host smart-09e80ba7-27c5-450d-9896-2c1995d1c704
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224591527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3224591527
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2269406373
Short name T68
Test name
Test status
Simulation time 1034570777 ps
CPU time 2.02 seconds
Started Jul 16 05:09:52 PM PDT 24
Finished Jul 16 05:09:55 PM PDT 24
Peak memory 196048 kb
Host smart-57d86a48-3bee-4eb2-b827-d11ce8185a02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269406373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2269406373
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1022967245
Short name T1217
Test name
Test status
Simulation time 386532118 ps
CPU time 0.95 seconds
Started Jul 16 05:09:50 PM PDT 24
Finished Jul 16 05:09:51 PM PDT 24
Peak memory 200492 kb
Host smart-c30ae0f1-4005-40c9-a3fa-604c668805d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022967245 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1022967245
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1067336272
Short name T69
Test name
Test status
Simulation time 59214772 ps
CPU time 0.61 seconds
Started Jul 16 05:09:55 PM PDT 24
Finished Jul 16 05:09:56 PM PDT 24
Peak memory 196260 kb
Host smart-0e07ebf8-5b12-4aeb-b965-700a789c4914
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067336272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1067336272
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3694259248
Short name T1263
Test name
Test status
Simulation time 39658325 ps
CPU time 0.59 seconds
Started Jul 16 05:09:56 PM PDT 24
Finished Jul 16 05:09:57 PM PDT 24
Peak memory 195148 kb
Host smart-9f9d42c1-cb93-4d22-866b-e3ef335e79a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694259248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3694259248
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.697700146
Short name T84
Test name
Test status
Simulation time 15568369 ps
CPU time 0.72 seconds
Started Jul 16 05:09:53 PM PDT 24
Finished Jul 16 05:09:55 PM PDT 24
Peak memory 196604 kb
Host smart-9da71077-c513-4a2e-b68e-986ca1ef5cc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697700146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.697700146
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.718396235
Short name T1267
Test name
Test status
Simulation time 218161534 ps
CPU time 2.13 seconds
Started Jul 16 05:09:53 PM PDT 24
Finished Jul 16 05:09:57 PM PDT 24
Peak memory 200804 kb
Host smart-caa0a92c-8b5d-4af6-aecc-93373edd0b9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718396235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.718396235
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3126173001
Short name T1248
Test name
Test status
Simulation time 91314112 ps
CPU time 1.34 seconds
Started Jul 16 05:10:01 PM PDT 24
Finished Jul 16 05:10:03 PM PDT 24
Peak memory 200240 kb
Host smart-1f3b0710-6e5f-4f02-b2f7-0247ab4b2d7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126173001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3126173001
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.867320937
Short name T1186
Test name
Test status
Simulation time 12933501 ps
CPU time 0.65 seconds
Started Jul 16 05:10:24 PM PDT 24
Finished Jul 16 05:10:26 PM PDT 24
Peak memory 195044 kb
Host smart-faa04bfa-0f9b-414b-aabf-edc04bd60508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867320937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.867320937
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2544531639
Short name T1188
Test name
Test status
Simulation time 18967277 ps
CPU time 0.55 seconds
Started Jul 16 05:10:19 PM PDT 24
Finished Jul 16 05:10:21 PM PDT 24
Peak memory 195020 kb
Host smart-761a21cd-d618-4f39-acac-6ef2df01ab2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544531639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2544531639
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3295185722
Short name T1286
Test name
Test status
Simulation time 45393405 ps
CPU time 0.57 seconds
Started Jul 16 05:10:21 PM PDT 24
Finished Jul 16 05:10:22 PM PDT 24
Peak memory 194992 kb
Host smart-9a027cda-3c9c-457c-9994-016000d6e81d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295185722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3295185722
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.344140962
Short name T1219
Test name
Test status
Simulation time 17833053 ps
CPU time 0.58 seconds
Started Jul 16 05:10:26 PM PDT 24
Finished Jul 16 05:10:28 PM PDT 24
Peak memory 195108 kb
Host smart-c41370c4-77fa-422e-a69f-d7f8c0474c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344140962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.344140962
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1270445519
Short name T1203
Test name
Test status
Simulation time 51695094 ps
CPU time 0.61 seconds
Started Jul 16 05:10:22 PM PDT 24
Finished Jul 16 05:10:23 PM PDT 24
Peak memory 195052 kb
Host smart-5f81e164-6812-4db5-9060-cdb5679de1e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270445519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1270445519
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.857719765
Short name T1205
Test name
Test status
Simulation time 13930119 ps
CPU time 0.59 seconds
Started Jul 16 05:10:23 PM PDT 24
Finished Jul 16 05:10:25 PM PDT 24
Peak memory 195076 kb
Host smart-c3ed3fd3-8fae-44b3-ac7c-c4c4c856cf96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857719765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.857719765
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3529821540
Short name T1293
Test name
Test status
Simulation time 45908135 ps
CPU time 0.63 seconds
Started Jul 16 05:10:23 PM PDT 24
Finished Jul 16 05:10:25 PM PDT 24
Peak memory 195056 kb
Host smart-c3adf2fd-17d7-4265-816c-adcb5cb82318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529821540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3529821540
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.717991984
Short name T1239
Test name
Test status
Simulation time 13475653 ps
CPU time 0.57 seconds
Started Jul 16 05:10:22 PM PDT 24
Finished Jul 16 05:10:24 PM PDT 24
Peak memory 195100 kb
Host smart-c8d3e16b-8b8f-4e7d-aa18-a2c154ef3316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717991984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.717991984
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1922349988
Short name T1281
Test name
Test status
Simulation time 13079234 ps
CPU time 0.63 seconds
Started Jul 16 05:10:26 PM PDT 24
Finished Jul 16 05:10:28 PM PDT 24
Peak memory 195152 kb
Host smart-f0304274-ad01-471e-8735-a6d606403a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922349988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1922349988
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2590318702
Short name T1189
Test name
Test status
Simulation time 13435971 ps
CPU time 0.56 seconds
Started Jul 16 05:10:26 PM PDT 24
Finished Jul 16 05:10:28 PM PDT 24
Peak memory 195100 kb
Host smart-d718d820-d68e-4ede-b346-b8e101846897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590318702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2590318702
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.8231590
Short name T1306
Test name
Test status
Simulation time 60696831 ps
CPU time 0.81 seconds
Started Jul 16 05:10:29 PM PDT 24
Finished Jul 16 05:10:31 PM PDT 24
Peak memory 200392 kb
Host smart-f1925ba3-7b80-42cd-a190-80a4f432e967
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8231590 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.8231590
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3865680565
Short name T1253
Test name
Test status
Simulation time 29236509 ps
CPU time 0.58 seconds
Started Jul 16 05:09:52 PM PDT 24
Finished Jul 16 05:09:54 PM PDT 24
Peak memory 196060 kb
Host smart-ff99dc2e-28fd-4402-b541-987479c98fc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865680565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3865680565
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.757921032
Short name T1245
Test name
Test status
Simulation time 112266805 ps
CPU time 0.55 seconds
Started Jul 16 05:09:53 PM PDT 24
Finished Jul 16 05:09:55 PM PDT 24
Peak memory 195068 kb
Host smart-c1475e14-f7c8-4266-8cc9-ef9159eae411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757921032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.757921032
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4190094507
Short name T1231
Test name
Test status
Simulation time 25557685 ps
CPU time 0.73 seconds
Started Jul 16 05:10:19 PM PDT 24
Finished Jul 16 05:10:20 PM PDT 24
Peak memory 196500 kb
Host smart-b5cd2f97-ed9e-43e2-9307-a3941e703bd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190094507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.4190094507
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.681151249
Short name T1313
Test name
Test status
Simulation time 506737841 ps
CPU time 2.19 seconds
Started Jul 16 05:09:53 PM PDT 24
Finished Jul 16 05:09:56 PM PDT 24
Peak memory 200804 kb
Host smart-92ad3db3-b8d8-406b-8139-eccd117817b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681151249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.681151249
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.621612959
Short name T1207
Test name
Test status
Simulation time 100209152 ps
CPU time 0.84 seconds
Started Jul 16 05:09:53 PM PDT 24
Finished Jul 16 05:09:55 PM PDT 24
Peak memory 200484 kb
Host smart-ab26baab-0895-4c0b-89ff-52047cbd1982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621612959 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.621612959
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.893404815
Short name T1261
Test name
Test status
Simulation time 59649390 ps
CPU time 0.62 seconds
Started Jul 16 05:09:52 PM PDT 24
Finished Jul 16 05:09:53 PM PDT 24
Peak memory 195772 kb
Host smart-0625f418-6d76-4f30-8824-86c2b2e4956a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893404815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.893404815
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2406767959
Short name T1196
Test name
Test status
Simulation time 85873121 ps
CPU time 0.54 seconds
Started Jul 16 05:10:35 PM PDT 24
Finished Jul 16 05:10:36 PM PDT 24
Peak memory 195048 kb
Host smart-7d320611-0a99-4188-9474-83014ada7c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406767959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2406767959
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3514156291
Short name T91
Test name
Test status
Simulation time 15272958 ps
CPU time 0.62 seconds
Started Jul 16 05:09:51 PM PDT 24
Finished Jul 16 05:09:52 PM PDT 24
Peak memory 195292 kb
Host smart-26e84778-9b2b-4b8f-b1e2-1a7022fc46ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514156291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3514156291
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3101748028
Short name T1191
Test name
Test status
Simulation time 427604190 ps
CPU time 1.98 seconds
Started Jul 16 05:10:01 PM PDT 24
Finished Jul 16 05:10:04 PM PDT 24
Peak memory 200736 kb
Host smart-6b0a250c-88ae-4a64-a4c0-760aad550b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101748028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3101748028
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.278233727
Short name T101
Test name
Test status
Simulation time 159015624 ps
CPU time 1.31 seconds
Started Jul 16 05:10:01 PM PDT 24
Finished Jul 16 05:10:03 PM PDT 24
Peak memory 200116 kb
Host smart-fcf07b0a-c714-4d61-99ff-19063acaad7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278233727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.278233727
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2710758605
Short name T1218
Test name
Test status
Simulation time 26640665 ps
CPU time 1.25 seconds
Started Jul 16 05:10:15 PM PDT 24
Finished Jul 16 05:10:17 PM PDT 24
Peak memory 200792 kb
Host smart-e169fb2e-c62d-4606-adc7-48ee4161c12a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710758605 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2710758605
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.737600913
Short name T63
Test name
Test status
Simulation time 21363683 ps
CPU time 0.57 seconds
Started Jul 16 05:09:58 PM PDT 24
Finished Jul 16 05:09:59 PM PDT 24
Peak memory 196076 kb
Host smart-f7cf32ca-7ad7-4f39-a6b7-d1215e2b9096
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737600913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.737600913
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2823933700
Short name T1200
Test name
Test status
Simulation time 25851442 ps
CPU time 0.6 seconds
Started Jul 16 05:09:54 PM PDT 24
Finished Jul 16 05:09:56 PM PDT 24
Peak memory 195088 kb
Host smart-99ee2fd4-06e2-459b-ad2e-3eb62fc605aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823933700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2823933700
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3968397163
Short name T1237
Test name
Test status
Simulation time 22896940 ps
CPU time 0.67 seconds
Started Jul 16 05:09:58 PM PDT 24
Finished Jul 16 05:09:59 PM PDT 24
Peak memory 196544 kb
Host smart-69e5d5f2-e1ee-43f2-a40f-99bbfd965b51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968397163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3968397163
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2561872725
Short name T1182
Test name
Test status
Simulation time 29970755 ps
CPU time 1.47 seconds
Started Jul 16 05:10:11 PM PDT 24
Finished Jul 16 05:10:14 PM PDT 24
Peak memory 200804 kb
Host smart-2e3ee6fc-c454-45be-8e07-17201ac69f19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561872725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2561872725
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.132053177
Short name T1310
Test name
Test status
Simulation time 49079225 ps
CPU time 0.96 seconds
Started Jul 16 05:10:17 PM PDT 24
Finished Jul 16 05:10:18 PM PDT 24
Peak memory 199728 kb
Host smart-4402b229-888f-42e0-beb7-e257659062e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132053177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.132053177
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2557571405
Short name T1199
Test name
Test status
Simulation time 50091175 ps
CPU time 0.69 seconds
Started Jul 16 05:09:53 PM PDT 24
Finished Jul 16 05:09:55 PM PDT 24
Peak memory 198412 kb
Host smart-6a522add-3be2-4d43-a283-1b55364ec629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557571405 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2557571405
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1882359441
Short name T1314
Test name
Test status
Simulation time 16510682 ps
CPU time 0.58 seconds
Started Jul 16 05:10:14 PM PDT 24
Finished Jul 16 05:10:16 PM PDT 24
Peak memory 196044 kb
Host smart-b0393df3-0f00-483d-969e-27fc70a12e3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882359441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1882359441
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.4072473587
Short name T1190
Test name
Test status
Simulation time 125639165 ps
CPU time 0.54 seconds
Started Jul 16 05:10:02 PM PDT 24
Finished Jul 16 05:10:03 PM PDT 24
Peak memory 195128 kb
Host smart-e30d4390-4c65-40b1-afc7-4cd00bef05ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072473587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.4072473587
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1714158742
Short name T1254
Test name
Test status
Simulation time 47414317 ps
CPU time 0.67 seconds
Started Jul 16 05:10:02 PM PDT 24
Finished Jul 16 05:10:03 PM PDT 24
Peak memory 195048 kb
Host smart-ba34a5ed-c871-466b-b63b-661a814a5135
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714158742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1714158742
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1068026632
Short name T1315
Test name
Test status
Simulation time 67193942 ps
CPU time 1.55 seconds
Started Jul 16 05:09:52 PM PDT 24
Finished Jul 16 05:09:54 PM PDT 24
Peak memory 200336 kb
Host smart-a4c7c9a3-4af1-41ac-80b4-600120bee4c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068026632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1068026632
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.451102609
Short name T103
Test name
Test status
Simulation time 95232843 ps
CPU time 1.29 seconds
Started Jul 16 05:09:49 PM PDT 24
Finished Jul 16 05:09:51 PM PDT 24
Peak memory 200260 kb
Host smart-dd350a2b-dde2-498c-9adf-1e98e2e57db4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451102609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.451102609
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2899881246
Short name T1210
Test name
Test status
Simulation time 43619099 ps
CPU time 0.88 seconds
Started Jul 16 05:10:16 PM PDT 24
Finished Jul 16 05:10:17 PM PDT 24
Peak memory 200548 kb
Host smart-3f9a2b4a-aeba-4d2e-ac4d-32468ac8454a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899881246 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2899881246
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1894459071
Short name T73
Test name
Test status
Simulation time 32703641 ps
CPU time 0.61 seconds
Started Jul 16 05:10:23 PM PDT 24
Finished Jul 16 05:10:25 PM PDT 24
Peak memory 196348 kb
Host smart-32c6c8ab-a832-4b54-8733-62d45613b7b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894459071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1894459071
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.271831049
Short name T1198
Test name
Test status
Simulation time 12972850 ps
CPU time 0.59 seconds
Started Jul 16 05:10:23 PM PDT 24
Finished Jul 16 05:10:25 PM PDT 24
Peak memory 195076 kb
Host smart-c9930cb4-3925-4538-9d32-417f20fb296c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271831049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.271831049
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4153296840
Short name T1282
Test name
Test status
Simulation time 25823490 ps
CPU time 0.71 seconds
Started Jul 16 05:10:13 PM PDT 24
Finished Jul 16 05:10:14 PM PDT 24
Peak memory 195640 kb
Host smart-26877ca4-7887-41cf-bb84-f1aa8649130e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153296840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4153296840
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1972652360
Short name T1184
Test name
Test status
Simulation time 294407183 ps
CPU time 2.6 seconds
Started Jul 16 05:10:02 PM PDT 24
Finished Jul 16 05:10:05 PM PDT 24
Peak memory 200588 kb
Host smart-63ef70f1-1565-4e9a-aba2-6bb1dac7ee41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972652360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1972652360
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1663300280
Short name T1290
Test name
Test status
Simulation time 40615798 ps
CPU time 0.93 seconds
Started Jul 16 05:10:05 PM PDT 24
Finished Jul 16 05:10:06 PM PDT 24
Peak memory 199384 kb
Host smart-04b08d00-d497-4139-a47c-e2bdec9f7283
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663300280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1663300280
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.3015972206
Short name T1120
Test name
Test status
Simulation time 15465320 ps
CPU time 0.63 seconds
Started Jul 16 04:56:26 PM PDT 24
Finished Jul 16 04:56:27 PM PDT 24
Peak memory 195496 kb
Host smart-930d503b-e94d-4912-8b8e-a001c4a3e335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015972206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3015972206
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1023000439
Short name T942
Test name
Test status
Simulation time 24664366243 ps
CPU time 11.29 seconds
Started Jul 16 04:55:58 PM PDT 24
Finished Jul 16 04:56:15 PM PDT 24
Peak memory 199920 kb
Host smart-a33fa6ee-81d5-410a-88d4-0114053f80e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023000439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1023000439
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.342457455
Short name T43
Test name
Test status
Simulation time 97796284479 ps
CPU time 150.09 seconds
Started Jul 16 04:56:13 PM PDT 24
Finished Jul 16 04:58:44 PM PDT 24
Peak memory 199724 kb
Host smart-f99ec923-364c-4d0e-8d86-c7d1a1efbe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342457455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.342457455
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.844112853
Short name T1053
Test name
Test status
Simulation time 115175670885 ps
CPU time 46.18 seconds
Started Jul 16 04:56:14 PM PDT 24
Finished Jul 16 04:57:01 PM PDT 24
Peak memory 199688 kb
Host smart-74a641d6-8da7-4fff-8cfc-51ac1be5a824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844112853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.844112853
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.997684228
Short name T988
Test name
Test status
Simulation time 22972872183 ps
CPU time 11.7 seconds
Started Jul 16 04:56:17 PM PDT 24
Finished Jul 16 04:56:29 PM PDT 24
Peak memory 200092 kb
Host smart-671f2db3-e6ab-4903-9e41-5391eb65e256
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997684228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.997684228
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.316787204
Short name T1088
Test name
Test status
Simulation time 99188521956 ps
CPU time 708.96 seconds
Started Jul 16 04:56:32 PM PDT 24
Finished Jul 16 05:08:23 PM PDT 24
Peak memory 199856 kb
Host smart-840fe58d-077f-489c-90a4-b084d0e71737
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=316787204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.316787204
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3702949964
Short name T783
Test name
Test status
Simulation time 5976336708 ps
CPU time 7.62 seconds
Started Jul 16 04:56:31 PM PDT 24
Finished Jul 16 04:56:41 PM PDT 24
Peak memory 199552 kb
Host smart-06ab4759-4db9-41ec-9d3c-1ce4cc9a3a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702949964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3702949964
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1430714887
Short name T1145
Test name
Test status
Simulation time 38895536126 ps
CPU time 65.91 seconds
Started Jul 16 04:57:21 PM PDT 24
Finished Jul 16 04:58:28 PM PDT 24
Peak memory 199944 kb
Host smart-b949c6da-2c29-419c-a945-80a069157d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430714887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1430714887
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2029483969
Short name T995
Test name
Test status
Simulation time 6997817742 ps
CPU time 87.69 seconds
Started Jul 16 04:56:31 PM PDT 24
Finished Jul 16 04:58:00 PM PDT 24
Peak memory 199752 kb
Host smart-8375bf7d-2a9e-48f8-a5d2-ac141d1b1870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029483969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2029483969
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1099536616
Short name T556
Test name
Test status
Simulation time 5054142049 ps
CPU time 9.43 seconds
Started Jul 16 04:56:18 PM PDT 24
Finished Jul 16 04:56:28 PM PDT 24
Peak memory 198092 kb
Host smart-aa604e69-0762-405b-a37e-dbf21cf1ae00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1099536616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1099536616
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2903570839
Short name T120
Test name
Test status
Simulation time 123611592241 ps
CPU time 54.6 seconds
Started Jul 16 04:56:17 PM PDT 24
Finished Jul 16 04:57:13 PM PDT 24
Peak memory 199752 kb
Host smart-643dec4a-c9a8-45c0-b06d-1f0d927d8cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903570839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2903570839
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3774194511
Short name T622
Test name
Test status
Simulation time 5387419938 ps
CPU time 4.33 seconds
Started Jul 16 04:56:04 PM PDT 24
Finished Jul 16 04:56:12 PM PDT 24
Peak memory 196548 kb
Host smart-62dcb2ce-9491-4714-bbed-8c742d4389bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774194511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3774194511
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3604756588
Short name T927
Test name
Test status
Simulation time 10573907264 ps
CPU time 40.8 seconds
Started Jul 16 04:56:26 PM PDT 24
Finished Jul 16 04:57:07 PM PDT 24
Peak memory 199740 kb
Host smart-2c2680ac-de23-40e3-b817-bffc75c00f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604756588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3604756588
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3807014535
Short name T883
Test name
Test status
Simulation time 297065316271 ps
CPU time 586.93 seconds
Started Jul 16 04:56:22 PM PDT 24
Finished Jul 16 05:06:10 PM PDT 24
Peak memory 199740 kb
Host smart-957c21ce-88fe-4afd-91c4-8a2335501680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807014535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3807014535
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2320872444
Short name T786
Test name
Test status
Simulation time 56422496882 ps
CPU time 536.55 seconds
Started Jul 16 04:56:43 PM PDT 24
Finished Jul 16 05:05:40 PM PDT 24
Peak memory 216356 kb
Host smart-da97027e-fa3b-445c-a368-32b7ede7216c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320872444 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2320872444
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.632923144
Short name T382
Test name
Test status
Simulation time 8013548102 ps
CPU time 8.85 seconds
Started Jul 16 04:56:23 PM PDT 24
Finished Jul 16 04:56:33 PM PDT 24
Peak memory 199732 kb
Host smart-cb57db1b-3bf0-487c-8c99-fd8cd66cfd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632923144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.632923144
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2047288041
Short name T407
Test name
Test status
Simulation time 106846958630 ps
CPU time 41.37 seconds
Started Jul 16 04:56:04 PM PDT 24
Finished Jul 16 04:56:53 PM PDT 24
Peak memory 199752 kb
Host smart-f3e5c553-bcc4-476c-8d9f-a3ce703b995b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047288041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2047288041
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1251881941
Short name T632
Test name
Test status
Simulation time 78755382 ps
CPU time 0.56 seconds
Started Jul 16 04:56:26 PM PDT 24
Finished Jul 16 04:56:27 PM PDT 24
Peak memory 195128 kb
Host smart-cd081de9-2fea-4eda-97da-0e4056374cfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251881941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1251881941
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.905510045
Short name T806
Test name
Test status
Simulation time 76643826727 ps
CPU time 58.8 seconds
Started Jul 16 04:56:31 PM PDT 24
Finished Jul 16 04:57:31 PM PDT 24
Peak memory 199736 kb
Host smart-f05fc123-1453-4180-afab-77fe1466e05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905510045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.905510045
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.865081246
Short name T417
Test name
Test status
Simulation time 104396045409 ps
CPU time 75.82 seconds
Started Jul 16 04:56:22 PM PDT 24
Finished Jul 16 04:57:39 PM PDT 24
Peak memory 199740 kb
Host smart-7a62f92a-7477-4d5a-96a6-e1857535f5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865081246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.865081246
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3735680325
Short name T219
Test name
Test status
Simulation time 225149083387 ps
CPU time 95.3 seconds
Started Jul 16 04:56:30 PM PDT 24
Finished Jul 16 04:58:07 PM PDT 24
Peak memory 199748 kb
Host smart-f67fc7b8-f148-4245-80fa-a71a614e3a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735680325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3735680325
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3446626342
Short name T355
Test name
Test status
Simulation time 184375246046 ps
CPU time 39.54 seconds
Started Jul 16 04:56:19 PM PDT 24
Finished Jul 16 04:57:00 PM PDT 24
Peak memory 196964 kb
Host smart-58113575-26df-4765-a45f-10f67648dee3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446626342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3446626342
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2138560266
Short name T1156
Test name
Test status
Simulation time 168823083042 ps
CPU time 594.29 seconds
Started Jul 16 04:56:30 PM PDT 24
Finished Jul 16 05:06:25 PM PDT 24
Peak memory 199760 kb
Host smart-92b0ad1b-5bed-4d92-8d0f-faa0d89333c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138560266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2138560266
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.690244386
Short name T664
Test name
Test status
Simulation time 6809082579 ps
CPU time 10.48 seconds
Started Jul 16 04:56:27 PM PDT 24
Finished Jul 16 04:56:38 PM PDT 24
Peak memory 198636 kb
Host smart-48787d21-d84d-4eb4-80b3-8a19a8c2f3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690244386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.690244386
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3229214810
Short name T1160
Test name
Test status
Simulation time 16384988884 ps
CPU time 21.99 seconds
Started Jul 16 04:56:28 PM PDT 24
Finished Jul 16 04:56:51 PM PDT 24
Peak memory 199936 kb
Host smart-1106071c-dc45-489c-89a7-fb424bdecbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229214810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3229214810
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1646096285
Short name T1034
Test name
Test status
Simulation time 8892747828 ps
CPU time 471.56 seconds
Started Jul 16 04:56:22 PM PDT 24
Finished Jul 16 05:04:14 PM PDT 24
Peak memory 199672 kb
Host smart-8c237c0d-34f0-4ab0-93b4-efd6623a2621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646096285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1646096285
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2168328151
Short name T597
Test name
Test status
Simulation time 5556902072 ps
CPU time 11.39 seconds
Started Jul 16 04:56:35 PM PDT 24
Finished Jul 16 04:56:47 PM PDT 24
Peak memory 197916 kb
Host smart-81d32ce4-6b1c-49e6-8237-746f7ec5be52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168328151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2168328151
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2773061562
Short name T926
Test name
Test status
Simulation time 175154097673 ps
CPU time 26.61 seconds
Started Jul 16 04:56:20 PM PDT 24
Finished Jul 16 04:56:48 PM PDT 24
Peak memory 199620 kb
Host smart-a66ee891-4fc3-4814-8def-b188cfbb765b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773061562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2773061562
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.776886266
Short name T847
Test name
Test status
Simulation time 5987227370 ps
CPU time 2.45 seconds
Started Jul 16 04:56:32 PM PDT 24
Finished Jul 16 04:56:36 PM PDT 24
Peak memory 196528 kb
Host smart-4d65de02-49f3-4695-b96e-7df7474ec83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776886266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.776886266
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3010383353
Short name T30
Test name
Test status
Simulation time 65533344 ps
CPU time 0.85 seconds
Started Jul 16 04:56:21 PM PDT 24
Finished Jul 16 04:56:23 PM PDT 24
Peak memory 218120 kb
Host smart-aaec5c6a-58be-4f2c-b15c-2a1c03631d03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010383353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3010383353
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.745884621
Short name T115
Test name
Test status
Simulation time 6367349604 ps
CPU time 6.36 seconds
Started Jul 16 04:56:24 PM PDT 24
Finished Jul 16 04:56:31 PM PDT 24
Peak memory 199404 kb
Host smart-9f981d74-43a0-4cc5-ba59-a0d9a705bedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745884621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.745884621
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1520442832
Short name T600
Test name
Test status
Simulation time 248818251336 ps
CPU time 225.75 seconds
Started Jul 16 04:56:20 PM PDT 24
Finished Jul 16 05:00:07 PM PDT 24
Peak memory 210700 kb
Host smart-07120731-49f0-4d93-8311-855aef0e61cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520442832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1520442832
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1607081909
Short name T666
Test name
Test status
Simulation time 7964697985 ps
CPU time 10.49 seconds
Started Jul 16 04:56:32 PM PDT 24
Finished Jul 16 04:56:44 PM PDT 24
Peak memory 199848 kb
Host smart-fc6c6444-e917-43ca-9b6c-02d346700f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607081909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1607081909
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2201849316
Short name T429
Test name
Test status
Simulation time 150603759759 ps
CPU time 98.98 seconds
Started Jul 16 04:56:10 PM PDT 24
Finished Jul 16 04:57:49 PM PDT 24
Peak memory 199724 kb
Host smart-6dccc609-afde-44ec-9d51-08c0349eba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201849316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2201849316
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3030969334
Short name T824
Test name
Test status
Simulation time 130717661 ps
CPU time 0.55 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 04:56:49 PM PDT 24
Peak memory 195096 kb
Host smart-a3a4587f-8cf5-42f9-931c-fd2365e12797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030969334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3030969334
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3918966530
Short name T1003
Test name
Test status
Simulation time 122081774349 ps
CPU time 82.06 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 04:58:12 PM PDT 24
Peak memory 199592 kb
Host smart-cff5437e-97a5-4835-b04e-6d59d1d4c3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918966530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3918966530
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2067423205
Short name T638
Test name
Test status
Simulation time 34386240322 ps
CPU time 8.59 seconds
Started Jul 16 04:56:38 PM PDT 24
Finished Jul 16 04:56:48 PM PDT 24
Peak memory 199804 kb
Host smart-f85dd84e-eba4-43de-a255-709e75c18efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067423205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2067423205
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2752239201
Short name T318
Test name
Test status
Simulation time 170033395260 ps
CPU time 131.64 seconds
Started Jul 16 04:56:51 PM PDT 24
Finished Jul 16 04:59:04 PM PDT 24
Peak memory 198816 kb
Host smart-d1906fe7-9af9-4dbf-8aa7-6d55ee19f38e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752239201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2752239201
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.841977879
Short name T257
Test name
Test status
Simulation time 65609674009 ps
CPU time 391.46 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 05:03:21 PM PDT 24
Peak memory 199728 kb
Host smart-785ae4fd-603c-4836-8799-6065396597f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841977879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.841977879
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3726505793
Short name T672
Test name
Test status
Simulation time 5030079086 ps
CPU time 3.37 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:56:55 PM PDT 24
Peak memory 199428 kb
Host smart-502d57dc-cd18-4203-9ecd-4b9d2e712ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726505793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3726505793
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1495814615
Short name T938
Test name
Test status
Simulation time 70493761891 ps
CPU time 81.48 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 04:58:07 PM PDT 24
Peak memory 200024 kb
Host smart-1f81e110-df6c-4113-9602-a6f6d42b5f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495814615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1495814615
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3976362715
Short name T503
Test name
Test status
Simulation time 18105862131 ps
CPU time 283.97 seconds
Started Jul 16 04:56:39 PM PDT 24
Finished Jul 16 05:01:24 PM PDT 24
Peak memory 199732 kb
Host smart-47025258-bf67-43d3-af00-eeb6aca69141
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3976362715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3976362715
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3913870012
Short name T22
Test name
Test status
Simulation time 6927478681 ps
CPU time 50.84 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 04:57:41 PM PDT 24
Peak memory 197972 kb
Host smart-411831c5-dae2-4e6f-ab67-16d05d12d2a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913870012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3913870012
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.496086840
Short name T961
Test name
Test status
Simulation time 84414992121 ps
CPU time 131.52 seconds
Started Jul 16 04:56:37 PM PDT 24
Finished Jul 16 04:58:49 PM PDT 24
Peak memory 199812 kb
Host smart-8b76a511-0642-45d8-afb3-85889d878b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496086840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.496086840
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.647301865
Short name T591
Test name
Test status
Simulation time 2212428509 ps
CPU time 3.71 seconds
Started Jul 16 04:57:15 PM PDT 24
Finished Jul 16 04:57:20 PM PDT 24
Peak memory 195320 kb
Host smart-ee14ea61-70d4-4d1c-8d60-5f2f1520181a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647301865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.647301865
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2812774865
Short name T433
Test name
Test status
Simulation time 5905726040 ps
CPU time 17.19 seconds
Started Jul 16 04:56:45 PM PDT 24
Finished Jul 16 04:57:03 PM PDT 24
Peak memory 199780 kb
Host smart-8fe8c292-623e-4e08-8c18-9769086ecdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812774865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2812774865
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.92716271
Short name T797
Test name
Test status
Simulation time 235588792856 ps
CPU time 405.72 seconds
Started Jul 16 04:56:40 PM PDT 24
Finished Jul 16 05:03:27 PM PDT 24
Peak memory 199664 kb
Host smart-58698f5d-43a0-4f7e-8c44-1747e7a26f38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92716271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.92716271
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1302094573
Short name T60
Test name
Test status
Simulation time 30971016890 ps
CPU time 616.23 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 05:07:07 PM PDT 24
Peak memory 215332 kb
Host smart-83bd6d1c-6f38-4835-ac2a-c7b43069d7ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302094573 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1302094573
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2405396859
Short name T575
Test name
Test status
Simulation time 2520273755 ps
CPU time 1.84 seconds
Started Jul 16 04:56:39 PM PDT 24
Finished Jul 16 04:56:42 PM PDT 24
Peak memory 199700 kb
Host smart-a20ad91d-bedd-479e-86ab-7b6f32186360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405396859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2405396859
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3816041671
Short name T827
Test name
Test status
Simulation time 128527805490 ps
CPU time 48.48 seconds
Started Jul 16 04:56:51 PM PDT 24
Finished Jul 16 04:57:41 PM PDT 24
Peak memory 199792 kb
Host smart-274f9200-69cf-444c-844c-031f5defa2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816041671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3816041671
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.629771837
Short name T920
Test name
Test status
Simulation time 9562587252 ps
CPU time 7.26 seconds
Started Jul 16 04:59:30 PM PDT 24
Finished Jul 16 04:59:38 PM PDT 24
Peak memory 199576 kb
Host smart-a31bd8e2-8d55-462e-b0f0-2632ea44a0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629771837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.629771837
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1747562312
Short name T375
Test name
Test status
Simulation time 88203922907 ps
CPU time 132.26 seconds
Started Jul 16 04:59:35 PM PDT 24
Finished Jul 16 05:01:48 PM PDT 24
Peak memory 199800 kb
Host smart-f8a30a65-0b1c-4afa-9d4d-6fc3cd5aecd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747562312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1747562312
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3693019430
Short name T319
Test name
Test status
Simulation time 19108874816 ps
CPU time 37.38 seconds
Started Jul 16 04:59:28 PM PDT 24
Finished Jul 16 05:00:06 PM PDT 24
Peak memory 199756 kb
Host smart-6142a529-023c-42fa-a3e6-dd4bcec1671b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693019430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3693019430
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2235439925
Short name T986
Test name
Test status
Simulation time 71749897755 ps
CPU time 13.26 seconds
Started Jul 16 04:59:30 PM PDT 24
Finished Jul 16 04:59:44 PM PDT 24
Peak memory 199792 kb
Host smart-b35f1bdb-fad9-4c89-8b77-a784e2120807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235439925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2235439925
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1462007708
Short name T887
Test name
Test status
Simulation time 141454851232 ps
CPU time 198.13 seconds
Started Jul 16 04:59:35 PM PDT 24
Finished Jul 16 05:02:53 PM PDT 24
Peak memory 199672 kb
Host smart-00c7b527-53bf-456c-97e7-c5191ca14e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462007708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1462007708
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.898758654
Short name T682
Test name
Test status
Simulation time 34039346282 ps
CPU time 18.56 seconds
Started Jul 16 04:59:30 PM PDT 24
Finished Jul 16 04:59:50 PM PDT 24
Peak memory 199852 kb
Host smart-f3f53ba7-e528-40e0-9986-90149a4255c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898758654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.898758654
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1682755487
Short name T478
Test name
Test status
Simulation time 12465035395 ps
CPU time 11.56 seconds
Started Jul 16 04:59:34 PM PDT 24
Finished Jul 16 04:59:46 PM PDT 24
Peak memory 199876 kb
Host smart-c0da7b52-df1e-421e-bb93-53b168c93162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682755487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1682755487
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2372259756
Short name T623
Test name
Test status
Simulation time 19957104704 ps
CPU time 27.31 seconds
Started Jul 16 04:59:41 PM PDT 24
Finished Jul 16 05:00:09 PM PDT 24
Peak memory 199812 kb
Host smart-2c6747b7-64d8-4757-8ff0-2af996602ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372259756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2372259756
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.991105932
Short name T508
Test name
Test status
Simulation time 87224357861 ps
CPU time 63.2 seconds
Started Jul 16 04:59:29 PM PDT 24
Finished Jul 16 05:00:34 PM PDT 24
Peak memory 199784 kb
Host smart-9e2d2ec8-0902-4448-a0f9-dac51f720994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991105932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.991105932
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.6481722
Short name T238
Test name
Test status
Simulation time 104534924374 ps
CPU time 144.6 seconds
Started Jul 16 04:59:32 PM PDT 24
Finished Jul 16 05:01:58 PM PDT 24
Peak memory 199820 kb
Host smart-7d721506-69d8-46b6-92e5-ac5ffa6bd9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6481722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.6481722
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2984056041
Short name T465
Test name
Test status
Simulation time 11869005 ps
CPU time 0.56 seconds
Started Jul 16 04:56:52 PM PDT 24
Finished Jul 16 04:56:53 PM PDT 24
Peak memory 195048 kb
Host smart-f53c74e1-33c8-49d6-bb83-272feb13345d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984056041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2984056041
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3036706610
Short name T92
Test name
Test status
Simulation time 42782549961 ps
CPU time 22.61 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 04:57:16 PM PDT 24
Peak memory 199728 kb
Host smart-1ecd8d9b-3e16-4027-b4ae-0b2e80dd297c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036706610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3036706610
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.165328013
Short name T1020
Test name
Test status
Simulation time 14944120830 ps
CPU time 13.04 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 04:57:02 PM PDT 24
Peak memory 199344 kb
Host smart-98067572-4b26-40de-a431-cd1ca6a3d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165328013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.165328013
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.2426973780
Short name T1098
Test name
Test status
Simulation time 63495490750 ps
CPU time 104.17 seconds
Started Jul 16 04:57:08 PM PDT 24
Finished Jul 16 04:58:53 PM PDT 24
Peak memory 199852 kb
Host smart-707d59ab-e5ae-4e73-a457-dd19030d1c40
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426973780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2426973780
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2943055054
Short name T1127
Test name
Test status
Simulation time 245545308460 ps
CPU time 743.6 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 05:09:35 PM PDT 24
Peak memory 199824 kb
Host smart-ba6ec4d8-94e9-45ec-9127-c9a6eb3ab5ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943055054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2943055054
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1666710916
Short name T386
Test name
Test status
Simulation time 7000147073 ps
CPU time 6.15 seconds
Started Jul 16 04:56:50 PM PDT 24
Finished Jul 16 04:56:58 PM PDT 24
Peak memory 198080 kb
Host smart-73843921-b1f2-455c-abdc-cb6f92357f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666710916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1666710916
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.518308750
Short name T760
Test name
Test status
Simulation time 131716620699 ps
CPU time 290.69 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 05:01:42 PM PDT 24
Peak memory 208320 kb
Host smart-ab13da93-0ffa-48f9-9b67-5578114ba4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518308750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.518308750
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1577662677
Short name T261
Test name
Test status
Simulation time 24571952119 ps
CPU time 504.9 seconds
Started Jul 16 04:57:00 PM PDT 24
Finished Jul 16 05:05:27 PM PDT 24
Peak memory 199780 kb
Host smart-cf7b8919-846d-4fb5-8a24-1a98c60269e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577662677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1577662677
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2137108403
Short name T1011
Test name
Test status
Simulation time 5828263001 ps
CPU time 50.31 seconds
Started Jul 16 04:57:04 PM PDT 24
Finished Jul 16 04:57:55 PM PDT 24
Peak memory 199004 kb
Host smart-e19a5e61-832e-451c-882d-772d106bd38f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137108403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2137108403
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2502519394
Short name T719
Test name
Test status
Simulation time 78282621063 ps
CPU time 114.33 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:58:42 PM PDT 24
Peak memory 199792 kb
Host smart-eafb0626-2b4d-4863-9cfc-85c3b182b094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502519394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2502519394
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3127798089
Short name T424
Test name
Test status
Simulation time 4621261598 ps
CPU time 8.13 seconds
Started Jul 16 04:57:12 PM PDT 24
Finished Jul 16 04:57:21 PM PDT 24
Peak memory 195880 kb
Host smart-b30f1410-9b60-4f33-9dbb-83c3fbd84ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127798089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3127798089
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.360894440
Short name T999
Test name
Test status
Simulation time 6200410253 ps
CPU time 8.59 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:57:00 PM PDT 24
Peak memory 199452 kb
Host smart-8a8f499f-2cb9-47fd-81fa-5e9ccd5a798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360894440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.360894440
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2453476899
Short name T93
Test name
Test status
Simulation time 104609382110 ps
CPU time 496.27 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 05:05:04 PM PDT 24
Peak memory 199720 kb
Host smart-57e02bd9-e34c-4ea8-a02e-ef161303ee13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453476899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2453476899
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.329928054
Short name T1101
Test name
Test status
Simulation time 102042879714 ps
CPU time 296.81 seconds
Started Jul 16 04:56:50 PM PDT 24
Finished Jul 16 05:01:49 PM PDT 24
Peak memory 216600 kb
Host smart-88bb3895-399e-4107-b806-ead727597363
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329928054 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.329928054
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1596172828
Short name T694
Test name
Test status
Simulation time 1948111422 ps
CPU time 1.68 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:56:49 PM PDT 24
Peak memory 198656 kb
Host smart-7d703f03-f0f5-4f17-917f-ff26e58613a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596172828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1596172828
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3484416159
Short name T792
Test name
Test status
Simulation time 39046182648 ps
CPU time 67.47 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 04:57:56 PM PDT 24
Peak memory 199804 kb
Host smart-1f96ceac-a4a3-4f77-b529-f2710b242f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484416159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3484416159
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.915261797
Short name T1092
Test name
Test status
Simulation time 104341365217 ps
CPU time 85.85 seconds
Started Jul 16 04:59:32 PM PDT 24
Finished Jul 16 05:00:59 PM PDT 24
Peak memory 199588 kb
Host smart-d82ff668-aa1a-4388-a432-1b979563a5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915261797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.915261797
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3343919629
Short name T731
Test name
Test status
Simulation time 62902383085 ps
CPU time 95.14 seconds
Started Jul 16 04:59:40 PM PDT 24
Finished Jul 16 05:01:16 PM PDT 24
Peak memory 199760 kb
Host smart-8f34ed02-5f1f-4d7c-9421-4fc096640e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343919629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3343919629
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1516618761
Short name T558
Test name
Test status
Simulation time 94111534971 ps
CPU time 270.07 seconds
Started Jul 16 04:59:29 PM PDT 24
Finished Jul 16 05:04:00 PM PDT 24
Peak memory 199816 kb
Host smart-15c7a5dd-84f5-41cc-bdc8-f6e456799b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516618761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1516618761
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2085775847
Short name T286
Test name
Test status
Simulation time 163415753874 ps
CPU time 64.72 seconds
Started Jul 16 04:59:37 PM PDT 24
Finished Jul 16 05:00:42 PM PDT 24
Peak memory 199768 kb
Host smart-624be9ce-887d-4dc7-a5cc-c408f7761a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085775847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2085775847
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1632231072
Short name T1015
Test name
Test status
Simulation time 121219751886 ps
CPU time 70.58 seconds
Started Jul 16 04:59:30 PM PDT 24
Finished Jul 16 05:00:42 PM PDT 24
Peak memory 199780 kb
Host smart-49b3baf7-9894-4197-a6cb-23633143196f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632231072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1632231072
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3570551403
Short name T1168
Test name
Test status
Simulation time 34473460400 ps
CPU time 12.19 seconds
Started Jul 16 04:59:42 PM PDT 24
Finished Jul 16 04:59:55 PM PDT 24
Peak memory 199804 kb
Host smart-494515fc-a9d1-4d12-a68c-528bd1df4b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570551403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3570551403
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.441962065
Short name T1060
Test name
Test status
Simulation time 29094986475 ps
CPU time 46.78 seconds
Started Jul 16 04:59:41 PM PDT 24
Finished Jul 16 05:00:29 PM PDT 24
Peak memory 199756 kb
Host smart-6eb015f5-79df-4039-86da-0db27ae8a013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441962065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.441962065
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.4264607170
Short name T818
Test name
Test status
Simulation time 18415434 ps
CPU time 0.57 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 04:56:50 PM PDT 24
Peak memory 195128 kb
Host smart-9e785cc1-67de-4908-8b72-3f4ae523e9d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264607170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4264607170
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.965983639
Short name T329
Test name
Test status
Simulation time 34801957170 ps
CPU time 49.04 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 04:57:39 PM PDT 24
Peak memory 199772 kb
Host smart-eda32c07-a7cb-4030-b481-35b5168d075e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965983639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.965983639
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.935966028
Short name T1008
Test name
Test status
Simulation time 367423314152 ps
CPU time 46.47 seconds
Started Jul 16 04:56:52 PM PDT 24
Finished Jul 16 04:57:39 PM PDT 24
Peak memory 199816 kb
Host smart-242db690-bbc0-42f5-a848-42931c5ee02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935966028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.935966028
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.4186606457
Short name T15
Test name
Test status
Simulation time 9828829895 ps
CPU time 11.55 seconds
Started Jul 16 04:56:50 PM PDT 24
Finished Jul 16 04:57:04 PM PDT 24
Peak memory 199784 kb
Host smart-5ccaecef-0fb7-4f25-8800-7d6ca2af0d54
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186606457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.4186606457
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3780053638
Short name T640
Test name
Test status
Simulation time 149809871431 ps
CPU time 848.14 seconds
Started Jul 16 04:57:03 PM PDT 24
Finished Jul 16 05:11:13 PM PDT 24
Peak memory 199888 kb
Host smart-b519c231-6bbe-4809-91fc-7ca705560cb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3780053638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3780053638
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2414794069
Short name T331
Test name
Test status
Simulation time 2106810180 ps
CPU time 3.03 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 04:56:52 PM PDT 24
Peak memory 197928 kb
Host smart-dedf2ca8-0baf-42d2-bbb7-cf6abaac9e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414794069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2414794069
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.761840105
Short name T853
Test name
Test status
Simulation time 84188147775 ps
CPU time 71.67 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:58:03 PM PDT 24
Peak memory 199936 kb
Host smart-c1d3fd6a-243a-45e1-a473-8da298f2df86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761840105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.761840105
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3539579946
Short name T521
Test name
Test status
Simulation time 16250456742 ps
CPU time 245.37 seconds
Started Jul 16 04:56:55 PM PDT 24
Finished Jul 16 05:01:01 PM PDT 24
Peak memory 199816 kb
Host smart-ce0f1560-31a8-4e3d-a9d9-75a60b58a693
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539579946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3539579946
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2152473598
Short name T691
Test name
Test status
Simulation time 2357202874 ps
CPU time 4.5 seconds
Started Jul 16 04:56:50 PM PDT 24
Finished Jul 16 04:56:57 PM PDT 24
Peak memory 197612 kb
Host smart-ba68de8f-59d1-4eb6-827a-478a12d871ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2152473598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2152473598
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2972323274
Short name T752
Test name
Test status
Simulation time 10710874547 ps
CPU time 15.03 seconds
Started Jul 16 04:57:30 PM PDT 24
Finished Jul 16 04:57:46 PM PDT 24
Peak memory 198396 kb
Host smart-c95eb178-a09d-4966-818e-3d2028247c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972323274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2972323274
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2960419754
Short name T642
Test name
Test status
Simulation time 44947574622 ps
CPU time 18.64 seconds
Started Jul 16 04:57:12 PM PDT 24
Finished Jul 16 04:57:32 PM PDT 24
Peak memory 195716 kb
Host smart-3bbecc75-45e4-4d5e-81ca-5dd410ad7fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960419754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2960419754
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3691308518
Short name T438
Test name
Test status
Simulation time 975041043 ps
CPU time 4.99 seconds
Started Jul 16 04:56:53 PM PDT 24
Finished Jul 16 04:56:58 PM PDT 24
Peak memory 199344 kb
Host smart-0eba30af-4765-4ab6-a8cd-f28b2b27a3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691308518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3691308518
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1731987199
Short name T933
Test name
Test status
Simulation time 199569983477 ps
CPU time 112.65 seconds
Started Jul 16 04:56:50 PM PDT 24
Finished Jul 16 04:58:45 PM PDT 24
Peak memory 199728 kb
Host smart-a593a25e-b26b-4559-b77e-15e6e8971ed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731987199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1731987199
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3824529333
Short name T702
Test name
Test status
Simulation time 528537534697 ps
CPU time 1982.44 seconds
Started Jul 16 04:56:51 PM PDT 24
Finished Jul 16 05:29:55 PM PDT 24
Peak memory 224384 kb
Host smart-b8749a92-770a-4e0a-b5dd-c3250745d434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824529333 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3824529333
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3118282062
Short name T19
Test name
Test status
Simulation time 6425987448 ps
CPU time 11.75 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 04:57:02 PM PDT 24
Peak memory 199152 kb
Host smart-c807e1be-6ff0-42e0-9d73-4399735ad44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118282062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3118282062
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2901956896
Short name T730
Test name
Test status
Simulation time 62753238654 ps
CPU time 27.36 seconds
Started Jul 16 04:57:29 PM PDT 24
Finished Jul 16 04:57:57 PM PDT 24
Peak memory 199704 kb
Host smart-26ebf218-2010-49ba-90b0-e0f6ada52902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901956896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2901956896
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1773738781
Short name T224
Test name
Test status
Simulation time 41880324781 ps
CPU time 77.92 seconds
Started Jul 16 04:59:42 PM PDT 24
Finished Jul 16 05:01:01 PM PDT 24
Peak memory 199916 kb
Host smart-20a2d518-7193-4797-9464-4238993c858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773738781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1773738781
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.930234833
Short name T1179
Test name
Test status
Simulation time 43773874419 ps
CPU time 59.03 seconds
Started Jul 16 04:59:42 PM PDT 24
Finished Jul 16 05:00:42 PM PDT 24
Peak memory 199728 kb
Host smart-13fc3e52-efee-44c1-b1bf-0ffaea156075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930234833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.930234833
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3713435918
Short name T562
Test name
Test status
Simulation time 188545493920 ps
CPU time 25.54 seconds
Started Jul 16 04:59:40 PM PDT 24
Finished Jul 16 05:00:06 PM PDT 24
Peak memory 199712 kb
Host smart-0246b4a0-5212-4cd9-8b6b-6bb432f96a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713435918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3713435918
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1748078879
Short name T174
Test name
Test status
Simulation time 151535067846 ps
CPU time 66.68 seconds
Started Jul 16 04:59:43 PM PDT 24
Finished Jul 16 05:00:50 PM PDT 24
Peak memory 199908 kb
Host smart-0a926f3d-87ef-482f-b8d1-1918c07feb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748078879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1748078879
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.4237511029
Short name T788
Test name
Test status
Simulation time 195264085772 ps
CPU time 92.4 seconds
Started Jul 16 04:59:41 PM PDT 24
Finished Jul 16 05:01:15 PM PDT 24
Peak memory 199808 kb
Host smart-a96f8613-bf66-4f55-9418-a7c93483c0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237511029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.4237511029
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.513580034
Short name T1090
Test name
Test status
Simulation time 83191715765 ps
CPU time 221.44 seconds
Started Jul 16 04:59:41 PM PDT 24
Finished Jul 16 05:03:23 PM PDT 24
Peak memory 199792 kb
Host smart-f3accaa9-8f56-4106-ba3c-e4ab70b02fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513580034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.513580034
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.130869806
Short name T1166
Test name
Test status
Simulation time 113165612 ps
CPU time 0.55 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 04:56:49 PM PDT 24
Peak memory 194084 kb
Host smart-e9a8363b-e96b-4603-b4e3-ef6e17fea435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130869806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.130869806
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3215387081
Short name T1071
Test name
Test status
Simulation time 79225132582 ps
CPU time 132.2 seconds
Started Jul 16 04:56:52 PM PDT 24
Finished Jul 16 04:59:05 PM PDT 24
Peak memory 199732 kb
Host smart-9fefcb90-80b2-4f68-8864-8418dcee4bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215387081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3215387081
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.4131078357
Short name T1000
Test name
Test status
Simulation time 129012403131 ps
CPU time 213.66 seconds
Started Jul 16 04:56:58 PM PDT 24
Finished Jul 16 05:00:32 PM PDT 24
Peak memory 199600 kb
Host smart-a135ab22-28ad-46ab-a6f9-48ba5ca83d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131078357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.4131078357
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2973764878
Short name T253
Test name
Test status
Simulation time 151444142298 ps
CPU time 202.67 seconds
Started Jul 16 04:57:01 PM PDT 24
Finished Jul 16 05:00:25 PM PDT 24
Peak memory 199856 kb
Host smart-c47ffa32-703b-4245-9b9c-dd44b1af5bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973764878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2973764878
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2135586998
Short name T499
Test name
Test status
Simulation time 293350458238 ps
CPU time 405.13 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 05:03:33 PM PDT 24
Peak memory 198036 kb
Host smart-3552a0f1-bd0d-46d2-b4c1-9202ffc94bc7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135586998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2135586998
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1512896769
Short name T436
Test name
Test status
Simulation time 104718074841 ps
CPU time 362.79 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 05:02:52 PM PDT 24
Peak memory 199812 kb
Host smart-daf8fba7-44e8-4dc7-9d27-d8335186a63f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1512896769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1512896769
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3280873663
Short name T848
Test name
Test status
Simulation time 5779718530 ps
CPU time 3.53 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 04:56:53 PM PDT 24
Peak memory 198324 kb
Host smart-9198983f-b6c0-4923-b343-b540841abc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280873663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3280873663
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2571973266
Short name T450
Test name
Test status
Simulation time 125567220467 ps
CPU time 230.83 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 05:00:39 PM PDT 24
Peak memory 199784 kb
Host smart-ef22084b-e05d-4ee0-b16e-8a1292be5178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571973266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2571973266
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1324783206
Short name T7
Test name
Test status
Simulation time 11089566452 ps
CPU time 441.76 seconds
Started Jul 16 04:56:52 PM PDT 24
Finished Jul 16 05:04:15 PM PDT 24
Peak memory 199760 kb
Host smart-bdc4b1e9-104c-4007-8c3e-63c0ba4b727d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324783206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1324783206
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.4142923368
Short name T915
Test name
Test status
Simulation time 6899021605 ps
CPU time 53.89 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:57:41 PM PDT 24
Peak memory 198896 kb
Host smart-1ea19c59-1cb5-4050-9f0c-b1a21becc1bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142923368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.4142923368
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.257510572
Short name T928
Test name
Test status
Simulation time 30911129826 ps
CPU time 50.21 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:57:38 PM PDT 24
Peak memory 199740 kb
Host smart-13a9a551-aefc-40d1-8694-0088e29fd685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257510572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.257510572
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.755367590
Short name T867
Test name
Test status
Simulation time 1533150112 ps
CPU time 1.32 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:56:50 PM PDT 24
Peak memory 195244 kb
Host smart-4fcd16f2-5117-4866-8d03-8a5d75ce3c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755367590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.755367590
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.4254931624
Short name T586
Test name
Test status
Simulation time 5368385253 ps
CPU time 10.08 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:57:01 PM PDT 24
Peak memory 199640 kb
Host smart-a3930888-cb37-45a2-8352-765b16e2312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254931624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.4254931624
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.4217380190
Short name T157
Test name
Test status
Simulation time 163064216288 ps
CPU time 327.05 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 05:02:12 PM PDT 24
Peak memory 208056 kb
Host smart-6baf0406-54a0-4e96-b938-4dd0598e29a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217380190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.4217380190
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1600421618
Short name T1146
Test name
Test status
Simulation time 277891229251 ps
CPU time 726.13 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 05:08:57 PM PDT 24
Peak memory 224656 kb
Host smart-9bb37bf0-952e-4c91-9de6-a60469a7089f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600421618 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1600421618
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2894680858
Short name T470
Test name
Test status
Simulation time 977599029 ps
CPU time 5.6 seconds
Started Jul 16 04:56:50 PM PDT 24
Finished Jul 16 04:56:58 PM PDT 24
Peak memory 198208 kb
Host smart-51cb2773-7a8e-46dd-ab69-ac07e9f9de41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894680858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2894680858
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.698076267
Short name T260
Test name
Test status
Simulation time 40882230909 ps
CPU time 35.88 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:57:23 PM PDT 24
Peak memory 199712 kb
Host smart-5acfeb9d-fd47-4074-9d17-e29ee12846f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698076267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.698076267
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1499758790
Short name T313
Test name
Test status
Simulation time 89612279976 ps
CPU time 126.92 seconds
Started Jul 16 04:59:43 PM PDT 24
Finished Jul 16 05:01:50 PM PDT 24
Peak memory 199860 kb
Host smart-993eb7f0-de51-402c-8ee3-3c2143eb0b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499758790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1499758790
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2437792327
Short name T744
Test name
Test status
Simulation time 27126636160 ps
CPU time 39.5 seconds
Started Jul 16 04:59:40 PM PDT 24
Finished Jul 16 05:00:20 PM PDT 24
Peak memory 199712 kb
Host smart-6f151902-b28c-4677-85c5-1252a4795fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437792327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2437792327
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.4214752681
Short name T796
Test name
Test status
Simulation time 46628694285 ps
CPU time 186.3 seconds
Started Jul 16 04:59:43 PM PDT 24
Finished Jul 16 05:02:50 PM PDT 24
Peak memory 199756 kb
Host smart-6351a6a9-ffb9-4485-a5a7-dda43d326d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214752681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4214752681
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3630215829
Short name T136
Test name
Test status
Simulation time 46310515700 ps
CPU time 77.01 seconds
Started Jul 16 04:59:42 PM PDT 24
Finished Jul 16 05:01:00 PM PDT 24
Peak memory 199756 kb
Host smart-7f3b9490-ea4a-4aea-abe6-df3e82fbcdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630215829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3630215829
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3409235668
Short name T76
Test name
Test status
Simulation time 88888358687 ps
CPU time 30.83 seconds
Started Jul 16 04:59:41 PM PDT 24
Finished Jul 16 05:00:13 PM PDT 24
Peak memory 199712 kb
Host smart-e5f43e3a-f571-477c-b6ff-7147dcccfaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409235668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3409235668
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3970240099
Short name T869
Test name
Test status
Simulation time 77202461518 ps
CPU time 116.41 seconds
Started Jul 16 04:59:42 PM PDT 24
Finished Jul 16 05:01:40 PM PDT 24
Peak memory 199840 kb
Host smart-77315def-2ad7-41d1-bca1-edbe620bbf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970240099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3970240099
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2237497342
Short name T582
Test name
Test status
Simulation time 82730058187 ps
CPU time 16.87 seconds
Started Jul 16 04:59:42 PM PDT 24
Finished Jul 16 05:00:00 PM PDT 24
Peak memory 199548 kb
Host smart-547f6206-e356-460a-9cc2-febb83a68796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237497342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2237497342
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3087294241
Short name T567
Test name
Test status
Simulation time 30788513 ps
CPU time 0.53 seconds
Started Jul 16 04:56:53 PM PDT 24
Finished Jul 16 04:56:55 PM PDT 24
Peak memory 195096 kb
Host smart-5b2e995f-1180-4700-a792-56e59fed15fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087294241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3087294241
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.855057561
Short name T275
Test name
Test status
Simulation time 24579280143 ps
CPU time 31.48 seconds
Started Jul 16 04:56:55 PM PDT 24
Finished Jul 16 04:57:27 PM PDT 24
Peak memory 199856 kb
Host smart-eac4ba71-9236-4a05-a02c-df2c27c1a7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855057561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.855057561
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3685761156
Short name T728
Test name
Test status
Simulation time 42184029476 ps
CPU time 12.82 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:57:04 PM PDT 24
Peak memory 199752 kb
Host smart-27578151-995b-400c-b8d8-d2b826987532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685761156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3685761156
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.941189753
Short name T1085
Test name
Test status
Simulation time 38882974896 ps
CPU time 14.68 seconds
Started Jul 16 04:56:53 PM PDT 24
Finished Jul 16 04:57:08 PM PDT 24
Peak memory 199748 kb
Host smart-7e9d2e65-50e9-4792-99e6-d928ab6e9f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941189753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.941189753
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3366282092
Short name T742
Test name
Test status
Simulation time 55520187043 ps
CPU time 82.71 seconds
Started Jul 16 04:57:30 PM PDT 24
Finished Jul 16 04:58:53 PM PDT 24
Peak memory 199328 kb
Host smart-460a8c34-7519-4dbf-99da-928becde03c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366282092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3366282092
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.100372706
Short name T762
Test name
Test status
Simulation time 175045810337 ps
CPU time 780.47 seconds
Started Jul 16 04:57:40 PM PDT 24
Finished Jul 16 05:10:41 PM PDT 24
Peak memory 199700 kb
Host smart-8a557902-37ae-4897-8572-9283d88087b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100372706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.100372706
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2574137576
Short name T662
Test name
Test status
Simulation time 8392604941 ps
CPU time 27.57 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 04:57:17 PM PDT 24
Peak memory 199768 kb
Host smart-1992518b-f500-4786-bdc5-004dc617336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574137576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2574137576
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.418427683
Short name T352
Test name
Test status
Simulation time 80315414880 ps
CPU time 86.56 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:58:18 PM PDT 24
Peak memory 199836 kb
Host smart-bc08870c-ff2c-4a9e-86b5-1e4ac1a79ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418427683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.418427683
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2826397788
Short name T820
Test name
Test status
Simulation time 14637246995 ps
CPU time 149.54 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:59:21 PM PDT 24
Peak memory 199848 kb
Host smart-63b30d2f-4f25-4296-9d5c-3304296eb623
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2826397788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2826397788
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.4034140539
Short name T605
Test name
Test status
Simulation time 2326258110 ps
CPU time 7.25 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 04:56:58 PM PDT 24
Peak memory 198776 kb
Host smart-dbf30325-2f78-4d08-9854-42510274afb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034140539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.4034140539
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.767197617
Short name T1140
Test name
Test status
Simulation time 37093479009 ps
CPU time 26.99 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:57:18 PM PDT 24
Peak memory 198068 kb
Host smart-6c7a1940-d851-4bc4-811a-62acd7d41fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767197617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.767197617
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.967662737
Short name T1171
Test name
Test status
Simulation time 3816854783 ps
CPU time 1.78 seconds
Started Jul 16 04:57:39 PM PDT 24
Finished Jul 16 04:57:42 PM PDT 24
Peak memory 196560 kb
Host smart-d19821e0-8e9f-406c-a1cc-bda4f0828d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967662737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.967662737
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2334168978
Short name T51
Test name
Test status
Simulation time 685616380 ps
CPU time 1.86 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:56:53 PM PDT 24
Peak memory 199180 kb
Host smart-e0235daa-a098-46da-ba8c-dee04c768fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334168978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2334168978
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3574004519
Short name T655
Test name
Test status
Simulation time 368449522594 ps
CPU time 165.88 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 04:59:36 PM PDT 24
Peak memory 199892 kb
Host smart-6957ac46-005f-41a1-8f3f-fc8da7b12d27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574004519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3574004519
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3519175335
Short name T107
Test name
Test status
Simulation time 65306110863 ps
CPU time 204.61 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 05:00:15 PM PDT 24
Peak memory 208032 kb
Host smart-4482f852-40a8-45e8-be6a-2393e51cf447
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519175335 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3519175335
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3779673458
Short name T409
Test name
Test status
Simulation time 1864731418 ps
CPU time 2.04 seconds
Started Jul 16 04:57:30 PM PDT 24
Finished Jul 16 04:57:33 PM PDT 24
Peak memory 198516 kb
Host smart-cabdd310-0d4a-4583-bb21-1e8d60ff7a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779673458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3779673458
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3374251436
Short name T746
Test name
Test status
Simulation time 132674548473 ps
CPU time 167.44 seconds
Started Jul 16 04:56:47 PM PDT 24
Finished Jul 16 04:59:37 PM PDT 24
Peak memory 199620 kb
Host smart-56810d39-64df-4fd8-a82c-ab76bc5a4ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374251436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3374251436
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3502607059
Short name T223
Test name
Test status
Simulation time 35622897359 ps
CPU time 9.24 seconds
Started Jul 16 04:59:40 PM PDT 24
Finished Jul 16 04:59:50 PM PDT 24
Peak memory 200124 kb
Host smart-a75533f6-1b34-47ff-a009-655ec89432e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502607059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3502607059
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3288383684
Short name T1073
Test name
Test status
Simulation time 16410838473 ps
CPU time 26.09 seconds
Started Jul 16 04:59:54 PM PDT 24
Finished Jul 16 05:00:21 PM PDT 24
Peak memory 199708 kb
Host smart-3504a231-2672-4c20-bc7a-6bf808862d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288383684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3288383684
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.4148635035
Short name T207
Test name
Test status
Simulation time 47356857640 ps
CPU time 7.43 seconds
Started Jul 16 04:59:40 PM PDT 24
Finished Jul 16 04:59:48 PM PDT 24
Peak memory 199820 kb
Host smart-9450a129-4166-48ac-9d48-84bc103e6dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148635035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.4148635035
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.874988309
Short name T1129
Test name
Test status
Simulation time 33239297771 ps
CPU time 50.96 seconds
Started Jul 16 04:59:51 PM PDT 24
Finished Jul 16 05:00:42 PM PDT 24
Peak memory 199752 kb
Host smart-c96b361c-67ba-41cc-a61f-339d86e82341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874988309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.874988309
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3832945759
Short name T704
Test name
Test status
Simulation time 66534430817 ps
CPU time 201.67 seconds
Started Jul 16 04:59:41 PM PDT 24
Finished Jul 16 05:03:04 PM PDT 24
Peak memory 199696 kb
Host smart-ba647db4-a5a4-4940-97af-9fd3423bf10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832945759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3832945759
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3435254268
Short name T609
Test name
Test status
Simulation time 43530638795 ps
CPU time 17.68 seconds
Started Jul 16 04:59:40 PM PDT 24
Finished Jul 16 04:59:58 PM PDT 24
Peak memory 199768 kb
Host smart-60a599f9-f201-4527-9704-6c7ab0968284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435254268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3435254268
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.145644078
Short name T225
Test name
Test status
Simulation time 22437874420 ps
CPU time 32.25 seconds
Started Jul 16 04:59:50 PM PDT 24
Finished Jul 16 05:00:22 PM PDT 24
Peak memory 199692 kb
Host smart-ff5a2969-fb9b-4a9c-b11a-4a856f2ae94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145644078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.145644078
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.632926031
Short name T189
Test name
Test status
Simulation time 8388843747 ps
CPU time 13.17 seconds
Started Jul 16 04:59:40 PM PDT 24
Finished Jul 16 04:59:54 PM PDT 24
Peak memory 199720 kb
Host smart-9732c3df-3ac8-4e76-9373-fb1ec33a6ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632926031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.632926031
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2037482533
Short name T1009
Test name
Test status
Simulation time 15016257199 ps
CPU time 24.09 seconds
Started Jul 16 04:59:43 PM PDT 24
Finished Jul 16 05:00:08 PM PDT 24
Peak memory 199420 kb
Host smart-7def5a86-714a-4ed9-aece-5f46a3118620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037482533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2037482533
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3282376838
Short name T863
Test name
Test status
Simulation time 91142032 ps
CPU time 0.57 seconds
Started Jul 16 04:56:58 PM PDT 24
Finished Jul 16 04:56:59 PM PDT 24
Peak memory 195128 kb
Host smart-d9ff43d2-8dc5-4275-a08b-22a1eeba114c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282376838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3282376838
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2852930275
Short name T670
Test name
Test status
Simulation time 30941853772 ps
CPU time 44.09 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 04:57:56 PM PDT 24
Peak memory 199828 kb
Host smart-51664a20-fdeb-4d3f-a023-86f9477ddce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852930275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2852930275
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2699121316
Short name T498
Test name
Test status
Simulation time 178460583707 ps
CPU time 190.58 seconds
Started Jul 16 04:57:09 PM PDT 24
Finished Jul 16 05:00:21 PM PDT 24
Peak memory 199912 kb
Host smart-ede66ece-6d1e-4f58-a2ce-f59d0162ec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699121316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2699121316
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.406327617
Short name T353
Test name
Test status
Simulation time 30403811303 ps
CPU time 24.3 seconds
Started Jul 16 04:57:04 PM PDT 24
Finished Jul 16 04:57:30 PM PDT 24
Peak memory 199476 kb
Host smart-d5b1cbb1-1029-4fa2-8402-91cd5a13d64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406327617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.406327617
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.125810814
Short name T1130
Test name
Test status
Simulation time 31455555997 ps
CPU time 11.78 seconds
Started Jul 16 04:56:59 PM PDT 24
Finished Jul 16 04:57:12 PM PDT 24
Peak memory 197740 kb
Host smart-8a704ea4-03ba-4b17-a073-b5ed343e0e42
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125810814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.125810814
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3849101696
Short name T415
Test name
Test status
Simulation time 44437218633 ps
CPU time 240.44 seconds
Started Jul 16 04:56:57 PM PDT 24
Finished Jul 16 05:00:58 PM PDT 24
Peak memory 199736 kb
Host smart-8a9ab7dd-2f78-4ab2-a6d1-6b7ababaa387
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849101696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3849101696
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.459471289
Short name T408
Test name
Test status
Simulation time 6282521971 ps
CPU time 10.32 seconds
Started Jul 16 04:56:56 PM PDT 24
Finished Jul 16 04:57:07 PM PDT 24
Peak memory 198532 kb
Host smart-ac0da9e7-9c21-49c1-800b-ee5731f70470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459471289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.459471289
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.4286690348
Short name T611
Test name
Test status
Simulation time 202883488806 ps
CPU time 112.19 seconds
Started Jul 16 04:56:56 PM PDT 24
Finished Jul 16 04:58:49 PM PDT 24
Peak memory 199988 kb
Host smart-a303c174-5290-49cb-845e-8523e9fd58a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286690348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.4286690348
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3735458316
Short name T1119
Test name
Test status
Simulation time 28827291326 ps
CPU time 1664.55 seconds
Started Jul 16 04:56:59 PM PDT 24
Finished Jul 16 05:24:45 PM PDT 24
Peak memory 199756 kb
Host smart-7df6d4f8-6ec3-4fee-be52-ec91ee7b2ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3735458316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3735458316
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.231661342
Short name T517
Test name
Test status
Simulation time 5574828271 ps
CPU time 26.05 seconds
Started Jul 16 04:57:11 PM PDT 24
Finished Jul 16 04:57:39 PM PDT 24
Peak memory 198240 kb
Host smart-0523df98-8d74-4377-a7b0-6736d756866f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231661342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.231661342
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2470752098
Short name T1087
Test name
Test status
Simulation time 11404111242 ps
CPU time 20.15 seconds
Started Jul 16 04:57:00 PM PDT 24
Finished Jul 16 04:57:21 PM PDT 24
Peak memory 199692 kb
Host smart-b1e57100-d750-40df-9d32-f1797c8e2a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470752098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2470752098
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.221580432
Short name T383
Test name
Test status
Simulation time 2998695038 ps
CPU time 1.67 seconds
Started Jul 16 04:56:58 PM PDT 24
Finished Jul 16 04:57:01 PM PDT 24
Peak memory 196316 kb
Host smart-0941774f-489e-4110-92a9-f34059e730f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221580432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.221580432
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2285026429
Short name T837
Test name
Test status
Simulation time 307628692 ps
CPU time 1.57 seconds
Started Jul 16 04:56:58 PM PDT 24
Finished Jul 16 04:57:01 PM PDT 24
Peak memory 199628 kb
Host smart-3b478001-4033-44af-b7c7-30e7a5e8657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285026429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2285026429
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3302421758
Short name T881
Test name
Test status
Simulation time 249526038841 ps
CPU time 330.71 seconds
Started Jul 16 04:57:01 PM PDT 24
Finished Jul 16 05:02:33 PM PDT 24
Peak memory 199724 kb
Host smart-b3bba684-6410-4906-8bca-e12a0cd693a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302421758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3302421758
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3460849700
Short name T155
Test name
Test status
Simulation time 1459900662394 ps
CPU time 1019.41 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 05:14:11 PM PDT 24
Peak memory 224692 kb
Host smart-f6116520-8968-41c8-b3cb-2f91923b0aaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460849700 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3460849700
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.137663888
Short name T1066
Test name
Test status
Simulation time 614959184 ps
CPU time 3.25 seconds
Started Jul 16 04:56:59 PM PDT 24
Finished Jul 16 04:57:03 PM PDT 24
Peak memory 198588 kb
Host smart-833745fa-a127-43b8-bb52-02bcf50c940b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137663888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.137663888
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2705811526
Short name T982
Test name
Test status
Simulation time 113301860816 ps
CPU time 117.46 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:59:13 PM PDT 24
Peak memory 199696 kb
Host smart-f852180a-1b56-41b1-b9e3-a241d8b80cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705811526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2705811526
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1266880736
Short name T854
Test name
Test status
Simulation time 233103744876 ps
CPU time 40.97 seconds
Started Jul 16 04:59:42 PM PDT 24
Finished Jul 16 05:00:24 PM PDT 24
Peak memory 199632 kb
Host smart-d62846ae-3c56-4195-8350-16ea5232b6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266880736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1266880736
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.4161323803
Short name T698
Test name
Test status
Simulation time 108295492608 ps
CPU time 179.83 seconds
Started Jul 16 04:59:56 PM PDT 24
Finished Jul 16 05:02:56 PM PDT 24
Peak memory 199848 kb
Host smart-879a1ee6-52d1-464c-82d8-6e90733f8cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161323803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.4161323803
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2347386924
Short name T679
Test name
Test status
Simulation time 35641791278 ps
CPU time 34.3 seconds
Started Jul 16 04:59:53 PM PDT 24
Finished Jul 16 05:00:28 PM PDT 24
Peak memory 199824 kb
Host smart-eaf89663-1ee8-4a87-9b0d-3dfd6dfd6c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347386924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2347386924
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3116640104
Short name T243
Test name
Test status
Simulation time 10482225144 ps
CPU time 16.8 seconds
Started Jul 16 04:59:52 PM PDT 24
Finished Jul 16 05:00:09 PM PDT 24
Peak memory 199916 kb
Host smart-13372225-20f8-4978-bb6f-69311360c157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116640104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3116640104
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.192907421
Short name T768
Test name
Test status
Simulation time 212372182733 ps
CPU time 99.89 seconds
Started Jul 16 04:59:54 PM PDT 24
Finished Jul 16 05:01:34 PM PDT 24
Peak memory 199728 kb
Host smart-3871e79e-3bed-49d6-9003-e26dce37a81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192907421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.192907421
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1535391099
Short name T596
Test name
Test status
Simulation time 17951085221 ps
CPU time 8.05 seconds
Started Jul 16 04:59:55 PM PDT 24
Finished Jul 16 05:00:03 PM PDT 24
Peak memory 199732 kb
Host smart-1ca51e86-7fe7-49ff-a85b-85a5efff2db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535391099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1535391099
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3905912808
Short name T502
Test name
Test status
Simulation time 23723503 ps
CPU time 0.61 seconds
Started Jul 16 04:56:58 PM PDT 24
Finished Jul 16 04:57:00 PM PDT 24
Peak memory 195168 kb
Host smart-eeacc650-9689-44cb-8dc1-ca040b60beda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905912808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3905912808
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.483836994
Short name T941
Test name
Test status
Simulation time 24713319161 ps
CPU time 42.89 seconds
Started Jul 16 04:56:58 PM PDT 24
Finished Jul 16 04:57:42 PM PDT 24
Peak memory 199792 kb
Host smart-010d1844-5531-4e74-80e5-9e6cea231a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483836994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.483836994
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.344191552
Short name T182
Test name
Test status
Simulation time 35212121374 ps
CPU time 13.93 seconds
Started Jul 16 04:56:58 PM PDT 24
Finished Jul 16 04:57:13 PM PDT 24
Peak memory 199692 kb
Host smart-101f8e6c-fc53-46aa-b159-0f6d4c04f50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344191552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.344191552
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.239469696
Short name T217
Test name
Test status
Simulation time 111073835523 ps
CPU time 144.75 seconds
Started Jul 16 04:57:00 PM PDT 24
Finished Jul 16 04:59:26 PM PDT 24
Peak memory 199816 kb
Host smart-a43d78ac-1a3a-4b4b-a113-b64c0671e55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239469696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.239469696
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3026783470
Short name T635
Test name
Test status
Simulation time 46487765762 ps
CPU time 98.56 seconds
Started Jul 16 04:56:58 PM PDT 24
Finished Jul 16 04:58:43 PM PDT 24
Peak memory 199780 kb
Host smart-3749d2c6-5d62-42a3-824b-640d96d6f0e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026783470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3026783470
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2255863500
Short name T580
Test name
Test status
Simulation time 103477794269 ps
CPU time 428.74 seconds
Started Jul 16 04:57:04 PM PDT 24
Finished Jul 16 05:04:15 PM PDT 24
Peak memory 199760 kb
Host smart-5ef36e67-871d-48bb-b143-cea2b07e3c53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2255863500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2255863500
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2856098125
Short name T873
Test name
Test status
Simulation time 2385279257 ps
CPU time 2.34 seconds
Started Jul 16 04:57:15 PM PDT 24
Finished Jul 16 04:57:19 PM PDT 24
Peak memory 198524 kb
Host smart-de442d8a-401a-4c43-b7f6-72a38e0b81dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856098125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2856098125
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.994544957
Short name T299
Test name
Test status
Simulation time 27312954900 ps
CPU time 46.78 seconds
Started Jul 16 04:57:01 PM PDT 24
Finished Jul 16 04:57:49 PM PDT 24
Peak memory 199908 kb
Host smart-0c54e36e-055c-4274-a30d-f16fcd29da7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994544957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.994544957
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3473980674
Short name T1077
Test name
Test status
Simulation time 12608987776 ps
CPU time 683.22 seconds
Started Jul 16 04:57:03 PM PDT 24
Finished Jul 16 05:08:28 PM PDT 24
Peak memory 199876 kb
Host smart-981d1570-c70a-4ab7-9f0c-8855976fca12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3473980674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3473980674
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2908698889
Short name T1105
Test name
Test status
Simulation time 3989252112 ps
CPU time 29.4 seconds
Started Jul 16 04:57:01 PM PDT 24
Finished Jul 16 04:57:32 PM PDT 24
Peak memory 197832 kb
Host smart-c9b8a0a0-44b5-4a02-b4bf-27502feab1a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908698889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2908698889
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.199564892
Short name T809
Test name
Test status
Simulation time 25423936661 ps
CPU time 13 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 04:57:25 PM PDT 24
Peak memory 199312 kb
Host smart-4ab29d83-8932-4611-b096-861e9cd1d786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199564892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.199564892
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1830916763
Short name T613
Test name
Test status
Simulation time 1904779919 ps
CPU time 3.26 seconds
Started Jul 16 04:57:09 PM PDT 24
Finished Jul 16 04:57:14 PM PDT 24
Peak memory 195188 kb
Host smart-f5c1d05d-1fa5-4512-91fd-292f1779f2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830916763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1830916763
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.4226222936
Short name T970
Test name
Test status
Simulation time 431377396 ps
CPU time 1.72 seconds
Started Jul 16 04:56:57 PM PDT 24
Finished Jul 16 04:56:59 PM PDT 24
Peak memory 198660 kb
Host smart-4321f0e1-7f21-4331-a323-23c65e0abf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226222936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.4226222936
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.476468733
Short name T740
Test name
Test status
Simulation time 240521527677 ps
CPU time 346.85 seconds
Started Jul 16 04:56:58 PM PDT 24
Finished Jul 16 05:02:46 PM PDT 24
Peak memory 199788 kb
Host smart-76df8fc1-bff4-4a1a-989d-9399e2e4716f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476468733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.476468733
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3375260178
Short name T58
Test name
Test status
Simulation time 188132339748 ps
CPU time 760.48 seconds
Started Jul 16 04:57:02 PM PDT 24
Finished Jul 16 05:09:44 PM PDT 24
Peak memory 231548 kb
Host smart-60cde202-e88d-47f1-9520-3f8ddd3cae89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375260178 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3375260178
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1913176088
Short name T1001
Test name
Test status
Simulation time 6983098570 ps
CPU time 15.85 seconds
Started Jul 16 04:57:01 PM PDT 24
Finished Jul 16 04:57:18 PM PDT 24
Peak memory 199772 kb
Host smart-55b69c81-14f3-4651-9f4d-059a9f9b2770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913176088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1913176088
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1662377367
Short name T764
Test name
Test status
Simulation time 35576303672 ps
CPU time 11.24 seconds
Started Jul 16 04:57:00 PM PDT 24
Finished Jul 16 04:57:13 PM PDT 24
Peak memory 196708 kb
Host smart-3bc77241-538f-4b92-8505-9c9f559aede0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662377367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1662377367
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2087291370
Short name T151
Test name
Test status
Simulation time 95213933555 ps
CPU time 241.14 seconds
Started Jul 16 04:59:53 PM PDT 24
Finished Jul 16 05:03:55 PM PDT 24
Peak memory 199740 kb
Host smart-47d39a30-442c-4a39-b8d6-a95c97dd0381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087291370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2087291370
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2559639641
Short name T976
Test name
Test status
Simulation time 161305602778 ps
CPU time 63.78 seconds
Started Jul 16 04:59:54 PM PDT 24
Finished Jul 16 05:00:58 PM PDT 24
Peak memory 199688 kb
Host smart-0aa9d3a2-b611-4663-a40c-cf59b6d8e2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559639641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2559639641
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2752868285
Short name T1161
Test name
Test status
Simulation time 50683072229 ps
CPU time 17.7 seconds
Started Jul 16 04:59:58 PM PDT 24
Finished Jul 16 05:00:16 PM PDT 24
Peak memory 200012 kb
Host smart-bad9838f-64d9-47a0-96ac-c49ebff2c0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752868285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2752868285
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3225131158
Short name T205
Test name
Test status
Simulation time 42189429029 ps
CPU time 50.72 seconds
Started Jul 16 04:59:57 PM PDT 24
Finished Jul 16 05:00:48 PM PDT 24
Peak memory 199724 kb
Host smart-944d68fe-84f1-439d-80d1-d4093f95dc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225131158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3225131158
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2738205014
Short name T162
Test name
Test status
Simulation time 139157554177 ps
CPU time 104.95 seconds
Started Jul 16 04:59:54 PM PDT 24
Finished Jul 16 05:01:40 PM PDT 24
Peak memory 199848 kb
Host smart-e2a259d2-71cf-4882-b6f5-ae67940d0a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738205014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2738205014
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3834954249
Short name T865
Test name
Test status
Simulation time 58690981578 ps
CPU time 93.89 seconds
Started Jul 16 04:59:54 PM PDT 24
Finished Jul 16 05:01:29 PM PDT 24
Peak memory 199856 kb
Host smart-3acdcab0-9df6-45df-8877-ba2aee824911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834954249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3834954249
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3904020276
Short name T931
Test name
Test status
Simulation time 52350467823 ps
CPU time 48.54 seconds
Started Jul 16 04:59:54 PM PDT 24
Finished Jul 16 05:00:43 PM PDT 24
Peak memory 199644 kb
Host smart-c0180f63-baec-4e60-9a54-2ff2e5d1b945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904020276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3904020276
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3868994047
Short name T710
Test name
Test status
Simulation time 159491039383 ps
CPU time 170.99 seconds
Started Jul 16 04:59:54 PM PDT 24
Finished Jul 16 05:02:46 PM PDT 24
Peak memory 199864 kb
Host smart-01952398-8404-4039-b844-c43bcf41ebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868994047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3868994047
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1329629173
Short name T905
Test name
Test status
Simulation time 24554905 ps
CPU time 0.55 seconds
Started Jul 16 04:57:04 PM PDT 24
Finished Jul 16 04:57:06 PM PDT 24
Peak memory 195084 kb
Host smart-fefa3019-5fce-42cf-a681-8de89ac368bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329629173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1329629173
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.990431833
Short name T404
Test name
Test status
Simulation time 42342606958 ps
CPU time 60.02 seconds
Started Jul 16 04:57:02 PM PDT 24
Finished Jul 16 04:58:04 PM PDT 24
Peak memory 199684 kb
Host smart-8b3f2b02-c5af-45c6-acfd-a66dc8bed1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990431833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.990431833
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1249407911
Short name T156
Test name
Test status
Simulation time 133784070066 ps
CPU time 138.15 seconds
Started Jul 16 04:56:59 PM PDT 24
Finished Jul 16 04:59:18 PM PDT 24
Peak memory 199812 kb
Host smart-a9ee5a35-aa2b-4567-ac3a-eba4fd3e74d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249407911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1249407911
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1472613204
Short name T443
Test name
Test status
Simulation time 24835378234 ps
CPU time 51.28 seconds
Started Jul 16 04:56:59 PM PDT 24
Finished Jul 16 04:57:51 PM PDT 24
Peak memory 199808 kb
Host smart-c8f171eb-3890-4e21-8886-7b8ab70ebc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472613204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1472613204
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.950785728
Short name T269
Test name
Test status
Simulation time 25470557910 ps
CPU time 56.95 seconds
Started Jul 16 04:56:57 PM PDT 24
Finished Jul 16 04:57:55 PM PDT 24
Peak memory 199900 kb
Host smart-2f6a3208-50bf-4f72-b562-559c5ba561c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950785728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.950785728
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.4093570147
Short name T451
Test name
Test status
Simulation time 24773237873 ps
CPU time 118.38 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 04:59:09 PM PDT 24
Peak memory 199640 kb
Host smart-0ab46c47-c377-4bce-a4d6-36d9370c9798
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093570147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.4093570147
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2581678482
Short name T685
Test name
Test status
Simulation time 2640848980 ps
CPU time 2.18 seconds
Started Jul 16 04:57:11 PM PDT 24
Finished Jul 16 04:57:14 PM PDT 24
Peak memory 198204 kb
Host smart-33970980-cda9-4644-8f19-0facc1c2c816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581678482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2581678482
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.403450088
Short name T411
Test name
Test status
Simulation time 32710025364 ps
CPU time 210.19 seconds
Started Jul 16 04:57:03 PM PDT 24
Finished Jul 16 05:00:34 PM PDT 24
Peak memory 199664 kb
Host smart-f3c88f65-23b3-431d-8f78-c66e08faa88a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403450088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.403450088
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.4131885649
Short name T1167
Test name
Test status
Simulation time 1300999138 ps
CPU time 1.96 seconds
Started Jul 16 04:56:59 PM PDT 24
Finished Jul 16 04:57:02 PM PDT 24
Peak memory 197892 kb
Host smart-bedd0f17-553e-44c5-ab59-5929343695af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131885649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.4131885649
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.274532660
Short name T131
Test name
Test status
Simulation time 56784457275 ps
CPU time 90.11 seconds
Started Jul 16 04:56:58 PM PDT 24
Finished Jul 16 04:58:28 PM PDT 24
Peak memory 199792 kb
Host smart-3aa6f4fe-8752-4b03-a204-77bab267606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274532660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.274532660
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.126675089
Short name T356
Test name
Test status
Simulation time 4343638233 ps
CPU time 2.1 seconds
Started Jul 16 04:57:01 PM PDT 24
Finished Jul 16 04:57:04 PM PDT 24
Peak memory 196600 kb
Host smart-5f245130-bd44-4863-adcd-b73b18dd30fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126675089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.126675089
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2781129819
Short name T431
Test name
Test status
Simulation time 489129286 ps
CPU time 2.35 seconds
Started Jul 16 04:57:05 PM PDT 24
Finished Jul 16 04:57:09 PM PDT 24
Peak memory 199612 kb
Host smart-e43cb61b-17ff-478d-aa2c-8439c955c6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781129819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2781129819
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3894976013
Short name T279
Test name
Test status
Simulation time 109677912933 ps
CPU time 348.39 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 05:03:00 PM PDT 24
Peak memory 199696 kb
Host smart-a8cc6e96-816f-4242-8c82-600ee8a12c84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894976013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3894976013
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2137231513
Short name T109
Test name
Test status
Simulation time 33057795095 ps
CPU time 154.89 seconds
Started Jul 16 04:56:58 PM PDT 24
Finished Jul 16 04:59:33 PM PDT 24
Peak memory 211852 kb
Host smart-94a706ed-1bc9-453a-80af-a421f11c38b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137231513 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2137231513
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1936924873
Short name T295
Test name
Test status
Simulation time 401738759 ps
CPU time 1.21 seconds
Started Jul 16 04:57:06 PM PDT 24
Finished Jul 16 04:57:08 PM PDT 24
Peak memory 199796 kb
Host smart-003eb465-ef91-46aa-8883-10f11495857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936924873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1936924873
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2792394648
Short name T474
Test name
Test status
Simulation time 32207868520 ps
CPU time 40.65 seconds
Started Jul 16 04:56:59 PM PDT 24
Finished Jul 16 04:57:41 PM PDT 24
Peak memory 199552 kb
Host smart-43f5eae9-7d63-4ad2-8958-03cd4c9f91d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792394648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2792394648
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1846210163
Short name T268
Test name
Test status
Simulation time 71212508118 ps
CPU time 34.55 seconds
Started Jul 16 04:59:56 PM PDT 24
Finished Jul 16 05:00:31 PM PDT 24
Peak memory 199760 kb
Host smart-f83e7a78-8e38-4d06-838e-1a87370afa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846210163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1846210163
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2395913898
Short name T171
Test name
Test status
Simulation time 23987185549 ps
CPU time 24.29 seconds
Started Jul 16 04:59:53 PM PDT 24
Finished Jul 16 05:00:19 PM PDT 24
Peak memory 199808 kb
Host smart-465d01bd-c309-4df1-842c-f5f07924de90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395913898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2395913898
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1426729231
Short name T1135
Test name
Test status
Simulation time 28979065736 ps
CPU time 21.39 seconds
Started Jul 16 04:59:53 PM PDT 24
Finished Jul 16 05:00:15 PM PDT 24
Peak memory 199696 kb
Host smart-57ca4358-767b-4f76-8c68-b8c8b7851e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426729231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1426729231
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1216594126
Short name T231
Test name
Test status
Simulation time 380171040064 ps
CPU time 622.32 seconds
Started Jul 16 04:59:57 PM PDT 24
Finished Jul 16 05:10:20 PM PDT 24
Peak memory 199804 kb
Host smart-ff98ade0-ba8e-4f93-9d0c-823a8cb5a682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216594126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1216594126
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3998293747
Short name T294
Test name
Test status
Simulation time 96459377561 ps
CPU time 76.33 seconds
Started Jul 16 04:59:53 PM PDT 24
Finished Jul 16 05:01:10 PM PDT 24
Peak memory 199668 kb
Host smart-e2fd0f19-1bd0-4737-a669-68c43b2f6a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998293747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3998293747
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3564147484
Short name T1030
Test name
Test status
Simulation time 32341348463 ps
CPU time 58.83 seconds
Started Jul 16 04:59:57 PM PDT 24
Finished Jul 16 05:00:56 PM PDT 24
Peak memory 200084 kb
Host smart-b8fb7939-27c0-4150-8531-cc6ed45a3e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564147484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3564147484
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.4037411059
Short name T654
Test name
Test status
Simulation time 21693431832 ps
CPU time 38.76 seconds
Started Jul 16 04:59:54 PM PDT 24
Finished Jul 16 05:00:33 PM PDT 24
Peak memory 199572 kb
Host smart-6e1bbbb9-3f39-4a88-afd9-b02dce02bff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037411059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.4037411059
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1283562621
Short name T813
Test name
Test status
Simulation time 12845408 ps
CPU time 0.53 seconds
Started Jul 16 04:57:01 PM PDT 24
Finished Jul 16 04:57:03 PM PDT 24
Peak memory 195396 kb
Host smart-f7c9c667-443a-4f80-b57b-4780f26993cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283562621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1283562621
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.327387925
Short name T461
Test name
Test status
Simulation time 157277309336 ps
CPU time 178.18 seconds
Started Jul 16 04:57:00 PM PDT 24
Finished Jul 16 04:59:59 PM PDT 24
Peak memory 199764 kb
Host smart-d5b55831-51a4-402a-a4f9-c2c0c82b073f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327387925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.327387925
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2166977320
Short name T1113
Test name
Test status
Simulation time 86600470502 ps
CPU time 200.19 seconds
Started Jul 16 04:57:04 PM PDT 24
Finished Jul 16 05:00:25 PM PDT 24
Peak memory 199668 kb
Host smart-2f72d906-0417-4e9a-80d5-d13170e3aa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166977320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2166977320
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.836109377
Short name T1072
Test name
Test status
Simulation time 22256800192 ps
CPU time 52.83 seconds
Started Jul 16 04:57:02 PM PDT 24
Finished Jul 16 04:57:57 PM PDT 24
Peak memory 199936 kb
Host smart-8144c49b-79b5-4870-bafb-365d54e729d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836109377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.836109377
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3771079938
Short name T364
Test name
Test status
Simulation time 26606936903 ps
CPU time 14.82 seconds
Started Jul 16 04:57:12 PM PDT 24
Finished Jul 16 04:57:28 PM PDT 24
Peak memory 199836 kb
Host smart-3e04c36f-1026-4b10-bf7f-870ce52307e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771079938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3771079938
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2596077786
Short name T452
Test name
Test status
Simulation time 102936462370 ps
CPU time 917.59 seconds
Started Jul 16 04:57:08 PM PDT 24
Finished Jul 16 05:12:31 PM PDT 24
Peak memory 199724 kb
Host smart-cb288c53-edbd-48be-adfc-063fb6826cd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2596077786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2596077786
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2817221274
Short name T367
Test name
Test status
Simulation time 6208015023 ps
CPU time 5.88 seconds
Started Jul 16 04:57:02 PM PDT 24
Finished Jul 16 04:57:09 PM PDT 24
Peak memory 198296 kb
Host smart-aad8952a-8794-40a1-a4a3-71a9568e9c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817221274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2817221274
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1931456819
Short name T756
Test name
Test status
Simulation time 34729318684 ps
CPU time 8.23 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 04:57:20 PM PDT 24
Peak memory 194548 kb
Host smart-5e02972e-d172-4387-9459-09a543293e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931456819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1931456819
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3782260309
Short name T571
Test name
Test status
Simulation time 8268583998 ps
CPU time 422.04 seconds
Started Jul 16 04:57:04 PM PDT 24
Finished Jul 16 05:04:07 PM PDT 24
Peak memory 199752 kb
Host smart-f6f148fa-d939-405e-9af3-c49a3f58be10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782260309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3782260309
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1080246299
Short name T1063
Test name
Test status
Simulation time 3468102203 ps
CPU time 12.62 seconds
Started Jul 16 04:57:02 PM PDT 24
Finished Jul 16 04:57:16 PM PDT 24
Peak memory 197564 kb
Host smart-195e13d7-99d3-4114-932f-72555f942d00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1080246299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1080246299
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1555195459
Short name T649
Test name
Test status
Simulation time 135017149837 ps
CPU time 825.95 seconds
Started Jul 16 04:57:12 PM PDT 24
Finished Jul 16 05:10:59 PM PDT 24
Peak memory 199820 kb
Host smart-e0b19ff1-de7b-44c2-ae6a-db8c6e0e6a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555195459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1555195459
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3881922599
Short name T296
Test name
Test status
Simulation time 5085488785 ps
CPU time 4.28 seconds
Started Jul 16 04:57:04 PM PDT 24
Finished Jul 16 04:57:09 PM PDT 24
Peak memory 196356 kb
Host smart-0e5b1a75-d146-4b3c-88e1-3f0117ee6798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881922599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3881922599
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.105605859
Short name T293
Test name
Test status
Simulation time 872820178 ps
CPU time 2.6 seconds
Started Jul 16 04:57:06 PM PDT 24
Finished Jul 16 04:57:10 PM PDT 24
Peak memory 198696 kb
Host smart-701e2e0c-dd3c-4c8f-b3b1-d77bfc5f02d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105605859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.105605859
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.616641594
Short name T511
Test name
Test status
Simulation time 343802014894 ps
CPU time 665.16 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 05:08:17 PM PDT 24
Peak memory 199724 kb
Host smart-6f035a3f-b24d-465b-baff-7cf32d9848e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616641594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.616641594
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3364241777
Short name T1024
Test name
Test status
Simulation time 29803999526 ps
CPU time 271.98 seconds
Started Jul 16 04:57:08 PM PDT 24
Finished Jul 16 05:01:41 PM PDT 24
Peak memory 216376 kb
Host smart-f828e3e3-c2fb-4a48-8473-d89ecb9b57f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364241777 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3364241777
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2054342926
Short name T289
Test name
Test status
Simulation time 3986282694 ps
CPU time 1.51 seconds
Started Jul 16 04:57:09 PM PDT 24
Finished Jul 16 04:57:11 PM PDT 24
Peak memory 198916 kb
Host smart-e7206d39-30bb-439a-9608-ecc0041ff5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054342926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2054342926
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.467612997
Short name T527
Test name
Test status
Simulation time 16032459862 ps
CPU time 14.2 seconds
Started Jul 16 04:57:06 PM PDT 24
Finished Jul 16 04:57:21 PM PDT 24
Peak memory 199680 kb
Host smart-378d5bf6-62e2-40e5-8027-9ba74b1b9c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467612997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.467612997
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3569953280
Short name T145
Test name
Test status
Simulation time 108050808430 ps
CPU time 74.26 seconds
Started Jul 16 04:59:52 PM PDT 24
Finished Jul 16 05:01:07 PM PDT 24
Peak memory 200104 kb
Host smart-8a1ddc86-8ddb-44a8-937c-20dd71be53c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569953280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3569953280
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2847784124
Short name T1012
Test name
Test status
Simulation time 23438970164 ps
CPU time 35.57 seconds
Started Jul 16 04:59:53 PM PDT 24
Finished Jul 16 05:00:29 PM PDT 24
Peak memory 199688 kb
Host smart-c8acf943-c4df-464d-901a-83b5bf4251b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847784124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2847784124
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1302097844
Short name T1038
Test name
Test status
Simulation time 16571206115 ps
CPU time 31.93 seconds
Started Jul 16 04:59:53 PM PDT 24
Finished Jul 16 05:00:26 PM PDT 24
Peak memory 199784 kb
Host smart-92bb364a-b7dc-4070-96d6-de46ddd78213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302097844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1302097844
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1367315847
Short name T1131
Test name
Test status
Simulation time 366919093411 ps
CPU time 59.15 seconds
Started Jul 16 04:59:56 PM PDT 24
Finished Jul 16 05:00:56 PM PDT 24
Peak memory 199920 kb
Host smart-e9a87de1-1c6f-4f6c-a4b0-a5edacdb8adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367315847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1367315847
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3416230313
Short name T614
Test name
Test status
Simulation time 90231649314 ps
CPU time 72.6 seconds
Started Jul 16 04:59:56 PM PDT 24
Finished Jul 16 05:01:09 PM PDT 24
Peak memory 199776 kb
Host smart-1dcb80e7-6e91-471c-a803-4976747bc81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416230313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3416230313
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2500716034
Short name T282
Test name
Test status
Simulation time 5380375331 ps
CPU time 8.86 seconds
Started Jul 16 04:59:57 PM PDT 24
Finished Jul 16 05:00:07 PM PDT 24
Peak memory 199824 kb
Host smart-79d96c16-885e-4830-82d8-6ab5d1973219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500716034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2500716034
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.995569945
Short name T573
Test name
Test status
Simulation time 124406489270 ps
CPU time 186.9 seconds
Started Jul 16 04:59:54 PM PDT 24
Finished Jul 16 05:03:02 PM PDT 24
Peak memory 199732 kb
Host smart-dd13988e-5261-4f5b-b04a-8cb7ccfccca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995569945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.995569945
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3063455754
Short name T878
Test name
Test status
Simulation time 52806213044 ps
CPU time 37.78 seconds
Started Jul 16 04:59:53 PM PDT 24
Finished Jul 16 05:00:31 PM PDT 24
Peak memory 199744 kb
Host smart-fd3ade09-a58b-45d2-9b52-d49117aad390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063455754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3063455754
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1804936500
Short name T964
Test name
Test status
Simulation time 8609452049 ps
CPU time 14.04 seconds
Started Jul 16 04:59:53 PM PDT 24
Finished Jul 16 05:00:08 PM PDT 24
Peak memory 199880 kb
Host smart-a7788d9e-24ea-417a-a2f7-ca1fe14d03f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804936500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1804936500
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2061665654
Short name T674
Test name
Test status
Simulation time 41994596817 ps
CPU time 34.37 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:57:49 PM PDT 24
Peak memory 199860 kb
Host smart-4556cf90-3287-4fad-8787-c45176ad2dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061665654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2061665654
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2573815990
Short name T940
Test name
Test status
Simulation time 185325467061 ps
CPU time 34.42 seconds
Started Jul 16 04:57:09 PM PDT 24
Finished Jul 16 04:57:45 PM PDT 24
Peak memory 199732 kb
Host smart-03448011-58df-454d-9932-b4a1579fb9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573815990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2573815990
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_intr.1243262409
Short name T333
Test name
Test status
Simulation time 195628114881 ps
CPU time 321.72 seconds
Started Jul 16 04:57:09 PM PDT 24
Finished Jul 16 05:02:32 PM PDT 24
Peak memory 199724 kb
Host smart-6dad262d-50e8-42d5-b727-e8a14dab2ca5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243262409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1243262409
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1072485248
Short name T724
Test name
Test status
Simulation time 28926506188 ps
CPU time 93.98 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:58:49 PM PDT 24
Peak memory 199884 kb
Host smart-c07d9105-e7c4-4d26-bbf2-993d0595bbea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072485248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1072485248
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1224306164
Short name T673
Test name
Test status
Simulation time 5981423485 ps
CPU time 11.03 seconds
Started Jul 16 04:57:16 PM PDT 24
Finished Jul 16 04:57:28 PM PDT 24
Peak memory 198248 kb
Host smart-3aed14f1-c141-40df-8406-f3c7c6c9933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224306164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1224306164
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1874217562
Short name T663
Test name
Test status
Simulation time 126546581615 ps
CPU time 47.95 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:58:03 PM PDT 24
Peak memory 200076 kb
Host smart-296d7519-8581-4488-bfe3-e5974339cd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874217562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1874217562
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2338800821
Short name T787
Test name
Test status
Simulation time 1694253528 ps
CPU time 78.96 seconds
Started Jul 16 04:57:03 PM PDT 24
Finished Jul 16 04:58:24 PM PDT 24
Peak memory 199756 kb
Host smart-9a939b2e-1ea4-4b5a-9bcf-caaeceaf169d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338800821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2338800821
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3871110360
Short name T341
Test name
Test status
Simulation time 4042055683 ps
CPU time 9.5 seconds
Started Jul 16 04:57:02 PM PDT 24
Finished Jul 16 04:57:13 PM PDT 24
Peak memory 197872 kb
Host smart-a0b82cbe-0e2a-4fbd-8509-fdc5c8268bc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871110360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3871110360
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2328582463
Short name T706
Test name
Test status
Simulation time 65545069880 ps
CPU time 11.86 seconds
Started Jul 16 04:57:07 PM PDT 24
Finished Jul 16 04:57:19 PM PDT 24
Peak memory 199712 kb
Host smart-56d1e009-6735-4133-adfe-9703bcf98596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328582463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2328582463
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.810802041
Short name T1116
Test name
Test status
Simulation time 38413988078 ps
CPU time 13.74 seconds
Started Jul 16 04:57:13 PM PDT 24
Finished Jul 16 04:57:28 PM PDT 24
Peak memory 195952 kb
Host smart-f1382376-2420-4ecf-a347-b3299864d633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810802041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.810802041
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.562879307
Short name T1099
Test name
Test status
Simulation time 261310945 ps
CPU time 1.55 seconds
Started Jul 16 04:56:59 PM PDT 24
Finished Jul 16 04:57:02 PM PDT 24
Peak memory 198240 kb
Host smart-ea1406fb-88f0-4f30-8c45-b1208b169118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562879307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.562879307
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1255152881
Short name T167
Test name
Test status
Simulation time 45366040012 ps
CPU time 92.48 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:58:48 PM PDT 24
Peak memory 199736 kb
Host smart-a87eeb46-4664-4cc4-bc23-9a5e50c85188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255152881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1255152881
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1889975999
Short name T608
Test name
Test status
Simulation time 180764797007 ps
CPU time 680.74 seconds
Started Jul 16 04:57:15 PM PDT 24
Finished Jul 16 05:08:37 PM PDT 24
Peak memory 216232 kb
Host smart-8809c91b-5c50-4dca-bc68-e4f7f1e18737
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889975999 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1889975999
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.357522401
Short name T1158
Test name
Test status
Simulation time 1107295120 ps
CPU time 2.38 seconds
Started Jul 16 04:57:05 PM PDT 24
Finished Jul 16 04:57:08 PM PDT 24
Peak memory 198956 kb
Host smart-f6f24e64-c4ac-4f07-88a3-088a4eb85e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357522401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.357522401
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2230928911
Short name T321
Test name
Test status
Simulation time 4163689516 ps
CPU time 6.7 seconds
Started Jul 16 04:57:17 PM PDT 24
Finished Jul 16 04:57:25 PM PDT 24
Peak memory 198652 kb
Host smart-50c723b3-beed-4810-9696-86e4000915da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230928911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2230928911
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1205584984
Short name T42
Test name
Test status
Simulation time 24734266935 ps
CPU time 4.47 seconds
Started Jul 16 04:59:52 PM PDT 24
Finished Jul 16 04:59:57 PM PDT 24
Peak memory 199840 kb
Host smart-bf05b391-6487-42fd-aa38-3fa05dfade2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205584984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1205584984
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1915228835
Short name T1067
Test name
Test status
Simulation time 14736616961 ps
CPU time 9.12 seconds
Started Jul 16 04:59:55 PM PDT 24
Finished Jul 16 05:00:05 PM PDT 24
Peak memory 199856 kb
Host smart-b755be5c-780f-40bb-9a28-f61b7c3aae0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915228835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1915228835
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.887053386
Short name T1082
Test name
Test status
Simulation time 73828200312 ps
CPU time 48.41 seconds
Started Jul 16 04:59:55 PM PDT 24
Finished Jul 16 05:00:44 PM PDT 24
Peak memory 199840 kb
Host smart-1e696c52-cea0-431c-85c5-37ed975dc535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887053386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.887053386
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.4066699308
Short name T220
Test name
Test status
Simulation time 103540292046 ps
CPU time 77.22 seconds
Started Jul 16 04:59:52 PM PDT 24
Finished Jul 16 05:01:10 PM PDT 24
Peak memory 199748 kb
Host smart-2ed7f25b-25c2-4936-9b9f-4aaf848f5c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066699308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.4066699308
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3773975823
Short name T687
Test name
Test status
Simulation time 47334298432 ps
CPU time 50.61 seconds
Started Jul 16 04:59:55 PM PDT 24
Finished Jul 16 05:00:46 PM PDT 24
Peak memory 199732 kb
Host smart-8a6de07f-5b4e-4b09-a981-73de7ccf5a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773975823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3773975823
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1750777091
Short name T755
Test name
Test status
Simulation time 39486776276 ps
CPU time 14.48 seconds
Started Jul 16 04:59:52 PM PDT 24
Finished Jul 16 05:00:07 PM PDT 24
Peak memory 199476 kb
Host smart-3f8bfa8b-08c7-443b-b776-cecb5fea6cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750777091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1750777091
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1742111919
Short name T195
Test name
Test status
Simulation time 46020672958 ps
CPU time 18.8 seconds
Started Jul 16 04:59:51 PM PDT 24
Finished Jul 16 05:00:10 PM PDT 24
Peak memory 199800 kb
Host smart-6b9b9ed6-46f4-4320-aa4e-721fbab93965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742111919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1742111919
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2702777504
Short name T202
Test name
Test status
Simulation time 26785388340 ps
CPU time 63.97 seconds
Started Jul 16 05:00:09 PM PDT 24
Finished Jul 16 05:01:14 PM PDT 24
Peak memory 199856 kb
Host smart-3c08a639-cd42-4c3b-b283-cbc55607ea1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702777504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2702777504
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3038416105
Short name T793
Test name
Test status
Simulation time 369220044062 ps
CPU time 138.75 seconds
Started Jul 16 05:00:07 PM PDT 24
Finished Jul 16 05:02:26 PM PDT 24
Peak memory 199824 kb
Host smart-62fbc235-0443-4d09-ad55-e34fcde83403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038416105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3038416105
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.734307115
Short name T200
Test name
Test status
Simulation time 207181162226 ps
CPU time 329.81 seconds
Started Jul 16 05:00:05 PM PDT 24
Finished Jul 16 05:05:36 PM PDT 24
Peak memory 199816 kb
Host smart-196570c3-d194-4f6e-a964-75d54ce39c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734307115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.734307115
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.621720871
Short name T1165
Test name
Test status
Simulation time 40045122 ps
CPU time 0.55 seconds
Started Jul 16 04:56:23 PM PDT 24
Finished Jul 16 04:56:25 PM PDT 24
Peak memory 195408 kb
Host smart-a82bb6b8-3be5-460f-8389-e0c47bfd498a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621720871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.621720871
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3334467691
Short name T504
Test name
Test status
Simulation time 131213341237 ps
CPU time 389.66 seconds
Started Jul 16 04:56:35 PM PDT 24
Finished Jul 16 05:03:06 PM PDT 24
Peak memory 199756 kb
Host smart-dac7f617-4d7d-43c3-bfe0-fc95887e852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334467691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3334467691
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2493742953
Short name T851
Test name
Test status
Simulation time 10866815777 ps
CPU time 8.72 seconds
Started Jul 16 04:56:32 PM PDT 24
Finished Jul 16 04:56:43 PM PDT 24
Peak memory 199492 kb
Host smart-377be929-cb40-428e-aa21-43a182f79660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493742953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2493742953
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1243600605
Short name T132
Test name
Test status
Simulation time 84901361416 ps
CPU time 63.07 seconds
Started Jul 16 04:56:23 PM PDT 24
Finished Jul 16 04:57:27 PM PDT 24
Peak memory 199896 kb
Host smart-4ddd52e3-8a7f-42e1-ad61-b39e9792ac1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243600605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1243600605
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.261146990
Short name T759
Test name
Test status
Simulation time 192040996428 ps
CPU time 366.61 seconds
Started Jul 16 04:56:37 PM PDT 24
Finished Jul 16 05:02:45 PM PDT 24
Peak memory 199740 kb
Host smart-d59baaf3-3a1c-4252-bab1-cef651a2106a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261146990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.261146990
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3936969565
Short name T656
Test name
Test status
Simulation time 111524176552 ps
CPU time 395.42 seconds
Started Jul 16 04:56:24 PM PDT 24
Finished Jul 16 05:03:00 PM PDT 24
Peak memory 199708 kb
Host smart-46ff9423-f745-430a-b708-23ad6d40f0ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936969565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3936969565
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2320383029
Short name T919
Test name
Test status
Simulation time 1839719309 ps
CPU time 2.16 seconds
Started Jul 16 04:56:21 PM PDT 24
Finished Jul 16 04:56:24 PM PDT 24
Peak memory 197040 kb
Host smart-68e123f3-3da4-4069-893d-9e8c037fd719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320383029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2320383029
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2582726500
Short name T523
Test name
Test status
Simulation time 46463372413 ps
CPU time 29.25 seconds
Started Jul 16 04:56:30 PM PDT 24
Finished Jul 16 04:57:01 PM PDT 24
Peak memory 199352 kb
Host smart-b5727704-9f49-4fa4-a2c6-9a412f15b722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582726500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2582726500
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2925971587
Short name T615
Test name
Test status
Simulation time 8643288621 ps
CPU time 114.63 seconds
Started Jul 16 04:56:29 PM PDT 24
Finished Jul 16 04:58:25 PM PDT 24
Peak memory 199776 kb
Host smart-e68edf8c-bcbb-4b53-a077-4c507ab4b007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925971587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2925971587
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3167305599
Short name T50
Test name
Test status
Simulation time 5060516928 ps
CPU time 25.5 seconds
Started Jul 16 04:56:30 PM PDT 24
Finished Jul 16 04:56:56 PM PDT 24
Peak memory 198940 kb
Host smart-8f659248-bb63-4c7d-bc23-96a94da38793
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167305599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3167305599
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.801876270
Short name T1164
Test name
Test status
Simulation time 198542703232 ps
CPU time 380.2 seconds
Started Jul 16 04:56:33 PM PDT 24
Finished Jul 16 05:02:55 PM PDT 24
Peak memory 199704 kb
Host smart-4498dc66-4c2d-4ad5-bfa6-c3f3f72e472f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801876270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.801876270
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.465007706
Short name T805
Test name
Test status
Simulation time 33073170099 ps
CPU time 12.71 seconds
Started Jul 16 04:56:30 PM PDT 24
Finished Jul 16 04:56:44 PM PDT 24
Peak memory 195672 kb
Host smart-2f81bcc2-1ed7-4bc4-84ed-18d997d86fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465007706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.465007706
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3768295115
Short name T104
Test name
Test status
Simulation time 226918403 ps
CPU time 0.83 seconds
Started Jul 16 04:56:24 PM PDT 24
Finished Jul 16 04:56:26 PM PDT 24
Peak memory 218204 kb
Host smart-ee320e51-2971-429c-b20d-677b5f7df253
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768295115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3768295115
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2727344603
Short name T380
Test name
Test status
Simulation time 509441593 ps
CPU time 2.1 seconds
Started Jul 16 04:56:29 PM PDT 24
Finished Jul 16 04:56:33 PM PDT 24
Peak memory 198212 kb
Host smart-78f2671b-3a59-4207-bdbd-43d1de9bc5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727344603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2727344603
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2280851512
Short name T1169
Test name
Test status
Simulation time 244225505322 ps
CPU time 56.76 seconds
Started Jul 16 04:56:40 PM PDT 24
Finished Jul 16 04:57:37 PM PDT 24
Peak memory 199684 kb
Host smart-0f5f9dd2-d88e-4a2b-a56f-3b069b4ee2ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280851512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2280851512
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2553764524
Short name T14
Test name
Test status
Simulation time 20905553287 ps
CPU time 405.49 seconds
Started Jul 16 04:56:30 PM PDT 24
Finished Jul 16 05:03:17 PM PDT 24
Peak memory 216516 kb
Host smart-c90a0f8d-d783-472c-91ec-22cdae8bd4ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553764524 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2553764524
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3630371044
Short name T466
Test name
Test status
Simulation time 1217282158 ps
CPU time 1.85 seconds
Started Jul 16 04:56:29 PM PDT 24
Finished Jul 16 04:56:32 PM PDT 24
Peak memory 198376 kb
Host smart-9fa88d03-d398-473b-bad6-255da740f25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630371044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3630371044
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3914559670
Short name T843
Test name
Test status
Simulation time 31213979582 ps
CPU time 22.73 seconds
Started Jul 16 04:56:31 PM PDT 24
Finished Jul 16 04:56:55 PM PDT 24
Peak memory 198964 kb
Host smart-ca2506d1-bfca-4cb6-bfa7-42a0d500bb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914559670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3914559670
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1132723154
Short name T1
Test name
Test status
Simulation time 39884730 ps
CPU time 0.55 seconds
Started Jul 16 04:57:16 PM PDT 24
Finished Jul 16 04:57:18 PM PDT 24
Peak memory 194148 kb
Host smart-d8c10951-b746-463b-a8cd-9214a7e7f6b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132723154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1132723154
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3594195679
Short name T1139
Test name
Test status
Simulation time 125342453035 ps
CPU time 251.27 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 05:01:27 PM PDT 24
Peak memory 199744 kb
Host smart-9fdfe999-6aaf-4112-abec-6c80b808493d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594195679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3594195679
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.208373413
Short name T134
Test name
Test status
Simulation time 54022587821 ps
CPU time 23.33 seconds
Started Jul 16 04:57:06 PM PDT 24
Finished Jul 16 04:57:30 PM PDT 24
Peak memory 199668 kb
Host smart-aaa63e49-e93d-4468-918b-50bfdcb4dc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208373413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.208373413
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3539526015
Short name T1018
Test name
Test status
Simulation time 68547169508 ps
CPU time 42.27 seconds
Started Jul 16 04:57:11 PM PDT 24
Finished Jul 16 04:57:55 PM PDT 24
Peak memory 199844 kb
Host smart-fd57d8e8-2013-42a0-bb52-6d6babb0934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539526015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3539526015
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.4158381396
Short name T1106
Test name
Test status
Simulation time 20391524785 ps
CPU time 33.25 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 04:57:44 PM PDT 24
Peak memory 199408 kb
Host smart-dd36b82a-7d8e-4df8-90da-4b29fbe0b8dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158381396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.4158381396
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2819178220
Short name T457
Test name
Test status
Simulation time 172443856070 ps
CPU time 453.32 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 05:04:49 PM PDT 24
Peak memory 199788 kb
Host smart-702d3494-4830-41a6-842b-684055317ea7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2819178220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2819178220
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3753122356
Short name T1117
Test name
Test status
Simulation time 6632505688 ps
CPU time 4.4 seconds
Started Jul 16 04:57:23 PM PDT 24
Finished Jul 16 04:57:28 PM PDT 24
Peak memory 199268 kb
Host smart-63fc9a70-f5b4-4c6c-af09-027f7c48a59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753122356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3753122356
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3960053710
Short name T464
Test name
Test status
Simulation time 180877479336 ps
CPU time 156.59 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 04:59:48 PM PDT 24
Peak memory 199696 kb
Host smart-97c58a40-bfec-4423-9b62-c3cd0ca4737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960053710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3960053710
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1842879440
Short name T1061
Test name
Test status
Simulation time 2891753433 ps
CPU time 141.53 seconds
Started Jul 16 04:57:09 PM PDT 24
Finished Jul 16 04:59:32 PM PDT 24
Peak memory 199788 kb
Host smart-03bb04e7-f30a-40a3-9f30-e0e1872376d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1842879440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1842879440
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1031091307
Short name T336
Test name
Test status
Simulation time 3983202297 ps
CPU time 32.32 seconds
Started Jul 16 04:57:16 PM PDT 24
Finished Jul 16 04:57:50 PM PDT 24
Peak memory 198732 kb
Host smart-dbf6a7e9-dcf5-40af-8eac-56dd820f42ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1031091307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1031091307
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3206913302
Short name T165
Test name
Test status
Simulation time 202348854352 ps
CPU time 67.88 seconds
Started Jul 16 04:57:04 PM PDT 24
Finished Jul 16 04:58:13 PM PDT 24
Peak memory 199844 kb
Host smart-3c521f23-4d52-4bf6-adf3-db4d78c7935c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206913302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3206913302
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3683622383
Short name T25
Test name
Test status
Simulation time 35092411064 ps
CPU time 24.15 seconds
Started Jul 16 04:57:09 PM PDT 24
Finished Jul 16 04:57:34 PM PDT 24
Peak memory 195880 kb
Host smart-d976452e-bbf4-4380-9e36-dbe73726ed0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683622383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3683622383
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3137094435
Short name T401
Test name
Test status
Simulation time 892057880 ps
CPU time 3.4 seconds
Started Jul 16 04:57:12 PM PDT 24
Finished Jul 16 04:57:16 PM PDT 24
Peak memory 198280 kb
Host smart-e1d3af69-36ba-4576-b702-3d1b5fd7b26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137094435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3137094435
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3094755789
Short name T402
Test name
Test status
Simulation time 57626297344 ps
CPU time 266.38 seconds
Started Jul 16 04:57:06 PM PDT 24
Finished Jul 16 05:01:33 PM PDT 24
Peak memory 199704 kb
Host smart-b1e48a88-e62f-40c7-aaee-d792de5aadc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094755789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3094755789
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2511897677
Short name T290
Test name
Test status
Simulation time 7302379211 ps
CPU time 9.23 seconds
Started Jul 16 04:57:02 PM PDT 24
Finished Jul 16 04:57:12 PM PDT 24
Peak memory 199692 kb
Host smart-c9942286-a0da-48d5-8d52-a89d6e25e7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511897677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2511897677
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3853958718
Short name T900
Test name
Test status
Simulation time 3552149317 ps
CPU time 2.7 seconds
Started Jul 16 04:57:12 PM PDT 24
Finished Jul 16 04:57:16 PM PDT 24
Peak memory 199712 kb
Host smart-4a812036-1985-4864-a7b9-dad7178400b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853958718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3853958718
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2436233713
Short name T1178
Test name
Test status
Simulation time 112583801483 ps
CPU time 95.48 seconds
Started Jul 16 05:00:08 PM PDT 24
Finished Jul 16 05:01:44 PM PDT 24
Peak memory 199504 kb
Host smart-4a354a18-3b26-48d3-8b8e-2c027b409200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436233713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2436233713
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3966258407
Short name T585
Test name
Test status
Simulation time 83077136463 ps
CPU time 25.93 seconds
Started Jul 16 05:00:08 PM PDT 24
Finished Jul 16 05:00:35 PM PDT 24
Peak memory 199540 kb
Host smart-41355a75-eb48-4771-a519-999612637fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966258407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3966258407
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2179906514
Short name T811
Test name
Test status
Simulation time 113537454343 ps
CPU time 171.12 seconds
Started Jul 16 05:00:09 PM PDT 24
Finished Jul 16 05:03:01 PM PDT 24
Peak memory 199784 kb
Host smart-142c9b26-9563-43e0-b6a6-73bbe1835f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179906514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2179906514
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1316681578
Short name T962
Test name
Test status
Simulation time 253534951035 ps
CPU time 96.55 seconds
Started Jul 16 05:00:07 PM PDT 24
Finished Jul 16 05:01:45 PM PDT 24
Peak memory 199748 kb
Host smart-ed7f72a1-5f12-404d-9c7b-b1223da420ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316681578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1316681578
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3845667525
Short name T980
Test name
Test status
Simulation time 7698586386 ps
CPU time 13.66 seconds
Started Jul 16 05:00:06 PM PDT 24
Finished Jul 16 05:00:20 PM PDT 24
Peak memory 199772 kb
Host smart-e96b2474-fc3b-4adc-9d54-1f414a8b932d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845667525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3845667525
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3212186419
Short name T254
Test name
Test status
Simulation time 28560192338 ps
CPU time 7.05 seconds
Started Jul 16 05:00:10 PM PDT 24
Finished Jul 16 05:00:17 PM PDT 24
Peak memory 199736 kb
Host smart-5c605aa1-84f3-4ef2-9e47-1437298e01ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212186419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3212186419
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3837042540
Short name T326
Test name
Test status
Simulation time 19817495 ps
CPU time 0.53 seconds
Started Jul 16 04:57:02 PM PDT 24
Finished Jul 16 04:57:04 PM PDT 24
Peak memory 194088 kb
Host smart-051c3e48-6a0b-483d-8cf4-104efa51b639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837042540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3837042540
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.623767097
Short name T305
Test name
Test status
Simulation time 215496593896 ps
CPU time 130.74 seconds
Started Jul 16 04:57:11 PM PDT 24
Finished Jul 16 04:59:23 PM PDT 24
Peak memory 199752 kb
Host smart-43816ebb-103e-4e17-bafb-e9920ddbe361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623767097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.623767097
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2659091989
Short name T139
Test name
Test status
Simulation time 11311342976 ps
CPU time 20.15 seconds
Started Jul 16 04:57:11 PM PDT 24
Finished Jul 16 04:57:33 PM PDT 24
Peak memory 199700 kb
Host smart-83c34036-edc3-47be-940c-2f44f52f8d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659091989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2659091989
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.888350025
Short name T141
Test name
Test status
Simulation time 164568041088 ps
CPU time 34.43 seconds
Started Jul 16 04:57:11 PM PDT 24
Finished Jul 16 04:57:47 PM PDT 24
Peak memory 199756 kb
Host smart-4efffd12-8ffd-4452-b9d2-242af2346e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888350025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.888350025
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3315960051
Short name T1028
Test name
Test status
Simulation time 34045100837 ps
CPU time 56.48 seconds
Started Jul 16 04:56:59 PM PDT 24
Finished Jul 16 04:57:56 PM PDT 24
Peak memory 198764 kb
Host smart-165a59f9-3c63-4b60-8a87-7fdfa15e4416
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315960051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3315960051
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3574192962
Short name T594
Test name
Test status
Simulation time 221536090275 ps
CPU time 292.54 seconds
Started Jul 16 04:57:11 PM PDT 24
Finished Jul 16 05:02:05 PM PDT 24
Peak memory 199744 kb
Host smart-9529356e-77dd-46de-ba9d-51283cdd4b20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3574192962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3574192962
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1662925113
Short name T975
Test name
Test status
Simulation time 5477626418 ps
CPU time 10.17 seconds
Started Jul 16 04:57:03 PM PDT 24
Finished Jul 16 04:57:15 PM PDT 24
Peak memory 199696 kb
Host smart-261a8d9d-cb33-4539-aac1-fe3299a676ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662925113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1662925113
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1288094533
Short name T780
Test name
Test status
Simulation time 154770020146 ps
CPU time 62.04 seconds
Started Jul 16 04:57:02 PM PDT 24
Finished Jul 16 04:58:06 PM PDT 24
Peak memory 200036 kb
Host smart-a1ee56d7-31b1-4086-831d-a402a95ba618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288094533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1288094533
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1257988917
Short name T846
Test name
Test status
Simulation time 19691399826 ps
CPU time 215.54 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 05:00:47 PM PDT 24
Peak memory 199676 kb
Host smart-6b6b5be7-0cec-417e-aca6-a5b80c7ecc20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1257988917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1257988917
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3037658916
Short name T337
Test name
Test status
Simulation time 3386318640 ps
CPU time 5.21 seconds
Started Jul 16 04:57:03 PM PDT 24
Finished Jul 16 04:57:09 PM PDT 24
Peak memory 198920 kb
Host smart-dba86689-f5f1-41f9-9186-7864c6ca4d8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037658916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3037658916
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.573580458
Short name T426
Test name
Test status
Simulation time 167748275952 ps
CPU time 20.98 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 04:57:33 PM PDT 24
Peak memory 199692 kb
Host smart-1a6ec9d8-4ab8-4fb0-9b6b-21d772c94d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573580458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.573580458
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.53381219
Short name T835
Test name
Test status
Simulation time 5738747827 ps
CPU time 2.55 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 04:57:14 PM PDT 24
Peak memory 196312 kb
Host smart-6f1e3be7-c7fc-4694-b418-f02b89de02ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53381219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.53381219
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.186195264
Short name T968
Test name
Test status
Simulation time 635527023 ps
CPU time 2.02 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:57:18 PM PDT 24
Peak memory 198584 kb
Host smart-94b56e2a-b620-459c-989f-0366467d39ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186195264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.186195264
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2892672008
Short name T406
Test name
Test status
Simulation time 308061918298 ps
CPU time 377.98 seconds
Started Jul 16 04:57:17 PM PDT 24
Finished Jul 16 05:03:36 PM PDT 24
Peak memory 208192 kb
Host smart-2b8fa7a4-67ee-45aa-888e-8dbdccff6b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892672008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2892672008
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1682224745
Short name T471
Test name
Test status
Simulation time 37446997498 ps
CPU time 156.83 seconds
Started Jul 16 04:57:09 PM PDT 24
Finished Jul 16 04:59:47 PM PDT 24
Peak memory 216120 kb
Host smart-7cdaaecc-95e0-43d8-a3a8-16348a7d8571
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682224745 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1682224745
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2363104652
Short name T570
Test name
Test status
Simulation time 502448856 ps
CPU time 1.67 seconds
Started Jul 16 04:57:06 PM PDT 24
Finished Jul 16 04:57:08 PM PDT 24
Peak memory 197840 kb
Host smart-fbc560b7-6d31-4e6a-866b-97e3dd6ebf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363104652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2363104652
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3280387311
Short name T458
Test name
Test status
Simulation time 77110296225 ps
CPU time 71.6 seconds
Started Jul 16 04:57:10 PM PDT 24
Finished Jul 16 04:58:23 PM PDT 24
Peak memory 199808 kb
Host smart-e1de08e1-6925-42e8-bedd-d28c1c4ec13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280387311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3280387311
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1972075264
Short name T365
Test name
Test status
Simulation time 34800916227 ps
CPU time 18.12 seconds
Started Jul 16 05:00:08 PM PDT 24
Finished Jul 16 05:00:27 PM PDT 24
Peak memory 199728 kb
Host smart-dd0120b8-cb67-498d-9761-4d815e12cd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972075264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1972075264
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2811902314
Short name T839
Test name
Test status
Simulation time 22105102032 ps
CPU time 5.21 seconds
Started Jul 16 05:00:09 PM PDT 24
Finished Jul 16 05:00:15 PM PDT 24
Peak memory 199716 kb
Host smart-5035fcc8-a39a-4315-b1d4-42df15d3b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811902314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2811902314
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2147418430
Short name T175
Test name
Test status
Simulation time 52823856531 ps
CPU time 22.82 seconds
Started Jul 16 05:00:08 PM PDT 24
Finished Jul 16 05:00:32 PM PDT 24
Peak memory 199876 kb
Host smart-53573de2-241a-4b7f-b307-4367aaa00ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147418430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2147418430
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.4136533588
Short name T802
Test name
Test status
Simulation time 45860579372 ps
CPU time 77.04 seconds
Started Jul 16 05:00:07 PM PDT 24
Finished Jul 16 05:01:26 PM PDT 24
Peak memory 199552 kb
Host smart-ef9ccfbd-cee8-4ff4-93ce-63bf7a15b61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136533588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4136533588
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1559209004
Short name T180
Test name
Test status
Simulation time 204731378537 ps
CPU time 79.49 seconds
Started Jul 16 05:00:08 PM PDT 24
Finished Jul 16 05:01:28 PM PDT 24
Peak memory 199804 kb
Host smart-22406c26-cb0c-4c99-9b6f-7d4e3c233d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559209004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1559209004
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1401048770
Short name T860
Test name
Test status
Simulation time 28936897525 ps
CPU time 47.54 seconds
Started Jul 16 05:00:07 PM PDT 24
Finished Jul 16 05:00:55 PM PDT 24
Peak memory 199792 kb
Host smart-85801145-6a94-4877-bdef-15898b8af994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401048770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1401048770
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2199464016
Short name T1110
Test name
Test status
Simulation time 34623698112 ps
CPU time 64.8 seconds
Started Jul 16 05:00:10 PM PDT 24
Finished Jul 16 05:01:15 PM PDT 24
Peak memory 199776 kb
Host smart-b94009d0-5129-4346-ba7d-a5f0ab3ca0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199464016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2199464016
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1437215128
Short name T803
Test name
Test status
Simulation time 48876570574 ps
CPU time 39.92 seconds
Started Jul 16 05:00:08 PM PDT 24
Finished Jul 16 05:00:49 PM PDT 24
Peak memory 199760 kb
Host smart-342ce3fb-7fb2-4b71-ba45-641e60031fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437215128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1437215128
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2973164258
Short name T743
Test name
Test status
Simulation time 68177261684 ps
CPU time 40.91 seconds
Started Jul 16 05:00:07 PM PDT 24
Finished Jul 16 05:00:48 PM PDT 24
Peak memory 199584 kb
Host smart-d746b28b-d2b6-4dfe-9f5c-89fe7016ace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973164258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2973164258
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.651414902
Short name T841
Test name
Test status
Simulation time 42446401 ps
CPU time 0.62 seconds
Started Jul 16 04:57:20 PM PDT 24
Finished Jul 16 04:57:21 PM PDT 24
Peak memory 194404 kb
Host smart-41c627ae-e1d0-48ed-a9fb-8290b7110cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651414902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.651414902
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3322357150
Short name T904
Test name
Test status
Simulation time 165746894070 ps
CPU time 407.46 seconds
Started Jul 16 04:57:25 PM PDT 24
Finished Jul 16 05:04:13 PM PDT 24
Peak memory 199680 kb
Host smart-d7a6da24-7ee1-4b23-8c2d-70880df2edb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322357150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3322357150
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1144788696
Short name T38
Test name
Test status
Simulation time 13414937524 ps
CPU time 22.34 seconds
Started Jul 16 04:57:13 PM PDT 24
Finished Jul 16 04:57:37 PM PDT 24
Peak memory 199688 kb
Host smart-30ef7dd2-35e8-4a16-b3c6-eb5f3e26dd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144788696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1144788696
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.115382917
Short name T789
Test name
Test status
Simulation time 82841176772 ps
CPU time 149.46 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:59:45 PM PDT 24
Peak memory 199816 kb
Host smart-261647f9-946a-49aa-9717-4958b4247ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115382917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.115382917
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.4176742846
Short name T1019
Test name
Test status
Simulation time 59682019915 ps
CPU time 24.91 seconds
Started Jul 16 04:57:15 PM PDT 24
Finished Jul 16 04:57:42 PM PDT 24
Peak memory 198768 kb
Host smart-e60e32e5-744a-4a6f-a9fe-5fe052df57f0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176742846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.4176742846
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2775418528
Short name T480
Test name
Test status
Simulation time 87395950749 ps
CPU time 512.99 seconds
Started Jul 16 04:57:16 PM PDT 24
Finished Jul 16 05:05:50 PM PDT 24
Peak memory 199640 kb
Host smart-7a80ab3d-d1cd-4fdb-9683-ec3ae7e77b56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2775418528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2775418528
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1821380719
Short name T1014
Test name
Test status
Simulation time 11809191691 ps
CPU time 20.29 seconds
Started Jul 16 04:57:20 PM PDT 24
Finished Jul 16 04:57:41 PM PDT 24
Peak memory 199752 kb
Host smart-6d08f1ce-11df-4bf2-b981-bbb184ec090a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821380719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1821380719
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1600651099
Short name T74
Test name
Test status
Simulation time 80316371660 ps
CPU time 136.36 seconds
Started Jul 16 04:57:15 PM PDT 24
Finished Jul 16 04:59:33 PM PDT 24
Peak memory 200032 kb
Host smart-d00753ff-4277-4fb1-b44c-e3f0c5f37a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600651099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1600651099
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1185717507
Short name T551
Test name
Test status
Simulation time 25257548321 ps
CPU time 249.19 seconds
Started Jul 16 04:57:20 PM PDT 24
Finished Jul 16 05:01:30 PM PDT 24
Peak memory 199876 kb
Host smart-1f2aa05b-e885-4c2b-982c-6cfbd7185f65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1185717507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1185717507
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.692034303
Short name T804
Test name
Test status
Simulation time 2642975232 ps
CPU time 4.58 seconds
Started Jul 16 04:57:19 PM PDT 24
Finished Jul 16 04:57:24 PM PDT 24
Peak memory 197992 kb
Host smart-8f346181-edff-4bf9-9c60-5cdfaa0b3fb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692034303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.692034303
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1227988832
Short name T118
Test name
Test status
Simulation time 55436557396 ps
CPU time 75.7 seconds
Started Jul 16 04:57:31 PM PDT 24
Finished Jul 16 04:58:47 PM PDT 24
Peak memory 199728 kb
Host smart-dbacc905-ccfc-43d0-b536-11028dd6299d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227988832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1227988832
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1891222238
Short name T545
Test name
Test status
Simulation time 2980591017 ps
CPU time 5.03 seconds
Started Jul 16 04:57:16 PM PDT 24
Finished Jul 16 04:57:23 PM PDT 24
Peak memory 195792 kb
Host smart-a595b9f3-55aa-465a-8235-1c0592851af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891222238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1891222238
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2073465321
Short name T607
Test name
Test status
Simulation time 804054153 ps
CPU time 3.06 seconds
Started Jul 16 04:57:26 PM PDT 24
Finished Jul 16 04:57:29 PM PDT 24
Peak memory 198092 kb
Host smart-7f3490ee-d42f-405f-bfb8-6dc862bbfca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073465321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2073465321
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3872310275
Short name T1173
Test name
Test status
Simulation time 95474497317 ps
CPU time 182.52 seconds
Started Jul 16 04:57:15 PM PDT 24
Finished Jul 16 05:00:19 PM PDT 24
Peak memory 215572 kb
Host smart-986154b6-cee1-4bf9-9599-89dca7c2b214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872310275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3872310275
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3857242475
Short name T49
Test name
Test status
Simulation time 8017164523 ps
CPU time 10.23 seconds
Started Jul 16 04:57:13 PM PDT 24
Finished Jul 16 04:57:25 PM PDT 24
Peak memory 199476 kb
Host smart-f6491c23-8ce1-415e-ae88-fbd1fddd1323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857242475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3857242475
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3318547411
Short name T648
Test name
Test status
Simulation time 31725376632 ps
CPU time 51.43 seconds
Started Jul 16 05:00:08 PM PDT 24
Finished Jul 16 05:01:01 PM PDT 24
Peak memory 199624 kb
Host smart-ff90e001-bc1b-40bd-91b1-b12328a9fc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318547411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3318547411
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3858603761
Short name T774
Test name
Test status
Simulation time 49342310856 ps
CPU time 31.87 seconds
Started Jul 16 05:00:07 PM PDT 24
Finished Jul 16 05:00:40 PM PDT 24
Peak memory 199900 kb
Host smart-382656d2-dca5-4145-a0db-b3b61cfe49c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858603761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3858603761
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4282589835
Short name T579
Test name
Test status
Simulation time 42259908504 ps
CPU time 17.21 seconds
Started Jul 16 05:00:08 PM PDT 24
Finished Jul 16 05:00:26 PM PDT 24
Peak memory 199780 kb
Host smart-2194374b-77c4-48e0-916a-a0fe13b9b5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282589835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4282589835
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1842996319
Short name T1037
Test name
Test status
Simulation time 199209181700 ps
CPU time 79.53 seconds
Started Jul 16 05:00:08 PM PDT 24
Finished Jul 16 05:01:28 PM PDT 24
Peak memory 199788 kb
Host smart-b94254d9-5a6b-4409-bc19-dfc0e80686d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842996319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1842996319
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2202007374
Short name T688
Test name
Test status
Simulation time 108236326945 ps
CPU time 161.55 seconds
Started Jul 16 05:00:17 PM PDT 24
Finished Jul 16 05:02:59 PM PDT 24
Peak memory 199904 kb
Host smart-52f31144-7d33-49a9-8ed5-c8629b139388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202007374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2202007374
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1135002254
Short name T916
Test name
Test status
Simulation time 46695463592 ps
CPU time 94.88 seconds
Started Jul 16 05:00:06 PM PDT 24
Finished Jul 16 05:01:42 PM PDT 24
Peak memory 199852 kb
Host smart-e5735fcf-4dc3-4834-aba7-a08d69d4cbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135002254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1135002254
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.4152949877
Short name T252
Test name
Test status
Simulation time 78265630967 ps
CPU time 30.63 seconds
Started Jul 16 05:00:09 PM PDT 24
Finished Jul 16 05:00:41 PM PDT 24
Peak memory 199328 kb
Host smart-da95a759-a00f-4676-815f-08ec9c958972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152949877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.4152949877
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1384954645
Short name T985
Test name
Test status
Simulation time 30425238700 ps
CPU time 16.6 seconds
Started Jul 16 05:00:08 PM PDT 24
Finished Jul 16 05:00:26 PM PDT 24
Peak memory 199332 kb
Host smart-02b44f93-ff9a-4b6c-8995-63cea8665c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384954645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1384954645
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1899975165
Short name T1022
Test name
Test status
Simulation time 42914269 ps
CPU time 0.56 seconds
Started Jul 16 04:57:30 PM PDT 24
Finished Jul 16 04:57:32 PM PDT 24
Peak memory 195476 kb
Host smart-277593b7-1f90-4e62-a00e-122ee04f8e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899975165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1899975165
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2971739510
Short name T79
Test name
Test status
Simulation time 45868969213 ps
CPU time 5.96 seconds
Started Jul 16 04:57:27 PM PDT 24
Finished Jul 16 04:57:34 PM PDT 24
Peak memory 199640 kb
Host smart-4586ca3a-6ab1-4eb3-9cbf-259c5a70abd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971739510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2971739510
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.935417195
Short name T522
Test name
Test status
Simulation time 100906558978 ps
CPU time 30.74 seconds
Started Jul 16 04:57:23 PM PDT 24
Finished Jul 16 04:57:54 PM PDT 24
Peak memory 200116 kb
Host smart-e222b573-e90f-4fd6-974e-ea711525bbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935417195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.935417195
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1264530799
Short name T204
Test name
Test status
Simulation time 34982914142 ps
CPU time 72.05 seconds
Started Jul 16 04:57:22 PM PDT 24
Finished Jul 16 04:58:34 PM PDT 24
Peak memory 199688 kb
Host smart-75e7a05e-6b8d-4ecd-ad02-cc9e8d6a5d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264530799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1264530799
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2053429339
Short name T822
Test name
Test status
Simulation time 8226326933 ps
CPU time 4.74 seconds
Started Jul 16 04:57:26 PM PDT 24
Finished Jul 16 04:57:31 PM PDT 24
Peak memory 198704 kb
Host smart-7beb0397-cd7d-4076-9632-6b74fc8279b1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053429339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2053429339
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1399680865
Short name T1045
Test name
Test status
Simulation time 135225516230 ps
CPU time 310.08 seconds
Started Jul 16 04:57:13 PM PDT 24
Finished Jul 16 05:02:24 PM PDT 24
Peak memory 199736 kb
Host smart-648406eb-bc51-422b-84ee-8e35b346af64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399680865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1399680865
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.4248017421
Short name T894
Test name
Test status
Simulation time 7001019313 ps
CPU time 8.11 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:57:24 PM PDT 24
Peak memory 198724 kb
Host smart-0368f546-12b5-4c7b-a3a7-9de0e3a34a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248017421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.4248017421
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1864187758
Short name T1048
Test name
Test status
Simulation time 77623126273 ps
CPU time 74.25 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:58:30 PM PDT 24
Peak memory 200028 kb
Host smart-70878e19-9c2d-420e-aaff-8616c14e47a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864187758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1864187758
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2590307236
Short name T414
Test name
Test status
Simulation time 9632864521 ps
CPU time 133.54 seconds
Started Jul 16 04:57:13 PM PDT 24
Finished Jul 16 04:59:27 PM PDT 24
Peak memory 199700 kb
Host smart-e05886dd-b6a0-4dde-a862-5c0f7c202739
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2590307236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2590307236
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.398293301
Short name T354
Test name
Test status
Simulation time 4670375172 ps
CPU time 5.11 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:57:21 PM PDT 24
Peak memory 198924 kb
Host smart-f46ed989-9a1f-41f3-8f53-9ddd37e7895a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=398293301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.398293301
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.995802113
Short name T146
Test name
Test status
Simulation time 30917403970 ps
CPU time 27.2 seconds
Started Jul 16 04:57:13 PM PDT 24
Finished Jul 16 04:57:41 PM PDT 24
Peak memory 199364 kb
Host smart-a1b4dc57-80fa-4db2-a8c8-dc3d19660ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995802113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.995802113
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3578486954
Short name T561
Test name
Test status
Simulation time 4258718579 ps
CPU time 2.03 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:57:18 PM PDT 24
Peak memory 195800 kb
Host smart-7ef2f0e1-86fa-4363-941c-13fb91d4e959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578486954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3578486954
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.423687490
Short name T550
Test name
Test status
Simulation time 310366642 ps
CPU time 1.08 seconds
Started Jul 16 04:57:16 PM PDT 24
Finished Jul 16 04:57:19 PM PDT 24
Peak memory 199040 kb
Host smart-5fbc7115-ebc7-4bba-8b8f-7524fc58c15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423687490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.423687490
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2160936946
Short name T936
Test name
Test status
Simulation time 7030426722 ps
CPU time 65.86 seconds
Started Jul 16 04:57:20 PM PDT 24
Finished Jul 16 04:58:26 PM PDT 24
Peak memory 199660 kb
Host smart-d16aeb06-81e9-4bb1-a36b-53f795caa580
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160936946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2160936946
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.704688561
Short name T183
Test name
Test status
Simulation time 417119792487 ps
CPU time 1559.47 seconds
Started Jul 16 04:57:29 PM PDT 24
Finished Jul 16 05:23:29 PM PDT 24
Peak memory 228720 kb
Host smart-c3049fd9-314b-445c-ac44-7db48925cb9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704688561 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.704688561
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3578373917
Short name T647
Test name
Test status
Simulation time 3377241426 ps
CPU time 1.69 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:57:18 PM PDT 24
Peak memory 198588 kb
Host smart-e883d78b-e9d8-4f09-aeff-e628f93ad122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578373917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3578373917
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3621324877
Short name T709
Test name
Test status
Simulation time 36329510467 ps
CPU time 57.79 seconds
Started Jul 16 04:57:24 PM PDT 24
Finished Jul 16 04:58:22 PM PDT 24
Peak memory 199752 kb
Host smart-97cf6845-896f-4848-95ee-632869aabc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621324877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3621324877
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2242644538
Short name T258
Test name
Test status
Simulation time 42978644583 ps
CPU time 18.83 seconds
Started Jul 16 05:00:07 PM PDT 24
Finished Jul 16 05:00:26 PM PDT 24
Peak memory 199812 kb
Host smart-7bf46f74-9f50-4dc5-bbeb-7bfd1289d6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242644538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2242644538
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1615875091
Short name T227
Test name
Test status
Simulation time 20321218490 ps
CPU time 16.92 seconds
Started Jul 16 05:00:09 PM PDT 24
Finished Jul 16 05:00:26 PM PDT 24
Peak memory 199740 kb
Host smart-a9b0b67c-fd90-47fb-92da-5cb056f7c88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615875091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1615875091
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.653729664
Short name T956
Test name
Test status
Simulation time 10987042267 ps
CPU time 17.74 seconds
Started Jul 16 05:00:09 PM PDT 24
Finished Jul 16 05:00:28 PM PDT 24
Peak memory 199856 kb
Host smart-813f6fd1-82ec-4f07-afc5-d587286587f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653729664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.653729664
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1073523486
Short name T1033
Test name
Test status
Simulation time 42443177473 ps
CPU time 79.37 seconds
Started Jul 16 05:00:07 PM PDT 24
Finished Jul 16 05:01:27 PM PDT 24
Peak memory 199788 kb
Host smart-341d8b92-388c-4705-a102-289a3f35d71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073523486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1073523486
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2033247271
Short name T487
Test name
Test status
Simulation time 72702096489 ps
CPU time 49.46 seconds
Started Jul 16 05:00:07 PM PDT 24
Finished Jul 16 05:00:57 PM PDT 24
Peak memory 199780 kb
Host smart-56c804a8-c507-4d17-a34d-135717e82d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033247271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2033247271
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2183090436
Short name T766
Test name
Test status
Simulation time 215673895223 ps
CPU time 32.61 seconds
Started Jul 16 05:00:09 PM PDT 24
Finished Jul 16 05:00:43 PM PDT 24
Peak memory 199792 kb
Host smart-8a8be5bc-fb1e-45c5-8878-69d3a7d513c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183090436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2183090436
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.644225495
Short name T372
Test name
Test status
Simulation time 10377970440 ps
CPU time 16.75 seconds
Started Jul 16 05:00:24 PM PDT 24
Finished Jul 16 05:00:41 PM PDT 24
Peak memory 199840 kb
Host smart-ec95b20f-f9a0-4cd0-9541-f60ddf488bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644225495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.644225495
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.402683527
Short name T1032
Test name
Test status
Simulation time 109866116274 ps
CPU time 22.2 seconds
Started Jul 16 05:00:19 PM PDT 24
Finished Jul 16 05:00:42 PM PDT 24
Peak memory 199872 kb
Host smart-7b990a7b-17a3-4610-aadd-8b9d4714261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402683527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.402683527
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4154774267
Short name T754
Test name
Test status
Simulation time 13717667 ps
CPU time 0.55 seconds
Started Jul 16 04:57:28 PM PDT 24
Finished Jul 16 04:57:30 PM PDT 24
Peak memory 195140 kb
Host smart-2bab3be4-ed77-42c6-b93a-a22e49be8137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154774267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4154774267
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3835175374
Short name T114
Test name
Test status
Simulation time 318044496002 ps
CPU time 342.45 seconds
Started Jul 16 04:57:15 PM PDT 24
Finished Jul 16 05:02:58 PM PDT 24
Peak memory 199828 kb
Host smart-18fd2230-a130-407d-8006-83a370414359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835175374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3835175374
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.158402493
Short name T1059
Test name
Test status
Simulation time 71249447037 ps
CPU time 132.18 seconds
Started Jul 16 04:57:11 PM PDT 24
Finished Jul 16 04:59:24 PM PDT 24
Peak memory 199792 kb
Host smart-fb4f868e-b158-41d3-b63b-e62387c270e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158402493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.158402493
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.226833915
Short name T135
Test name
Test status
Simulation time 42045039108 ps
CPU time 76.44 seconds
Started Jul 16 04:57:22 PM PDT 24
Finished Jul 16 04:58:39 PM PDT 24
Peak memory 199728 kb
Host smart-1b61b1bd-402d-4dce-bc21-4a258d627450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226833915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.226833915
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3102970923
Short name T334
Test name
Test status
Simulation time 31785313644 ps
CPU time 14.31 seconds
Started Jul 16 04:57:16 PM PDT 24
Finished Jul 16 04:57:32 PM PDT 24
Peak memory 199268 kb
Host smart-39e50c47-2929-4c1b-a14e-df7bdcf8d5a9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102970923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3102970923
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1846686347
Short name T300
Test name
Test status
Simulation time 94747766160 ps
CPU time 663.76 seconds
Started Jul 16 04:57:36 PM PDT 24
Finished Jul 16 05:08:40 PM PDT 24
Peak memory 199784 kb
Host smart-5e24ee68-32a2-49ad-93e1-bd424926937b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1846686347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1846686347
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.110240189
Short name T776
Test name
Test status
Simulation time 3435362287 ps
CPU time 3.93 seconds
Started Jul 16 04:57:12 PM PDT 24
Finished Jul 16 04:57:17 PM PDT 24
Peak memory 197628 kb
Host smart-90ff88d9-5fb0-4f63-9627-a1a7aa018400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110240189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.110240189
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.4037514073
Short name T610
Test name
Test status
Simulation time 72484027277 ps
CPU time 124.44 seconds
Started Jul 16 04:57:13 PM PDT 24
Finished Jul 16 04:59:19 PM PDT 24
Peak memory 200096 kb
Host smart-c1411354-4c3b-4897-aae9-5519a002abe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037514073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4037514073
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1714975372
Short name T990
Test name
Test status
Simulation time 12363596628 ps
CPU time 172.74 seconds
Started Jul 16 04:57:20 PM PDT 24
Finished Jul 16 05:00:13 PM PDT 24
Peak memory 199840 kb
Host smart-d7411bd4-fac2-4d87-b905-730768bd2d60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714975372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1714975372
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3001976608
Short name T338
Test name
Test status
Simulation time 3625609158 ps
CPU time 26.14 seconds
Started Jul 16 04:57:14 PM PDT 24
Finished Jul 16 04:57:42 PM PDT 24
Peak memory 197644 kb
Host smart-287eab28-1845-4b73-a757-6f71c851ed56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001976608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3001976608
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3917064666
Short name T18
Test name
Test status
Simulation time 93081796636 ps
CPU time 35.61 seconds
Started Jul 16 04:57:16 PM PDT 24
Finished Jul 16 04:57:53 PM PDT 24
Peak memory 199664 kb
Host smart-28a1eedc-5324-4cef-bc89-52f58850187c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917064666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3917064666
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3018833641
Short name T952
Test name
Test status
Simulation time 3783309269 ps
CPU time 2.09 seconds
Started Jul 16 04:57:26 PM PDT 24
Finished Jul 16 04:57:29 PM PDT 24
Peak memory 195568 kb
Host smart-16895521-f912-428a-a7c1-2065421e8af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018833641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3018833641
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2099589581
Short name T1069
Test name
Test status
Simulation time 5715496006 ps
CPU time 10.72 seconds
Started Jul 16 04:57:16 PM PDT 24
Finished Jul 16 04:57:28 PM PDT 24
Peak memory 199480 kb
Host smart-a2f55d45-d8e3-4c79-bf64-b7362db15cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099589581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2099589581
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.920926898
Short name T714
Test name
Test status
Simulation time 209241695933 ps
CPU time 156.85 seconds
Started Jul 16 04:57:33 PM PDT 24
Finished Jul 16 05:00:10 PM PDT 24
Peak memory 199728 kb
Host smart-e50cdc9d-56d0-4c86-811e-4ee679b0578a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920926898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.920926898
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2256463904
Short name T660
Test name
Test status
Simulation time 48219353096 ps
CPU time 835.99 seconds
Started Jul 16 04:57:39 PM PDT 24
Finished Jul 16 05:11:36 PM PDT 24
Peak memory 216412 kb
Host smart-7577322c-522d-46a3-8c33-313486581bb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256463904 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2256463904
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3246059797
Short name T828
Test name
Test status
Simulation time 1211941587 ps
CPU time 3.78 seconds
Started Jul 16 04:57:12 PM PDT 24
Finished Jul 16 04:57:17 PM PDT 24
Peak memory 199532 kb
Host smart-8af2b4cd-8c60-49be-904d-a0052efcd06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246059797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3246059797
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3017546535
Short name T997
Test name
Test status
Simulation time 145425772568 ps
CPU time 26.14 seconds
Started Jul 16 05:00:21 PM PDT 24
Finished Jul 16 05:00:47 PM PDT 24
Peak memory 199704 kb
Host smart-615f611f-b8b2-4078-9b1c-97ca3276b785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017546535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3017546535
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2714869586
Short name T298
Test name
Test status
Simulation time 50959494441 ps
CPU time 84.26 seconds
Started Jul 16 05:00:17 PM PDT 24
Finished Jul 16 05:01:42 PM PDT 24
Peak memory 199820 kb
Host smart-56363c56-08d3-40dd-b915-559aa8117c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714869586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2714869586
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2663825568
Short name T1041
Test name
Test status
Simulation time 110050932337 ps
CPU time 149.55 seconds
Started Jul 16 05:00:18 PM PDT 24
Finished Jul 16 05:02:49 PM PDT 24
Peak memory 199816 kb
Host smart-3d7e94fd-44cd-473d-b51d-d64851ad73bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663825568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2663825568
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3810818814
Short name T799
Test name
Test status
Simulation time 186332987965 ps
CPU time 26.61 seconds
Started Jul 16 05:00:18 PM PDT 24
Finished Jul 16 05:00:46 PM PDT 24
Peak memory 199844 kb
Host smart-c3afdd44-51a7-4129-abb0-b738d4a3c0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810818814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3810818814
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1135787673
Short name T209
Test name
Test status
Simulation time 204273010055 ps
CPU time 308.91 seconds
Started Jul 16 05:00:17 PM PDT 24
Finished Jul 16 05:05:28 PM PDT 24
Peak memory 199804 kb
Host smart-1ede7152-e007-401e-a27c-2c17329b0b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135787673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1135787673
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2227426019
Short name T910
Test name
Test status
Simulation time 122843660696 ps
CPU time 52.06 seconds
Started Jul 16 05:00:17 PM PDT 24
Finished Jul 16 05:01:10 PM PDT 24
Peak memory 199772 kb
Host smart-354264a8-528d-4505-9aa3-cbd037c3bb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227426019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2227426019
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2519279129
Short name T773
Test name
Test status
Simulation time 43727772835 ps
CPU time 62.06 seconds
Started Jul 16 05:00:18 PM PDT 24
Finished Jul 16 05:01:22 PM PDT 24
Peak memory 199864 kb
Host smart-f6d2317a-1e71-48ac-bf30-35ac1f7d9cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519279129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2519279129
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2694448859
Short name T323
Test name
Test status
Simulation time 25945788805 ps
CPU time 30.62 seconds
Started Jul 16 05:00:18 PM PDT 24
Finished Jul 16 05:00:50 PM PDT 24
Peak memory 199872 kb
Host smart-8da4a12a-2adc-4109-8f18-87f079a157f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694448859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2694448859
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2032362665
Short name T542
Test name
Test status
Simulation time 169995650409 ps
CPU time 36.82 seconds
Started Jul 16 05:00:19 PM PDT 24
Finished Jul 16 05:00:57 PM PDT 24
Peak memory 199836 kb
Host smart-8e747c90-60a6-4fc3-980d-6dba9d90b199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032362665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2032362665
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2185483899
Short name T418
Test name
Test status
Simulation time 33088434 ps
CPU time 0.55 seconds
Started Jul 16 04:57:33 PM PDT 24
Finished Jul 16 04:57:34 PM PDT 24
Peak memory 195376 kb
Host smart-050b8df2-1e1f-4146-ad2f-3811925ee0eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185483899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2185483899
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.466266811
Short name T514
Test name
Test status
Simulation time 82503702548 ps
CPU time 124.84 seconds
Started Jul 16 04:57:35 PM PDT 24
Finished Jul 16 04:59:40 PM PDT 24
Peak memory 199760 kb
Host smart-df8257d0-747a-47ab-8409-996f2cfd6346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466266811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.466266811
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1496516119
Short name T533
Test name
Test status
Simulation time 224099357535 ps
CPU time 203.1 seconds
Started Jul 16 04:57:31 PM PDT 24
Finished Jul 16 05:00:55 PM PDT 24
Peak memory 199860 kb
Host smart-f5498655-5788-4faa-b140-5cf94adbd242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496516119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1496516119
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1609566198
Short name T665
Test name
Test status
Simulation time 210306223420 ps
CPU time 52.18 seconds
Started Jul 16 04:57:30 PM PDT 24
Finished Jul 16 04:58:23 PM PDT 24
Peak memory 199580 kb
Host smart-4588637e-107c-4a16-9726-f8f52ca2c65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609566198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1609566198
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2812612292
Short name T646
Test name
Test status
Simulation time 22812029020 ps
CPU time 12.96 seconds
Started Jul 16 04:57:31 PM PDT 24
Finished Jul 16 04:57:45 PM PDT 24
Peak memory 199796 kb
Host smart-cbe22ad0-5fba-4271-a653-cd11edefed17
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812612292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2812612292
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.907705060
Short name T955
Test name
Test status
Simulation time 173415328348 ps
CPU time 1104.09 seconds
Started Jul 16 04:57:31 PM PDT 24
Finished Jul 16 05:15:56 PM PDT 24
Peak memory 199732 kb
Host smart-a6f0b1fb-4fc2-4104-a76d-b5158d1adf28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=907705060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.907705060
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.307368609
Short name T1138
Test name
Test status
Simulation time 5933980725 ps
CPU time 3.33 seconds
Started Jul 16 04:57:32 PM PDT 24
Finished Jul 16 04:57:36 PM PDT 24
Peak memory 199344 kb
Host smart-a042a2ed-4f26-40b3-ae4a-22f5015d20ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307368609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.307368609
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2532881043
Short name T840
Test name
Test status
Simulation time 158728287874 ps
CPU time 252.45 seconds
Started Jul 16 04:57:33 PM PDT 24
Finished Jul 16 05:01:46 PM PDT 24
Peak memory 208236 kb
Host smart-2def61b6-8de7-4a77-a59e-fc2d930bd293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532881043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2532881043
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1884623077
Short name T419
Test name
Test status
Simulation time 13181554172 ps
CPU time 179.63 seconds
Started Jul 16 04:57:32 PM PDT 24
Finished Jul 16 05:00:32 PM PDT 24
Peak memory 199800 kb
Host smart-4860a1a3-ba3b-4c09-be84-20ed73b8998d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1884623077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1884623077
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1699948697
Short name T830
Test name
Test status
Simulation time 5496211220 ps
CPU time 21.7 seconds
Started Jul 16 04:57:28 PM PDT 24
Finished Jul 16 04:57:50 PM PDT 24
Peak memory 199592 kb
Host smart-2e9d1266-922a-49a4-aa20-ecf216c21941
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699948697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1699948697
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2255589217
Short name T606
Test name
Test status
Simulation time 33296978514 ps
CPU time 18.1 seconds
Started Jul 16 04:57:27 PM PDT 24
Finished Jul 16 04:57:46 PM PDT 24
Peak memory 199800 kb
Host smart-8d849d6b-7cab-41e1-baec-d5ea6edac516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255589217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2255589217
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2101680824
Short name T1027
Test name
Test status
Simulation time 3749409446 ps
CPU time 3.45 seconds
Started Jul 16 04:57:35 PM PDT 24
Finished Jul 16 04:57:39 PM PDT 24
Peak memory 196044 kb
Host smart-fb2bfddb-416f-4c88-a7e7-5ac1e9e946ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101680824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2101680824
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.4146552580
Short name T732
Test name
Test status
Simulation time 322857190 ps
CPU time 1.04 seconds
Started Jul 16 04:57:33 PM PDT 24
Finished Jul 16 04:57:34 PM PDT 24
Peak memory 198528 kb
Host smart-5c28241e-3139-4d44-887d-6b9e7fc275d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146552580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.4146552580
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2919571063
Short name T696
Test name
Test status
Simulation time 227318081847 ps
CPU time 221.8 seconds
Started Jul 16 04:57:35 PM PDT 24
Finished Jul 16 05:01:17 PM PDT 24
Peak memory 208168 kb
Host smart-a1d18941-fd76-4bc7-8f1b-c8c8c24f8e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919571063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2919571063
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3622498039
Short name T1013
Test name
Test status
Simulation time 95486476444 ps
CPU time 1069.05 seconds
Started Jul 16 04:57:30 PM PDT 24
Finished Jul 16 05:15:20 PM PDT 24
Peak memory 225820 kb
Host smart-26f71c88-c8ce-4a8f-8f5f-7d908a4b9d8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622498039 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3622498039
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3681458566
Short name T569
Test name
Test status
Simulation time 1495674346 ps
CPU time 2.36 seconds
Started Jul 16 04:57:28 PM PDT 24
Finished Jul 16 04:57:31 PM PDT 24
Peak memory 198644 kb
Host smart-5c249c76-6b16-4e6b-bbc9-6a8261b3d71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681458566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3681458566
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3046597261
Short name T1125
Test name
Test status
Simulation time 71558897455 ps
CPU time 60.62 seconds
Started Jul 16 04:57:33 PM PDT 24
Finished Jul 16 04:58:34 PM PDT 24
Peak memory 199800 kb
Host smart-c3711be3-7db0-45d3-a6ec-2b20c4158f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046597261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3046597261
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3518640737
Short name T529
Test name
Test status
Simulation time 253897682291 ps
CPU time 72.98 seconds
Started Jul 16 05:00:18 PM PDT 24
Finished Jul 16 05:01:33 PM PDT 24
Peak memory 199596 kb
Host smart-c2ee35a6-af72-4a18-bd31-8f854534f053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518640737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3518640737
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.887609202
Short name T932
Test name
Test status
Simulation time 8947141967 ps
CPU time 17.7 seconds
Started Jul 16 05:00:17 PM PDT 24
Finished Jul 16 05:00:35 PM PDT 24
Peak memory 199756 kb
Host smart-0a752b4e-9bcd-4668-956c-3c9acd1a65f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887609202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.887609202
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3658438738
Short name T140
Test name
Test status
Simulation time 120145330093 ps
CPU time 100.6 seconds
Started Jul 16 05:00:24 PM PDT 24
Finished Jul 16 05:02:05 PM PDT 24
Peak memory 199704 kb
Host smart-ee5d69c8-8519-49c9-95e9-96911293bd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658438738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3658438738
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1666734803
Short name T779
Test name
Test status
Simulation time 96739228846 ps
CPU time 129.67 seconds
Started Jul 16 05:00:20 PM PDT 24
Finished Jul 16 05:02:31 PM PDT 24
Peak memory 199668 kb
Host smart-eb97e1e8-8c86-4732-ac4e-4c8f53b720fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666734803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1666734803
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.784434886
Short name T725
Test name
Test status
Simulation time 36185236706 ps
CPU time 13.79 seconds
Started Jul 16 05:00:18 PM PDT 24
Finished Jul 16 05:00:33 PM PDT 24
Peak memory 199604 kb
Host smart-b2851195-93cb-4693-9c3c-4cb30ab70dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784434886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.784434886
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2273268585
Short name T315
Test name
Test status
Simulation time 12246015607 ps
CPU time 7.85 seconds
Started Jul 16 05:00:19 PM PDT 24
Finished Jul 16 05:00:28 PM PDT 24
Peak memory 199840 kb
Host smart-333da306-41ca-45df-ab09-9425fbe2e67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273268585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2273268585
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3365101622
Short name T1181
Test name
Test status
Simulation time 130994280555 ps
CPU time 356.12 seconds
Started Jul 16 05:00:24 PM PDT 24
Finished Jul 16 05:06:21 PM PDT 24
Peak memory 199816 kb
Host smart-2e3d9dea-2809-45df-9da9-c97c640bad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365101622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3365101622
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1817897923
Short name T366
Test name
Test status
Simulation time 82882002233 ps
CPU time 113.24 seconds
Started Jul 16 05:00:18 PM PDT 24
Finished Jul 16 05:02:13 PM PDT 24
Peak memory 199704 kb
Host smart-60ba7382-571f-4b9c-aabb-5a896a75f6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817897923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1817897923
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2515171189
Short name T948
Test name
Test status
Simulation time 98689559068 ps
CPU time 479.59 seconds
Started Jul 16 05:00:19 PM PDT 24
Finished Jul 16 05:08:20 PM PDT 24
Peak memory 199756 kb
Host smart-c09bed4e-81fe-4279-83a2-e1750188280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515171189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2515171189
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.460629509
Short name T1136
Test name
Test status
Simulation time 18119373 ps
CPU time 0.57 seconds
Started Jul 16 04:57:24 PM PDT 24
Finished Jul 16 04:57:25 PM PDT 24
Peak memory 195152 kb
Host smart-747ed544-3d63-4b85-838c-34f4c837c5b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460629509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.460629509
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3573628159
Short name T124
Test name
Test status
Simulation time 21430729162 ps
CPU time 33.39 seconds
Started Jul 16 04:57:34 PM PDT 24
Finished Jul 16 04:58:08 PM PDT 24
Peak memory 199772 kb
Host smart-31c4103d-4fb9-40c1-872f-f08dae428232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573628159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3573628159
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.410248251
Short name T898
Test name
Test status
Simulation time 185662121937 ps
CPU time 145.97 seconds
Started Jul 16 04:57:24 PM PDT 24
Finished Jul 16 04:59:50 PM PDT 24
Peak memory 199836 kb
Host smart-b50d2efc-0f18-4bbb-a3c6-61e2382dba75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410248251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.410248251
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.181033669
Short name T237
Test name
Test status
Simulation time 30326590702 ps
CPU time 34.67 seconds
Started Jul 16 04:57:34 PM PDT 24
Finished Jul 16 04:58:09 PM PDT 24
Peak memory 199748 kb
Host smart-744ccfb5-8fbc-4cc5-a6f6-9b31bfff403b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181033669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.181033669
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3815915008
Short name T21
Test name
Test status
Simulation time 20833351142 ps
CPU time 33.39 seconds
Started Jul 16 04:57:34 PM PDT 24
Finished Jul 16 04:58:08 PM PDT 24
Peak memory 197884 kb
Host smart-47d897be-a324-4f60-b9d2-3bf897ef6110
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815915008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3815915008
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3767234521
Short name T262
Test name
Test status
Simulation time 102138837875 ps
CPU time 458.7 seconds
Started Jul 16 04:57:26 PM PDT 24
Finished Jul 16 05:05:05 PM PDT 24
Peak memory 199760 kb
Host smart-d5b0cab0-5932-4edd-920a-824dbb134f86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767234521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3767234521
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1830729068
Short name T795
Test name
Test status
Simulation time 3896813270 ps
CPU time 8.16 seconds
Started Jul 16 04:57:24 PM PDT 24
Finished Jul 16 04:57:32 PM PDT 24
Peak memory 198956 kb
Host smart-1271d71d-4da3-491f-b3e2-fe254c34562a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830729068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1830729068
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.4069790231
Short name T588
Test name
Test status
Simulation time 34959851147 ps
CPU time 49.98 seconds
Started Jul 16 04:57:34 PM PDT 24
Finished Jul 16 04:58:25 PM PDT 24
Peak memory 199844 kb
Host smart-b00be860-655c-48bb-9c9c-402a51968fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069790231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.4069790231
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2165640827
Short name T549
Test name
Test status
Simulation time 13084856809 ps
CPU time 154.17 seconds
Started Jul 16 04:57:28 PM PDT 24
Finished Jul 16 05:00:03 PM PDT 24
Peak memory 199732 kb
Host smart-71eb01b7-7dff-4ec7-9a51-49b9288bd90a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165640827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2165640827
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1176206541
Short name T741
Test name
Test status
Simulation time 5680533515 ps
CPU time 7.97 seconds
Started Jul 16 04:57:30 PM PDT 24
Finished Jul 16 04:57:39 PM PDT 24
Peak memory 198648 kb
Host smart-5461d134-4811-4088-a8ca-5b4abcd22b19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1176206541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1176206541
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.4240356411
Short name T184
Test name
Test status
Simulation time 74968417436 ps
CPU time 79.3 seconds
Started Jul 16 04:57:32 PM PDT 24
Finished Jul 16 04:58:52 PM PDT 24
Peak memory 199724 kb
Host smart-758f5aae-b78d-46d1-abe0-b6ae772be3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240356411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.4240356411
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3071598119
Short name T475
Test name
Test status
Simulation time 2331805146 ps
CPU time 1.44 seconds
Started Jul 16 04:57:34 PM PDT 24
Finished Jul 16 04:57:36 PM PDT 24
Peak memory 195344 kb
Host smart-538f0b30-70d2-4cab-a2a8-4246baef9d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071598119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3071598119
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2308643466
Short name T639
Test name
Test status
Simulation time 270543008 ps
CPU time 1.29 seconds
Started Jul 16 04:57:32 PM PDT 24
Finished Jul 16 04:57:34 PM PDT 24
Peak memory 198016 kb
Host smart-c4547e81-9636-41ec-8d02-61b732a4ee5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308643466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2308643466
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3850954744
Short name T769
Test name
Test status
Simulation time 113455313975 ps
CPU time 55.83 seconds
Started Jul 16 04:57:28 PM PDT 24
Finished Jul 16 04:58:25 PM PDT 24
Peak memory 199944 kb
Host smart-1894e164-d700-4e53-a5dd-9f81f5147ada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850954744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3850954744
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3783480033
Short name T644
Test name
Test status
Simulation time 18234853659 ps
CPU time 206.84 seconds
Started Jul 16 04:57:38 PM PDT 24
Finished Jul 16 05:01:05 PM PDT 24
Peak memory 216296 kb
Host smart-d1f10a27-7f74-4079-a9f2-48eed132b72f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783480033 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3783480033
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.861796195
Short name T446
Test name
Test status
Simulation time 2794991482 ps
CPU time 2.62 seconds
Started Jul 16 04:57:29 PM PDT 24
Finished Jul 16 04:57:33 PM PDT 24
Peak memory 198880 kb
Host smart-3ace9743-3019-40e7-b7f1-c8541e5d79cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861796195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.861796195
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3956204060
Short name T977
Test name
Test status
Simulation time 63874410473 ps
CPU time 53.93 seconds
Started Jul 16 04:57:34 PM PDT 24
Finished Jul 16 04:58:29 PM PDT 24
Peak memory 199872 kb
Host smart-0bb83c61-df6a-4bc4-be00-3fb45d66fe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956204060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3956204060
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1194494242
Short name T981
Test name
Test status
Simulation time 172958116147 ps
CPU time 87.09 seconds
Started Jul 16 05:00:19 PM PDT 24
Finished Jul 16 05:01:47 PM PDT 24
Peak memory 199816 kb
Host smart-d992899d-95f1-4e7c-9cdf-8b12fd4d2e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194494242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1194494242
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.411839185
Short name T668
Test name
Test status
Simulation time 25335958352 ps
CPU time 9.57 seconds
Started Jul 16 05:00:19 PM PDT 24
Finished Jul 16 05:00:30 PM PDT 24
Peak memory 199412 kb
Host smart-18eeb393-1da2-4ac2-8061-e78f8d7c2c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411839185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.411839185
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.4185703634
Short name T495
Test name
Test status
Simulation time 86227049307 ps
CPU time 37.41 seconds
Started Jul 16 05:00:24 PM PDT 24
Finished Jul 16 05:01:02 PM PDT 24
Peak memory 199864 kb
Host smart-a4052c4f-36fa-4556-95c5-adcb18c404e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185703634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.4185703634
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3159368095
Short name T1078
Test name
Test status
Simulation time 166148913052 ps
CPU time 227.21 seconds
Started Jul 16 05:00:18 PM PDT 24
Finished Jul 16 05:04:06 PM PDT 24
Peak memory 199836 kb
Host smart-dd192cbb-5dc3-4674-beb2-4ec59d643c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159368095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3159368095
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2810870120
Short name T1047
Test name
Test status
Simulation time 91543110466 ps
CPU time 83.14 seconds
Started Jul 16 05:00:19 PM PDT 24
Finished Jul 16 05:01:43 PM PDT 24
Peak memory 199780 kb
Host smart-172014af-b2e1-4a7a-99d4-0542cc65805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810870120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2810870120
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.324468771
Short name T281
Test name
Test status
Simulation time 27297790799 ps
CPU time 44.37 seconds
Started Jul 16 05:00:17 PM PDT 24
Finished Jul 16 05:01:03 PM PDT 24
Peak memory 199544 kb
Host smart-687a0cdb-8655-439f-a434-49af12fb2f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324468771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.324468771
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2545976469
Short name T678
Test name
Test status
Simulation time 32580137589 ps
CPU time 53.22 seconds
Started Jul 16 05:00:18 PM PDT 24
Finished Jul 16 05:01:12 PM PDT 24
Peak memory 200160 kb
Host smart-b6aa5ef2-af20-47fc-9e94-f107af6c40b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545976469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2545976469
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3152518958
Short name T148
Test name
Test status
Simulation time 79306083037 ps
CPU time 59.34 seconds
Started Jul 16 05:00:23 PM PDT 24
Finished Jul 16 05:01:23 PM PDT 24
Peak memory 199804 kb
Host smart-b101da16-2e33-4e91-9bfd-334ef1fa229a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152518958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3152518958
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.509154695
Short name T1112
Test name
Test status
Simulation time 127924990902 ps
CPU time 92.04 seconds
Started Jul 16 05:00:19 PM PDT 24
Finished Jul 16 05:01:52 PM PDT 24
Peak memory 199940 kb
Host smart-f4141d9d-746f-4d19-bd0a-5ff4609759af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509154695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.509154695
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.279942950
Short name T78
Test name
Test status
Simulation time 50981876252 ps
CPU time 21.16 seconds
Started Jul 16 05:00:18 PM PDT 24
Finished Jul 16 05:00:41 PM PDT 24
Peak memory 199780 kb
Host smart-f67739e8-ac4d-4104-a27d-f39b76a49138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279942950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.279942950
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.4225363434
Short name T467
Test name
Test status
Simulation time 19212889 ps
CPU time 0.58 seconds
Started Jul 16 04:57:38 PM PDT 24
Finished Jul 16 04:57:39 PM PDT 24
Peak memory 195212 kb
Host smart-e64d017c-e811-46a4-a81a-7b91c489791c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225363434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4225363434
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.487259447
Short name T587
Test name
Test status
Simulation time 96277587014 ps
CPU time 24.06 seconds
Started Jul 16 04:57:27 PM PDT 24
Finished Jul 16 04:57:52 PM PDT 24
Peak memory 199736 kb
Host smart-b75aea8a-bc66-4647-b64e-0bc708369093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487259447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.487259447
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.174525514
Short name T892
Test name
Test status
Simulation time 113991285477 ps
CPU time 152.28 seconds
Started Jul 16 04:57:31 PM PDT 24
Finished Jul 16 05:00:04 PM PDT 24
Peak memory 199792 kb
Host smart-e1406534-4ae9-4f5a-80b8-bafcacfe1271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174525514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.174525514
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.4007935844
Short name T1104
Test name
Test status
Simulation time 118739121169 ps
CPU time 91.38 seconds
Started Jul 16 04:57:41 PM PDT 24
Finished Jul 16 04:59:14 PM PDT 24
Peak memory 199824 kb
Host smart-4defe755-2f89-409f-bf4a-4fe688299e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007935844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.4007935844
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2331207349
Short name T601
Test name
Test status
Simulation time 42941405609 ps
CPU time 62.13 seconds
Started Jul 16 04:57:42 PM PDT 24
Finished Jul 16 04:58:45 PM PDT 24
Peak memory 198896 kb
Host smart-cf640f91-8ffc-43a2-aa8d-290bbfd42c8b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331207349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2331207349
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1788520107
Short name T834
Test name
Test status
Simulation time 255067084301 ps
CPU time 242 seconds
Started Jul 16 04:57:42 PM PDT 24
Finished Jul 16 05:01:45 PM PDT 24
Peak memory 199716 kb
Host smart-fa3a5219-72cb-47b5-b3ce-9b72fb4ed255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788520107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1788520107
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1567952099
Short name T393
Test name
Test status
Simulation time 5700833397 ps
CPU time 14.52 seconds
Started Jul 16 04:57:44 PM PDT 24
Finished Jul 16 04:57:59 PM PDT 24
Peak memory 199628 kb
Host smart-26a15ebd-8b2e-4ee4-994b-8629c6fdb6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567952099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1567952099
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2835392260
Short name T41
Test name
Test status
Simulation time 106510377575 ps
CPU time 144.71 seconds
Started Jul 16 04:57:41 PM PDT 24
Finished Jul 16 05:00:06 PM PDT 24
Peak memory 199436 kb
Host smart-4713f8e6-7cf3-4e31-bc0a-0eba16e9b6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835392260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2835392260
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2096980234
Short name T528
Test name
Test status
Simulation time 9949078171 ps
CPU time 423.1 seconds
Started Jul 16 04:57:39 PM PDT 24
Finished Jul 16 05:04:43 PM PDT 24
Peak memory 199672 kb
Host smart-bba0b8ae-4ead-4f7e-b2ed-d0be8865f377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2096980234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2096980234
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3315331647
Short name T749
Test name
Test status
Simulation time 4232113010 ps
CPU time 9.89 seconds
Started Jul 16 04:57:39 PM PDT 24
Finished Jul 16 04:57:50 PM PDT 24
Peak memory 197956 kb
Host smart-3f416dd6-b3ee-4336-8122-9b9de98359cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3315331647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3315331647
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.566657854
Short name T945
Test name
Test status
Simulation time 24137974718 ps
CPU time 10.66 seconds
Started Jul 16 04:57:39 PM PDT 24
Finished Jul 16 04:57:50 PM PDT 24
Peak memory 198660 kb
Host smart-f81ff7be-a36b-4e6d-bc61-a222a1ef9a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566657854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.566657854
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1292662741
Short name T327
Test name
Test status
Simulation time 3185313935 ps
CPU time 5.66 seconds
Started Jul 16 04:57:41 PM PDT 24
Finished Jul 16 04:57:47 PM PDT 24
Peak memory 196240 kb
Host smart-8c787ac9-5152-4c0a-8d71-8a3c18bffa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292662741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1292662741
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.228660046
Short name T280
Test name
Test status
Simulation time 647177241 ps
CPU time 1.83 seconds
Started Jul 16 04:57:36 PM PDT 24
Finished Jul 16 04:57:38 PM PDT 24
Peak memory 198688 kb
Host smart-85c93605-2dc1-4625-ae02-aff135eb8c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228660046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.228660046
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1002328657
Short name T880
Test name
Test status
Simulation time 123881586445 ps
CPU time 59.98 seconds
Started Jul 16 04:57:41 PM PDT 24
Finished Jul 16 04:58:42 PM PDT 24
Peak memory 209568 kb
Host smart-310dadd3-3391-4fe4-89ff-8db45d682590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002328657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1002328657
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1021402974
Short name T989
Test name
Test status
Simulation time 108432276376 ps
CPU time 411.1 seconds
Started Jul 16 04:57:43 PM PDT 24
Finished Jul 16 05:04:35 PM PDT 24
Peak memory 216312 kb
Host smart-c8598a92-a776-4548-99a8-09f7a49a976c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021402974 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1021402974
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1615967923
Short name T388
Test name
Test status
Simulation time 1459276808 ps
CPU time 1.92 seconds
Started Jul 16 04:57:40 PM PDT 24
Finished Jul 16 04:57:42 PM PDT 24
Peak memory 198488 kb
Host smart-94260a50-78a7-4a32-bba8-568a5fd1d5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615967923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1615967923
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3906552081
Short name T914
Test name
Test status
Simulation time 3602277569 ps
CPU time 5.65 seconds
Started Jul 16 04:57:33 PM PDT 24
Finished Jul 16 04:57:39 PM PDT 24
Peak memory 198240 kb
Host smart-1b59b5c3-9de6-48e8-9ee1-474f2dce19ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906552081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3906552081
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1354685471
Short name T185
Test name
Test status
Simulation time 45229494146 ps
CPU time 36 seconds
Started Jul 16 05:00:19 PM PDT 24
Finished Jul 16 05:00:56 PM PDT 24
Peak memory 199852 kb
Host smart-5f8c5369-eaa5-4d07-9b7f-955cff79884b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354685471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1354685471
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3993905751
Short name T273
Test name
Test status
Simulation time 28214912331 ps
CPU time 62.03 seconds
Started Jul 16 05:00:31 PM PDT 24
Finished Jul 16 05:01:33 PM PDT 24
Peak memory 199648 kb
Host smart-e9decd65-925c-449d-8438-6a574e3b2046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993905751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3993905751
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2426232538
Short name T163
Test name
Test status
Simulation time 253166590932 ps
CPU time 41.75 seconds
Started Jul 16 05:00:31 PM PDT 24
Finished Jul 16 05:01:13 PM PDT 24
Peak memory 199728 kb
Host smart-edbe33d3-0f9f-4fd3-afcd-247a90db7b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426232538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2426232538
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.468548666
Short name T850
Test name
Test status
Simulation time 143104601710 ps
CPU time 166.42 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:03:19 PM PDT 24
Peak memory 199912 kb
Host smart-141bff57-22b1-48ce-94fc-3a92bb2b91ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468548666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.468548666
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1960088454
Short name T1055
Test name
Test status
Simulation time 86575978607 ps
CPU time 195.64 seconds
Started Jul 16 05:00:31 PM PDT 24
Finished Jul 16 05:03:48 PM PDT 24
Peak memory 199680 kb
Host smart-a3ff1b37-03ba-42df-85ae-ab837c276a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960088454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1960088454
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.256497210
Short name T958
Test name
Test status
Simulation time 34497391340 ps
CPU time 15.82 seconds
Started Jul 16 05:00:33 PM PDT 24
Finished Jul 16 05:00:49 PM PDT 24
Peak memory 199780 kb
Host smart-f18f38ec-dcd0-47f1-82e3-9225a80ac02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256497210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.256497210
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1955611757
Short name T246
Test name
Test status
Simulation time 29306699266 ps
CPU time 24.51 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:00:58 PM PDT 24
Peak memory 199696 kb
Host smart-747728c8-fe1a-4f2f-94f0-1ecd5ce24b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955611757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1955611757
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3278441601
Short name T861
Test name
Test status
Simulation time 43322133163 ps
CPU time 69.97 seconds
Started Jul 16 05:00:31 PM PDT 24
Finished Jul 16 05:01:42 PM PDT 24
Peak memory 199820 kb
Host smart-27eb4a6d-8622-42be-8fbd-b2d05c240f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278441601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3278441601
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3487598046
Short name T798
Test name
Test status
Simulation time 96470740504 ps
CPU time 39.71 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:01:12 PM PDT 24
Peak memory 199804 kb
Host smart-9ac379c6-1bf6-47d0-a156-09c94d19d167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487598046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3487598046
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.682858913
Short name T228
Test name
Test status
Simulation time 157359016070 ps
CPU time 67.6 seconds
Started Jul 16 05:00:31 PM PDT 24
Finished Jul 16 05:01:40 PM PDT 24
Peak memory 199680 kb
Host smart-85c29d55-6c8f-47fe-a715-0a1ea2ca532c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682858913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.682858913
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1501104986
Short name T737
Test name
Test status
Simulation time 38191235 ps
CPU time 0.53 seconds
Started Jul 16 04:57:42 PM PDT 24
Finished Jul 16 04:57:44 PM PDT 24
Peak memory 195400 kb
Host smart-140ae663-7edc-4301-85d2-82fa4d5f690c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501104986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1501104986
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3103027406
Short name T481
Test name
Test status
Simulation time 28036334474 ps
CPU time 61.67 seconds
Started Jul 16 04:57:50 PM PDT 24
Finished Jul 16 04:58:53 PM PDT 24
Peak memory 199772 kb
Host smart-5d72306e-7570-4152-8e70-689fe6446b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103027406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3103027406
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.707652486
Short name T934
Test name
Test status
Simulation time 184038519372 ps
CPU time 154.44 seconds
Started Jul 16 04:57:42 PM PDT 24
Finished Jul 16 05:00:17 PM PDT 24
Peak memory 199772 kb
Host smart-aaa7620d-bff3-4692-8dca-9d364e7b429d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707652486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.707652486
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3481610635
Short name T448
Test name
Test status
Simulation time 7174566309 ps
CPU time 14.12 seconds
Started Jul 16 04:57:43 PM PDT 24
Finished Jul 16 04:57:58 PM PDT 24
Peak memory 199628 kb
Host smart-ebe2008d-dada-4c84-b844-e330bebe0a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481610635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3481610635
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3576548485
Short name T1057
Test name
Test status
Simulation time 118044504823 ps
CPU time 88.64 seconds
Started Jul 16 04:57:45 PM PDT 24
Finished Jul 16 04:59:14 PM PDT 24
Peak memory 196628 kb
Host smart-5076c0be-eda0-4946-b7f1-7983d233fbe3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576548485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3576548485
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3831740864
Short name T532
Test name
Test status
Simulation time 64483689146 ps
CPU time 331.64 seconds
Started Jul 16 04:57:39 PM PDT 24
Finished Jul 16 05:03:12 PM PDT 24
Peak memory 199836 kb
Host smart-e7483167-99b2-47be-a201-cca7c5c07cd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831740864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3831740864
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.752503648
Short name T469
Test name
Test status
Simulation time 4754544314 ps
CPU time 1.36 seconds
Started Jul 16 04:57:37 PM PDT 24
Finished Jul 16 04:57:39 PM PDT 24
Peak memory 197688 kb
Host smart-21690a24-98e3-42d6-b5fc-8d8579cf714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752503648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.752503648
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3802235601
Short name T272
Test name
Test status
Simulation time 36893947349 ps
CPU time 19.24 seconds
Started Jul 16 04:57:42 PM PDT 24
Finished Jul 16 04:58:02 PM PDT 24
Peak memory 198516 kb
Host smart-d998a1e8-bbe0-4fa6-b608-fb8e01d132f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802235601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3802235601
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.328902107
Short name T906
Test name
Test status
Simulation time 14370105584 ps
CPU time 353.28 seconds
Started Jul 16 04:57:40 PM PDT 24
Finished Jul 16 05:03:35 PM PDT 24
Peak memory 199712 kb
Host smart-707d3516-71ad-416a-beac-94068b978e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328902107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.328902107
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2948516282
Short name T340
Test name
Test status
Simulation time 3401014879 ps
CPU time 3.96 seconds
Started Jul 16 04:57:43 PM PDT 24
Finished Jul 16 04:57:47 PM PDT 24
Peak memory 197760 kb
Host smart-1aeaa0d9-4731-42c1-a59d-7d1b5e5d0dd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948516282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2948516282
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.4235266838
Short name T693
Test name
Test status
Simulation time 129897697906 ps
CPU time 183.5 seconds
Started Jul 16 04:57:39 PM PDT 24
Finished Jul 16 05:00:44 PM PDT 24
Peak memory 199840 kb
Host smart-9d310f34-6a0f-4b0f-9f0b-64c08c2aef5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235266838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.4235266838
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3010004181
Short name T1036
Test name
Test status
Simulation time 4209278589 ps
CPU time 2.05 seconds
Started Jul 16 04:57:39 PM PDT 24
Finished Jul 16 04:57:42 PM PDT 24
Peak memory 196192 kb
Host smart-e6733d2f-d1c9-49ed-8beb-2619234e9287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010004181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3010004181
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3395019680
Short name T1154
Test name
Test status
Simulation time 670578807 ps
CPU time 1.94 seconds
Started Jul 16 04:57:42 PM PDT 24
Finished Jul 16 04:57:45 PM PDT 24
Peak memory 199328 kb
Host smart-ffa96ee0-e743-451f-b9f9-4f81f1743021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395019680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3395019680
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2880262747
Short name T909
Test name
Test status
Simulation time 231301210695 ps
CPU time 95.95 seconds
Started Jul 16 04:57:40 PM PDT 24
Finished Jul 16 04:59:17 PM PDT 24
Peak memory 199700 kb
Host smart-01788265-95f5-4433-922d-000774cdc6e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880262747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2880262747
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3447154775
Short name T483
Test name
Test status
Simulation time 73959629408 ps
CPU time 497 seconds
Started Jul 16 04:57:43 PM PDT 24
Finished Jul 16 05:06:01 PM PDT 24
Peak memory 216292 kb
Host smart-d20211dc-e7c8-4db3-a112-5797de759dc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447154775 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3447154775
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3370527023
Short name T534
Test name
Test status
Simulation time 6769404601 ps
CPU time 29.22 seconds
Started Jul 16 04:57:41 PM PDT 24
Finished Jul 16 04:58:11 PM PDT 24
Peak memory 199752 kb
Host smart-00ef1584-f1dd-462f-874d-d3438e48842b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370527023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3370527023
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.98871950
Short name T432
Test name
Test status
Simulation time 17961004649 ps
CPU time 12.79 seconds
Started Jul 16 04:57:41 PM PDT 24
Finished Jul 16 04:57:55 PM PDT 24
Peak memory 198408 kb
Host smart-10770c83-b37d-425d-9f09-68b43c66207f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98871950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.98871950
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2299152252
Short name T538
Test name
Test status
Simulation time 73057437235 ps
CPU time 25.59 seconds
Started Jul 16 05:00:34 PM PDT 24
Finished Jul 16 05:01:00 PM PDT 24
Peak memory 199728 kb
Host smart-401ae9c6-3727-4def-9545-40cb9ede0f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299152252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2299152252
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2485456862
Short name T301
Test name
Test status
Simulation time 46570136607 ps
CPU time 12.94 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:00:46 PM PDT 24
Peak memory 199848 kb
Host smart-d204de73-a7bc-45d8-9d9e-6d769a3d2a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485456862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2485456862
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1517817103
Short name T1021
Test name
Test status
Simulation time 89849955529 ps
CPU time 125.12 seconds
Started Jul 16 05:00:33 PM PDT 24
Finished Jul 16 05:02:39 PM PDT 24
Peak memory 199864 kb
Host smart-59851564-4447-4bbb-81ee-108c5f1e6611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517817103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1517817103
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2264773233
Short name T849
Test name
Test status
Simulation time 51247266285 ps
CPU time 37.45 seconds
Started Jul 16 05:00:31 PM PDT 24
Finished Jul 16 05:01:09 PM PDT 24
Peak memory 199840 kb
Host smart-01b7e9b5-588f-436b-98fb-3472d3200a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264773233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2264773233
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.4161229137
Short name T264
Test name
Test status
Simulation time 213339747690 ps
CPU time 264.49 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:04:58 PM PDT 24
Peak memory 199836 kb
Host smart-dda68b5f-16e2-4e8d-9235-0408b03e5dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161229137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.4161229137
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2188670909
Short name T218
Test name
Test status
Simulation time 90632438359 ps
CPU time 29.05 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:01:02 PM PDT 24
Peak memory 199592 kb
Host smart-bbc30dd8-b707-4d92-b041-e1d2b2ce68a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188670909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2188670909
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3483080009
Short name T1157
Test name
Test status
Simulation time 60122434168 ps
CPU time 52.45 seconds
Started Jul 16 05:00:30 PM PDT 24
Finished Jul 16 05:01:23 PM PDT 24
Peak memory 199736 kb
Host smart-1d63d7c6-fd1b-49f0-ba8f-64b3159fa5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483080009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3483080009
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.59731414
Short name T1126
Test name
Test status
Simulation time 50488412413 ps
CPU time 20.67 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:00:54 PM PDT 24
Peak memory 199872 kb
Host smart-fd2f8fef-3ac8-40d6-b1ed-aaee68450b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59731414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.59731414
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1740924341
Short name T625
Test name
Test status
Simulation time 5881165343 ps
CPU time 11.6 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:00:45 PM PDT 24
Peak memory 199816 kb
Host smart-e97e3502-bbbb-4444-9319-cfcf2d39e14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740924341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1740924341
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.710804940
Short name T627
Test name
Test status
Simulation time 14176604 ps
CPU time 0.57 seconds
Started Jul 16 04:57:52 PM PDT 24
Finished Jul 16 04:57:54 PM PDT 24
Peak memory 195132 kb
Host smart-ed2c0e8c-ca94-46cc-a056-0d726417a39b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710804940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.710804940
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1870373066
Short name T179
Test name
Test status
Simulation time 42880441826 ps
CPU time 17.97 seconds
Started Jul 16 04:57:38 PM PDT 24
Finished Jul 16 04:57:56 PM PDT 24
Peak memory 199552 kb
Host smart-a82aff30-f353-42fe-9f87-3cbcb5037ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870373066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1870373066
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1873149613
Short name T1031
Test name
Test status
Simulation time 79412288498 ps
CPU time 136.44 seconds
Started Jul 16 04:57:39 PM PDT 24
Finished Jul 16 04:59:56 PM PDT 24
Peak memory 199800 kb
Host smart-f791e24d-7e87-4f2f-9625-2cd5f0690e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873149613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1873149613
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.131661214
Short name T322
Test name
Test status
Simulation time 106056595663 ps
CPU time 18.02 seconds
Started Jul 16 04:57:39 PM PDT 24
Finished Jul 16 04:57:58 PM PDT 24
Peak memory 199792 kb
Host smart-f2f0f139-c82b-4352-808e-cfbee106894c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131661214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.131661214
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3395107098
Short name T1010
Test name
Test status
Simulation time 232104934736 ps
CPU time 158.63 seconds
Started Jul 16 04:57:42 PM PDT 24
Finished Jul 16 05:00:21 PM PDT 24
Peak memory 196652 kb
Host smart-1486026e-d7d1-4b30-bd66-9f9faea49242
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395107098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3395107098
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3194101044
Short name T944
Test name
Test status
Simulation time 96738303061 ps
CPU time 235.8 seconds
Started Jul 16 04:57:44 PM PDT 24
Finished Jul 16 05:01:40 PM PDT 24
Peak memory 200144 kb
Host smart-17b46214-2c96-4d32-af3c-71a01555879d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194101044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3194101044
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2022423428
Short name T1096
Test name
Test status
Simulation time 1143595082 ps
CPU time 1.12 seconds
Started Jul 16 04:57:40 PM PDT 24
Finished Jul 16 04:57:42 PM PDT 24
Peak memory 196024 kb
Host smart-43ded2ca-9153-4991-851d-f30f390c80a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022423428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2022423428
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3875374071
Short name T984
Test name
Test status
Simulation time 38842919814 ps
CPU time 30.8 seconds
Started Jul 16 04:57:40 PM PDT 24
Finished Jul 16 04:58:11 PM PDT 24
Peak memory 198552 kb
Host smart-ffa5176c-2081-42f6-a939-98c2efd39bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875374071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3875374071
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2546234243
Short name T868
Test name
Test status
Simulation time 6299144719 ps
CPU time 53.35 seconds
Started Jul 16 04:57:42 PM PDT 24
Finished Jul 16 04:58:36 PM PDT 24
Peak memory 199676 kb
Host smart-26634f92-28a0-44ab-a2bb-8154818606e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546234243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2546234243
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2453776397
Short name T930
Test name
Test status
Simulation time 2724577990 ps
CPU time 14.38 seconds
Started Jul 16 04:57:39 PM PDT 24
Finished Jul 16 04:57:54 PM PDT 24
Peak memory 198976 kb
Host smart-c5e2c65e-3bd8-40d8-8be1-de4e780fcf08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453776397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2453776397
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1644423674
Short name T1142
Test name
Test status
Simulation time 78952326893 ps
CPU time 67.98 seconds
Started Jul 16 04:57:45 PM PDT 24
Finished Jul 16 04:58:53 PM PDT 24
Peak memory 199612 kb
Host smart-120db97e-027d-4067-a958-19f76c29fa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644423674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1644423674
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1536113153
Short name T303
Test name
Test status
Simulation time 4305645648 ps
CPU time 3.92 seconds
Started Jul 16 04:57:42 PM PDT 24
Finished Jul 16 04:57:46 PM PDT 24
Peak memory 196008 kb
Host smart-473c8a46-3ab8-442e-84dd-34975a2a58e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536113153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1536113153
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2058247054
Short name T708
Test name
Test status
Simulation time 498943457 ps
CPU time 1.33 seconds
Started Jul 16 04:57:41 PM PDT 24
Finished Jul 16 04:57:43 PM PDT 24
Peak memory 198316 kb
Host smart-1e0eeeff-1fd9-4bfb-97ea-adc9b7129f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058247054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2058247054
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.493146365
Short name T150
Test name
Test status
Simulation time 208090219538 ps
CPU time 1043.58 seconds
Started Jul 16 04:57:53 PM PDT 24
Finished Jul 16 05:15:18 PM PDT 24
Peak memory 199708 kb
Host smart-7da2d154-2968-4788-9b50-4e37362e5b3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493146365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.493146365
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2052322743
Short name T866
Test name
Test status
Simulation time 45752406681 ps
CPU time 467.56 seconds
Started Jul 16 04:57:41 PM PDT 24
Finished Jul 16 05:05:29 PM PDT 24
Peak memory 215352 kb
Host smart-a6f57498-3a46-4f9b-b114-257eafdb34dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052322743 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2052322743
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1317935124
Short name T325
Test name
Test status
Simulation time 507370337 ps
CPU time 1.14 seconds
Started Jul 16 04:57:38 PM PDT 24
Finished Jul 16 04:57:40 PM PDT 24
Peak memory 197880 kb
Host smart-92fbbf8c-1b69-4014-bf0b-0f3eb37572e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317935124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1317935124
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.4154454917
Short name T395
Test name
Test status
Simulation time 7367286578 ps
CPU time 11.56 seconds
Started Jul 16 04:57:41 PM PDT 24
Finished Jul 16 04:57:53 PM PDT 24
Peak memory 199724 kb
Host smart-992a46bf-b907-44d9-a40c-e39b04714dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154454917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.4154454917
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2938432642
Short name T216
Test name
Test status
Simulation time 12244372430 ps
CPU time 9.09 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:00:42 PM PDT 24
Peak memory 199776 kb
Host smart-6402cbba-6164-4ae4-9164-9bf1457f016a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938432642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2938432642
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3193740806
Short name T751
Test name
Test status
Simulation time 31364600474 ps
CPU time 52.02 seconds
Started Jul 16 05:00:34 PM PDT 24
Finished Jul 16 05:01:27 PM PDT 24
Peak memory 199712 kb
Host smart-389f2e62-837f-4461-b56c-31a4ad4d4e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193740806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3193740806
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.610716606
Short name T1044
Test name
Test status
Simulation time 21012661038 ps
CPU time 35.61 seconds
Started Jul 16 05:00:33 PM PDT 24
Finished Jul 16 05:01:09 PM PDT 24
Peak memory 199780 kb
Host smart-fc8cf0a9-8956-4a4e-8b0b-a2ff3d9f809e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610716606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.610716606
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3762890945
Short name T251
Test name
Test status
Simulation time 18263295614 ps
CPU time 43.17 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:01:16 PM PDT 24
Peak memory 199836 kb
Host smart-8ca786b4-41c1-435c-8419-f736722bc09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762890945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3762890945
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1954817683
Short name T490
Test name
Test status
Simulation time 104189086357 ps
CPU time 22.41 seconds
Started Jul 16 05:00:33 PM PDT 24
Finished Jul 16 05:00:56 PM PDT 24
Peak memory 199864 kb
Host smart-2cf8a061-3cc3-42e7-a3f2-75d8e169c699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954817683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1954817683
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2925619272
Short name T559
Test name
Test status
Simulation time 53585669148 ps
CPU time 46.36 seconds
Started Jul 16 05:00:32 PM PDT 24
Finished Jul 16 05:01:19 PM PDT 24
Peak memory 199664 kb
Host smart-bd307b6e-60ea-4684-bc2b-6648d853b07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925619272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2925619272
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2637000320
Short name T324
Test name
Test status
Simulation time 56840997368 ps
CPU time 24.05 seconds
Started Jul 16 05:00:43 PM PDT 24
Finished Jul 16 05:01:08 PM PDT 24
Peak memory 199756 kb
Host smart-b97b92ff-8994-4878-9299-c41694bcf0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637000320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2637000320
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2021482049
Short name T636
Test name
Test status
Simulation time 39884381352 ps
CPU time 16.63 seconds
Started Jul 16 05:00:47 PM PDT 24
Finished Jul 16 05:01:05 PM PDT 24
Peak memory 199772 kb
Host smart-a2b1a8df-5133-4291-8fdd-1d52b5c67347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021482049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2021482049
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2674121710
Short name T119
Test name
Test status
Simulation time 32004975 ps
CPU time 0.58 seconds
Started Jul 16 04:56:14 PM PDT 24
Finished Jul 16 04:56:15 PM PDT 24
Peak memory 195768 kb
Host smart-b7e2a65d-37f2-4228-a1d8-01da0c5e946b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674121710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2674121710
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3795017057
Short name T669
Test name
Test status
Simulation time 35649635438 ps
CPU time 57.68 seconds
Started Jul 16 04:56:27 PM PDT 24
Finished Jul 16 04:57:25 PM PDT 24
Peak memory 199772 kb
Host smart-8367d90f-28b8-4381-b906-a642da6354de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795017057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3795017057
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2304462605
Short name T808
Test name
Test status
Simulation time 149040634943 ps
CPU time 216.15 seconds
Started Jul 16 04:56:30 PM PDT 24
Finished Jul 16 05:00:07 PM PDT 24
Peak memory 199812 kb
Host smart-56bb082a-ae5c-4d34-80c2-2f36ff64e6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304462605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2304462605
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.588785871
Short name T187
Test name
Test status
Simulation time 4192008035 ps
CPU time 7.6 seconds
Started Jul 16 04:56:29 PM PDT 24
Finished Jul 16 04:56:37 PM PDT 24
Peak memory 199536 kb
Host smart-2b2936ee-5564-4a27-a897-0fa27d6ea3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588785871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.588785871
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.4159292734
Short name T677
Test name
Test status
Simulation time 430140165063 ps
CPU time 650.92 seconds
Started Jul 16 04:56:32 PM PDT 24
Finished Jul 16 05:07:25 PM PDT 24
Peak memory 199816 kb
Host smart-d9033ca0-a864-49a1-96ae-7bd8146a61c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159292734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4159292734
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.649698928
Short name T379
Test name
Test status
Simulation time 84470362593 ps
CPU time 341.31 seconds
Started Jul 16 04:56:28 PM PDT 24
Finished Jul 16 05:02:10 PM PDT 24
Peak memory 199680 kb
Host smart-93c424b6-6fd6-408a-9196-1321854dc7ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649698928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.649698928
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.665293401
Short name T598
Test name
Test status
Simulation time 333408630 ps
CPU time 0.77 seconds
Started Jul 16 04:56:26 PM PDT 24
Finished Jul 16 04:56:27 PM PDT 24
Peak memory 195924 kb
Host smart-f9e662dc-9cdb-4617-8b2a-756334bcef0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665293401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.665293401
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.578531526
Short name T950
Test name
Test status
Simulation time 81510068556 ps
CPU time 155.89 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 04:59:21 PM PDT 24
Peak memory 199556 kb
Host smart-ef014dea-0161-4d91-ae45-c81a2a1d2c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578531526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.578531526
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.341990499
Short name T1064
Test name
Test status
Simulation time 15472018830 ps
CPU time 883.9 seconds
Started Jul 16 04:56:14 PM PDT 24
Finished Jul 16 05:10:59 PM PDT 24
Peak memory 200160 kb
Host smart-e60109d9-e2c8-4b44-9ff7-fcdfb3d5f9f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=341990499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.341990499
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2893703192
Short name T425
Test name
Test status
Simulation time 5554298000 ps
CPU time 47.1 seconds
Started Jul 16 04:56:29 PM PDT 24
Finished Jul 16 04:57:17 PM PDT 24
Peak memory 198204 kb
Host smart-7c69ce7f-ca74-4bd0-a95b-9a69f0699bba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893703192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2893703192
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2291206705
Short name T308
Test name
Test status
Simulation time 164975055424 ps
CPU time 53.43 seconds
Started Jul 16 04:56:24 PM PDT 24
Finished Jul 16 04:57:18 PM PDT 24
Peak memory 199672 kb
Host smart-6dd41104-2a84-414f-afd4-f988d648d7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291206705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2291206705
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.571841111
Short name T348
Test name
Test status
Simulation time 1922559908 ps
CPU time 1.97 seconds
Started Jul 16 04:56:28 PM PDT 24
Finished Jul 16 04:56:31 PM PDT 24
Peak memory 195408 kb
Host smart-54c4a5db-4032-466c-9e54-4a8b3ba5c911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571841111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.571841111
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.835114221
Short name T105
Test name
Test status
Simulation time 171478286 ps
CPU time 0.88 seconds
Started Jul 16 04:56:30 PM PDT 24
Finished Jul 16 04:56:32 PM PDT 24
Peak memory 218180 kb
Host smart-f62ebf10-2d04-4f0c-b137-288dca6eaffd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835114221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.835114221
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1173264408
Short name T925
Test name
Test status
Simulation time 927947400 ps
CPU time 1.78 seconds
Started Jul 16 04:56:25 PM PDT 24
Finished Jul 16 04:56:27 PM PDT 24
Peak memory 198648 kb
Host smart-10204192-5bf7-4060-b5cc-272443cc80b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173264408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1173264408
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.160624240
Short name T690
Test name
Test status
Simulation time 7205050285 ps
CPU time 10.21 seconds
Started Jul 16 04:56:27 PM PDT 24
Finished Jul 16 04:56:38 PM PDT 24
Peak memory 199500 kb
Host smart-3d266fb9-b0fc-4c6c-b9dc-509743ecdf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160624240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.160624240
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3377277437
Short name T781
Test name
Test status
Simulation time 187571010997 ps
CPU time 30.12 seconds
Started Jul 16 04:56:19 PM PDT 24
Finished Jul 16 04:56:50 PM PDT 24
Peak memory 199808 kb
Host smart-e72bd008-cfcc-4aa0-ac7d-9873e316bf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377277437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3377277437
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1762043616
Short name T641
Test name
Test status
Simulation time 13180413 ps
CPU time 0.56 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 04:57:51 PM PDT 24
Peak memory 195176 kb
Host smart-46b13b48-7175-4820-aea9-834f45cc3560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762043616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1762043616
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2200070825
Short name T1076
Test name
Test status
Simulation time 129922798029 ps
CPU time 89.77 seconds
Started Jul 16 04:57:47 PM PDT 24
Finished Jul 16 04:59:18 PM PDT 24
Peak memory 199768 kb
Host smart-0731e836-9895-4854-a967-9646f0bb06b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200070825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2200070825
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2842806603
Short name T593
Test name
Test status
Simulation time 35325357438 ps
CPU time 26.11 seconds
Started Jul 16 04:57:50 PM PDT 24
Finished Jul 16 04:58:17 PM PDT 24
Peak memory 199152 kb
Host smart-3b725ac3-52c6-4c1e-af66-380bdd5c4023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842806603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2842806603
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3617896198
Short name T531
Test name
Test status
Simulation time 153001448599 ps
CPU time 40.52 seconds
Started Jul 16 04:57:50 PM PDT 24
Finished Jul 16 04:58:32 PM PDT 24
Peak memory 199808 kb
Host smart-e1b723e5-ae73-40b7-bf7d-396ffce799fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617896198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3617896198
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1823051187
Short name T285
Test name
Test status
Simulation time 21456047774 ps
CPU time 13.43 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 04:58:04 PM PDT 24
Peak memory 199664 kb
Host smart-e98c68d1-b89b-46bc-9268-7ccbdf39bb2c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823051187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1823051187
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.4289875987
Short name T1086
Test name
Test status
Simulation time 123841760862 ps
CPU time 318.5 seconds
Started Jul 16 04:57:47 PM PDT 24
Finished Jul 16 05:03:06 PM PDT 24
Peak memory 199712 kb
Host smart-b6df0c50-82d3-49b4-adc0-a2c2d11dc4f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4289875987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.4289875987
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2066344689
Short name T734
Test name
Test status
Simulation time 8701806877 ps
CPU time 9.11 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 04:57:59 PM PDT 24
Peak memory 199432 kb
Host smart-f34f45ff-e53e-4820-83af-1ab46fa138b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066344689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2066344689
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3727026829
Short name T978
Test name
Test status
Simulation time 50231108968 ps
CPU time 21.06 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 04:58:12 PM PDT 24
Peak memory 199256 kb
Host smart-7d4cd959-3143-4741-95c0-96c934b24c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727026829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3727026829
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2355347752
Short name T1147
Test name
Test status
Simulation time 12635185323 ps
CPU time 295.02 seconds
Started Jul 16 04:57:48 PM PDT 24
Finished Jul 16 05:02:44 PM PDT 24
Peak memory 199756 kb
Host smart-2b36b479-97ff-425a-9f89-dbc3b76b36a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355347752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2355347752
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1391706769
Short name T45
Test name
Test status
Simulation time 6410465981 ps
CPU time 56.89 seconds
Started Jul 16 04:57:51 PM PDT 24
Finished Jul 16 04:58:49 PM PDT 24
Peak memory 199824 kb
Host smart-887ad862-9660-4635-a3d7-b4d151debd16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1391706769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1391706769
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1386096016
Short name T812
Test name
Test status
Simulation time 39624976120 ps
CPU time 16.12 seconds
Started Jul 16 04:57:53 PM PDT 24
Finished Jul 16 04:58:10 PM PDT 24
Peak memory 196908 kb
Host smart-c24f6586-117c-4d4b-a7bc-6e9558a2057e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386096016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1386096016
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3645181231
Short name T400
Test name
Test status
Simulation time 40974697404 ps
CPU time 10.61 seconds
Started Jul 16 04:57:46 PM PDT 24
Finished Jul 16 04:57:57 PM PDT 24
Peak memory 195676 kb
Host smart-f94515c1-e8c8-4f5f-874d-db1291191755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645181231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3645181231
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2753338166
Short name T810
Test name
Test status
Simulation time 5889304076 ps
CPU time 19.34 seconds
Started Jul 16 04:57:46 PM PDT 24
Finished Jul 16 04:58:05 PM PDT 24
Peak memory 199588 kb
Host smart-308e4617-5470-4458-a9db-9521a252e38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753338166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2753338166
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1565493666
Short name T718
Test name
Test status
Simulation time 376086227976 ps
CPU time 560.54 seconds
Started Jul 16 04:57:47 PM PDT 24
Finished Jul 16 05:07:09 PM PDT 24
Peak memory 199708 kb
Host smart-e977fb0c-73f2-4818-b4ed-0e6006231fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565493666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1565493666
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1123459282
Short name T128
Test name
Test status
Simulation time 114522809182 ps
CPU time 346.52 seconds
Started Jul 16 04:57:52 PM PDT 24
Finished Jul 16 05:03:40 PM PDT 24
Peak memory 216328 kb
Host smart-ce165b04-6fac-449c-95e3-5e5335b18154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123459282 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1123459282
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.223987861
Short name T650
Test name
Test status
Simulation time 9445124572 ps
CPU time 5.54 seconds
Started Jul 16 04:57:47 PM PDT 24
Finished Jul 16 04:57:54 PM PDT 24
Peak memory 199172 kb
Host smart-3f794223-04a7-4fe5-bef4-c3d262c662d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223987861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.223987861
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3506241726
Short name T277
Test name
Test status
Simulation time 63403052536 ps
CPU time 120.65 seconds
Started Jul 16 04:57:53 PM PDT 24
Finished Jul 16 04:59:54 PM PDT 24
Peak memory 199808 kb
Host smart-39f486d1-b4e2-46de-8c8e-4e6ed38cdb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506241726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3506241726
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2065438654
Short name T27
Test name
Test status
Simulation time 11842053 ps
CPU time 0.55 seconds
Started Jul 16 04:57:48 PM PDT 24
Finished Jul 16 04:57:49 PM PDT 24
Peak memory 194756 kb
Host smart-0f71a166-3e81-4cc1-ad49-bec92ae1a12c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065438654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2065438654
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1636281166
Short name T557
Test name
Test status
Simulation time 53366404095 ps
CPU time 84.19 seconds
Started Jul 16 04:57:48 PM PDT 24
Finished Jul 16 04:59:14 PM PDT 24
Peak memory 199800 kb
Host smart-25eda8c3-1b17-4028-b63b-409704f256a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636281166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1636281166
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3987850926
Short name T142
Test name
Test status
Simulation time 446987427693 ps
CPU time 74.24 seconds
Started Jul 16 04:57:51 PM PDT 24
Finished Jul 16 04:59:06 PM PDT 24
Peak memory 199752 kb
Host smart-d73de0a8-5ecb-4cdf-8cd5-f5c52c59feaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987850926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3987850926
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2982521125
Short name T267
Test name
Test status
Simulation time 109287715340 ps
CPU time 18.53 seconds
Started Jul 16 04:57:47 PM PDT 24
Finished Jul 16 04:58:07 PM PDT 24
Peak memory 199668 kb
Host smart-f1bda660-0f20-42d1-a079-b44042171dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982521125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2982521125
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3440671629
Short name T763
Test name
Test status
Simulation time 63021478667 ps
CPU time 110.08 seconds
Started Jul 16 04:57:46 PM PDT 24
Finished Jul 16 04:59:36 PM PDT 24
Peak memory 199696 kb
Host smart-1a017781-0053-439d-85f4-150be97f77fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440671629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3440671629
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.663724564
Short name T463
Test name
Test status
Simulation time 77045866593 ps
CPU time 138.11 seconds
Started Jul 16 04:57:47 PM PDT 24
Finished Jul 16 05:00:06 PM PDT 24
Peak memory 199816 kb
Host smart-499ffc7c-1ddc-4b06-9fce-210575a37108
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663724564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.663724564
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1021895338
Short name T695
Test name
Test status
Simulation time 1732652946 ps
CPU time 1.93 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 04:57:53 PM PDT 24
Peak memory 198520 kb
Host smart-1956a835-9062-4ce4-b829-ceae2890cbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021895338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1021895338
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2586597094
Short name T612
Test name
Test status
Simulation time 48070120131 ps
CPU time 80.46 seconds
Started Jul 16 04:57:48 PM PDT 24
Finished Jul 16 04:59:10 PM PDT 24
Peak memory 199924 kb
Host smart-fc649c91-7786-4704-b499-3dc8f84a50f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586597094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2586597094
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1162915443
Short name T547
Test name
Test status
Simulation time 11158241324 ps
CPU time 125.57 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 04:59:56 PM PDT 24
Peak memory 199768 kb
Host smart-7e164347-4858-4179-8662-ed55dc188931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162915443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1162915443
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1412165458
Short name T358
Test name
Test status
Simulation time 7765109985 ps
CPU time 69.68 seconds
Started Jul 16 04:57:47 PM PDT 24
Finished Jul 16 04:58:57 PM PDT 24
Peak memory 198064 kb
Host smart-f443d721-1c91-4871-967e-1ffa860047c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1412165458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1412165458
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3236903939
Short name T143
Test name
Test status
Simulation time 108603532931 ps
CPU time 51.83 seconds
Started Jul 16 04:57:47 PM PDT 24
Finished Jul 16 04:58:40 PM PDT 24
Peak memory 199764 kb
Host smart-ab9a94ea-7b63-4233-85cc-7d3bb3b2aa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236903939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3236903939
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.171322016
Short name T430
Test name
Test status
Simulation time 2926114877 ps
CPU time 4.65 seconds
Started Jul 16 04:57:50 PM PDT 24
Finished Jul 16 04:57:56 PM PDT 24
Peak memory 195708 kb
Host smart-a6b45fa5-3811-4a08-8cda-8049551435bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171322016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.171322016
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2450787106
Short name T520
Test name
Test status
Simulation time 5910156040 ps
CPU time 10.34 seconds
Started Jul 16 04:57:48 PM PDT 24
Finished Jul 16 04:58:00 PM PDT 24
Peak memory 199868 kb
Host smart-211f21f7-9f6f-46b5-bd23-68f59d9eb1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450787106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2450787106
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1931995714
Short name T1074
Test name
Test status
Simulation time 95787287174 ps
CPU time 830.58 seconds
Started Jul 16 04:57:50 PM PDT 24
Finished Jul 16 05:11:42 PM PDT 24
Peak memory 200088 kb
Host smart-e7f2a4bf-6ed6-4cb4-8c2f-e7dc8c883c5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931995714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1931995714
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1728988810
Short name T684
Test name
Test status
Simulation time 27821534885 ps
CPU time 423.91 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 05:04:54 PM PDT 24
Peak memory 213660 kb
Host smart-fe9029c1-c871-407c-b4f0-9bfccc7b6f03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728988810 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1728988810
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1893637364
Short name T954
Test name
Test status
Simulation time 1805927053 ps
CPU time 1.63 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 04:57:51 PM PDT 24
Peak memory 199416 kb
Host smart-2c60f133-237e-48b8-ad35-e323138355f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893637364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1893637364
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2492197408
Short name T814
Test name
Test status
Simulation time 15718119397 ps
CPU time 25.71 seconds
Started Jul 16 04:57:54 PM PDT 24
Finished Jul 16 04:58:20 PM PDT 24
Peak memory 199824 kb
Host smart-ee6dfe97-f158-4535-833d-2b2989b9718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492197408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2492197408
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1968588031
Short name T819
Test name
Test status
Simulation time 12582409 ps
CPU time 0.55 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 04:57:51 PM PDT 24
Peak memory 195068 kb
Host smart-2bcd4fb8-d6ad-4df7-aedc-211ea5c6cf82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968588031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1968588031
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1214440254
Short name T599
Test name
Test status
Simulation time 213054776383 ps
CPU time 96.15 seconds
Started Jul 16 04:57:52 PM PDT 24
Finished Jul 16 04:59:29 PM PDT 24
Peak memory 199856 kb
Host smart-54c0f111-4b38-4feb-a6d8-383a5197f502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214440254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1214440254
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.7361102
Short name T509
Test name
Test status
Simulation time 136465337593 ps
CPU time 221.6 seconds
Started Jul 16 04:57:52 PM PDT 24
Finished Jul 16 05:01:34 PM PDT 24
Peak memory 199780 kb
Host smart-1cd1bb96-3fee-4db9-bf77-05bb5b07656c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7361102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.7361102
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3097793489
Short name T362
Test name
Test status
Simulation time 38281797580 ps
CPU time 91.04 seconds
Started Jul 16 04:57:47 PM PDT 24
Finished Jul 16 04:59:19 PM PDT 24
Peak memory 199912 kb
Host smart-2be16574-f595-4341-908e-5a3911cb72d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097793489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3097793489
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.4017275451
Short name T800
Test name
Test status
Simulation time 27606198456 ps
CPU time 8.84 seconds
Started Jul 16 04:57:53 PM PDT 24
Finished Jul 16 04:58:03 PM PDT 24
Peak memory 199468 kb
Host smart-b1f2e508-8709-47c2-9725-a94bbbc29882
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017275451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4017275451
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3898862502
Short name T782
Test name
Test status
Simulation time 173028909619 ps
CPU time 1461.09 seconds
Started Jul 16 04:57:54 PM PDT 24
Finished Jul 16 05:22:16 PM PDT 24
Peak memory 199800 kb
Host smart-2bb16bfd-f56a-497a-b1f8-31ffd7f220ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3898862502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3898862502
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1432202579
Short name T369
Test name
Test status
Simulation time 3783558882 ps
CPU time 5.64 seconds
Started Jul 16 04:57:51 PM PDT 24
Finished Jul 16 04:57:57 PM PDT 24
Peak memory 199676 kb
Host smart-acfb0331-5aff-440f-aa3a-adf83f5776f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432202579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1432202579
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1229422171
Short name T794
Test name
Test status
Simulation time 97645051518 ps
CPU time 72.8 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 04:59:04 PM PDT 24
Peak memory 200280 kb
Host smart-390b976a-204b-420a-bde8-501eada9f291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229422171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1229422171
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1590520848
Short name T1006
Test name
Test status
Simulation time 8779453173 ps
CPU time 403.68 seconds
Started Jul 16 04:57:51 PM PDT 24
Finished Jul 16 05:04:36 PM PDT 24
Peak memory 199780 kb
Host smart-94c0e147-56b6-44ef-a2ff-00091aad4693
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1590520848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1590520848
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1618274995
Short name T376
Test name
Test status
Simulation time 1902868591 ps
CPU time 8.74 seconds
Started Jul 16 04:57:50 PM PDT 24
Finished Jul 16 04:58:00 PM PDT 24
Peak memory 197612 kb
Host smart-32e00970-6f08-4693-83b5-de27da5f51e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1618274995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1618274995
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2483723858
Short name T317
Test name
Test status
Simulation time 23332150822 ps
CPU time 18.05 seconds
Started Jul 16 04:57:51 PM PDT 24
Finished Jul 16 04:58:10 PM PDT 24
Peak memory 199784 kb
Host smart-d79eaccc-7153-454c-8212-a679dc83e1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483723858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2483723858
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.260130904
Short name T578
Test name
Test status
Simulation time 42128411553 ps
CPU time 44.77 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 04:58:35 PM PDT 24
Peak memory 196528 kb
Host smart-884c6c40-f7f3-4b61-a059-8280084bd213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260130904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.260130904
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.602434513
Short name T314
Test name
Test status
Simulation time 5372076039 ps
CPU time 18.43 seconds
Started Jul 16 04:57:48 PM PDT 24
Finished Jul 16 04:58:07 PM PDT 24
Peak memory 199708 kb
Host smart-00e09e4f-eee1-4d34-85f4-84bd8dd343c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602434513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.602434513
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1321983158
Short name T918
Test name
Test status
Simulation time 137663169225 ps
CPU time 112.15 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 04:59:42 PM PDT 24
Peak memory 199748 kb
Host smart-44f2d1dd-119f-4b18-8cde-af8f55a364a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321983158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1321983158
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3719651630
Short name T1118
Test name
Test status
Simulation time 41284845380 ps
CPU time 195.1 seconds
Started Jul 16 04:57:53 PM PDT 24
Finished Jul 16 05:01:09 PM PDT 24
Peak memory 216244 kb
Host smart-f72bddc9-93a4-4640-8349-65c062f35a57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719651630 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3719651630
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2206772791
Short name T1162
Test name
Test status
Simulation time 792479299 ps
CPU time 1.47 seconds
Started Jul 16 04:57:53 PM PDT 24
Finished Jul 16 04:57:55 PM PDT 24
Peak memory 197752 kb
Host smart-e712e565-3eeb-45d1-8ca4-1a7441fc14bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206772791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2206772791
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.4273447611
Short name T1149
Test name
Test status
Simulation time 56663163322 ps
CPU time 30.6 seconds
Started Jul 16 04:57:55 PM PDT 24
Finished Jul 16 04:58:26 PM PDT 24
Peak memory 199772 kb
Host smart-8320ed45-0216-428c-a3f8-383e3837abe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273447611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.4273447611
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2104156787
Short name T872
Test name
Test status
Simulation time 35604170 ps
CPU time 0.6 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 04:58:03 PM PDT 24
Peak memory 195128 kb
Host smart-61297b7c-aac9-4d2e-87bd-1aca802d6c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104156787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2104156787
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1920099939
Short name T993
Test name
Test status
Simulation time 43241042540 ps
CPU time 33.07 seconds
Started Jul 16 04:57:47 PM PDT 24
Finished Jul 16 04:58:21 PM PDT 24
Peak memory 199836 kb
Host smart-686b507c-32b6-4566-9405-02306a5e0269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920099939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1920099939
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2123418840
Short name T152
Test name
Test status
Simulation time 138507405404 ps
CPU time 39.53 seconds
Started Jul 16 04:57:47 PM PDT 24
Finished Jul 16 04:58:27 PM PDT 24
Peak memory 199776 kb
Host smart-87c39d8d-5b23-46ee-8da2-cdb8340f3408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123418840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2123418840
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2980844681
Short name T712
Test name
Test status
Simulation time 101036895363 ps
CPU time 72.04 seconds
Started Jul 16 04:57:53 PM PDT 24
Finished Jul 16 04:59:06 PM PDT 24
Peak memory 199732 kb
Host smart-766ed676-defb-454c-bbca-9eb257bd5146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980844681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2980844681
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2169386856
Short name T1091
Test name
Test status
Simulation time 1758636659 ps
CPU time 1.18 seconds
Started Jul 16 04:57:47 PM PDT 24
Finished Jul 16 04:57:49 PM PDT 24
Peak memory 195580 kb
Host smart-4942978e-ccba-46fe-a215-bf51f1f4f341
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169386856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2169386856
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3132516161
Short name T657
Test name
Test status
Simulation time 131605626811 ps
CPU time 624.97 seconds
Started Jul 16 04:57:59 PM PDT 24
Finished Jul 16 05:08:24 PM PDT 24
Peak memory 199936 kb
Host smart-d52ea13a-6ea9-4df2-9df9-1769b4f65742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132516161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3132516161
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3454645395
Short name T633
Test name
Test status
Simulation time 6615079237 ps
CPU time 9.49 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 04:58:11 PM PDT 24
Peak memory 199468 kb
Host smart-33e4bbee-4105-4940-9894-bba89d9da00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454645395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3454645395
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1971040152
Short name T1062
Test name
Test status
Simulation time 140003092304 ps
CPU time 149.18 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 05:00:19 PM PDT 24
Peak memory 208228 kb
Host smart-022b79f8-b49f-4390-aafb-599f78569987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971040152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1971040152
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2063445669
Short name T1114
Test name
Test status
Simulation time 10389392062 ps
CPU time 158.02 seconds
Started Jul 16 04:57:59 PM PDT 24
Finished Jul 16 05:00:38 PM PDT 24
Peak memory 199872 kb
Host smart-2810751e-470d-4a83-b762-319b1951f65c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063445669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2063445669
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1615991747
Short name T1051
Test name
Test status
Simulation time 1924610597 ps
CPU time 3.44 seconds
Started Jul 16 04:57:49 PM PDT 24
Finished Jul 16 04:57:54 PM PDT 24
Peak memory 198836 kb
Host smart-0f6ee18c-c236-4cbe-9e89-3c535d901d2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615991747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1615991747
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1791225173
Short name T505
Test name
Test status
Simulation time 20409592746 ps
CPU time 24.53 seconds
Started Jul 16 04:58:00 PM PDT 24
Finished Jul 16 04:58:26 PM PDT 24
Peak memory 199796 kb
Host smart-8586b27c-cb75-4d8d-86ed-a3dd4f76d54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791225173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1791225173
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1120964069
Short name T1175
Test name
Test status
Simulation time 5046783350 ps
CPU time 8.3 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 04:58:11 PM PDT 24
Peak memory 196312 kb
Host smart-6c6cbed8-ce1d-4b5d-9e1d-922b9f490f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120964069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1120964069
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1854626690
Short name T974
Test name
Test status
Simulation time 5888627688 ps
CPU time 19.24 seconds
Started Jul 16 04:57:53 PM PDT 24
Finished Jul 16 04:58:13 PM PDT 24
Peak memory 199576 kb
Host smart-feb79696-607f-4231-8c03-0573d37d7703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854626690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1854626690
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3461605059
Short name T222
Test name
Test status
Simulation time 151445220022 ps
CPU time 57.92 seconds
Started Jul 16 04:58:00 PM PDT 24
Finished Jul 16 04:58:58 PM PDT 24
Peak memory 199748 kb
Host smart-3adcb554-9845-41bf-b3bf-0fbbe00fdb1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461605059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3461605059
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2774715466
Short name T389
Test name
Test status
Simulation time 1845165898 ps
CPU time 1.74 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 04:58:04 PM PDT 24
Peak memory 198156 kb
Host smart-2483976a-2971-49bc-9daf-3f95f406d717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774715466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2774715466
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.212418451
Short name T689
Test name
Test status
Simulation time 17752110664 ps
CPU time 6.92 seconds
Started Jul 16 04:57:53 PM PDT 24
Finished Jul 16 04:58:01 PM PDT 24
Peak memory 197036 kb
Host smart-e9cd46f6-db4b-4ed6-ac04-e12512c71d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212418451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.212418451
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3767624446
Short name T121
Test name
Test status
Simulation time 17200529 ps
CPU time 0.58 seconds
Started Jul 16 04:58:00 PM PDT 24
Finished Jul 16 04:58:02 PM PDT 24
Peak memory 195524 kb
Host smart-a065d806-a240-4322-9f68-c526c0b360c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767624446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3767624446
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3520065015
Short name T1002
Test name
Test status
Simulation time 222520143381 ps
CPU time 76.78 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 04:59:18 PM PDT 24
Peak memory 199708 kb
Host smart-7fb28a8c-771e-46a1-8200-213af4065d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520065015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3520065015
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2760105959
Short name T680
Test name
Test status
Simulation time 137644009936 ps
CPU time 219.3 seconds
Started Jul 16 04:58:00 PM PDT 24
Finished Jul 16 05:01:40 PM PDT 24
Peak memory 199752 kb
Host smart-4591f162-dcdb-41c8-aaac-040c86451e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760105959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2760105959
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3331552717
Short name T1083
Test name
Test status
Simulation time 34703669328 ps
CPU time 47.48 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 04:58:50 PM PDT 24
Peak memory 199804 kb
Host smart-9b1de80f-2669-47ff-aa69-9bbea907e983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331552717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3331552717
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1570039635
Short name T1153
Test name
Test status
Simulation time 14734732270 ps
CPU time 23.28 seconds
Started Jul 16 04:58:06 PM PDT 24
Finished Jul 16 04:58:30 PM PDT 24
Peak memory 199656 kb
Host smart-da0609fe-5df2-4c34-8e51-9dc0cf872329
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570039635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1570039635
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1967072205
Short name T535
Test name
Test status
Simulation time 42557866267 ps
CPU time 153.41 seconds
Started Jul 16 04:58:04 PM PDT 24
Finished Jul 16 05:00:38 PM PDT 24
Peak memory 199836 kb
Host smart-9be1a025-a229-414a-9eb6-d9d43431f968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1967072205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1967072205
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1513189883
Short name T726
Test name
Test status
Simulation time 11194751735 ps
CPU time 25.63 seconds
Started Jul 16 04:58:02 PM PDT 24
Finished Jul 16 04:58:29 PM PDT 24
Peak memory 199592 kb
Host smart-cfbe5a07-8c52-4cb7-b1df-d5f8905519e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513189883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1513189883
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2593536803
Short name T855
Test name
Test status
Simulation time 38589419202 ps
CPU time 56.82 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 04:58:59 PM PDT 24
Peak memory 199984 kb
Host smart-f6d30acc-c75d-45b0-a7f2-29cd736489ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593536803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2593536803
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.397995928
Short name T391
Test name
Test status
Simulation time 18479801390 ps
CPU time 229.94 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 05:01:52 PM PDT 24
Peak memory 199780 kb
Host smart-3fe50287-b44b-4451-96ec-6e261b4ef092
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=397995928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.397995928
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.393927026
Short name T891
Test name
Test status
Simulation time 3904661277 ps
CPU time 7.8 seconds
Started Jul 16 04:58:02 PM PDT 24
Finished Jul 16 04:58:11 PM PDT 24
Peak memory 197988 kb
Host smart-55bd3959-69f2-4997-b8fc-7147f7fa2bfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=393927026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.393927026
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1312419310
Short name T1141
Test name
Test status
Simulation time 4619738257 ps
CPU time 7.92 seconds
Started Jul 16 04:57:59 PM PDT 24
Finished Jul 16 04:58:08 PM PDT 24
Peak memory 199352 kb
Host smart-3358ca25-5a76-4b4d-8d96-81c0fa34cdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312419310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1312419310
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3565925326
Short name T54
Test name
Test status
Simulation time 42889054980 ps
CPU time 14.3 seconds
Started Jul 16 04:58:04 PM PDT 24
Finished Jul 16 04:58:19 PM PDT 24
Peak memory 196264 kb
Host smart-0f7d6954-e15e-4523-a79b-d00f6a2799af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565925326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3565925326
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.514263716
Short name T343
Test name
Test status
Simulation time 6171052201 ps
CPU time 6.76 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 04:58:09 PM PDT 24
Peak memory 199108 kb
Host smart-84ddcc09-265a-446e-8a72-f71f52cf1b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514263716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.514263716
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2338491566
Short name T173
Test name
Test status
Simulation time 106082296302 ps
CPU time 815.37 seconds
Started Jul 16 04:58:06 PM PDT 24
Finished Jul 16 05:11:42 PM PDT 24
Peak memory 199700 kb
Host smart-f597bfd6-78f4-4c8d-8ea1-ecc45e4f2ce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338491566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2338491566
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.4116100123
Short name T939
Test name
Test status
Simulation time 120346328908 ps
CPU time 744.08 seconds
Started Jul 16 04:58:00 PM PDT 24
Finished Jul 16 05:10:25 PM PDT 24
Peak memory 216528 kb
Host smart-84dfdb2f-8bbc-4dce-b17a-bb224d1a41ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116100123 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.4116100123
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3630465142
Short name T387
Test name
Test status
Simulation time 1086553803 ps
CPU time 1.17 seconds
Started Jul 16 04:58:02 PM PDT 24
Finished Jul 16 04:58:04 PM PDT 24
Peak memory 197576 kb
Host smart-e999d5d5-b6df-4d14-9be1-407f06607a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630465142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3630465142
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1202176720
Short name T711
Test name
Test status
Simulation time 36659987281 ps
CPU time 55.29 seconds
Started Jul 16 04:57:58 PM PDT 24
Finished Jul 16 04:58:54 PM PDT 24
Peak memory 199752 kb
Host smart-71a13f0f-e809-4cc8-87e2-f2b7b4f4ae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202176720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1202176720
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.444679568
Short name T838
Test name
Test status
Simulation time 24766579 ps
CPU time 0.59 seconds
Started Jul 16 04:58:04 PM PDT 24
Finished Jul 16 04:58:05 PM PDT 24
Peak memory 195152 kb
Host smart-300ed1f8-8efc-49a1-abf5-bec9a979986b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444679568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.444679568
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.885638230
Short name T1159
Test name
Test status
Simulation time 67354303500 ps
CPU time 114.47 seconds
Started Jul 16 04:58:00 PM PDT 24
Finished Jul 16 04:59:55 PM PDT 24
Peak memory 199776 kb
Host smart-f9de11f3-1db5-4849-8610-b23dc0dc12ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885638230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.885638230
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1531441661
Short name T972
Test name
Test status
Simulation time 57372705711 ps
CPU time 23.57 seconds
Started Jul 16 04:58:03 PM PDT 24
Finished Jul 16 04:58:27 PM PDT 24
Peak memory 199372 kb
Host smart-07a813f7-23fe-4f5e-8136-dc795c590a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531441661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1531441661
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_intr.245559274
Short name T127
Test name
Test status
Simulation time 31271738946 ps
CPU time 22.12 seconds
Started Jul 16 04:58:02 PM PDT 24
Finished Jul 16 04:58:25 PM PDT 24
Peak memory 198912 kb
Host smart-2203bc4a-40d9-4557-83e2-ab0a8394f1b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245559274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.245559274
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.550896593
Short name T493
Test name
Test status
Simulation time 82643214159 ps
CPU time 456.12 seconds
Started Jul 16 04:58:00 PM PDT 24
Finished Jul 16 05:05:38 PM PDT 24
Peak memory 199732 kb
Host smart-3580468c-db02-4271-a70c-25fc1c88bd0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=550896593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.550896593
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1175458014
Short name T359
Test name
Test status
Simulation time 7618653072 ps
CPU time 7.87 seconds
Started Jul 16 04:58:00 PM PDT 24
Finished Jul 16 04:58:08 PM PDT 24
Peak memory 199372 kb
Host smart-8d9bc9c5-f444-4364-9712-a7e10fed3c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175458014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1175458014
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2695216323
Short name T361
Test name
Test status
Simulation time 111086958781 ps
CPU time 166.33 seconds
Started Jul 16 04:58:03 PM PDT 24
Finished Jul 16 05:00:50 PM PDT 24
Peak memory 199060 kb
Host smart-182623ab-40cd-42d3-9194-9ce05a5d03eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695216323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2695216323
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1547071150
Short name T439
Test name
Test status
Simulation time 7083814329 ps
CPU time 59.11 seconds
Started Jul 16 05:02:21 PM PDT 24
Finished Jul 16 05:03:21 PM PDT 24
Peak memory 198876 kb
Host smart-efbfbb9a-f76f-48cf-bff7-8411c64be3f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547071150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1547071150
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.793116944
Short name T912
Test name
Test status
Simulation time 199315838760 ps
CPU time 128.38 seconds
Started Jul 16 04:57:59 PM PDT 24
Finished Jul 16 05:00:08 PM PDT 24
Peak memory 199744 kb
Host smart-9cc75555-7389-486d-bf12-a39089740755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793116944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.793116944
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3868196706
Short name T339
Test name
Test status
Simulation time 2879964210 ps
CPU time 2.76 seconds
Started Jul 16 04:57:59 PM PDT 24
Finished Jul 16 04:58:03 PM PDT 24
Peak memory 196340 kb
Host smart-b86a1e2e-de30-4c00-b9a3-0ba7a37b2c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868196706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3868196706
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2839339392
Short name T899
Test name
Test status
Simulation time 5378336091 ps
CPU time 14.45 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 04:58:17 PM PDT 24
Peak memory 199744 kb
Host smart-468674f2-9eda-4029-8810-3d51e3260114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839339392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2839339392
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3677749690
Short name T123
Test name
Test status
Simulation time 75951522099 ps
CPU time 167.28 seconds
Started Jul 16 04:58:02 PM PDT 24
Finished Jul 16 05:00:51 PM PDT 24
Peak memory 199804 kb
Host smart-d1cfbe4a-8377-4aef-bb20-7c6ea016132c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677749690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3677749690
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1136296875
Short name T442
Test name
Test status
Simulation time 862364511 ps
CPU time 2.67 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 04:58:04 PM PDT 24
Peak memory 198192 kb
Host smart-322c7dd1-247b-4cd8-b389-18a4e2daa13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136296875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1136296875
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.4270431636
Short name T2
Test name
Test status
Simulation time 82415963530 ps
CPU time 33.23 seconds
Started Jul 16 04:58:06 PM PDT 24
Finished Jul 16 04:58:40 PM PDT 24
Peak memory 199676 kb
Host smart-2717e8ba-7097-45f7-a955-2222012aad5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270431636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.4270431636
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3192511317
Short name T864
Test name
Test status
Simulation time 36415331 ps
CPU time 0.6 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 04:58:18 PM PDT 24
Peak memory 195152 kb
Host smart-201ac2fe-626b-4cfd-a786-d5e25e8b4c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192511317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3192511317
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.622068356
Short name T659
Test name
Test status
Simulation time 18943047243 ps
CPU time 28.24 seconds
Started Jul 16 04:58:02 PM PDT 24
Finished Jul 16 04:58:31 PM PDT 24
Peak memory 199804 kb
Host smart-751a2e0d-8ffb-445d-928c-2e03cd8c48c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622068356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.622068356
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1448756406
Short name T410
Test name
Test status
Simulation time 229565471695 ps
CPU time 140.66 seconds
Started Jul 16 04:57:59 PM PDT 24
Finished Jul 16 05:00:20 PM PDT 24
Peak memory 199684 kb
Host smart-7f09b35a-fa26-4f97-9a78-ab3635612388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448756406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1448756406
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2072582237
Short name T1065
Test name
Test status
Simulation time 20199047317 ps
CPU time 28.63 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 04:58:31 PM PDT 24
Peak memory 199688 kb
Host smart-6511c118-1099-45ef-8ec0-cfd49da4458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072582237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2072582237
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2996885108
Short name T255
Test name
Test status
Simulation time 112672851312 ps
CPU time 183.01 seconds
Started Jul 16 04:58:02 PM PDT 24
Finished Jul 16 05:01:06 PM PDT 24
Peak memory 199772 kb
Host smart-e176c0bf-26fb-4904-9c97-5f73c8a926f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996885108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2996885108
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2473137568
Short name T256
Test name
Test status
Simulation time 117664588638 ps
CPU time 352.75 seconds
Started Jul 16 04:58:16 PM PDT 24
Finished Jul 16 05:04:09 PM PDT 24
Peak memory 199724 kb
Host smart-59d712c0-afd6-4374-9dc3-02cb454aeabb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473137568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2473137568
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1528124588
Short name T721
Test name
Test status
Simulation time 3094261629 ps
CPU time 3.91 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 04:58:21 PM PDT 24
Peak memory 198428 kb
Host smart-b04d9747-f5d5-4e54-b0d9-03a1cf0df311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528124588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1528124588
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3183423312
Short name T307
Test name
Test status
Simulation time 133680085845 ps
CPU time 121.93 seconds
Started Jul 16 04:58:02 PM PDT 24
Finished Jul 16 05:00:05 PM PDT 24
Peak memory 199864 kb
Host smart-1f97cf83-3630-49fd-89d1-99a65d507242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183423312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3183423312
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.4127705754
Short name T821
Test name
Test status
Simulation time 11953764905 ps
CPU time 569.58 seconds
Started Jul 16 04:58:19 PM PDT 24
Finished Jul 16 05:07:49 PM PDT 24
Peak memory 199816 kb
Host smart-c505e01c-98e8-42dd-8e76-a835aafea046
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4127705754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4127705754
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.414871902
Short name T440
Test name
Test status
Simulation time 3380688587 ps
CPU time 28.17 seconds
Started Jul 16 04:58:02 PM PDT 24
Finished Jul 16 04:58:31 PM PDT 24
Peak memory 198864 kb
Host smart-dfe84484-7a1f-41f7-b5e0-305b876af680
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414871902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.414871902
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3998687394
Short name T745
Test name
Test status
Simulation time 63016187112 ps
CPU time 40.01 seconds
Started Jul 16 04:58:18 PM PDT 24
Finished Jul 16 04:58:59 PM PDT 24
Peak memory 199780 kb
Host smart-55c8245c-86d5-4168-933f-fa9567001d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998687394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3998687394
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2413745660
Short name T378
Test name
Test status
Simulation time 1415616879 ps
CPU time 1.19 seconds
Started Jul 16 04:58:04 PM PDT 24
Finished Jul 16 04:58:06 PM PDT 24
Peak memory 195416 kb
Host smart-31b34df0-f8fe-4d2d-848b-2b0d6c64a068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413745660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2413745660
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.4154832533
Short name T392
Test name
Test status
Simulation time 459539222 ps
CPU time 1.16 seconds
Started Jul 16 04:58:03 PM PDT 24
Finished Jul 16 04:58:05 PM PDT 24
Peak memory 198268 kb
Host smart-1b9a10b6-e30c-4624-a0a7-09390910919b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154832533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.4154832533
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.738438814
Short name T761
Test name
Test status
Simulation time 338260662532 ps
CPU time 816.22 seconds
Started Jul 16 04:58:19 PM PDT 24
Finished Jul 16 05:11:56 PM PDT 24
Peak memory 199744 kb
Host smart-a99071fe-c9b8-44de-9431-fcc2d309a3f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738438814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.738438814
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1666506506
Short name T692
Test name
Test status
Simulation time 236263038155 ps
CPU time 452.98 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 05:05:50 PM PDT 24
Peak memory 224652 kb
Host smart-6bafee66-ccab-481a-92f9-a835911b1821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666506506 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1666506506
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1103848132
Short name T396
Test name
Test status
Simulation time 673212504 ps
CPU time 2.29 seconds
Started Jul 16 04:58:18 PM PDT 24
Finished Jul 16 04:58:21 PM PDT 24
Peak memory 198712 kb
Host smart-88023afc-cb94-4556-b171-d42ca021d40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103848132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1103848132
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.523010704
Short name T1052
Test name
Test status
Simulation time 94560835768 ps
CPU time 159.76 seconds
Started Jul 16 04:58:01 PM PDT 24
Finished Jul 16 05:00:41 PM PDT 24
Peak memory 200164 kb
Host smart-7ca6070b-2e10-4ef6-9cf0-477569839535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523010704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.523010704
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2293820443
Short name T1007
Test name
Test status
Simulation time 37247201 ps
CPU time 0.61 seconds
Started Jul 16 04:58:19 PM PDT 24
Finished Jul 16 04:58:20 PM PDT 24
Peak memory 195452 kb
Host smart-bc27cd54-d9cd-4b4a-bd54-ef9bdc7e89e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293820443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2293820443
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3280488247
Short name T288
Test name
Test status
Simulation time 97832659917 ps
CPU time 67.35 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 04:59:25 PM PDT 24
Peak memory 199860 kb
Host smart-1ed22587-0a47-4fbd-84df-1be0dd5b85a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280488247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3280488247
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1815038482
Short name T176
Test name
Test status
Simulation time 30992788979 ps
CPU time 14.11 seconds
Started Jul 16 04:58:18 PM PDT 24
Finished Jul 16 04:58:33 PM PDT 24
Peak memory 199672 kb
Host smart-4a079f36-e6f6-437c-8284-cd6177effd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815038482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1815038482
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.333918896
Short name T966
Test name
Test status
Simulation time 8692899516 ps
CPU time 13.1 seconds
Started Jul 16 04:58:18 PM PDT 24
Finished Jul 16 04:58:32 PM PDT 24
Peak memory 199840 kb
Host smart-8230871d-8ae1-4062-a5ac-91b08bbbee8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333918896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.333918896
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.442376887
Short name T871
Test name
Test status
Simulation time 9875168367 ps
CPU time 15.29 seconds
Started Jul 16 04:58:18 PM PDT 24
Finished Jul 16 04:58:35 PM PDT 24
Peak memory 196148 kb
Host smart-e34efe50-8d74-432a-9429-93dbe5a71dc7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442376887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.442376887
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4097539811
Short name T1070
Test name
Test status
Simulation time 60776651261 ps
CPU time 354.24 seconds
Started Jul 16 04:58:18 PM PDT 24
Finished Jul 16 05:04:13 PM PDT 24
Peak memory 199852 kb
Host smart-da705541-2f8c-4144-b87a-b0de776ae185
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4097539811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4097539811
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3126986563
Short name T1095
Test name
Test status
Simulation time 9641875003 ps
CPU time 7.2 seconds
Started Jul 16 04:58:18 PM PDT 24
Finished Jul 16 04:58:26 PM PDT 24
Peak memory 198156 kb
Host smart-20ef6cd3-be98-494d-9d84-1a358070dfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126986563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3126986563
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.4059522972
Short name T346
Test name
Test status
Simulation time 7277737171 ps
CPU time 10.89 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 04:58:29 PM PDT 24
Peak memory 194580 kb
Host smart-dfc5f53e-3273-476e-88e9-be481dfd4f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059522972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.4059522972
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4148704137
Short name T266
Test name
Test status
Simulation time 15199059499 ps
CPU time 174.69 seconds
Started Jul 16 04:58:20 PM PDT 24
Finished Jul 16 05:01:15 PM PDT 24
Peak memory 199892 kb
Host smart-b7e02d0c-c7e1-4aea-b30a-8995bfa47ad0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148704137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4148704137
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.822519495
Short name T351
Test name
Test status
Simulation time 4453854816 ps
CPU time 9.24 seconds
Started Jul 16 04:58:19 PM PDT 24
Finished Jul 16 04:58:29 PM PDT 24
Peak memory 199200 kb
Host smart-d7451e08-f466-44be-b1c9-d64939b04432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822519495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.822519495
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1510983981
Short name T169
Test name
Test status
Simulation time 74227635513 ps
CPU time 111.96 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 05:00:09 PM PDT 24
Peak memory 199776 kb
Host smart-dd96c22b-6c0d-4f21-b52b-e38f3a9d8c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510983981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1510983981
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2118048438
Short name T363
Test name
Test status
Simulation time 537359746 ps
CPU time 1.01 seconds
Started Jul 16 04:58:19 PM PDT 24
Finished Jul 16 04:58:21 PM PDT 24
Peak memory 195260 kb
Host smart-c15188b1-bd56-48c8-b3d9-2fcf78e3aec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118048438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2118048438
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2589894684
Short name T287
Test name
Test status
Simulation time 488655051 ps
CPU time 3.24 seconds
Started Jul 16 04:58:18 PM PDT 24
Finished Jul 16 04:58:22 PM PDT 24
Peak memory 199440 kb
Host smart-f535712d-7e95-4665-8f6f-e721bccabdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589894684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2589894684
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.4166187755
Short name T164
Test name
Test status
Simulation time 456891921229 ps
CPU time 722.43 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 05:10:20 PM PDT 24
Peak memory 199868 kb
Host smart-303e8a16-79a5-49a4-9b7d-263df5b184bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166187755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.4166187755
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2234144382
Short name T507
Test name
Test status
Simulation time 124373975663 ps
CPU time 421.34 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 05:05:19 PM PDT 24
Peak memory 216588 kb
Host smart-5ba6f7ed-01dc-45d1-a9cb-9c2bd82c4ba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234144382 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2234144382
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2608429901
Short name T453
Test name
Test status
Simulation time 484001451 ps
CPU time 1.4 seconds
Started Jul 16 04:58:16 PM PDT 24
Finished Jul 16 04:58:17 PM PDT 24
Peak memory 198464 kb
Host smart-1e8dfc93-b376-49e3-b2b3-4e6700ddee85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608429901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2608429901
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2000519462
Short name T384
Test name
Test status
Simulation time 93262008600 ps
CPU time 134.75 seconds
Started Jul 16 04:58:22 PM PDT 24
Finished Jul 16 05:00:37 PM PDT 24
Peak memory 199676 kb
Host smart-e48e4dac-cf5a-4f07-8489-54d3d887bc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000519462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2000519462
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2626129259
Short name T26
Test name
Test status
Simulation time 15120981 ps
CPU time 0.63 seconds
Started Jul 16 04:58:19 PM PDT 24
Finished Jul 16 04:58:20 PM PDT 24
Peak memory 195452 kb
Host smart-8377fea1-bdae-4262-8c73-c2ac0e6298c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626129259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2626129259
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.4126879424
Short name T616
Test name
Test status
Simulation time 215394016892 ps
CPU time 57.53 seconds
Started Jul 16 04:58:19 PM PDT 24
Finished Jul 16 04:59:17 PM PDT 24
Peak memory 199744 kb
Host smart-d61dcb5f-83d6-4e12-9596-798d8cce1d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126879424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.4126879424
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1992571871
Short name T1123
Test name
Test status
Simulation time 173999865238 ps
CPU time 117.39 seconds
Started Jul 16 04:58:21 PM PDT 24
Finished Jul 16 05:00:19 PM PDT 24
Peak memory 199656 kb
Host smart-5011d779-9169-487c-a2ea-559eac598ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992571871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1992571871
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1158572413
Short name T39
Test name
Test status
Simulation time 23755327016 ps
CPU time 47.17 seconds
Started Jul 16 04:58:24 PM PDT 24
Finished Jul 16 04:59:12 PM PDT 24
Peak memory 199776 kb
Host smart-c89b72eb-afb5-4731-94c6-621945ecc765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158572413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1158572413
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2666562084
Short name T717
Test name
Test status
Simulation time 10099950531 ps
CPU time 3.02 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 04:58:21 PM PDT 24
Peak memory 196700 kb
Host smart-1f855e4c-3545-49d3-b5f5-ec21000b34e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666562084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2666562084
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.913876418
Short name T953
Test name
Test status
Simulation time 178205669684 ps
CPU time 111.28 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 05:00:09 PM PDT 24
Peak memory 199732 kb
Host smart-ee9be86f-29af-41e0-8128-3dc106795759
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=913876418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.913876418
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3987383808
Short name T902
Test name
Test status
Simulation time 8803000046 ps
CPU time 8.55 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 04:58:27 PM PDT 24
Peak memory 198804 kb
Host smart-3da8a6ef-5789-426c-8caf-49818b835d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987383808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3987383808
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.86779180
Short name T422
Test name
Test status
Simulation time 12803555717 ps
CPU time 22.04 seconds
Started Jul 16 04:58:18 PM PDT 24
Finished Jul 16 04:58:41 PM PDT 24
Peak memory 199956 kb
Host smart-6833f4e7-db60-4c1a-a0df-d2f009cf3cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86779180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.86779180
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1488251739
Short name T1172
Test name
Test status
Simulation time 21780019041 ps
CPU time 1001.24 seconds
Started Jul 16 04:58:22 PM PDT 24
Finished Jul 16 05:15:03 PM PDT 24
Peak memory 199648 kb
Host smart-16bea0ed-550e-4d39-b9e9-1c5ebdafd048
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488251739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1488251739
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1561536611
Short name T856
Test name
Test status
Simulation time 6824367307 ps
CPU time 61.33 seconds
Started Jul 16 04:58:19 PM PDT 24
Finished Jul 16 04:59:21 PM PDT 24
Peak memory 197992 kb
Host smart-64f77bdf-65be-45c2-a9ed-c807ecbb8bac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1561536611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1561536611
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2327892858
Short name T399
Test name
Test status
Simulation time 86333671857 ps
CPU time 32.24 seconds
Started Jul 16 04:58:20 PM PDT 24
Finished Jul 16 04:58:53 PM PDT 24
Peak memory 199768 kb
Host smart-54326ce6-b674-4d01-81df-e3c2313d5681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327892858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2327892858
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.177824779
Short name T1102
Test name
Test status
Simulation time 43173753201 ps
CPU time 28.61 seconds
Started Jul 16 04:58:18 PM PDT 24
Finished Jul 16 04:58:47 PM PDT 24
Peak memory 196176 kb
Host smart-4f9cd95e-4f45-445e-a228-b632e05a9aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177824779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.177824779
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1658888062
Short name T857
Test name
Test status
Simulation time 5970533886 ps
CPU time 19.72 seconds
Started Jul 16 04:58:16 PM PDT 24
Finished Jul 16 04:58:36 PM PDT 24
Peak memory 199628 kb
Host smart-9bfcc06f-805e-48aa-b1b2-e2c144d7ebe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658888062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1658888062
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.4288223760
Short name T24
Test name
Test status
Simulation time 53933924210 ps
CPU time 360.61 seconds
Started Jul 16 04:58:18 PM PDT 24
Finished Jul 16 05:04:19 PM PDT 24
Peak memory 215728 kb
Host smart-2667e51c-dc63-45fa-94d3-289c1b6c4f36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288223760 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.4288223760
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1793196637
Short name T923
Test name
Test status
Simulation time 8827534409 ps
CPU time 8.02 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 04:58:26 PM PDT 24
Peak memory 199276 kb
Host smart-551eb978-adf9-4d2b-83ca-ad6c1f743e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793196637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1793196637
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2638926110
Short name T456
Test name
Test status
Simulation time 50799897132 ps
CPU time 75.91 seconds
Started Jul 16 04:58:17 PM PDT 24
Finished Jul 16 04:59:33 PM PDT 24
Peak memory 199852 kb
Host smart-0a8d50ac-4458-4541-8f49-8d669a6ff1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638926110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2638926110
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2227949033
Short name T998
Test name
Test status
Simulation time 34704542 ps
CPU time 0.58 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 04:58:28 PM PDT 24
Peak memory 195416 kb
Host smart-26b883ae-2bd3-4f5e-afbe-951789f6502a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227949033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2227949033
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2302151711
Short name T1081
Test name
Test status
Simulation time 51579695045 ps
CPU time 20.28 seconds
Started Jul 16 04:58:20 PM PDT 24
Finished Jul 16 04:58:41 PM PDT 24
Peak memory 199852 kb
Host smart-e813f322-7c88-48b5-8564-6e8720ece711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302151711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2302151711
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.899382903
Short name T373
Test name
Test status
Simulation time 49011059650 ps
CPU time 41.68 seconds
Started Jul 16 04:58:29 PM PDT 24
Finished Jul 16 04:59:11 PM PDT 24
Peak memory 199772 kb
Host smart-37aadee9-f69d-4047-b4f6-228aad7874c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899382903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.899382903
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2950290992
Short name T701
Test name
Test status
Simulation time 66564945407 ps
CPU time 27.31 seconds
Started Jul 16 04:58:29 PM PDT 24
Finished Jul 16 04:58:57 PM PDT 24
Peak memory 199764 kb
Host smart-2a99c27d-9c6a-4dc0-8b9b-032078c5729b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950290992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2950290992
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3764096982
Short name T1109
Test name
Test status
Simulation time 277771140019 ps
CPU time 476.77 seconds
Started Jul 16 04:58:30 PM PDT 24
Finished Jul 16 05:06:27 PM PDT 24
Peak memory 199736 kb
Host smart-b0a650f1-7295-4782-b63b-bd8d01f54556
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764096982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3764096982
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.4090764706
Short name T1137
Test name
Test status
Simulation time 61963084343 ps
CPU time 397.31 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 05:05:06 PM PDT 24
Peak memory 199700 kb
Host smart-f22b746c-3fb0-4585-9673-5cbc18352609
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090764706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.4090764706
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1759363184
Short name T489
Test name
Test status
Simulation time 4308842302 ps
CPU time 12.58 seconds
Started Jul 16 04:58:26 PM PDT 24
Finished Jul 16 04:58:39 PM PDT 24
Peak memory 199700 kb
Host smart-16f438c4-b72c-4639-9929-da8ba69d9789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759363184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1759363184
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1967190982
Short name T310
Test name
Test status
Simulation time 187276142967 ps
CPU time 104.81 seconds
Started Jul 16 04:58:26 PM PDT 24
Finished Jul 16 05:00:12 PM PDT 24
Peak memory 199460 kb
Host smart-7fbe92ad-8557-4f1f-898a-e5f749ea49f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967190982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1967190982
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1455341244
Short name T574
Test name
Test status
Simulation time 10007500450 ps
CPU time 134.73 seconds
Started Jul 16 04:58:29 PM PDT 24
Finished Jul 16 05:00:44 PM PDT 24
Peak memory 199812 kb
Host smart-7b28d118-2911-4a99-b9e6-9ae134884fcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455341244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1455341244
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3037958415
Short name T494
Test name
Test status
Simulation time 2966964695 ps
CPU time 19.21 seconds
Started Jul 16 04:58:26 PM PDT 24
Finished Jul 16 04:58:46 PM PDT 24
Peak memory 197872 kb
Host smart-aa368550-ffa6-4b73-8952-41fb738f08ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037958415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3037958415
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1185641865
Short name T524
Test name
Test status
Simulation time 455453138340 ps
CPU time 36.5 seconds
Started Jul 16 04:58:28 PM PDT 24
Finished Jul 16 04:59:06 PM PDT 24
Peak memory 199788 kb
Host smart-2b34d0c2-6edd-4e49-a97a-66188c8621fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185641865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1185641865
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2654630712
Short name T518
Test name
Test status
Simulation time 3059019537 ps
CPU time 1.54 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 04:58:30 PM PDT 24
Peak memory 195776 kb
Host smart-dbf84dd1-b422-45e7-a6e3-3f247d990621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654630712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2654630712
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1630208090
Short name T870
Test name
Test status
Simulation time 5356359451 ps
CPU time 15.41 seconds
Started Jul 16 04:58:22 PM PDT 24
Finished Jul 16 04:58:38 PM PDT 24
Peak memory 199800 kb
Host smart-cea4ef4f-8b44-40fc-bf82-cfb420406b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630208090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1630208090
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.833670303
Short name T771
Test name
Test status
Simulation time 192501108491 ps
CPU time 711.46 seconds
Started Jul 16 04:58:34 PM PDT 24
Finished Jul 16 05:10:26 PM PDT 24
Peak memory 199760 kb
Host smart-1a32778c-14eb-4224-b3d6-e681b69f68d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833670303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.833670303
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2261424063
Short name T753
Test name
Test status
Simulation time 46226383989 ps
CPU time 637.04 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 05:09:06 PM PDT 24
Peak memory 216544 kb
Host smart-f06d4741-74ba-40d3-aea1-60463b1d8c85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261424063 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2261424063
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3041752930
Short name T826
Test name
Test status
Simulation time 5135941506 ps
CPU time 1.63 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 04:58:30 PM PDT 24
Peak memory 199124 kb
Host smart-2677ec17-070c-450b-bc15-a8bec87b9dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041752930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3041752930
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3157679741
Short name T420
Test name
Test status
Simulation time 94446528430 ps
CPU time 31.12 seconds
Started Jul 16 04:58:18 PM PDT 24
Finished Jul 16 04:58:50 PM PDT 24
Peak memory 199716 kb
Host smart-e05cd349-ae1e-4e54-8307-be5b33cd3c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157679741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3157679741
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3800572086
Short name T519
Test name
Test status
Simulation time 23873235 ps
CPU time 0.57 seconds
Started Jul 16 04:56:31 PM PDT 24
Finished Jul 16 04:56:33 PM PDT 24
Peak memory 195128 kb
Host smart-5d2bd57f-578d-4388-82a5-811a9f9b34ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800572086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3800572086
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2815165757
Short name T778
Test name
Test status
Simulation time 50471819555 ps
CPU time 69.73 seconds
Started Jul 16 04:56:32 PM PDT 24
Finished Jul 16 04:57:43 PM PDT 24
Peak memory 199820 kb
Host smart-90aad7da-9ccc-4812-a472-6dae11671767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815165757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2815165757
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3037490303
Short name T259
Test name
Test status
Simulation time 218152479033 ps
CPU time 539.38 seconds
Started Jul 16 04:56:41 PM PDT 24
Finished Jul 16 05:05:41 PM PDT 24
Peak memory 199756 kb
Host smart-696b476c-47df-443c-bf8d-e19e4117de3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037490303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3037490303
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3517780757
Short name T1005
Test name
Test status
Simulation time 50949791475 ps
CPU time 75.16 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:58:07 PM PDT 24
Peak memory 199764 kb
Host smart-0f44dd6f-c5a3-469f-b588-beec38d583c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517780757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3517780757
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.736389263
Short name T546
Test name
Test status
Simulation time 33400939619 ps
CPU time 16.15 seconds
Started Jul 16 04:56:43 PM PDT 24
Finished Jul 16 04:57:06 PM PDT 24
Peak memory 199856 kb
Host smart-d6dfb198-c471-46df-8307-d24b17529b86
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736389263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.736389263
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.537286009
Short name T583
Test name
Test status
Simulation time 86069192335 ps
CPU time 561.09 seconds
Started Jul 16 04:56:34 PM PDT 24
Finished Jul 16 05:05:57 PM PDT 24
Peak memory 199820 kb
Host smart-0446b844-ad0d-4dad-ad0c-a910ebfa651a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=537286009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.537286009
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2209568381
Short name T960
Test name
Test status
Simulation time 8248813555 ps
CPU time 6.62 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:56:54 PM PDT 24
Peak memory 199480 kb
Host smart-89095d9c-afae-4372-a408-51636e6891f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209568381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2209568381
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1440331290
Short name T1029
Test name
Test status
Simulation time 99211109580 ps
CPU time 208.73 seconds
Started Jul 16 04:56:39 PM PDT 24
Finished Jul 16 05:00:08 PM PDT 24
Peak memory 199436 kb
Host smart-81dd6cee-3b6c-40b7-b42f-043de7fc5761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440331290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1440331290
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2985674930
Short name T765
Test name
Test status
Simulation time 17674038996 ps
CPU time 394.55 seconds
Started Jul 16 04:56:41 PM PDT 24
Finished Jul 16 05:03:16 PM PDT 24
Peak memory 199800 kb
Host smart-00e50928-242d-4e26-bd8e-f3a6b4d0e647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985674930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2985674930
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2674116271
Short name T412
Test name
Test status
Simulation time 3357578171 ps
CPU time 7.61 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 04:56:53 PM PDT 24
Peak memory 197920 kb
Host smart-bc632bc8-3af5-4b1f-b8e9-2ac4b2b7fd99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2674116271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2674116271
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.4182915323
Short name T1148
Test name
Test status
Simulation time 45747751887 ps
CPU time 84.65 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 04:58:10 PM PDT 24
Peak memory 199696 kb
Host smart-c8d5ba5d-6b43-47cf-81db-1a460f6fdb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182915323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.4182915323
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2750515030
Short name T1170
Test name
Test status
Simulation time 3265647881 ps
CPU time 5.45 seconds
Started Jul 16 04:56:43 PM PDT 24
Finished Jul 16 04:56:50 PM PDT 24
Peak memory 195776 kb
Host smart-5b10d343-ff14-4a55-a82b-f1392e1841b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750515030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2750515030
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2717577150
Short name T29
Test name
Test status
Simulation time 299026998 ps
CPU time 0.87 seconds
Started Jul 16 04:56:43 PM PDT 24
Finished Jul 16 04:56:45 PM PDT 24
Peak memory 218248 kb
Host smart-7d68b91e-c6d5-4c9a-99b9-229aabcb803a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717577150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2717577150
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2062955015
Short name T330
Test name
Test status
Simulation time 5355363361 ps
CPU time 9.41 seconds
Started Jul 16 04:56:25 PM PDT 24
Finished Jul 16 04:56:35 PM PDT 24
Peak memory 199852 kb
Host smart-9136489e-08f2-402d-b7ad-3a11ef1f3067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062955015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2062955015
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.10576394
Short name T10
Test name
Test status
Simulation time 24629387892 ps
CPU time 11.68 seconds
Started Jul 16 04:56:45 PM PDT 24
Finished Jul 16 04:56:58 PM PDT 24
Peak memory 199708 kb
Host smart-1c8acdaa-1fe5-4b8c-8ae5-c6ce16465d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10576394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.10576394
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3695663656
Short name T1107
Test name
Test status
Simulation time 45571548507 ps
CPU time 1017.83 seconds
Started Jul 16 04:56:36 PM PDT 24
Finished Jul 16 05:13:35 PM PDT 24
Peak memory 213628 kb
Host smart-baf19a07-bb4e-462d-a9e7-ae3340589e20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695663656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3695663656
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3864611034
Short name T994
Test name
Test status
Simulation time 911536859 ps
CPU time 2.88 seconds
Started Jul 16 04:56:39 PM PDT 24
Finished Jul 16 04:56:43 PM PDT 24
Peak memory 198152 kb
Host smart-9e8a9748-57b9-49f3-ac60-ab049fe4b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864611034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3864611034
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2898945483
Short name T748
Test name
Test status
Simulation time 169553836153 ps
CPU time 112.2 seconds
Started Jul 16 04:56:31 PM PDT 24
Finished Jul 16 04:58:25 PM PDT 24
Peak memory 199780 kb
Host smart-91874fe9-3e41-4d59-95e2-d3446afbacb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898945483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2898945483
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2464370708
Short name T568
Test name
Test status
Simulation time 86600890 ps
CPU time 0.56 seconds
Started Jul 16 04:58:24 PM PDT 24
Finished Jul 16 04:58:25 PM PDT 24
Peak memory 194788 kb
Host smart-39a9f587-ee97-4515-af6c-13b44c49e7bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464370708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2464370708
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1520736723
Short name T888
Test name
Test status
Simulation time 111280227759 ps
CPU time 307.49 seconds
Started Jul 16 04:58:28 PM PDT 24
Finished Jul 16 05:03:37 PM PDT 24
Peak memory 199692 kb
Host smart-16bf9c75-6e0f-4cee-8dde-79efb399a4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520736723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1520736723
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.50414807
Short name T371
Test name
Test status
Simulation time 11122549732 ps
CPU time 19.81 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 04:58:49 PM PDT 24
Peak memory 199732 kb
Host smart-c1b1e5dd-962b-40b3-8ca5-f24716222ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50414807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.50414807
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3838646494
Short name T427
Test name
Test status
Simulation time 16323220115 ps
CPU time 8.84 seconds
Started Jul 16 04:58:24 PM PDT 24
Finished Jul 16 04:58:34 PM PDT 24
Peak memory 199716 kb
Host smart-b11c886b-0843-4661-a077-b0a9b6025333
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838646494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3838646494
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.4116732553
Short name T416
Test name
Test status
Simulation time 116297268652 ps
CPU time 238.11 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 05:02:27 PM PDT 24
Peak memory 199824 kb
Host smart-c1b62de3-5ae3-4bb2-99e8-02adb02548ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116732553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.4116732553
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3233863875
Short name T566
Test name
Test status
Simulation time 6889187509 ps
CPU time 3.54 seconds
Started Jul 16 04:58:30 PM PDT 24
Finished Jul 16 04:58:34 PM PDT 24
Peak memory 198832 kb
Host smart-e11f10af-ddcb-4fcd-ba3e-1da80a1dba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233863875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3233863875
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2560646654
Short name T1094
Test name
Test status
Simulation time 23317214858 ps
CPU time 9.5 seconds
Started Jul 16 04:58:34 PM PDT 24
Finished Jul 16 04:58:44 PM PDT 24
Peak memory 198468 kb
Host smart-7a1d4c36-a365-4ad7-9d48-1a13024803ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560646654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2560646654
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.826441638
Short name T1144
Test name
Test status
Simulation time 20681496154 ps
CPU time 1070.37 seconds
Started Jul 16 04:58:28 PM PDT 24
Finished Jul 16 05:16:20 PM PDT 24
Peak memory 199924 kb
Host smart-fb7e3cb3-eced-4565-be72-cfe7a71abd96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826441638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.826441638
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1885880358
Short name T530
Test name
Test status
Simulation time 2130486831 ps
CPU time 2.63 seconds
Started Jul 16 04:58:30 PM PDT 24
Finished Jul 16 04:58:33 PM PDT 24
Peak memory 197908 kb
Host smart-38a74468-05bf-4ed7-b060-8a9f33411866
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885880358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1885880358
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.461133386
Short name T715
Test name
Test status
Simulation time 30742373902 ps
CPU time 45.87 seconds
Started Jul 16 04:58:34 PM PDT 24
Finished Jul 16 04:59:20 PM PDT 24
Peak memory 199784 kb
Host smart-88203fb8-a9e0-43b4-b4e1-7eae890202d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461133386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.461133386
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.4209195720
Short name T304
Test name
Test status
Simulation time 31126065815 ps
CPU time 26.65 seconds
Started Jul 16 04:58:26 PM PDT 24
Finished Jul 16 04:58:53 PM PDT 24
Peak memory 196188 kb
Host smart-b564dcd6-1562-4ffb-bf16-c64ff17d431a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209195720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.4209195720
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.490196523
Short name T651
Test name
Test status
Simulation time 5472326411 ps
CPU time 9.61 seconds
Started Jul 16 04:58:24 PM PDT 24
Finished Jul 16 04:58:34 PM PDT 24
Peak memory 199808 kb
Host smart-71f0a74d-c03f-4953-a325-d2e300a6c10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490196523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.490196523
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1251161099
Short name T560
Test name
Test status
Simulation time 407905513155 ps
CPU time 946.97 seconds
Started Jul 16 04:58:25 PM PDT 24
Finished Jul 16 05:14:13 PM PDT 24
Peak memory 199832 kb
Host smart-e821ca20-927d-4716-a5b2-b146c48f96f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251161099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1251161099
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2696214764
Short name T884
Test name
Test status
Simulation time 125235963209 ps
CPU time 1140.52 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 05:17:29 PM PDT 24
Peak memory 224856 kb
Host smart-3fe3ad52-aaef-4de9-8df2-67cb8f41bd6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696214764 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2696214764
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3230438105
Short name T349
Test name
Test status
Simulation time 771504552 ps
CPU time 2.07 seconds
Started Jul 16 04:58:25 PM PDT 24
Finished Jul 16 04:58:28 PM PDT 24
Peak memory 199096 kb
Host smart-5946f145-7164-43a8-a7ff-4b1e7457b9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230438105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3230438105
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2430574896
Short name T1180
Test name
Test status
Simulation time 51817754387 ps
CPU time 16.16 seconds
Started Jul 16 04:58:25 PM PDT 24
Finished Jul 16 04:58:42 PM PDT 24
Peak memory 199472 kb
Host smart-ec87c976-9002-44c8-b06e-a8706a26ebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430574896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2430574896
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2124453270
Short name T1093
Test name
Test status
Simulation time 150149571 ps
CPU time 0.58 seconds
Started Jul 16 04:58:25 PM PDT 24
Finished Jul 16 04:58:26 PM PDT 24
Peak memory 195052 kb
Host smart-3e9abd4f-c4fb-416f-8ee2-922c84bd0f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124453270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2124453270
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3370163806
Short name T370
Test name
Test status
Simulation time 104684307494 ps
CPU time 173.42 seconds
Started Jul 16 04:58:24 PM PDT 24
Finished Jul 16 05:01:18 PM PDT 24
Peak memory 199832 kb
Host smart-7b59c8b5-18c3-4bd0-b716-9d2ee6164b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370163806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3370163806
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2052338258
Short name T1035
Test name
Test status
Simulation time 65352088296 ps
CPU time 53.03 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 04:59:21 PM PDT 24
Peak memory 199796 kb
Host smart-e59f868d-91b4-44b8-adf5-67b2f6b04030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052338258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2052338258
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1388573543
Short name T699
Test name
Test status
Simulation time 162930223732 ps
CPU time 66.11 seconds
Started Jul 16 04:58:26 PM PDT 24
Finished Jul 16 04:59:33 PM PDT 24
Peak memory 199756 kb
Host smart-86c4adb4-4a3e-4e00-8c14-ba3703306a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388573543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1388573543
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.92522167
Short name T506
Test name
Test status
Simulation time 61900895124 ps
CPU time 53.45 seconds
Started Jul 16 04:58:26 PM PDT 24
Finished Jul 16 04:59:21 PM PDT 24
Peak memory 199776 kb
Host smart-53a7c464-a9b6-4924-9bb5-507ca5a758d8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92522167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.92522167
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2187119843
Short name T278
Test name
Test status
Simulation time 42948161288 ps
CPU time 167.5 seconds
Started Jul 16 04:58:33 PM PDT 24
Finished Jul 16 05:01:21 PM PDT 24
Peak memory 199712 kb
Host smart-bca075ce-293f-4e56-8b66-82db8df3365a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187119843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2187119843
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3878602977
Short name T497
Test name
Test status
Simulation time 664743460 ps
CPU time 1.94 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 04:58:30 PM PDT 24
Peak memory 197380 kb
Host smart-13593d52-7aa7-4fb1-807a-495e876910ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878602977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3878602977
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.86944562
Short name T618
Test name
Test status
Simulation time 252528305023 ps
CPU time 111.84 seconds
Started Jul 16 04:58:30 PM PDT 24
Finished Jul 16 05:00:22 PM PDT 24
Peak memory 208164 kb
Host smart-c1a5a54f-2682-4fb7-97f4-876de4173766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86944562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.86944562
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.4193239431
Short name T829
Test name
Test status
Simulation time 27211364151 ps
CPU time 352.08 seconds
Started Jul 16 04:58:28 PM PDT 24
Finished Jul 16 05:04:21 PM PDT 24
Peak memory 199736 kb
Host smart-bd9de5cc-19c7-4025-a5a2-9cba306b01b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193239431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.4193239431
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3619119264
Short name T335
Test name
Test status
Simulation time 5591218266 ps
CPU time 50.07 seconds
Started Jul 16 04:58:25 PM PDT 24
Finished Jul 16 04:59:16 PM PDT 24
Peak memory 198048 kb
Host smart-04857713-8494-4060-8563-e7637fde1adc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619119264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3619119264
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1914925224
Short name T1039
Test name
Test status
Simulation time 129630197379 ps
CPU time 255.84 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 05:02:45 PM PDT 24
Peak memory 199792 kb
Host smart-92b63639-7bf0-4b8a-be2f-c97e5c67335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914925224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1914925224
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.671737680
Short name T738
Test name
Test status
Simulation time 4167420658 ps
CPU time 2.03 seconds
Started Jul 16 04:58:28 PM PDT 24
Finished Jul 16 04:58:31 PM PDT 24
Peak memory 195992 kb
Host smart-4edb209c-7fb3-4a47-bcd8-775636b1ef5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671737680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.671737680
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3847046245
Short name T342
Test name
Test status
Simulation time 10538389324 ps
CPU time 44.85 seconds
Started Jul 16 04:58:34 PM PDT 24
Finished Jul 16 04:59:19 PM PDT 24
Peak memory 199360 kb
Host smart-4645244a-1f16-4418-83f9-c12f8f9d19e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847046245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3847046245
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.4251226001
Short name T971
Test name
Test status
Simulation time 323249399117 ps
CPU time 313.41 seconds
Started Jul 16 04:58:29 PM PDT 24
Finished Jul 16 05:03:43 PM PDT 24
Peak memory 208236 kb
Host smart-522792be-f4e1-44b9-b047-25262ee84cec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251226001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.4251226001
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.4191882615
Short name T496
Test name
Test status
Simulation time 326317311824 ps
CPU time 795.2 seconds
Started Jul 16 04:58:25 PM PDT 24
Finished Jul 16 05:11:41 PM PDT 24
Peak memory 224736 kb
Host smart-b0495bbf-2d26-409c-89ac-1ad2d22cd5d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191882615 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.4191882615
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1434096324
Short name T552
Test name
Test status
Simulation time 7475113492 ps
CPU time 9.81 seconds
Started Jul 16 04:58:34 PM PDT 24
Finished Jul 16 04:58:44 PM PDT 24
Peak memory 199744 kb
Host smart-13b52a6f-25ae-4356-b085-1f3cc5988dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434096324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1434096324
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.371559162
Short name T482
Test name
Test status
Simulation time 55963661632 ps
CPU time 56.06 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 04:59:24 PM PDT 24
Peak memory 199808 kb
Host smart-f1cb0b97-a206-41ea-85ba-0506b5e8d736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371559162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.371559162
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.826615239
Short name T877
Test name
Test status
Simulation time 50264219 ps
CPU time 0.56 seconds
Started Jul 16 04:58:43 PM PDT 24
Finished Jul 16 04:58:44 PM PDT 24
Peak memory 195528 kb
Host smart-aa3d72c3-6ad1-4d99-b2d9-42ce3c2e9a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826615239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.826615239
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1142794278
Short name T48
Test name
Test status
Simulation time 143042797363 ps
CPU time 207.02 seconds
Started Jul 16 04:58:26 PM PDT 24
Finished Jul 16 05:01:55 PM PDT 24
Peak memory 199916 kb
Host smart-ce05d03b-32ca-46a1-835f-1a9c8bad2013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142794278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1142794278
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1273881966
Short name T703
Test name
Test status
Simulation time 25358668410 ps
CPU time 24.28 seconds
Started Jul 16 04:58:28 PM PDT 24
Finished Jul 16 04:58:53 PM PDT 24
Peak memory 199652 kb
Host smart-81697e02-af81-464d-9961-20138cc91dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273881966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1273881966
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2005985088
Short name T454
Test name
Test status
Simulation time 36945573699 ps
CPU time 64.28 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 04:59:32 PM PDT 24
Peak memory 199804 kb
Host smart-d087c0a4-c575-49b1-9ee9-479e11f2c331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005985088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2005985088
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3852051105
Short name T917
Test name
Test status
Simulation time 48577087141 ps
CPU time 38.08 seconds
Started Jul 16 04:58:44 PM PDT 24
Finished Jul 16 04:59:23 PM PDT 24
Peak memory 199520 kb
Host smart-94bfa00d-4fd9-46bb-8629-2c88fcbdd9a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852051105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3852051105
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1827415152
Short name T957
Test name
Test status
Simulation time 170484754084 ps
CPU time 914.72 seconds
Started Jul 16 04:58:40 PM PDT 24
Finished Jul 16 05:13:55 PM PDT 24
Peak memory 199760 kb
Host smart-150cc09a-a8a4-4c0d-87ef-c0884a390499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827415152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1827415152
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3562373817
Short name T727
Test name
Test status
Simulation time 4446307557 ps
CPU time 2.93 seconds
Started Jul 16 04:58:40 PM PDT 24
Finished Jul 16 04:58:44 PM PDT 24
Peak memory 198596 kb
Host smart-355a3877-c46f-4c36-8a4e-b3467d8728bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562373817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3562373817
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2489828324
Short name T602
Test name
Test status
Simulation time 140164610991 ps
CPU time 64.87 seconds
Started Jul 16 04:58:41 PM PDT 24
Finished Jul 16 04:59:47 PM PDT 24
Peak memory 200132 kb
Host smart-d70563bf-896a-4b0d-a39e-b236464e9a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489828324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2489828324
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.4074191930
Short name T122
Test name
Test status
Simulation time 20517520708 ps
CPU time 236.67 seconds
Started Jul 16 04:58:41 PM PDT 24
Finished Jul 16 05:02:39 PM PDT 24
Peak memory 199884 kb
Host smart-f3c2be60-516b-4b5a-8300-ba94894138ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074191930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.4074191930
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3195373662
Short name T444
Test name
Test status
Simulation time 6285223336 ps
CPU time 50.79 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 04:59:19 PM PDT 24
Peak memory 197860 kb
Host smart-6238f15c-fd87-4592-8c8c-e0255d4baeb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3195373662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3195373662
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.4105266674
Short name T913
Test name
Test status
Simulation time 197003102074 ps
CPU time 99.17 seconds
Started Jul 16 04:58:40 PM PDT 24
Finished Jul 16 05:00:20 PM PDT 24
Peak memory 199780 kb
Host smart-935ed009-1309-4fb9-bc9f-c139f49256a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105266674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.4105266674
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2828220155
Short name T1016
Test name
Test status
Simulation time 34063370656 ps
CPU time 44.03 seconds
Started Jul 16 04:58:39 PM PDT 24
Finished Jul 16 04:59:24 PM PDT 24
Peak memory 196484 kb
Host smart-ce9ef4d9-9876-438a-b62b-9565fdd45721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828220155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2828220155
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.194145955
Short name T862
Test name
Test status
Simulation time 950355207 ps
CPU time 1.94 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 04:58:30 PM PDT 24
Peak memory 198328 kb
Host smart-424c5144-9d00-4a6e-a9ca-c2b7576a684d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194145955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.194145955
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2473853004
Short name T903
Test name
Test status
Simulation time 636648964 ps
CPU time 1.33 seconds
Started Jul 16 04:58:37 PM PDT 24
Finished Jul 16 04:58:39 PM PDT 24
Peak memory 198984 kb
Host smart-d8c886d9-b2e1-438a-ac69-b49660bf24ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473853004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2473853004
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1565505462
Short name T1163
Test name
Test status
Simulation time 39659880290 ps
CPU time 65.44 seconds
Started Jul 16 04:58:27 PM PDT 24
Finished Jul 16 04:59:34 PM PDT 24
Peak memory 199760 kb
Host smart-1f5a580a-4e92-4d66-9e91-69280044a4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565505462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1565505462
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2940091326
Short name T455
Test name
Test status
Simulation time 39945399 ps
CPU time 0.56 seconds
Started Jul 16 04:58:41 PM PDT 24
Finished Jul 16 04:58:43 PM PDT 24
Peak memory 195508 kb
Host smart-cf906507-b886-408f-af62-f4363e2bd7a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940091326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2940091326
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3719094426
Short name T929
Test name
Test status
Simulation time 94136107927 ps
CPU time 63.51 seconds
Started Jul 16 04:58:40 PM PDT 24
Finished Jul 16 04:59:45 PM PDT 24
Peak memory 199652 kb
Host smart-cbfc9213-d5c9-496d-b01f-a7723881330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719094426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3719094426
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2797104824
Short name T833
Test name
Test status
Simulation time 68966741059 ps
CPU time 27.5 seconds
Started Jul 16 04:58:46 PM PDT 24
Finished Jul 16 04:59:14 PM PDT 24
Peak memory 199448 kb
Host smart-0a379d64-b8ef-4f11-8132-cd537417ccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797104824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2797104824
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3867938817
Short name T515
Test name
Test status
Simulation time 9540171051 ps
CPU time 16.34 seconds
Started Jul 16 04:58:45 PM PDT 24
Finished Jul 16 04:59:02 PM PDT 24
Peak memory 199880 kb
Host smart-7b1f414b-dbc6-4b2c-8c83-93cccbd50755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867938817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3867938817
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2502251455
Short name T1121
Test name
Test status
Simulation time 14540442205 ps
CPU time 30.4 seconds
Started Jul 16 04:58:39 PM PDT 24
Finished Jul 16 04:59:10 PM PDT 24
Peak memory 199824 kb
Host smart-65bb7a70-3e9d-4ac4-aba2-dbec0c7c7402
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502251455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2502251455
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1265065852
Short name T449
Test name
Test status
Simulation time 229414066359 ps
CPU time 261.69 seconds
Started Jul 16 04:58:39 PM PDT 24
Finished Jul 16 05:03:01 PM PDT 24
Peak memory 200084 kb
Host smart-188d3bb6-c9c8-4ca7-a901-8e6627764752
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265065852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1265065852
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.792573649
Short name T23
Test name
Test status
Simulation time 5327044426 ps
CPU time 5.48 seconds
Started Jul 16 04:58:41 PM PDT 24
Finished Jul 16 04:58:48 PM PDT 24
Peak memory 199408 kb
Host smart-b5f98895-2daf-45be-ad95-9e9c8854ad73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792573649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.792573649
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3645888011
Short name T37
Test name
Test status
Simulation time 107612692091 ps
CPU time 159.84 seconds
Started Jul 16 04:58:42 PM PDT 24
Finished Jul 16 05:01:23 PM PDT 24
Peak memory 199716 kb
Host smart-47f180c4-3b4a-4206-8828-6edfea03db46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645888011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3645888011
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2198515768
Short name T1023
Test name
Test status
Simulation time 17978388688 ps
CPU time 448.97 seconds
Started Jul 16 04:58:41 PM PDT 24
Finished Jul 16 05:06:11 PM PDT 24
Peak memory 199780 kb
Host smart-da15c574-0e6c-4639-87dc-3d59006783d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198515768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2198515768
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2940207370
Short name T908
Test name
Test status
Simulation time 5673505405 ps
CPU time 22.84 seconds
Started Jul 16 04:58:41 PM PDT 24
Finished Jul 16 04:59:05 PM PDT 24
Peak memory 198572 kb
Host smart-26a92c0c-691e-4f68-972b-1d4fe670e3ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2940207370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2940207370
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1608837848
Short name T160
Test name
Test status
Simulation time 117748027365 ps
CPU time 51.09 seconds
Started Jul 16 04:58:46 PM PDT 24
Finished Jul 16 04:59:37 PM PDT 24
Peak memory 199768 kb
Host smart-72751e44-6883-4190-97ff-6e4099933157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608837848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1608837848
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.549827349
Short name T265
Test name
Test status
Simulation time 2265765922 ps
CPU time 3.84 seconds
Started Jul 16 04:58:41 PM PDT 24
Finished Jul 16 04:58:46 PM PDT 24
Peak memory 195404 kb
Host smart-8c0f96ec-f551-4260-8e0c-0c13301d8d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549827349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.549827349
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1207042077
Short name T983
Test name
Test status
Simulation time 700613605 ps
CPU time 1.76 seconds
Started Jul 16 04:58:38 PM PDT 24
Finished Jul 16 04:58:41 PM PDT 24
Peak memory 198148 kb
Host smart-7a25b0b3-12a4-4aba-863e-fcc28f4d5f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207042077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1207042077
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.579454915
Short name T460
Test name
Test status
Simulation time 60885347703 ps
CPU time 747.96 seconds
Started Jul 16 04:58:42 PM PDT 24
Finished Jul 16 05:11:11 PM PDT 24
Peak memory 216528 kb
Host smart-a8e901e7-94cc-446e-bca5-94a00ea87f69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579454915 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.579454915
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.971529014
Short name T631
Test name
Test status
Simulation time 408319032 ps
CPU time 1.04 seconds
Started Jul 16 04:58:44 PM PDT 24
Finished Jul 16 04:58:46 PM PDT 24
Peak memory 198588 kb
Host smart-875f41f7-7114-4102-9880-08a52b35103b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971529014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.971529014
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.4059816026
Short name T996
Test name
Test status
Simulation time 52867166844 ps
CPU time 81.17 seconds
Started Jul 16 04:58:40 PM PDT 24
Finished Jul 16 05:00:02 PM PDT 24
Peak memory 199820 kb
Host smart-262a7617-7285-4a0e-8e7e-61dde1fa1b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059816026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.4059816026
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1857637936
Short name T735
Test name
Test status
Simulation time 36226741 ps
CPU time 0.56 seconds
Started Jul 16 04:58:39 PM PDT 24
Finished Jul 16 04:58:40 PM PDT 24
Peak memory 195176 kb
Host smart-23f7655e-afba-4a11-b994-67277cf598bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857637936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1857637936
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.957027298
Short name T817
Test name
Test status
Simulation time 179475093806 ps
CPU time 30.12 seconds
Started Jul 16 04:58:40 PM PDT 24
Finished Jul 16 04:59:11 PM PDT 24
Peak memory 199728 kb
Host smart-7103bf4a-176f-448c-ba86-daa08939cc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957027298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.957027298
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3941198612
Short name T801
Test name
Test status
Simulation time 100827829000 ps
CPU time 153.59 seconds
Started Jul 16 04:58:39 PM PDT 24
Finished Jul 16 05:01:14 PM PDT 24
Peak memory 199736 kb
Host smart-5bc5a201-82ee-4b87-8a5c-f15c2eba64f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941198612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3941198612
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2776475658
Short name T77
Test name
Test status
Simulation time 17452121117 ps
CPU time 8.27 seconds
Started Jul 16 04:58:44 PM PDT 24
Finished Jul 16 04:58:53 PM PDT 24
Peak memory 199400 kb
Host smart-60f26808-43d8-44a0-ab52-10c0face0a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776475658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2776475658
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.823917107
Short name T1025
Test name
Test status
Simulation time 48349700604 ps
CPU time 45.49 seconds
Started Jul 16 04:58:45 PM PDT 24
Finished Jul 16 04:59:31 PM PDT 24
Peak memory 199756 kb
Host smart-60932548-08e5-43aa-98f4-5c3b4ed32411
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823917107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.823917107
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2624308438
Short name T390
Test name
Test status
Simulation time 302798157434 ps
CPU time 388.37 seconds
Started Jul 16 04:58:42 PM PDT 24
Finished Jul 16 05:05:11 PM PDT 24
Peak memory 199700 kb
Host smart-afdaa9d0-e9a1-437b-b215-3f5ee9e521f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624308438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2624308438
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2568049206
Short name T441
Test name
Test status
Simulation time 2320355244 ps
CPU time 1.82 seconds
Started Jul 16 04:58:38 PM PDT 24
Finished Jul 16 04:58:40 PM PDT 24
Peak memory 199832 kb
Host smart-2ce1b72a-3794-4d54-9564-efea598239f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568049206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2568049206
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1806240719
Short name T283
Test name
Test status
Simulation time 34884309322 ps
CPU time 27.82 seconds
Started Jul 16 04:58:38 PM PDT 24
Finished Jul 16 04:59:07 PM PDT 24
Peak memory 200320 kb
Host smart-7ee92cdc-4a98-4835-801b-8e57a5f7eb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806240719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1806240719
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.929751872
Short name T963
Test name
Test status
Simulation time 22527205402 ps
CPU time 60.28 seconds
Started Jul 16 04:58:39 PM PDT 24
Finished Jul 16 04:59:40 PM PDT 24
Peak memory 199836 kb
Host smart-79cf99d1-38cd-4759-a1cd-70f5ac5435c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929751872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.929751872
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1558135699
Short name T645
Test name
Test status
Simulation time 3589230189 ps
CPU time 25.5 seconds
Started Jul 16 04:58:43 PM PDT 24
Finished Jul 16 04:59:09 PM PDT 24
Peak memory 197952 kb
Host smart-eec1e675-6025-4803-8baf-7ea957721ecf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558135699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1558135699
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1749838873
Short name T435
Test name
Test status
Simulation time 6819342574 ps
CPU time 10.37 seconds
Started Jul 16 04:58:39 PM PDT 24
Finished Jul 16 04:58:50 PM PDT 24
Peak memory 198940 kb
Host smart-3d0f3475-1278-4c7f-bd03-9d05a6195a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749838873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1749838873
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1666372837
Short name T924
Test name
Test status
Simulation time 35742998907 ps
CPU time 47.3 seconds
Started Jul 16 04:58:42 PM PDT 24
Finished Jul 16 04:59:30 PM PDT 24
Peak memory 195568 kb
Host smart-90359baa-d608-46c1-9029-f961ebe96e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666372837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1666372837
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.974207989
Short name T619
Test name
Test status
Simulation time 457710221 ps
CPU time 1.32 seconds
Started Jul 16 04:58:37 PM PDT 24
Finished Jul 16 04:58:39 PM PDT 24
Peak memory 198220 kb
Host smart-21e41646-3ab4-4de0-890e-3bab03e5a47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974207989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.974207989
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.4068677571
Short name T226
Test name
Test status
Simulation time 468664820645 ps
CPU time 360.15 seconds
Started Jul 16 04:58:39 PM PDT 24
Finished Jul 16 05:04:40 PM PDT 24
Peak memory 199724 kb
Host smart-b362611e-70bd-4ee1-8299-698b6ee2f2fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068677571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.4068677571
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3745451665
Short name T459
Test name
Test status
Simulation time 780045224861 ps
CPU time 868.92 seconds
Started Jul 16 04:58:42 PM PDT 24
Finished Jul 16 05:13:12 PM PDT 24
Peak memory 224772 kb
Host smart-757376b0-3956-4f15-a5fb-33153ad5037b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745451665 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3745451665
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1839048143
Short name T302
Test name
Test status
Simulation time 1138139266 ps
CPU time 1.66 seconds
Started Jul 16 04:58:40 PM PDT 24
Finished Jul 16 04:58:42 PM PDT 24
Peak memory 198748 kb
Host smart-fa690036-c387-413d-97c2-e95666731598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839048143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1839048143
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2116716118
Short name T707
Test name
Test status
Simulation time 268913104130 ps
CPU time 99.66 seconds
Started Jul 16 04:58:44 PM PDT 24
Finished Jul 16 05:00:25 PM PDT 24
Peak memory 199732 kb
Host smart-b11b0c82-6aae-4db4-8e48-8795d0f7ca18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116716118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2116716118
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3075334421
Short name T1133
Test name
Test status
Simulation time 12886710 ps
CPU time 0.58 seconds
Started Jul 16 04:58:51 PM PDT 24
Finished Jul 16 04:58:52 PM PDT 24
Peak memory 195100 kb
Host smart-0a62deff-3de7-4596-b0dc-20766d2dfc1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075334421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3075334421
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.272578195
Short name T158
Test name
Test status
Simulation time 206822397009 ps
CPU time 93.35 seconds
Started Jul 16 04:58:41 PM PDT 24
Finished Jul 16 05:00:15 PM PDT 24
Peak memory 199912 kb
Host smart-93473e60-fdfa-409d-adb6-9ea78ae1f0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272578195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.272578195
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.935443694
Short name T921
Test name
Test status
Simulation time 147287987706 ps
CPU time 50.58 seconds
Started Jul 16 04:59:18 PM PDT 24
Finished Jul 16 05:00:10 PM PDT 24
Peak memory 199548 kb
Host smart-a7364279-da33-46cd-a93b-5ce802cc9dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935443694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.935443694
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2964293945
Short name T1122
Test name
Test status
Simulation time 19299870570 ps
CPU time 32.49 seconds
Started Jul 16 04:58:46 PM PDT 24
Finished Jul 16 04:59:19 PM PDT 24
Peak memory 199904 kb
Host smart-37b2405c-1b43-4b47-ba36-e173f3c81262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964293945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2964293945
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.392735446
Short name T770
Test name
Test status
Simulation time 66122602209 ps
CPU time 24.13 seconds
Started Jul 16 04:58:42 PM PDT 24
Finished Jul 16 04:59:07 PM PDT 24
Peak memory 199948 kb
Host smart-f567574e-6680-434a-ac81-d23f7e6670d3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392735446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.392735446
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.502968361
Short name T423
Test name
Test status
Simulation time 120937532522 ps
CPU time 734.9 seconds
Started Jul 16 04:58:52 PM PDT 24
Finished Jul 16 05:11:08 PM PDT 24
Peak memory 199840 kb
Host smart-582d0922-7615-4c71-8259-3ee2bc2a260d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502968361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.502968361
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3220054289
Short name T1004
Test name
Test status
Simulation time 319773487 ps
CPU time 0.92 seconds
Started Jul 16 04:58:50 PM PDT 24
Finished Jul 16 04:58:52 PM PDT 24
Peak memory 198268 kb
Host smart-d54b7999-5c9f-4729-b702-b4b67fde94bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220054289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3220054289
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2627320263
Short name T377
Test name
Test status
Simulation time 131836710692 ps
CPU time 266.67 seconds
Started Jul 16 04:58:45 PM PDT 24
Finished Jul 16 05:03:12 PM PDT 24
Peak memory 208192 kb
Host smart-641a14ff-c849-469f-ab15-12352a4b2404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627320263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2627320263
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.620981229
Short name T1151
Test name
Test status
Simulation time 12077443322 ps
CPU time 242.85 seconds
Started Jul 16 04:58:50 PM PDT 24
Finished Jul 16 05:02:54 PM PDT 24
Peak memory 199876 kb
Host smart-5e40cca9-2e87-467a-a92e-2f3f85af2739
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=620981229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.620981229
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1591433072
Short name T413
Test name
Test status
Simulation time 6739280052 ps
CPU time 66.4 seconds
Started Jul 16 04:58:42 PM PDT 24
Finished Jul 16 04:59:49 PM PDT 24
Peak memory 199252 kb
Host smart-01899137-3a51-4b5b-862c-b2b8df8e365b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591433072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1591433072
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3606630610
Short name T328
Test name
Test status
Simulation time 13718332855 ps
CPU time 20.53 seconds
Started Jul 16 04:58:53 PM PDT 24
Finished Jul 16 04:59:14 PM PDT 24
Peak memory 198896 kb
Host smart-60f4a4ab-9a3d-42b8-b787-b6507c07ceb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606630610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3606630610
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1202148161
Short name T347
Test name
Test status
Simulation time 3792951030 ps
CPU time 5.77 seconds
Started Jul 16 04:58:52 PM PDT 24
Finished Jul 16 04:58:59 PM PDT 24
Peak memory 196700 kb
Host smart-d4640871-f167-44a6-b22f-a1e64b0aa31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202148161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1202148161
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2694123877
Short name T807
Test name
Test status
Simulation time 6196126188 ps
CPU time 19.81 seconds
Started Jul 16 04:58:41 PM PDT 24
Finished Jul 16 04:59:02 PM PDT 24
Peak memory 199780 kb
Host smart-3e36d57f-dcc6-4fe4-9002-5fe6a92452fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694123877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2694123877
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2992012219
Short name T500
Test name
Test status
Simulation time 358766983272 ps
CPU time 83.8 seconds
Started Jul 16 04:58:55 PM PDT 24
Finished Jul 16 05:00:20 PM PDT 24
Peak memory 199676 kb
Host smart-719a8971-a235-43b4-9d71-efc93ec25e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992012219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2992012219
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1217372077
Short name T540
Test name
Test status
Simulation time 10367058385 ps
CPU time 128.13 seconds
Started Jul 16 04:58:51 PM PDT 24
Finished Jul 16 05:01:00 PM PDT 24
Peak memory 209444 kb
Host smart-35e9c588-e9e8-41b6-9b60-02808a1a14bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217372077 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1217372077
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.158638437
Short name T626
Test name
Test status
Simulation time 4209396863 ps
CPU time 1.72 seconds
Started Jul 16 04:58:57 PM PDT 24
Finished Jul 16 04:59:00 PM PDT 24
Peak memory 198332 kb
Host smart-4a148205-22f8-4562-9fa3-40570652724a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158638437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.158638437
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.337188829
Short name T603
Test name
Test status
Simulation time 74988122654 ps
CPU time 36.94 seconds
Started Jul 16 04:58:44 PM PDT 24
Finished Jul 16 04:59:22 PM PDT 24
Peak memory 199700 kb
Host smart-b394126d-0e51-494b-98fd-5e7c944cc89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337188829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.337188829
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3234481185
Short name T592
Test name
Test status
Simulation time 11319939 ps
CPU time 0.57 seconds
Started Jul 16 04:58:57 PM PDT 24
Finished Jul 16 04:58:58 PM PDT 24
Peak memory 195044 kb
Host smart-b61f6000-2792-4ddc-b501-8192480cbaa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234481185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3234481185
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2601337937
Short name T563
Test name
Test status
Simulation time 36933543264 ps
CPU time 53.18 seconds
Started Jul 16 04:58:55 PM PDT 24
Finished Jul 16 04:59:48 PM PDT 24
Peak memory 199760 kb
Host smart-ae2e0959-e575-475a-b1af-f056d783da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601337937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2601337937
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2444022878
Short name T577
Test name
Test status
Simulation time 147615620176 ps
CPU time 28.55 seconds
Started Jul 16 04:58:59 PM PDT 24
Finished Jul 16 04:59:29 PM PDT 24
Peak memory 199764 kb
Host smart-72f128d6-d5f9-43c4-9502-207b21707a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444022878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2444022878
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1603254038
Short name T676
Test name
Test status
Simulation time 157068853741 ps
CPU time 42.65 seconds
Started Jul 16 04:58:51 PM PDT 24
Finished Jul 16 04:59:35 PM PDT 24
Peak memory 199812 kb
Host smart-4154439e-25fb-4ace-afff-172085a90fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603254038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1603254038
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.247671170
Short name T405
Test name
Test status
Simulation time 41381484232 ps
CPU time 97.41 seconds
Started Jul 16 04:58:53 PM PDT 24
Finished Jul 16 05:00:31 PM PDT 24
Peak memory 199760 kb
Host smart-fa0e6409-bcb4-476b-8dce-c0c524c8b4ba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247671170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.247671170
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3736288209
Short name T842
Test name
Test status
Simulation time 161520701278 ps
CPU time 1556.92 seconds
Started Jul 16 04:58:58 PM PDT 24
Finished Jul 16 05:24:56 PM PDT 24
Peak memory 199688 kb
Host smart-891d757d-69f8-43ba-a0ae-48b521551c3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3736288209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3736288209
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.4215110409
Short name T462
Test name
Test status
Simulation time 13069881736 ps
CPU time 7.79 seconds
Started Jul 16 04:58:51 PM PDT 24
Finished Jul 16 04:58:59 PM PDT 24
Peak memory 199692 kb
Host smart-2dd06c63-60c2-4b62-8f1c-d5888575a758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215110409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.4215110409
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2368461987
Short name T790
Test name
Test status
Simulation time 37781630005 ps
CPU time 17.67 seconds
Started Jul 16 04:58:55 PM PDT 24
Finished Jul 16 04:59:14 PM PDT 24
Peak memory 198916 kb
Host smart-f134f1ea-cfb9-46b9-9f76-7ba0c6998c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368461987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2368461987
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.340158444
Short name T479
Test name
Test status
Simulation time 10189544134 ps
CPU time 588.71 seconds
Started Jul 16 04:58:53 PM PDT 24
Finished Jul 16 05:08:42 PM PDT 24
Peak memory 199684 kb
Host smart-4c9219eb-5014-46c1-a23b-705ac309a0a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340158444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.340158444
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3774987625
Short name T969
Test name
Test status
Simulation time 2850114637 ps
CPU time 16.35 seconds
Started Jul 16 04:58:50 PM PDT 24
Finished Jul 16 04:59:07 PM PDT 24
Peak memory 197920 kb
Host smart-cba5e193-ec97-409f-a721-1f64cf675e8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3774987625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3774987625
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1190365132
Short name T965
Test name
Test status
Simulation time 121305490676 ps
CPU time 168.06 seconds
Started Jul 16 04:58:53 PM PDT 24
Finished Jul 16 05:01:42 PM PDT 24
Peak memory 199696 kb
Host smart-0f0e0b5c-f140-4cf9-8880-6933b93cb521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190365132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1190365132
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1210354085
Short name T628
Test name
Test status
Simulation time 1855048532 ps
CPU time 2.29 seconds
Started Jul 16 04:58:49 PM PDT 24
Finished Jul 16 04:58:52 PM PDT 24
Peak memory 195244 kb
Host smart-475cc84b-6a4a-4a07-8e3f-8a2b1c9c56bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210354085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1210354085
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.529112620
Short name T292
Test name
Test status
Simulation time 516955668 ps
CPU time 1.23 seconds
Started Jul 16 04:58:55 PM PDT 24
Finished Jul 16 04:58:57 PM PDT 24
Peak memory 198144 kb
Host smart-28b88344-1988-4360-bfba-118c0e794651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529112620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.529112620
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.4258816230
Short name T785
Test name
Test status
Simulation time 91024605194 ps
CPU time 200.61 seconds
Started Jul 16 04:58:50 PM PDT 24
Finished Jul 16 05:02:11 PM PDT 24
Peak memory 199736 kb
Host smart-2c35541f-67fd-42d8-8ff3-3408c0e68a0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258816230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.4258816230
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2920450569
Short name T1056
Test name
Test status
Simulation time 116914579411 ps
CPU time 985.97 seconds
Started Jul 16 04:58:51 PM PDT 24
Finished Jul 16 05:15:17 PM PDT 24
Peak memory 232912 kb
Host smart-0d7d4e5a-722c-44cb-a45e-a029e9a7327b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920450569 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2920450569
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2252951222
Short name T667
Test name
Test status
Simulation time 1965167645 ps
CPU time 2.49 seconds
Started Jul 16 04:58:50 PM PDT 24
Finished Jul 16 04:58:53 PM PDT 24
Peak memory 198420 kb
Host smart-718b996b-5339-4da2-bb67-58f9ba52cff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252951222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2252951222
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2379599311
Short name T876
Test name
Test status
Simulation time 149438907295 ps
CPU time 72.21 seconds
Started Jul 16 04:58:51 PM PDT 24
Finished Jul 16 05:00:04 PM PDT 24
Peak memory 199772 kb
Host smart-dc447367-f735-4fb8-9475-018c54c75f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379599311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2379599311
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.4022460845
Short name T897
Test name
Test status
Simulation time 16261886 ps
CPU time 0.58 seconds
Started Jul 16 04:58:52 PM PDT 24
Finished Jul 16 04:58:53 PM PDT 24
Peak memory 194128 kb
Host smart-809d0418-0040-4910-9f8d-8ff0a8a8c47c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022460845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.4022460845
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.4029678120
Short name T637
Test name
Test status
Simulation time 145422042976 ps
CPU time 103.89 seconds
Started Jul 16 04:58:50 PM PDT 24
Finished Jul 16 05:00:34 PM PDT 24
Peak memory 199812 kb
Host smart-dfe616a5-330e-4dba-b06e-2318e4ac67be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029678120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.4029678120
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1836131426
Short name T172
Test name
Test status
Simulation time 121930680176 ps
CPU time 196.5 seconds
Started Jul 16 04:58:52 PM PDT 24
Finished Jul 16 05:02:09 PM PDT 24
Peak memory 199736 kb
Host smart-32b7dcbc-0aa8-4326-b643-174c3f69ea27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836131426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1836131426
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3820749134
Short name T193
Test name
Test status
Simulation time 12004477543 ps
CPU time 12.93 seconds
Started Jul 16 04:58:52 PM PDT 24
Finished Jul 16 04:59:05 PM PDT 24
Peak memory 199776 kb
Host smart-07d6bb07-409f-4e38-8fe3-1ea79cebbbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820749134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3820749134
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2968152059
Short name T13
Test name
Test status
Simulation time 168944341686 ps
CPU time 256.05 seconds
Started Jul 16 04:58:59 PM PDT 24
Finished Jul 16 05:03:17 PM PDT 24
Peak memory 199712 kb
Host smart-c5505d40-8c55-4eac-b0bf-e723ee0279f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968152059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2968152059
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.849666292
Short name T836
Test name
Test status
Simulation time 76436149576 ps
CPU time 637.01 seconds
Started Jul 16 04:58:55 PM PDT 24
Finished Jul 16 05:09:32 PM PDT 24
Peak memory 199764 kb
Host smart-dc807041-5e89-4342-ac1a-e2d664f9ddae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=849666292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.849666292
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.395464788
Short name T1058
Test name
Test status
Simulation time 6418817956 ps
CPU time 3.78 seconds
Started Jul 16 04:58:51 PM PDT 24
Finished Jul 16 04:58:55 PM PDT 24
Peak memory 199640 kb
Host smart-aa84846e-e8ed-4635-af5c-0320cc597dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395464788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.395464788
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3658056924
Short name T312
Test name
Test status
Simulation time 10300917549 ps
CPU time 15.07 seconds
Started Jul 16 04:58:50 PM PDT 24
Finished Jul 16 04:59:06 PM PDT 24
Peak memory 194512 kb
Host smart-b89bbac9-ad5f-428e-bc98-d18907e057a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658056924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3658056924
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3953736343
Short name T858
Test name
Test status
Simulation time 19312753330 ps
CPU time 101.86 seconds
Started Jul 16 04:58:54 PM PDT 24
Finished Jul 16 05:00:36 PM PDT 24
Peak memory 199780 kb
Host smart-114d1c5d-68a4-4891-8f98-3df817ecd369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3953736343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3953736343
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1345792662
Short name T634
Test name
Test status
Simulation time 3516422942 ps
CPU time 6.77 seconds
Started Jul 16 04:58:59 PM PDT 24
Finished Jul 16 04:59:07 PM PDT 24
Peak memory 198044 kb
Host smart-17ab5cd4-9f15-4d40-8640-ec368dcc9147
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345792662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1345792662
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.355942250
Short name T713
Test name
Test status
Simulation time 33668497831 ps
CPU time 47.54 seconds
Started Jul 16 04:58:52 PM PDT 24
Finished Jul 16 04:59:40 PM PDT 24
Peak memory 199812 kb
Host smart-3dd704d1-b019-40cf-925a-93738343bc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355942250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.355942250
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2775012672
Short name T643
Test name
Test status
Simulation time 3806150098 ps
CPU time 2.18 seconds
Started Jul 16 04:58:59 PM PDT 24
Finished Jul 16 04:59:03 PM PDT 24
Peak memory 196372 kb
Host smart-76accd61-b0ae-4153-9a8b-1fb379494b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775012672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2775012672
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1706075188
Short name T276
Test name
Test status
Simulation time 245641808 ps
CPU time 1.47 seconds
Started Jul 16 04:58:53 PM PDT 24
Finished Jul 16 04:58:56 PM PDT 24
Peak memory 198456 kb
Host smart-f39e92c5-957d-4179-8336-10f43ca4f0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706075188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1706075188
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.4172842766
Short name T946
Test name
Test status
Simulation time 402003977264 ps
CPU time 490.32 seconds
Started Jul 16 04:58:54 PM PDT 24
Finished Jul 16 05:07:05 PM PDT 24
Peak memory 208148 kb
Host smart-c090bf65-f0bb-4fd4-955c-61880c5108b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172842766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4172842766
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2421518430
Short name T345
Test name
Test status
Simulation time 947260369 ps
CPU time 1.33 seconds
Started Jul 16 04:58:59 PM PDT 24
Finished Jul 16 04:59:02 PM PDT 24
Peak memory 197856 kb
Host smart-23c4c8e4-3c4b-46cf-a5f6-024d38b50a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421518430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2421518430
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1496873839
Short name T274
Test name
Test status
Simulation time 73967938637 ps
CPU time 67.22 seconds
Started Jul 16 04:58:54 PM PDT 24
Finished Jul 16 05:00:02 PM PDT 24
Peak memory 199800 kb
Host smart-a14970b0-d8ef-433e-bf13-3fef4dc223ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496873839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1496873839
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3248900488
Short name T697
Test name
Test status
Simulation time 11402280 ps
CPU time 0.61 seconds
Started Jul 16 04:59:06 PM PDT 24
Finished Jul 16 04:59:08 PM PDT 24
Peak memory 194808 kb
Host smart-12981d1f-cb38-4605-a7d3-d26699157210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248900488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3248900488
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1925594780
Short name T138
Test name
Test status
Simulation time 73761089601 ps
CPU time 37.12 seconds
Started Jul 16 04:58:56 PM PDT 24
Finished Jul 16 04:59:34 PM PDT 24
Peak memory 199816 kb
Host smart-8fe28b34-ca4a-4be1-a900-9190c35ba213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925594780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1925594780
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2954197140
Short name T181
Test name
Test status
Simulation time 15053745822 ps
CPU time 14.21 seconds
Started Jul 16 04:58:59 PM PDT 24
Finished Jul 16 04:59:14 PM PDT 24
Peak memory 199680 kb
Host smart-39a20239-a417-4e24-9853-f21565c8e08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954197140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2954197140
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2001919647
Short name T213
Test name
Test status
Simulation time 24999195189 ps
CPU time 41.13 seconds
Started Jul 16 04:58:57 PM PDT 24
Finished Jul 16 04:59:39 PM PDT 24
Peak memory 199716 kb
Host smart-776204f8-3f59-4c92-a170-946dc14df415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001919647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2001919647
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1707828396
Short name T951
Test name
Test status
Simulation time 38655509014 ps
CPU time 11.15 seconds
Started Jul 16 04:58:59 PM PDT 24
Finished Jul 16 04:59:12 PM PDT 24
Peak memory 199548 kb
Host smart-96eedf35-8673-49c9-b113-0c24f4fae5c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707828396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1707828396
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.567251005
Short name T1046
Test name
Test status
Simulation time 179971513679 ps
CPU time 644.59 seconds
Started Jul 16 04:59:00 PM PDT 24
Finished Jul 16 05:09:45 PM PDT 24
Peak memory 199724 kb
Host smart-71b978a2-c26d-488c-9222-390f7dc05dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567251005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.567251005
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3179843023
Short name T584
Test name
Test status
Simulation time 986641111 ps
CPU time 2.31 seconds
Started Jul 16 04:58:53 PM PDT 24
Finished Jul 16 04:58:56 PM PDT 24
Peak memory 195268 kb
Host smart-d7138808-e934-4ed2-992d-c5364e51af19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179843023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3179843023
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2237464645
Short name T541
Test name
Test status
Simulation time 132572300744 ps
CPU time 201.16 seconds
Started Jul 16 04:58:59 PM PDT 24
Finished Jul 16 05:02:22 PM PDT 24
Peak memory 199904 kb
Host smart-89ebc194-b918-4537-89ee-499883c21796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237464645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2237464645
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3267390920
Short name T486
Test name
Test status
Simulation time 21256103124 ps
CPU time 221.76 seconds
Started Jul 16 04:58:56 PM PDT 24
Finished Jul 16 05:02:38 PM PDT 24
Peak memory 199700 kb
Host smart-51683b23-9306-4b34-a36c-74a34f9f554b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267390920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3267390920
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1204978225
Short name T17
Test name
Test status
Simulation time 3169907649 ps
CPU time 11.85 seconds
Started Jul 16 04:58:54 PM PDT 24
Finished Jul 16 04:59:06 PM PDT 24
Peak memory 197912 kb
Host smart-ed86b748-0eed-41c5-ab79-b35ad5e08218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1204978225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1204978225
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3137842248
Short name T937
Test name
Test status
Simulation time 109328968980 ps
CPU time 197.05 seconds
Started Jul 16 04:58:56 PM PDT 24
Finished Jul 16 05:02:13 PM PDT 24
Peak memory 199816 kb
Host smart-037e20ff-3a4a-48e6-8926-bef60847b83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137842248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3137842248
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.780510348
Short name T543
Test name
Test status
Simulation time 2521890248 ps
CPU time 1.98 seconds
Started Jul 16 04:58:53 PM PDT 24
Finished Jul 16 04:58:56 PM PDT 24
Peak memory 195796 kb
Host smart-2676f060-e77c-4835-a334-4b0d40288d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780510348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.780510348
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3085515692
Short name T758
Test name
Test status
Simulation time 769007311 ps
CPU time 1.27 seconds
Started Jul 16 04:58:51 PM PDT 24
Finished Jul 16 04:58:53 PM PDT 24
Peak memory 198456 kb
Host smart-59f08a01-413d-4115-b17a-e8b7240c2da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085515692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3085515692
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1899099512
Short name T832
Test name
Test status
Simulation time 81355739851 ps
CPU time 501.3 seconds
Started Jul 16 04:59:09 PM PDT 24
Finished Jul 16 05:07:30 PM PDT 24
Peak memory 216320 kb
Host smart-d8d07b05-5010-4afb-8e1c-a54b23ed92f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899099512 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1899099512
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1370771086
Short name T510
Test name
Test status
Simulation time 1020737876 ps
CPU time 3.55 seconds
Started Jul 16 04:58:57 PM PDT 24
Finished Jul 16 04:59:01 PM PDT 24
Peak memory 199044 kb
Host smart-683d1b30-546e-4c81-883b-9a15d88f01d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370771086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1370771086
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3606048409
Short name T291
Test name
Test status
Simulation time 48712489987 ps
CPU time 29.6 seconds
Started Jul 16 04:58:54 PM PDT 24
Finished Jul 16 04:59:24 PM PDT 24
Peak memory 199808 kb
Host smart-52d47e29-71d9-4ec6-97ec-f4d541b83cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606048409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3606048409
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1861819512
Short name T1152
Test name
Test status
Simulation time 32122875 ps
CPU time 0.59 seconds
Started Jul 16 04:59:04 PM PDT 24
Finished Jul 16 04:59:04 PM PDT 24
Peak memory 195520 kb
Host smart-3e03b6b7-d9b0-4fee-ab89-82fadbb1b1f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861819512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1861819512
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3875728909
Short name T907
Test name
Test status
Simulation time 90384857717 ps
CPU time 129.85 seconds
Started Jul 16 04:59:04 PM PDT 24
Finished Jul 16 05:01:14 PM PDT 24
Peak memory 199776 kb
Host smart-68f584da-d1f1-4218-81c5-5cb07e3e4d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875728909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3875728909
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2884438611
Short name T297
Test name
Test status
Simulation time 28349424208 ps
CPU time 103.93 seconds
Started Jul 16 04:59:07 PM PDT 24
Finished Jul 16 05:00:52 PM PDT 24
Peak memory 199824 kb
Host smart-ee8710d3-14ec-4e6c-8f30-512915fd45a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884438611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2884438611
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2119264073
Short name T565
Test name
Test status
Simulation time 29710633730 ps
CPU time 42.63 seconds
Started Jul 16 04:59:06 PM PDT 24
Finished Jul 16 04:59:49 PM PDT 24
Peak memory 199776 kb
Host smart-127e07d6-b1ac-4f88-a77d-ca72fc624dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119264073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2119264073
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3699522035
Short name T468
Test name
Test status
Simulation time 49542775550 ps
CPU time 85.79 seconds
Started Jul 16 04:59:05 PM PDT 24
Finished Jul 16 05:00:32 PM PDT 24
Peak memory 199764 kb
Host smart-6870720b-5d98-48c1-ac84-bca12d4e8960
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699522035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3699522035
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2270498903
Short name T671
Test name
Test status
Simulation time 71726065960 ps
CPU time 327.38 seconds
Started Jul 16 04:59:04 PM PDT 24
Finished Jul 16 05:04:33 PM PDT 24
Peak memory 199692 kb
Host smart-4a5620cb-bcbf-4cb1-8b84-1df87f988b26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270498903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2270498903
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.961762770
Short name T1043
Test name
Test status
Simulation time 11131932815 ps
CPU time 21.13 seconds
Started Jul 16 04:59:04 PM PDT 24
Finished Jul 16 04:59:26 PM PDT 24
Peak memory 199896 kb
Host smart-355589c5-a133-450e-a0cb-99b16701e277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961762770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.961762770
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.249646272
Short name T385
Test name
Test status
Simulation time 119511852703 ps
CPU time 23.88 seconds
Started Jul 16 04:59:07 PM PDT 24
Finished Jul 16 04:59:32 PM PDT 24
Peak memory 199920 kb
Host smart-e9d72b3e-17e6-4702-a201-e470063a2f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249646272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.249646272
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1254097752
Short name T320
Test name
Test status
Simulation time 17308004118 ps
CPU time 402.09 seconds
Started Jul 16 04:59:02 PM PDT 24
Finished Jul 16 05:05:45 PM PDT 24
Peak memory 199700 kb
Host smart-ac631741-1434-4909-8ebc-c267ca9d309b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254097752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1254097752
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.4198167260
Short name T332
Test name
Test status
Simulation time 2408301225 ps
CPU time 4.29 seconds
Started Jul 16 04:59:06 PM PDT 24
Finished Jul 16 04:59:11 PM PDT 24
Peak memory 198396 kb
Host smart-2f3437f6-0a1d-437d-b1f0-03a5a21dfea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4198167260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.4198167260
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2060385579
Short name T80
Test name
Test status
Simulation time 73847224010 ps
CPU time 27.34 seconds
Started Jul 16 04:59:06 PM PDT 24
Finished Jul 16 04:59:35 PM PDT 24
Peak memory 199716 kb
Host smart-d95e9a38-676c-493b-adc1-b4628238b1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060385579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2060385579
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3816986722
Short name T1143
Test name
Test status
Simulation time 3183492386 ps
CPU time 4.98 seconds
Started Jul 16 04:59:07 PM PDT 24
Finished Jul 16 04:59:13 PM PDT 24
Peak memory 196236 kb
Host smart-cb2f51d1-7dbd-475a-a976-dfbd7601c55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816986722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3816986722
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.514738953
Short name T705
Test name
Test status
Simulation time 889449737 ps
CPU time 2.76 seconds
Started Jul 16 04:59:04 PM PDT 24
Finished Jul 16 04:59:07 PM PDT 24
Peak memory 199328 kb
Host smart-23b27dda-21cb-4eaf-adb8-560591461ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514738953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.514738953
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.835449696
Short name T784
Test name
Test status
Simulation time 47321684645 ps
CPU time 52.09 seconds
Started Jul 16 04:59:22 PM PDT 24
Finished Jul 16 05:00:15 PM PDT 24
Peak memory 199784 kb
Host smart-8ab2570c-5ac9-4869-9257-135682e3b4eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835449696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.835449696
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2725794274
Short name T33
Test name
Test status
Simulation time 61647336322 ps
CPU time 714.1 seconds
Started Jul 16 04:59:07 PM PDT 24
Finished Jul 16 05:11:02 PM PDT 24
Peak memory 216304 kb
Host smart-5482e19d-39c7-4c92-b46f-c837411eca83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725794274 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2725794274
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1984837170
Short name T1042
Test name
Test status
Simulation time 1919571949 ps
CPU time 2.31 seconds
Started Jul 16 04:59:05 PM PDT 24
Finished Jul 16 04:59:08 PM PDT 24
Peak memory 197628 kb
Host smart-39290af3-e1d9-47f4-99ac-8d691cfce47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984837170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1984837170
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1263715629
Short name T548
Test name
Test status
Simulation time 24166387991 ps
CPU time 9.77 seconds
Started Jul 16 04:59:04 PM PDT 24
Finished Jul 16 04:59:14 PM PDT 24
Peak memory 199556 kb
Host smart-7a096fcf-4d3b-46c1-8485-daa1e969a5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263715629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1263715629
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.938730789
Short name T681
Test name
Test status
Simulation time 14034500 ps
CPU time 0.59 seconds
Started Jul 16 04:56:33 PM PDT 24
Finished Jul 16 04:56:36 PM PDT 24
Peak memory 195124 kb
Host smart-e9c2ca93-330c-4d8d-a4d4-0c9139f6a630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938730789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.938730789
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2003920422
Short name T397
Test name
Test status
Simulation time 25867773385 ps
CPU time 35.17 seconds
Started Jul 16 04:56:39 PM PDT 24
Finished Jul 16 04:57:15 PM PDT 24
Peak memory 199940 kb
Host smart-454bf812-c1d5-4a15-b825-db309c5cf60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003920422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2003920422
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1079354277
Short name T512
Test name
Test status
Simulation time 40482033157 ps
CPU time 30.79 seconds
Started Jul 16 04:56:32 PM PDT 24
Finished Jul 16 04:57:04 PM PDT 24
Peak memory 199716 kb
Host smart-cf8a6a6a-1830-4eb2-bc8d-408fb7f9a8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079354277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1079354277
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1396527486
Short name T199
Test name
Test status
Simulation time 28219292349 ps
CPU time 66.88 seconds
Started Jul 16 04:56:35 PM PDT 24
Finished Jul 16 04:57:43 PM PDT 24
Peak memory 199728 kb
Host smart-f891e753-b88c-470b-90f7-ca65a6582897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396527486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1396527486
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.703343878
Short name T421
Test name
Test status
Simulation time 3966273834 ps
CPU time 2.54 seconds
Started Jul 16 04:56:32 PM PDT 24
Finished Jul 16 04:56:37 PM PDT 24
Peak memory 195660 kb
Host smart-d4d964f9-3b87-4658-9c82-24492af73498
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703343878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.703343878
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.947374737
Short name T943
Test name
Test status
Simulation time 124920579922 ps
CPU time 385.2 seconds
Started Jul 16 04:56:39 PM PDT 24
Finished Jul 16 05:03:05 PM PDT 24
Peak memory 199652 kb
Host smart-0a6ea63f-3e2f-485b-a061-a56cf3764a95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947374737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.947374737
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3887599393
Short name T935
Test name
Test status
Simulation time 4657989330 ps
CPU time 8.34 seconds
Started Jul 16 04:56:34 PM PDT 24
Finished Jul 16 04:56:44 PM PDT 24
Peak memory 199440 kb
Host smart-3cf68730-96be-4459-902b-fc144b114cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887599393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3887599393
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.700704989
Short name T879
Test name
Test status
Simulation time 58523807066 ps
CPU time 26.83 seconds
Started Jul 16 04:56:42 PM PDT 24
Finished Jul 16 04:57:09 PM PDT 24
Peak memory 199996 kb
Host smart-fb7d2d2a-d53a-4920-a6c7-ec50bed79449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700704989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.700704989
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3114430811
Short name T992
Test name
Test status
Simulation time 10975197925 ps
CPU time 96.43 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 04:58:22 PM PDT 24
Peak memory 199840 kb
Host smart-b004a1fe-ef10-4bad-a574-8eaef5914dc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3114430811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3114430811
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1287967861
Short name T344
Test name
Test status
Simulation time 4207949325 ps
CPU time 9.22 seconds
Started Jul 16 04:56:33 PM PDT 24
Finished Jul 16 04:56:44 PM PDT 24
Peak memory 197916 kb
Host smart-753736f4-c57e-4c70-b978-ee309301b064
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287967861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1287967861
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1551674806
Short name T576
Test name
Test status
Simulation time 68600164372 ps
CPU time 29.27 seconds
Started Jul 16 04:56:35 PM PDT 24
Finished Jul 16 04:57:06 PM PDT 24
Peak memory 199804 kb
Host smart-2b5375ae-7560-4368-99ea-cc15cc983a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551674806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1551674806
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.4030452134
Short name T1068
Test name
Test status
Simulation time 3613510030 ps
CPU time 2.28 seconds
Started Jul 16 04:56:32 PM PDT 24
Finished Jul 16 04:56:36 PM PDT 24
Peak memory 196224 kb
Host smart-c7e6bbd9-5dd6-427c-bdfe-5fb79a3c7054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030452134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4030452134
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1602695018
Short name T947
Test name
Test status
Simulation time 451118743 ps
CPU time 2.06 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 04:56:46 PM PDT 24
Peak memory 198792 kb
Host smart-26714006-22e6-499e-9543-ec0f0288422e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602695018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1602695018
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3922393188
Short name T501
Test name
Test status
Simulation time 130105126759 ps
CPU time 208.27 seconds
Started Jul 16 04:56:33 PM PDT 24
Finished Jul 16 05:00:03 PM PDT 24
Peak memory 199828 kb
Host smart-0edca93e-d346-4f6d-bda7-25f9ac49b5da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922393188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3922393188
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1301275932
Short name T170
Test name
Test status
Simulation time 60549450924 ps
CPU time 405.64 seconds
Started Jul 16 04:56:41 PM PDT 24
Finished Jul 16 05:03:27 PM PDT 24
Peak memory 216352 kb
Host smart-20435afb-e470-463f-8277-72c925311504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301275932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1301275932
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.4039724853
Short name T1054
Test name
Test status
Simulation time 1096022492 ps
CPU time 1.88 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:56:50 PM PDT 24
Peak memory 199264 kb
Host smart-c5f85773-4d34-4eae-a97f-764de237ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039724853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.4039724853
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1782741129
Short name T595
Test name
Test status
Simulation time 45820543425 ps
CPU time 198.24 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 05:00:03 PM PDT 24
Peak memory 199748 kb
Host smart-392451db-9c8d-412b-8e92-2b6e96f6f329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782741129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1782741129
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3159472646
Short name T186
Test name
Test status
Simulation time 26558704819 ps
CPU time 11.56 seconds
Started Jul 16 04:59:03 PM PDT 24
Finished Jul 16 04:59:15 PM PDT 24
Peak memory 199836 kb
Host smart-865dd0dd-347f-405a-98ef-198f2a49c327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159472646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3159472646
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1006364132
Short name T1100
Test name
Test status
Simulation time 73160466947 ps
CPU time 53.36 seconds
Started Jul 16 04:59:05 PM PDT 24
Finished Jul 16 04:59:59 PM PDT 24
Peak memory 199680 kb
Host smart-67ed432c-1a75-45f1-a810-db07da10db94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006364132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1006364132
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2777103950
Short name T129
Test name
Test status
Simulation time 283909754922 ps
CPU time 820.68 seconds
Started Jul 16 04:59:05 PM PDT 24
Finished Jul 16 05:12:46 PM PDT 24
Peak memory 216316 kb
Host smart-4a0639e9-7440-4e9c-b084-438515dc28e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777103950 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2777103950
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2334741097
Short name T630
Test name
Test status
Simulation time 14731780249 ps
CPU time 6 seconds
Started Jul 16 04:59:04 PM PDT 24
Finished Jul 16 04:59:11 PM PDT 24
Peak memory 199204 kb
Host smart-a30a0a2d-5870-45fa-9aec-1b6414c1f292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334741097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2334741097
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1835889906
Short name T20
Test name
Test status
Simulation time 86805587672 ps
CPU time 558.99 seconds
Started Jul 16 04:59:04 PM PDT 24
Finished Jul 16 05:08:24 PM PDT 24
Peak memory 216412 kb
Host smart-698dfd09-fa6d-40e1-95bf-9e59496ec390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835889906 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1835889906
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3888602353
Short name T1079
Test name
Test status
Simulation time 87921014920 ps
CPU time 61.81 seconds
Started Jul 16 04:59:05 PM PDT 24
Finished Jul 16 05:00:08 PM PDT 24
Peak memory 199748 kb
Host smart-b376db78-8318-418b-9b1a-83c7fe6be502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888602353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3888602353
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1641521931
Short name T816
Test name
Test status
Simulation time 32556796590 ps
CPU time 376.42 seconds
Started Jul 16 04:59:05 PM PDT 24
Finished Jul 16 05:05:22 PM PDT 24
Peak memory 214792 kb
Host smart-0e487398-9a4f-4109-b642-52758a23411f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641521931 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1641521931
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3099744760
Short name T777
Test name
Test status
Simulation time 16798718954 ps
CPU time 23.93 seconds
Started Jul 16 04:59:08 PM PDT 24
Finished Jul 16 04:59:33 PM PDT 24
Peak memory 198260 kb
Host smart-f17815f9-434a-4947-a37a-8b9d4bb58ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099744760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3099744760
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2165052375
Short name T874
Test name
Test status
Simulation time 147984547201 ps
CPU time 192.4 seconds
Started Jul 16 04:59:04 PM PDT 24
Finished Jul 16 05:02:17 PM PDT 24
Peak memory 215588 kb
Host smart-9924990d-3cc1-4f8e-9889-b5e7169dc9b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165052375 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2165052375
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3754728074
Short name T1040
Test name
Test status
Simulation time 182269547815 ps
CPU time 24.95 seconds
Started Jul 16 04:59:06 PM PDT 24
Finished Jul 16 04:59:32 PM PDT 24
Peak memory 199688 kb
Host smart-857b405c-e27c-4833-839a-8186570fe478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754728074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3754728074
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1317664997
Short name T485
Test name
Test status
Simulation time 24750163248 ps
CPU time 13.2 seconds
Started Jul 16 04:59:06 PM PDT 24
Finished Jul 16 04:59:21 PM PDT 24
Peak memory 199776 kb
Host smart-53b122f2-215d-42e6-ad4b-eac9107f6afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317664997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1317664997
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.4151663973
Short name T889
Test name
Test status
Simulation time 95613725754 ps
CPU time 264.62 seconds
Started Jul 16 04:59:06 PM PDT 24
Finished Jul 16 05:03:31 PM PDT 24
Peak memory 216388 kb
Host smart-4035556d-51e2-4df3-bcec-9b8d9b5cf1bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151663973 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.4151663973
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1375831884
Short name T772
Test name
Test status
Simulation time 135632126921 ps
CPU time 97.93 seconds
Started Jul 16 04:59:04 PM PDT 24
Finished Jul 16 05:00:43 PM PDT 24
Peak memory 199908 kb
Host smart-71deefe9-bc4c-4bd4-a51e-b87fa96bd945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375831884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1375831884
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3014702405
Short name T108
Test name
Test status
Simulation time 22349386964 ps
CPU time 198.25 seconds
Started Jul 16 04:59:04 PM PDT 24
Finished Jul 16 05:02:22 PM PDT 24
Peak memory 216604 kb
Host smart-902817a4-83d0-41c0-9443-a45c18e72265
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014702405 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3014702405
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.151473723
Short name T652
Test name
Test status
Simulation time 66240410689 ps
CPU time 13.44 seconds
Started Jul 16 04:59:18 PM PDT 24
Finished Jul 16 04:59:33 PM PDT 24
Peak memory 199776 kb
Host smart-c575a5b9-4c91-433f-ae9e-64a838b20969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151473723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.151473723
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1619120314
Short name T733
Test name
Test status
Simulation time 35141818592 ps
CPU time 442.6 seconds
Started Jul 16 04:59:19 PM PDT 24
Finished Jul 16 05:06:42 PM PDT 24
Peak memory 216216 kb
Host smart-da480bc1-2ca6-426d-8d4f-a4cc125a0ede
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619120314 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1619120314
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1488066804
Short name T212
Test name
Test status
Simulation time 42319125067 ps
CPU time 51.45 seconds
Started Jul 16 04:59:18 PM PDT 24
Finished Jul 16 05:00:10 PM PDT 24
Peak memory 199864 kb
Host smart-efea3399-0acb-4028-be06-83664135659b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488066804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1488066804
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1153915251
Short name T859
Test name
Test status
Simulation time 53181398026 ps
CPU time 1070.21 seconds
Started Jul 16 04:59:19 PM PDT 24
Finished Jul 16 05:17:11 PM PDT 24
Peak memory 229636 kb
Host smart-bc3cffd3-3038-4234-9ed0-83e31f0ec64d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153915251 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1153915251
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3693269679
Short name T374
Test name
Test status
Simulation time 14463622 ps
CPU time 0.56 seconds
Started Jul 16 04:56:36 PM PDT 24
Finished Jul 16 04:56:38 PM PDT 24
Peak memory 195100 kb
Host smart-243f2b14-517b-44f4-84a2-9bf24767dd82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693269679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3693269679
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2654184956
Short name T1150
Test name
Test status
Simulation time 83382443610 ps
CPU time 136.51 seconds
Started Jul 16 04:56:45 PM PDT 24
Finished Jul 16 04:59:03 PM PDT 24
Peak memory 199796 kb
Host smart-2badbb35-f886-41b4-aff5-bb99310086c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654184956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2654184956
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1031244338
Short name T166
Test name
Test status
Simulation time 71668629024 ps
CPU time 219.14 seconds
Started Jul 16 04:56:45 PM PDT 24
Finished Jul 16 05:00:25 PM PDT 24
Peak memory 199668 kb
Host smart-1a2d0978-5f42-432e-9348-38050b9ef92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031244338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1031244338
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1323166200
Short name T203
Test name
Test status
Simulation time 23980044920 ps
CPU time 52.38 seconds
Started Jul 16 04:56:34 PM PDT 24
Finished Jul 16 04:57:28 PM PDT 24
Peak memory 199752 kb
Host smart-836f6763-9cd7-4c97-b6e7-3950fe8588e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323166200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1323166200
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3519975972
Short name T844
Test name
Test status
Simulation time 177569446452 ps
CPU time 167.99 seconds
Started Jul 16 04:56:34 PM PDT 24
Finished Jul 16 04:59:24 PM PDT 24
Peak memory 199740 kb
Host smart-0f724d76-c0ce-40a5-8a2b-326b081f713f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519975972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3519975972
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3078296016
Short name T823
Test name
Test status
Simulation time 85336826887 ps
CPU time 444.03 seconds
Started Jul 16 04:56:39 PM PDT 24
Finished Jul 16 05:04:04 PM PDT 24
Peak memory 199648 kb
Host smart-f4502be3-8bb8-4fb9-bfeb-50638ecdadba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3078296016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3078296016
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2301396534
Short name T747
Test name
Test status
Simulation time 5085726621 ps
CPU time 4.38 seconds
Started Jul 16 04:56:34 PM PDT 24
Finished Jul 16 04:56:40 PM PDT 24
Peak memory 199784 kb
Host smart-49a1be93-fa26-44bb-99ad-147fe76e73a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301396534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2301396534
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1981103426
Short name T488
Test name
Test status
Simulation time 79575794526 ps
CPU time 60.34 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 04:57:51 PM PDT 24
Peak memory 208192 kb
Host smart-febbc6f5-c73f-48d5-a569-6488e25f3327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981103426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1981103426
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.4178923968
Short name T477
Test name
Test status
Simulation time 18417775817 ps
CPU time 222.74 seconds
Started Jul 16 04:56:36 PM PDT 24
Finished Jul 16 05:00:20 PM PDT 24
Peak memory 199764 kb
Host smart-de8e3411-4638-4472-8973-e2d3b7577c98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178923968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.4178923968
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.4207512775
Short name T445
Test name
Test status
Simulation time 2224102093 ps
CPU time 5.2 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 04:56:50 PM PDT 24
Peak memory 197844 kb
Host smart-5509631c-b252-4eeb-b767-cdfb68b8c920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4207512775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.4207512775
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.308671107
Short name T126
Test name
Test status
Simulation time 23022152139 ps
CPU time 39.49 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:57:26 PM PDT 24
Peak memory 199752 kb
Host smart-e5fc2a7b-5598-404f-9560-1d3fc0d53bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308671107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.308671107
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1527137995
Short name T1111
Test name
Test status
Simulation time 2502573448 ps
CPU time 2.32 seconds
Started Jul 16 04:56:30 PM PDT 24
Finished Jul 16 04:56:34 PM PDT 24
Peak memory 195716 kb
Host smart-7fdbef08-e0be-4b7d-83f2-dffa64a6483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527137995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1527137995
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1044486314
Short name T716
Test name
Test status
Simulation time 5366213456 ps
CPU time 24.25 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:57:12 PM PDT 24
Peak memory 199616 kb
Host smart-22623471-79cf-4a16-91fb-28f0d46ca1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044486314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1044486314
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2001411707
Short name T1026
Test name
Test status
Simulation time 439759222348 ps
CPU time 2744.74 seconds
Started Jul 16 04:56:37 PM PDT 24
Finished Jul 16 05:42:23 PM PDT 24
Peak memory 199724 kb
Host smart-0317468d-86e6-4e3e-9c0d-4921ae936f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001411707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2001411707
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1010703895
Short name T845
Test name
Test status
Simulation time 26142996575 ps
CPU time 221.8 seconds
Started Jul 16 04:56:50 PM PDT 24
Finished Jul 16 05:00:34 PM PDT 24
Peak memory 216356 kb
Host smart-b0ffff18-7004-4f1b-ab04-f676238f1227
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010703895 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1010703895
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1003435427
Short name T476
Test name
Test status
Simulation time 7718011919 ps
CPU time 6.83 seconds
Started Jul 16 04:56:33 PM PDT 24
Finished Jul 16 04:56:42 PM PDT 24
Peak memory 199624 kb
Host smart-1f3f180c-f647-4179-8186-86682b2836fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003435427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1003435427
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2056477879
Short name T729
Test name
Test status
Simulation time 30195670237 ps
CPU time 32.8 seconds
Started Jul 16 04:56:32 PM PDT 24
Finished Jul 16 04:57:06 PM PDT 24
Peak memory 199828 kb
Host smart-75d711d2-21f0-4613-82bb-083db9da6420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056477879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2056477879
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1923448746
Short name T190
Test name
Test status
Simulation time 129401172986 ps
CPU time 43.43 seconds
Started Jul 16 04:59:19 PM PDT 24
Finished Jul 16 05:00:04 PM PDT 24
Peak memory 199616 kb
Host smart-d5844264-17db-45cd-a5a2-ddc607b63039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923448746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1923448746
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.339804629
Short name T1174
Test name
Test status
Simulation time 114687792576 ps
CPU time 148.47 seconds
Started Jul 16 04:59:22 PM PDT 24
Finished Jul 16 05:01:51 PM PDT 24
Peak memory 199672 kb
Host smart-f62a0a41-e3b8-4160-b338-9ecf4795b082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339804629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.339804629
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2179771945
Short name T1177
Test name
Test status
Simulation time 36927966639 ps
CPU time 392.5 seconds
Started Jul 16 04:59:22 PM PDT 24
Finished Jul 16 05:05:55 PM PDT 24
Peak memory 216456 kb
Host smart-42680921-67f4-4946-b9ed-16ce8a6ca46f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179771945 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2179771945
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.652544638
Short name T61
Test name
Test status
Simulation time 1000403233329 ps
CPU time 718.7 seconds
Started Jul 16 04:59:17 PM PDT 24
Finished Jul 16 05:11:16 PM PDT 24
Peak memory 224740 kb
Host smart-e5502a75-63f1-4ffa-8f4a-b999622d2bef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652544638 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.652544638
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.4214932997
Short name T750
Test name
Test status
Simulation time 25119587427 ps
CPU time 31.43 seconds
Started Jul 16 04:59:19 PM PDT 24
Finished Jul 16 04:59:51 PM PDT 24
Peak memory 199452 kb
Host smart-915e1bcc-7d75-4488-bd6f-d046a7525730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214932997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.4214932997
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1236435198
Short name T736
Test name
Test status
Simulation time 25458339393 ps
CPU time 307.32 seconds
Started Jul 16 04:59:21 PM PDT 24
Finished Jul 16 05:04:29 PM PDT 24
Peak memory 213912 kb
Host smart-66211e73-b40b-4ea0-8398-cbf55e2b6798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236435198 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1236435198
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2759079350
Short name T553
Test name
Test status
Simulation time 31482253030 ps
CPU time 224.47 seconds
Started Jul 16 04:59:17 PM PDT 24
Finished Jul 16 05:03:03 PM PDT 24
Peak memory 215984 kb
Host smart-bba462de-3f96-407a-8d52-f8c2e5fb0820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759079350 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2759079350
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2026521465
Short name T491
Test name
Test status
Simulation time 47514357594 ps
CPU time 54.61 seconds
Started Jul 16 04:59:18 PM PDT 24
Finished Jul 16 05:00:14 PM PDT 24
Peak memory 199724 kb
Host smart-f97c6646-6767-4be9-bf52-a1be6dc19ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026521465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2026521465
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.683963110
Short name T604
Test name
Test status
Simulation time 27370367293 ps
CPU time 339.43 seconds
Started Jul 16 04:59:17 PM PDT 24
Finished Jul 16 05:04:57 PM PDT 24
Peak memory 215620 kb
Host smart-42b405fd-ce35-46c7-9704-39ea70de3e1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683963110 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.683963110
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.930703369
Short name T81
Test name
Test status
Simulation time 69554580467 ps
CPU time 124.65 seconds
Started Jul 16 04:59:19 PM PDT 24
Finished Jul 16 05:01:25 PM PDT 24
Peak memory 199852 kb
Host smart-4087a4ce-a0a5-499c-881c-8faa04a09acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930703369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.930703369
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.155349451
Short name T624
Test name
Test status
Simulation time 405920154351 ps
CPU time 717.69 seconds
Started Jul 16 04:59:22 PM PDT 24
Finished Jul 16 05:11:21 PM PDT 24
Peak memory 224560 kb
Host smart-c8ddf6b2-0dff-4d13-9e62-f0bda89d076f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155349451 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.155349451
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2627197901
Short name T723
Test name
Test status
Simulation time 22275692421 ps
CPU time 18.19 seconds
Started Jul 16 04:59:22 PM PDT 24
Finished Jul 16 04:59:41 PM PDT 24
Peak memory 199852 kb
Host smart-c0fea1b5-77b8-4f63-a58d-d58465121746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627197901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2627197901
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.80367836
Short name T852
Test name
Test status
Simulation time 75070148128 ps
CPU time 651.18 seconds
Started Jul 16 04:59:17 PM PDT 24
Finished Jul 16 05:10:10 PM PDT 24
Peak memory 224780 kb
Host smart-8d71ea29-a18c-4866-9dd0-dad2d672428a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80367836 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.80367836
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3884393365
Short name T492
Test name
Test status
Simulation time 17671339696 ps
CPU time 19.76 seconds
Started Jul 16 04:59:18 PM PDT 24
Finished Jul 16 04:59:38 PM PDT 24
Peak memory 199716 kb
Host smart-09d4c8fa-c7d8-481c-8b72-f6f22b56f03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884393365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3884393365
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3835346733
Short name T1155
Test name
Test status
Simulation time 173973140964 ps
CPU time 745.35 seconds
Started Jul 16 04:59:18 PM PDT 24
Finished Jul 16 05:11:45 PM PDT 24
Peak memory 215928 kb
Host smart-a1e3e408-ec5a-47e2-9386-98e8296d36d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835346733 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3835346733
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3951470081
Short name T893
Test name
Test status
Simulation time 61063603063 ps
CPU time 91.43 seconds
Started Jul 16 04:59:20 PM PDT 24
Finished Jul 16 05:00:52 PM PDT 24
Peak memory 199820 kb
Host smart-288f3f6a-c358-44b4-981d-df2571fe0f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951470081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3951470081
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3911252520
Short name T1075
Test name
Test status
Simulation time 40172575 ps
CPU time 0.6 seconds
Started Jul 16 04:56:37 PM PDT 24
Finished Jul 16 04:56:38 PM PDT 24
Peak memory 195128 kb
Host smart-371ddda2-3156-4e05-ae80-a990e1f1337b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911252520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3911252520
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.406620404
Short name T263
Test name
Test status
Simulation time 21961251589 ps
CPU time 27.27 seconds
Started Jul 16 04:56:42 PM PDT 24
Finished Jul 16 04:57:10 PM PDT 24
Peak memory 199760 kb
Host smart-47ecf897-fe10-4117-aad3-6d25aa7449a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406620404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.406620404
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2527578680
Short name T154
Test name
Test status
Simulation time 271990427071 ps
CPU time 295.69 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 05:01:47 PM PDT 24
Peak memory 199732 kb
Host smart-e38929af-d202-4de6-974b-00df627d1a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527578680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2527578680
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1523060049
Short name T922
Test name
Test status
Simulation time 112940346442 ps
CPU time 98.01 seconds
Started Jul 16 04:56:45 PM PDT 24
Finished Jul 16 04:58:24 PM PDT 24
Peak memory 199752 kb
Host smart-ff657c63-d9ad-4257-86ef-43dccb0df656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523060049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1523060049
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.954241271
Short name T473
Test name
Test status
Simulation time 8111619614 ps
CPU time 13.21 seconds
Started Jul 16 04:56:42 PM PDT 24
Finished Jul 16 04:56:56 PM PDT 24
Peak memory 196876 kb
Host smart-30c71aad-a258-49b9-b21d-d92f900934e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954241271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.954241271
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1854044632
Short name T525
Test name
Test status
Simulation time 123823677297 ps
CPU time 253.25 seconds
Started Jul 16 04:56:41 PM PDT 24
Finished Jul 16 05:00:55 PM PDT 24
Peak memory 199684 kb
Host smart-7d67ab00-11bb-4399-a5e6-528743d4cbef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1854044632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1854044632
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.565608793
Short name T4
Test name
Test status
Simulation time 11125678209 ps
CPU time 11.39 seconds
Started Jul 16 04:56:38 PM PDT 24
Finished Jul 16 04:56:50 PM PDT 24
Peak memory 198728 kb
Host smart-0bfef3a5-97df-4222-b483-97f8906105e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565608793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.565608793
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2435282859
Short name T513
Test name
Test status
Simulation time 107680689311 ps
CPU time 56 seconds
Started Jul 16 04:56:40 PM PDT 24
Finished Jul 16 04:57:37 PM PDT 24
Peak memory 208084 kb
Host smart-4a77a244-26a2-4fd3-a57e-a565329ab1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435282859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2435282859
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1309022205
Short name T1108
Test name
Test status
Simulation time 22736798223 ps
CPU time 635.15 seconds
Started Jul 16 04:56:39 PM PDT 24
Finished Jul 16 05:07:15 PM PDT 24
Peak memory 199824 kb
Host smart-87bad0b1-064d-4995-a079-b18bc1114060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309022205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1309022205
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2930452106
Short name T526
Test name
Test status
Simulation time 7647961942 ps
CPU time 64.66 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:57:52 PM PDT 24
Peak memory 197944 kb
Host smart-389b3153-f576-4cdc-8431-8f94e03b3c13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2930452106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2930452106
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1555381083
Short name T1050
Test name
Test status
Simulation time 50336101209 ps
CPU time 19.58 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:57:06 PM PDT 24
Peak memory 199468 kb
Host smart-9a55a501-5d48-4893-910e-c83fc8c132a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555381083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1555381083
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3256856610
Short name T882
Test name
Test status
Simulation time 47663276677 ps
CPU time 75.19 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:58:03 PM PDT 24
Peak memory 195888 kb
Host smart-2a4e6078-b285-435f-801b-4c580e29aea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256856610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3256856610
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3229330495
Short name T967
Test name
Test status
Simulation time 840246463 ps
CPU time 2.88 seconds
Started Jul 16 04:56:35 PM PDT 24
Finished Jul 16 04:56:39 PM PDT 24
Peak memory 198436 kb
Host smart-2762d8ad-bdb4-4fca-b899-51fd8c51752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229330495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3229330495
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3833335385
Short name T621
Test name
Test status
Simulation time 357224406910 ps
CPU time 188.46 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:59:56 PM PDT 24
Peak memory 199748 kb
Host smart-326bcebe-648f-460e-af52-8f0358c837a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833335385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3833335385
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1180945065
Short name T516
Test name
Test status
Simulation time 83593234482 ps
CPU time 255.33 seconds
Started Jul 16 04:56:42 PM PDT 24
Finished Jul 16 05:00:58 PM PDT 24
Peak memory 216536 kb
Host smart-94a52ee8-43c6-4514-95ae-335c7cc5b9f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180945065 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1180945065
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.455022812
Short name T1084
Test name
Test status
Simulation time 7265211189 ps
CPU time 9.4 seconds
Started Jul 16 04:56:43 PM PDT 24
Finished Jul 16 04:56:53 PM PDT 24
Peak memory 199660 kb
Host smart-d1702d57-0f52-42e7-a4bc-7ff6be54acb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455022812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.455022812
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1214293331
Short name T1103
Test name
Test status
Simulation time 65212175594 ps
CPU time 24.25 seconds
Started Jul 16 04:56:40 PM PDT 24
Finished Jul 16 04:57:05 PM PDT 24
Peak memory 197732 kb
Host smart-136cae51-febc-42fc-b687-c83a5e724122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214293331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1214293331
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1707556064
Short name T188
Test name
Test status
Simulation time 157450436331 ps
CPU time 52.9 seconds
Started Jul 16 04:59:17 PM PDT 24
Finished Jul 16 05:00:10 PM PDT 24
Peak memory 199800 kb
Host smart-5eee44d0-c5db-4baa-91d2-4c799b8cf745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707556064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1707556064
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3280417581
Short name T959
Test name
Test status
Simulation time 131319694891 ps
CPU time 414.11 seconds
Started Jul 16 04:59:18 PM PDT 24
Finished Jul 16 05:06:13 PM PDT 24
Peak memory 215908 kb
Host smart-020924f8-855f-44d6-9b9d-315f1dfe4064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280417581 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3280417581
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2607523385
Short name T208
Test name
Test status
Simulation time 84533337837 ps
CPU time 115.05 seconds
Started Jul 16 04:59:21 PM PDT 24
Finished Jul 16 05:01:17 PM PDT 24
Peak memory 199820 kb
Host smart-7ecaa7d3-f31a-4b5d-b71b-3d65c8313d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607523385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2607523385
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2982892663
Short name T720
Test name
Test status
Simulation time 38294967693 ps
CPU time 647.38 seconds
Started Jul 16 04:59:19 PM PDT 24
Finished Jul 16 05:10:08 PM PDT 24
Peak memory 216472 kb
Host smart-5c21fb72-7303-451f-a589-b68a08af5cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982892663 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2982892663
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1936310206
Short name T564
Test name
Test status
Simulation time 14559979556 ps
CPU time 289.65 seconds
Started Jul 16 04:59:18 PM PDT 24
Finished Jul 16 05:04:08 PM PDT 24
Peak memory 215952 kb
Host smart-ce79c129-191b-4404-b88a-0cab0b7beb7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936310206 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1936310206
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3870962313
Short name T284
Test name
Test status
Simulation time 92706724648 ps
CPU time 211.38 seconds
Started Jul 16 04:59:22 PM PDT 24
Finished Jul 16 05:02:54 PM PDT 24
Peak memory 199664 kb
Host smart-c71b74e4-0a75-4abb-8832-d697b5be4f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870962313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3870962313
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1945516278
Short name T815
Test name
Test status
Simulation time 311236786486 ps
CPU time 496.65 seconds
Started Jul 16 04:59:17 PM PDT 24
Finished Jul 16 05:07:35 PM PDT 24
Peak memory 216276 kb
Host smart-86ed26a0-0881-43cd-82e5-6ea8b1ccc342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945516278 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1945516278
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3007345988
Short name T1134
Test name
Test status
Simulation time 131344090583 ps
CPU time 14.43 seconds
Started Jul 16 04:59:17 PM PDT 24
Finished Jul 16 04:59:32 PM PDT 24
Peak memory 199808 kb
Host smart-4c2c7e7f-cca4-4b90-9f09-6033e1de5f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007345988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3007345988
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.4148849715
Short name T895
Test name
Test status
Simulation time 172312824706 ps
CPU time 1444.85 seconds
Started Jul 16 04:59:18 PM PDT 24
Finished Jul 16 05:23:24 PM PDT 24
Peak memory 224796 kb
Host smart-b9a9480e-df0f-4fdc-b82b-65746146e49b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148849715 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.4148849715
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.651816226
Short name T215
Test name
Test status
Simulation time 22597724986 ps
CPU time 15.76 seconds
Started Jul 16 04:59:23 PM PDT 24
Finished Jul 16 04:59:40 PM PDT 24
Peak memory 199800 kb
Host smart-a2ab47d3-6947-4e58-946e-66e4fac5b598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651816226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.651816226
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.407443468
Short name T57
Test name
Test status
Simulation time 205333169625 ps
CPU time 913.95 seconds
Started Jul 16 04:59:19 PM PDT 24
Finished Jul 16 05:14:34 PM PDT 24
Peak memory 216324 kb
Host smart-fc92f80c-9172-4621-b508-35f50d583d9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407443468 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.407443468
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3063431979
Short name T350
Test name
Test status
Simulation time 22465982799 ps
CPU time 20.14 seconds
Started Jul 16 04:59:24 PM PDT 24
Finished Jul 16 04:59:45 PM PDT 24
Peak memory 199760 kb
Host smart-4a4a0cde-97e7-454f-b2ce-009fb7fb12e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063431979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3063431979
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1396945607
Short name T398
Test name
Test status
Simulation time 197425737967 ps
CPU time 599.75 seconds
Started Jul 16 04:59:20 PM PDT 24
Finished Jul 16 05:09:20 PM PDT 24
Peak memory 224732 kb
Host smart-35629163-da26-4ea6-9810-50a008e81764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396945607 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1396945607
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3661552465
Short name T1176
Test name
Test status
Simulation time 88943049193 ps
CPU time 1192.58 seconds
Started Jul 16 04:59:18 PM PDT 24
Finished Jul 16 05:19:12 PM PDT 24
Peak memory 226792 kb
Host smart-72079b34-8aa5-48fa-b60b-a431fdbaebad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661552465 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3661552465
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1315331618
Short name T62
Test name
Test status
Simulation time 328413627805 ps
CPU time 935.1 seconds
Started Jul 16 04:59:22 PM PDT 24
Finished Jul 16 05:14:58 PM PDT 24
Peak memory 224752 kb
Host smart-7d84f792-b654-43d0-b44d-4c76a4ad86cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315331618 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1315331618
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.725693560
Short name T581
Test name
Test status
Simulation time 236251582804 ps
CPU time 473.3 seconds
Started Jul 16 04:59:22 PM PDT 24
Finished Jul 16 05:07:16 PM PDT 24
Peak memory 199780 kb
Host smart-9a3ac817-2921-4aab-9f7c-3a673521e884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725693560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.725693560
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1852585607
Short name T700
Test name
Test status
Simulation time 23136971887 ps
CPU time 220.66 seconds
Started Jul 16 04:59:21 PM PDT 24
Finished Jul 16 05:03:03 PM PDT 24
Peak memory 215884 kb
Host smart-5cb27a3c-487f-4975-8f76-ffe0cc8da6ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852585607 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1852585607
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.295603478
Short name T536
Test name
Test status
Simulation time 14540278 ps
CPU time 0.57 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:57:02 PM PDT 24
Peak memory 195112 kb
Host smart-de9c96d9-df2f-4824-9fb4-d3f920128cdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295603478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.295603478
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3030306364
Short name T973
Test name
Test status
Simulation time 57773505738 ps
CPU time 47.93 seconds
Started Jul 16 04:56:45 PM PDT 24
Finished Jul 16 04:57:34 PM PDT 24
Peak memory 199756 kb
Host smart-968ddd96-4213-4186-9c63-6ce8b9b5707f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030306364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3030306364
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2140432532
Short name T987
Test name
Test status
Simulation time 38272469375 ps
CPU time 15.39 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 04:57:06 PM PDT 24
Peak memory 199400 kb
Host smart-6bcbb4b7-9aef-439d-908c-84f26008ffbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140432532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2140432532
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3258358108
Short name T629
Test name
Test status
Simulation time 277851017358 ps
CPU time 30.91 seconds
Started Jul 16 04:56:36 PM PDT 24
Finished Jul 16 04:57:08 PM PDT 24
Peak memory 199860 kb
Host smart-6b5855fe-5b43-4e76-b9a7-6fe26a3e1873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258358108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3258358108
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.4262087420
Short name T357
Test name
Test status
Simulation time 73318281241 ps
CPU time 61.28 seconds
Started Jul 16 04:56:43 PM PDT 24
Finished Jul 16 04:57:45 PM PDT 24
Peak memory 199756 kb
Host smart-3e984c58-caf8-43f3-9098-6db423ed3f5d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262087420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.4262087420
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2013266848
Short name T653
Test name
Test status
Simulation time 91321958243 ps
CPU time 751.04 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 05:09:22 PM PDT 24
Peak memory 199792 kb
Host smart-ee8e56f7-b8a9-49af-9ade-16603fd604db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013266848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2013266848
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3728469096
Short name T403
Test name
Test status
Simulation time 3312521882 ps
CPU time 5.51 seconds
Started Jul 16 04:56:40 PM PDT 24
Finished Jul 16 04:56:46 PM PDT 24
Peak memory 197060 kb
Host smart-ff377399-15fa-4afb-8c34-4389f44826d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728469096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3728469096
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.785027231
Short name T434
Test name
Test status
Simulation time 248433384496 ps
CPU time 73.32 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 04:57:58 PM PDT 24
Peak memory 199992 kb
Host smart-a3702e3b-a5c3-4eac-a6a9-e29cea84bf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785027231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.785027231
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1819632091
Short name T437
Test name
Test status
Simulation time 13177705291 ps
CPU time 176.64 seconds
Started Jul 16 04:56:45 PM PDT 24
Finished Jul 16 04:59:43 PM PDT 24
Peak memory 199776 kb
Host smart-5a78bc08-d80d-40c6-97f9-84196f66c2a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819632091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1819632091
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1130634825
Short name T82
Test name
Test status
Simulation time 4187304039 ps
CPU time 28.2 seconds
Started Jul 16 04:56:50 PM PDT 24
Finished Jul 16 04:57:20 PM PDT 24
Peak memory 199172 kb
Host smart-ea4fd8b9-15d8-4d46-8c73-925d05bea31b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1130634825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1130634825
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1384365686
Short name T686
Test name
Test status
Simulation time 23738785203 ps
CPU time 35.57 seconds
Started Jul 16 04:56:38 PM PDT 24
Finished Jul 16 04:57:14 PM PDT 24
Peak memory 199768 kb
Host smart-833c0885-ea0e-4a0c-86fa-2251e83c3edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384365686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1384365686
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3172123916
Short name T572
Test name
Test status
Simulation time 4582924755 ps
CPU time 4.27 seconds
Started Jul 16 04:56:45 PM PDT 24
Finished Jul 16 04:56:51 PM PDT 24
Peak memory 195872 kb
Host smart-1a710b00-231c-4c66-a188-2c927e020874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172123916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3172123916
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.756259960
Short name T675
Test name
Test status
Simulation time 524415560 ps
CPU time 1.47 seconds
Started Jul 16 04:56:38 PM PDT 24
Finished Jul 16 04:56:41 PM PDT 24
Peak memory 198216 kb
Host smart-66f6a741-f3cd-4b0f-a156-aa657e94288c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756259960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.756259960
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.4056123450
Short name T147
Test name
Test status
Simulation time 217090351517 ps
CPU time 64.54 seconds
Started Jul 16 04:56:43 PM PDT 24
Finished Jul 16 04:57:48 PM PDT 24
Peak memory 199844 kb
Host smart-dc52377a-aea9-4e8c-8358-aa76a2343dcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056123450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4056123450
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3674718054
Short name T112
Test name
Test status
Simulation time 249276754399 ps
CPU time 481.97 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 05:04:52 PM PDT 24
Peak memory 224772 kb
Host smart-0b6db6a8-9f1b-4a0b-9211-4ab17933d2e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674718054 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3674718054
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2652750755
Short name T360
Test name
Test status
Simulation time 819739950 ps
CPU time 1.35 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 04:56:48 PM PDT 24
Peak memory 198088 kb
Host smart-b8115e32-3c71-44b1-acc5-a566e2330f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652750755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2652750755
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2813494149
Short name T447
Test name
Test status
Simulation time 36793261837 ps
CPU time 14.32 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 04:57:05 PM PDT 24
Peak memory 197452 kb
Host smart-f1120682-8abd-4604-91dc-4d7830d942e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813494149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2813494149
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3949231234
Short name T1017
Test name
Test status
Simulation time 803109247474 ps
CPU time 996.6 seconds
Started Jul 16 04:59:21 PM PDT 24
Finished Jul 16 05:15:58 PM PDT 24
Peak memory 224740 kb
Host smart-28ba0796-d479-449d-af60-610c4ccbdf19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949231234 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3949231234
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.4132478011
Short name T722
Test name
Test status
Simulation time 116972385740 ps
CPU time 188.55 seconds
Started Jul 16 04:59:23 PM PDT 24
Finished Jul 16 05:02:32 PM PDT 24
Peak memory 199780 kb
Host smart-cf61a43f-c4c3-45a6-8216-879a99dec4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132478011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.4132478011
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.4169821866
Short name T775
Test name
Test status
Simulation time 78552432961 ps
CPU time 878.9 seconds
Started Jul 16 04:59:19 PM PDT 24
Finished Jul 16 05:13:59 PM PDT 24
Peak memory 232940 kb
Host smart-2dd3751b-13af-4c9b-aa4a-79f889344540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169821866 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.4169821866
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.990340507
Short name T739
Test name
Test status
Simulation time 12416694955 ps
CPU time 22.58 seconds
Started Jul 16 04:59:18 PM PDT 24
Finished Jul 16 04:59:42 PM PDT 24
Peak memory 199768 kb
Host smart-b44371b1-9e69-46c1-b8c9-400662521fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990340507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.990340507
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.4144871741
Short name T896
Test name
Test status
Simulation time 34125565745 ps
CPU time 329.05 seconds
Started Jul 16 04:59:19 PM PDT 24
Finished Jul 16 05:04:49 PM PDT 24
Peak memory 216016 kb
Host smart-c1732ded-0ea3-44c4-8bc3-614aa6c28fe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144871741 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.4144871741
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2512838220
Short name T241
Test name
Test status
Simulation time 28075316971 ps
CPU time 39.89 seconds
Started Jul 16 04:59:21 PM PDT 24
Finished Jul 16 05:00:02 PM PDT 24
Peak memory 199836 kb
Host smart-d4fbdccf-0717-4743-a7d3-334945735843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512838220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2512838220
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3466636521
Short name T683
Test name
Test status
Simulation time 36888687986 ps
CPU time 562.19 seconds
Started Jul 16 04:59:19 PM PDT 24
Finished Jul 16 05:08:42 PM PDT 24
Peak memory 216588 kb
Host smart-60cb5204-ade9-4bd0-b3d9-63a99fa0cdf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466636521 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3466636521
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2079840347
Short name T539
Test name
Test status
Simulation time 60784259421 ps
CPU time 61.81 seconds
Started Jul 16 04:59:29 PM PDT 24
Finished Jul 16 05:00:32 PM PDT 24
Peak memory 199616 kb
Host smart-0a935a75-c20b-443d-98be-33ba9e635829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079840347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2079840347
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2580242427
Short name T1124
Test name
Test status
Simulation time 29711002041 ps
CPU time 177.44 seconds
Started Jul 16 04:59:34 PM PDT 24
Finished Jul 16 05:02:32 PM PDT 24
Peak memory 216152 kb
Host smart-49e1c745-c394-4cac-b4a9-3344b77e124c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580242427 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2580242427
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2270906903
Short name T658
Test name
Test status
Simulation time 7272113038 ps
CPU time 11.23 seconds
Started Jul 16 04:59:29 PM PDT 24
Finished Jul 16 04:59:42 PM PDT 24
Peak memory 199844 kb
Host smart-4442777b-45b7-4cad-955c-7ea27688793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270906903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2270906903
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1200577625
Short name T197
Test name
Test status
Simulation time 392147875269 ps
CPU time 1061.34 seconds
Started Jul 16 04:59:30 PM PDT 24
Finished Jul 16 05:17:13 PM PDT 24
Peak memory 226328 kb
Host smart-44185bda-392c-436f-a8ac-2bb5158952c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200577625 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1200577625
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.50360082
Short name T206
Test name
Test status
Simulation time 23825991606 ps
CPU time 21.04 seconds
Started Jul 16 04:59:30 PM PDT 24
Finished Jul 16 04:59:53 PM PDT 24
Peak memory 199652 kb
Host smart-30403ede-6279-4d9f-9480-fcc72e50f89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50360082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.50360082
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.753708728
Short name T110
Test name
Test status
Simulation time 130831067865 ps
CPU time 620.15 seconds
Started Jul 16 04:59:33 PM PDT 24
Finished Jul 16 05:09:54 PM PDT 24
Peak memory 216340 kb
Host smart-f2a08e46-2d99-4dd5-845a-3b73a4d1ad6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753708728 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.753708728
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3325755515
Short name T949
Test name
Test status
Simulation time 40252364229 ps
CPU time 60.71 seconds
Started Jul 16 04:59:35 PM PDT 24
Finished Jul 16 05:00:36 PM PDT 24
Peak memory 199900 kb
Host smart-4bde0158-04ab-4701-8002-57c0d1951256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325755515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3325755515
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.4017859515
Short name T113
Test name
Test status
Simulation time 240140181708 ps
CPU time 451.24 seconds
Started Jul 16 04:59:35 PM PDT 24
Finished Jul 16 05:07:07 PM PDT 24
Peak memory 225848 kb
Host smart-85d3841d-2cb4-4a7d-8db0-c18384505b1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017859515 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.4017859515
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3027682042
Short name T316
Test name
Test status
Simulation time 36658725290 ps
CPU time 116.41 seconds
Started Jul 16 04:59:37 PM PDT 24
Finished Jul 16 05:01:34 PM PDT 24
Peak memory 208392 kb
Host smart-69c69c75-61d6-446f-8ca6-6a3e2d200638
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027682042 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3027682042
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1288488909
Short name T144
Test name
Test status
Simulation time 53748158313 ps
CPU time 36.79 seconds
Started Jul 16 04:59:30 PM PDT 24
Finished Jul 16 05:00:08 PM PDT 24
Peak memory 199844 kb
Host smart-23418f0b-0877-4c1a-a22f-711e34108bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288488909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1288488909
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.727590727
Short name T885
Test name
Test status
Simulation time 119034370420 ps
CPU time 595.72 seconds
Started Jul 16 04:59:37 PM PDT 24
Finished Jul 16 05:09:33 PM PDT 24
Peak memory 224660 kb
Host smart-19fd68c5-5cc7-48de-bba0-036e5ad16173
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727590727 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.727590727
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.461513305
Short name T554
Test name
Test status
Simulation time 45995929 ps
CPU time 0.59 seconds
Started Jul 16 04:56:40 PM PDT 24
Finished Jul 16 04:56:41 PM PDT 24
Peak memory 195168 kb
Host smart-d220da66-d5f8-476b-a300-589ac2aee683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461513305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.461513305
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3767952105
Short name T472
Test name
Test status
Simulation time 48744218311 ps
CPU time 69.08 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 04:57:59 PM PDT 24
Peak memory 199740 kb
Host smart-714d7fe9-cbec-4b6a-8055-23dcf1c27b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767952105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3767952105
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3132804985
Short name T661
Test name
Test status
Simulation time 138029485699 ps
CPU time 151.58 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 04:59:21 PM PDT 24
Peak memory 199524 kb
Host smart-b64146e3-f401-4163-a366-d4a3d47a8c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132804985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3132804985
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.559213212
Short name T428
Test name
Test status
Simulation time 80639473753 ps
CPU time 30.09 seconds
Started Jul 16 04:56:45 PM PDT 24
Finished Jul 16 04:57:16 PM PDT 24
Peak memory 199780 kb
Host smart-b11d6a58-486b-49de-9d2a-5e594c27e660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559213212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.559213212
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3459532083
Short name T381
Test name
Test status
Simulation time 61175690993 ps
CPU time 50.04 seconds
Started Jul 16 04:56:53 PM PDT 24
Finished Jul 16 04:57:43 PM PDT 24
Peak memory 199704 kb
Host smart-a5733f4d-c0fb-4557-9e81-9cb8f5bf4add
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459532083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3459532083
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2241791750
Short name T886
Test name
Test status
Simulation time 120414629031 ps
CPU time 346.07 seconds
Started Jul 16 04:56:46 PM PDT 24
Finished Jul 16 05:02:34 PM PDT 24
Peak memory 199740 kb
Host smart-6386fef5-d74c-4c85-867f-ada33d0820b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2241791750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2241791750
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.380073455
Short name T991
Test name
Test status
Simulation time 3311796448 ps
CPU time 5.93 seconds
Started Jul 16 04:56:50 PM PDT 24
Finished Jul 16 04:56:58 PM PDT 24
Peak memory 199328 kb
Host smart-ab984753-a2e1-403d-9c1f-c54fbdf9249a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380073455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.380073455
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1935495002
Short name T309
Test name
Test status
Simulation time 28253146316 ps
CPU time 5.75 seconds
Started Jul 16 04:56:49 PM PDT 24
Finished Jul 16 04:56:57 PM PDT 24
Peak memory 199692 kb
Host smart-8dcc51c2-4878-4af3-822d-3d3564f3a507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935495002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1935495002
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3193012854
Short name T8
Test name
Test status
Simulation time 21316232811 ps
CPU time 956.25 seconds
Started Jul 16 04:56:50 PM PDT 24
Finished Jul 16 05:12:48 PM PDT 24
Peak memory 199732 kb
Host smart-acb78d00-9f99-4413-8c2e-ba5a16f59058
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193012854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3193012854
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.932925874
Short name T555
Test name
Test status
Simulation time 3068923640 ps
CPU time 10.72 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 04:57:01 PM PDT 24
Peak memory 198980 kb
Host smart-4027de65-d342-4cf9-b65b-13767a700129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=932925874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.932925874
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.372693392
Short name T979
Test name
Test status
Simulation time 6550210595 ps
CPU time 9.34 seconds
Started Jul 16 04:56:38 PM PDT 24
Finished Jul 16 04:56:48 PM PDT 24
Peak memory 197700 kb
Host smart-e4be83f9-1540-4be6-ac62-6af49632ac30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372693392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.372693392
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.225561655
Short name T1089
Test name
Test status
Simulation time 3402827736 ps
CPU time 1.98 seconds
Started Jul 16 04:56:38 PM PDT 24
Finished Jul 16 04:56:41 PM PDT 24
Peak memory 196148 kb
Host smart-516ab950-ed90-48ae-8d43-670ebb7b82c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225561655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.225561655
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2080851723
Short name T537
Test name
Test status
Simulation time 284184241 ps
CPU time 1.93 seconds
Started Jul 16 04:56:40 PM PDT 24
Finished Jul 16 04:56:43 PM PDT 24
Peak memory 198688 kb
Host smart-4bcbba19-00a8-4136-90b2-95400aa9ee5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080851723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2080851723
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2780829613
Short name T589
Test name
Test status
Simulation time 521131763088 ps
CPU time 681.43 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 05:08:06 PM PDT 24
Peak memory 199784 kb
Host smart-ce3ab6eb-fa64-4566-85d7-499758f41262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780829613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2780829613
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.45562438
Short name T59
Test name
Test status
Simulation time 251782717128 ps
CPU time 707.94 seconds
Started Jul 16 04:56:48 PM PDT 24
Finished Jul 16 05:08:39 PM PDT 24
Peak memory 224296 kb
Host smart-68793196-cff3-41db-9dba-f9f060f06bf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45562438 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.45562438
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1727039851
Short name T767
Test name
Test status
Simulation time 8542440087 ps
CPU time 15.35 seconds
Started Jul 16 04:56:43 PM PDT 24
Finished Jul 16 04:56:58 PM PDT 24
Peak memory 199492 kb
Host smart-94cc676c-16cc-41f1-b0a2-4af6ef48fd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727039851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1727039851
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1064922518
Short name T901
Test name
Test status
Simulation time 54917424283 ps
CPU time 46.11 seconds
Started Jul 16 04:56:44 PM PDT 24
Finished Jul 16 04:57:31 PM PDT 24
Peak memory 199676 kb
Host smart-60dac7a0-c3c0-47b1-a2ee-d04347ad814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064922518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1064922518
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1840491555
Short name T757
Test name
Test status
Simulation time 11348504422 ps
CPU time 125.06 seconds
Started Jul 16 04:59:29 PM PDT 24
Finished Jul 16 05:01:36 PM PDT 24
Peak memory 208112 kb
Host smart-ba8a7f13-34b0-4037-8d4d-ca739e194082
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840491555 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1840491555
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1408461429
Short name T791
Test name
Test status
Simulation time 116367464810 ps
CPU time 191.98 seconds
Started Jul 16 04:59:30 PM PDT 24
Finished Jul 16 05:02:43 PM PDT 24
Peak memory 199788 kb
Host smart-aaeeda87-d19a-46d9-9701-a9febfc1d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408461429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1408461429
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.693868214
Short name T544
Test name
Test status
Simulation time 106276171729 ps
CPU time 1150.9 seconds
Started Jul 16 04:59:29 PM PDT 24
Finished Jul 16 05:18:42 PM PDT 24
Peak memory 224668 kb
Host smart-7022a2f4-9b97-44fa-9e17-53f20e104aef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693868214 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.693868214
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.87869361
Short name T875
Test name
Test status
Simulation time 46230197421 ps
CPU time 36.93 seconds
Started Jul 16 04:59:29 PM PDT 24
Finished Jul 16 05:00:08 PM PDT 24
Peak memory 199760 kb
Host smart-113fc35f-a525-4c14-9caa-68a97bf9462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87869361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.87869361
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.4199557110
Short name T47
Test name
Test status
Simulation time 18365634948 ps
CPU time 29.92 seconds
Started Jul 16 04:59:32 PM PDT 24
Finished Jul 16 05:00:03 PM PDT 24
Peak memory 199724 kb
Host smart-0a722abf-c9d3-49b5-aa0a-002829b4a42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199557110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.4199557110
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.675891902
Short name T1128
Test name
Test status
Simulation time 45686249496 ps
CPU time 527.05 seconds
Started Jul 16 04:59:35 PM PDT 24
Finished Jul 16 05:08:22 PM PDT 24
Peak memory 215248 kb
Host smart-b03a3ef3-69fa-4d6c-a84a-8dc7221cb365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675891902 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.675891902
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2191733032
Short name T1115
Test name
Test status
Simulation time 112689037779 ps
CPU time 23.75 seconds
Started Jul 16 04:59:40 PM PDT 24
Finished Jul 16 05:00:05 PM PDT 24
Peak memory 199840 kb
Host smart-59553af3-b52c-4930-bd3b-9d5ced21817b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191733032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2191733032
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.308625987
Short name T111
Test name
Test status
Simulation time 202894678712 ps
CPU time 525.4 seconds
Started Jul 16 04:59:29 PM PDT 24
Finished Jul 16 05:08:14 PM PDT 24
Peak memory 229276 kb
Host smart-a2ab9607-2f99-4925-8cc5-94f9c2e2e4d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308625987 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.308625987
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.151099765
Short name T368
Test name
Test status
Simulation time 17743873782 ps
CPU time 15.24 seconds
Started Jul 16 04:59:30 PM PDT 24
Finished Jul 16 04:59:47 PM PDT 24
Peak memory 199368 kb
Host smart-2b4929fb-0400-45e8-8a4b-faf3da88d932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151099765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.151099765
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2513083869
Short name T831
Test name
Test status
Simulation time 21013595919 ps
CPU time 241.48 seconds
Started Jul 16 04:59:30 PM PDT 24
Finished Jul 16 05:03:33 PM PDT 24
Peak memory 211660 kb
Host smart-5e3ba3a3-5a57-419c-9521-53952d07dd2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513083869 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2513083869
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.588269671
Short name T214
Test name
Test status
Simulation time 62692690168 ps
CPU time 12.27 seconds
Started Jul 16 04:59:30 PM PDT 24
Finished Jul 16 04:59:44 PM PDT 24
Peak memory 199840 kb
Host smart-6fc5565d-2528-4b1a-9118-ccb816406b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588269671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.588269671
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2613799902
Short name T825
Test name
Test status
Simulation time 97042882440 ps
CPU time 498.89 seconds
Started Jul 16 04:59:34 PM PDT 24
Finished Jul 16 05:07:53 PM PDT 24
Peak memory 216556 kb
Host smart-ab9bc80a-3a8c-4716-ac5e-c7b053031daa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613799902 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2613799902
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.227248654
Short name T75
Test name
Test status
Simulation time 118573726903 ps
CPU time 20.05 seconds
Started Jul 16 04:59:29 PM PDT 24
Finished Jul 16 04:59:50 PM PDT 24
Peak memory 199872 kb
Host smart-69c56076-b6b8-4f49-8900-19f5b7df3b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227248654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.227248654
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1405535160
Short name T1132
Test name
Test status
Simulation time 46361725340 ps
CPU time 599.96 seconds
Started Jul 16 04:59:32 PM PDT 24
Finished Jul 16 05:09:33 PM PDT 24
Peak memory 216528 kb
Host smart-8bff22e2-70ef-4454-b695-917093b74b9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405535160 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1405535160
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2508177290
Short name T1049
Test name
Test status
Simulation time 104177024832 ps
CPU time 39.22 seconds
Started Jul 16 04:59:32 PM PDT 24
Finished Jul 16 05:00:12 PM PDT 24
Peak memory 199928 kb
Host smart-0d998c64-185d-4cee-89b9-4e9d73da817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508177290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2508177290
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3926581852
Short name T617
Test name
Test status
Simulation time 27595446479 ps
CPU time 211.75 seconds
Started Jul 16 04:59:31 PM PDT 24
Finished Jul 16 05:03:04 PM PDT 24
Peak memory 216508 kb
Host smart-f724a85b-c2b2-4b35-a086-131fdf114797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926581852 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3926581852
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.4287152777
Short name T1097
Test name
Test status
Simulation time 36902146873 ps
CPU time 13.26 seconds
Started Jul 16 04:59:37 PM PDT 24
Finished Jul 16 04:59:51 PM PDT 24
Peak memory 199524 kb
Host smart-4dd41941-214f-4e23-bbc7-869169858193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287152777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4287152777
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3726680694
Short name T484
Test name
Test status
Simulation time 259830022642 ps
CPU time 420.98 seconds
Started Jul 16 04:59:29 PM PDT 24
Finished Jul 16 05:06:32 PM PDT 24
Peak memory 216312 kb
Host smart-62f0b115-fe32-4c80-9dc7-23a1bc4743fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726680694 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3726680694
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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