Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	117712	1			T1	1		T2	61		T3	4
all_values[1]	117712	1			T1	1		T2	61		T3	4
all_values[2]	117712	1			T1	1		T2	61		T3	4
all_values[3]	117712	1			T1	1		T2	61		T3	4
all_values[4]	117712	1			T1	1		T2	61		T3	4
all_values[5]	117712	1			T1	1		T2	61		T3	4
all_values[6]	117712	1			T1	1		T2	61		T3	4
all_values[7]	117712	1			T1	1		T2	61		T3	4
all_values[8]	117712	1			T1	1		T2	61		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

540430

1

T1

7

T2

260

T3

27

auto[1]

518978

1

T1

2

T2

289

T3

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

963996

1

T1

7

T2

430

T3

25

auto[1]

95412

1

T1

2

T2

119

T3

11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	32467	1			T2	17		T4	10		T6	234
all_values[0]	auto[0]	auto[1]	25323	1			T1	1		T2	10		T3	4
all_values[0]	auto[1]	auto[0]	37938	1			T2	1		T5	6		T6	10
all_values[0]	auto[1]	auto[1]	21984	1			T2	33		T4	20		T5	3
all_values[1]	auto[0]	auto[0]	56108	1			T1	1		T2	10		T3	1
all_values[1]	auto[0]	auto[1]	1898	1			T2	1		T4	9		T7	2
all_values[1]	auto[1]	auto[0]	57845	1			T2	49		T3	2		T4	60
all_values[1]	auto[1]	auto[1]	1861	1			T2	1		T3	1		T9	10
all_values[2]	auto[0]	auto[0]	58025	1			T1	1		T2	7		T3	3
all_values[2]	auto[0]	auto[1]	2788	1			T2	4		T3	1		T4	8
all_values[2]	auto[1]	auto[0]	54443	1			T2	45		T4	74		T5	3
all_values[2]	auto[1]	auto[1]	2456	1			T2	5		T4	2		T6	6
all_values[3]	auto[0]	auto[0]	57967	1			T2	44		T3	2		T4	77
all_values[3]	auto[0]	auto[1]	330	1			T2	3		T3	1		T9	4
all_values[3]	auto[1]	auto[0]	59096	1			T1	1		T2	13		T3	1
all_values[3]	auto[1]	auto[1]	319	1			T2	1		T9	1		T12	9
all_values[4]	auto[0]	auto[0]	61311	1			T1	1		T2	31		T3	2
all_values[4]	auto[0]	auto[1]	521	1			T2	3		T9	2		T12	9
all_values[4]	auto[1]	auto[0]	55406	1			T2	23		T3	2		T4	3
all_values[4]	auto[1]	auto[1]	474	1			T2	4		T9	3		T12	4
all_values[5]	auto[0]	auto[0]	61522	1			T2	28		T3	2		T4	18
all_values[5]	auto[0]	auto[1]	184	1			T2	3		T9	1		T12	4
all_values[5]	auto[1]	auto[0]	55799	1			T1	1		T2	28		T3	2
all_values[5]	auto[1]	auto[1]	207	1			T2	2		T12	3		T26	2
all_values[6]	auto[0]	auto[0]	61950	1			T1	1		T2	27		T3	4
all_values[6]	auto[0]	auto[1]	190	1			T2	4		T9	1		T12	5
all_values[6]	auto[1]	auto[0]	55397	1			T2	26		T4	40		T5	6
all_values[6]	auto[1]	auto[1]	175	1			T2	4		T9	1		T12	6
all_values[7]	auto[0]	auto[0]	58011	1			T1	1		T2	31		T3	4
all_values[7]	auto[0]	auto[1]	395	1			T4	1		T9	2		T12	5
all_values[7]	auto[1]	auto[0]	58935	1			T2	28		T4	47		T5	41
all_values[7]	auto[1]	auto[1]	371	1			T2	2		T4	8		T9	2
all_values[8]	auto[0]	auto[0]	42238	1			T2	2		T4	68		T6	11
all_values[8]	auto[0]	auto[1]	19202	1			T1	1		T2	35		T3	3
all_values[8]	auto[1]	auto[0]	39538	1			T2	20		T4	18		T5	6
all_values[8]	auto[1]	auto[1]	16734	1			T2	4		T3	1		T4	21