Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2561

1

T1

1

T2

11

T3

1

auto[UartRx]

2561

1

T1

1

T2

11

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4559	1			T1	2		T2	10		T3	2
values[1]	45	1			T9	2		T25	1		T27	1
values[2]	46	1			T18	1		T12	1		T25	1
values[3]	42	1			T2	3		T28	1		T109	3
values[4]	47	1			T9	1		T30	1		T109	2
values[5]	62	1			T18	1		T30	4		T46	1
values[6]	61	1			T2	1		T9	1		T18	1
values[7]	50	1			T2	1		T25	1		T26	1
values[8]	57	1			T2	5		T9	1		T18	1
values[9]	67	1			T2	2		T9	3		T18	1
values[10]	52	1			T12	1		T27	3		T29	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2371	1			T1	1		T2	6		T3	1
auto[UartTx]	values[1]	12	1			T25	1		T153	1		T114	1
auto[UartTx]	values[2]	14	1			T29	1		T46	1		T50	1
auto[UartTx]	values[3]	16	1			T2	1		T28	1		T338	1
auto[UartTx]	values[4]	14	1			T9	1		T150	2		T107	2
auto[UartTx]	values[5]	20	1			T18	1		T30	2		T46	1
auto[UartTx]	values[6]	15	1			T2	1		T9	1		T18	1
auto[UartTx]	values[7]	15	1			T25	1		T29	1		T30	1
auto[UartTx]	values[8]	23	1			T2	2		T26	3		T51	1
auto[UartTx]	values[9]	28	1			T2	1		T9	2		T25	1
auto[UartTx]	values[10]	20	1			T27	2		T339	1		T114	2
auto[UartRx]	values[0]	2188	1			T1	1		T2	4		T3	1
auto[UartRx]	values[1]	33	1			T9	2		T27	1		T150	2
auto[UartRx]	values[2]	32	1			T18	1		T12	1		T25	1
auto[UartRx]	values[3]	26	1			T2	2		T109	3		T50	1
auto[UartRx]	values[4]	33	1			T30	1		T109	2		T138	1
auto[UartRx]	values[5]	42	1			T30	2		T50	1		T108	1
auto[UartRx]	values[6]	46	1			T25	2		T26	1		T29	1
auto[UartRx]	values[7]	35	1			T2	1		T26	1		T30	1
auto[UartRx]	values[8]	34	1			T2	3		T9	1		T18	1
auto[UartRx]	values[9]	39	1			T2	1		T9	1		T18	1
auto[UartRx]	values[10]	32	1			T12	1		T27	1		T29	1