Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2211	1			T1	15		T3	1		T4	5
auto[BaudRate115200]	1958	1			T1	9		T2	2		T4	1
auto[BaudRate230400]	2078	1			T1	6		T2	3		T3	4
auto[BaudRate128Kbps]	1989	1			T1	9		T5	1		T6	2
auto[BaudRate256Kbps]	2138	1			T1	6		T2	6		T3	1
auto[BaudRate1Mbps]	1908	1			T2	5		T3	1		T6	2
auto[BaudRate1p5Mbps]	1414	1			T2	3		T5	1		T7	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1860	1			T340	39		T253	1		T254	5
freqs[25]	1252	1			T6	10		T251	10		T29	64
freqs[48]	683	1			T9	94		T14	2		T299	1
freqs[50]	484	1			T4	8		T119	9		T257	8
freqs[100]	1509	1			T7	8		T8	7		T84	6

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	217	1			T340	3		T254	1		T176	1
auto[BaudRate9600]	freqs[25]	247	1			T29	6		T341	12		T152	2
auto[BaudRate9600]	freqs[48]	88	1			T9	15		T16	2		T144	1
auto[BaudRate9600]	freqs[50]	65	1			T4	5		T119	1		T342	1
auto[BaudRate9600]	freqs[100]	245	1			T8	1		T13	2		T28	11
auto[BaudRate115200]	freqs[24]	283	1			T340	9		T253	1		T254	2
auto[BaudRate115200]	freqs[25]	159	1			T6	3		T29	7		T152	2
auto[BaudRate115200]	freqs[48]	96	1			T9	8		T16	3		T184	2
auto[BaudRate115200]	freqs[50]	48	1			T4	1		T119	2		T342	1
auto[BaudRate115200]	freqs[100]	200	1			T7	2		T84	1		T28	4
auto[BaudRate230400]	freqs[24]	328	1			T340	6		T176	3		T280	2
auto[BaudRate230400]	freqs[25]	163	1			T6	1		T29	5		T152	2
auto[BaudRate230400]	freqs[48]	105	1			T9	16		T14	1		T16	3
auto[BaudRate230400]	freqs[50]	61	1			T4	1		T119	2		T257	1
auto[BaudRate230400]	freqs[100]	212	1			T8	2		T13	1		T28	14
auto[BaudRate128Kbps]	freqs[24]	257	1			T340	9		T254	1		T260	1
auto[BaudRate128Kbps]	freqs[25]	175	1			T6	2		T29	14		T341	3
auto[BaudRate128Kbps]	freqs[48]	110	1			T9	16		T16	6		T40	2
auto[BaudRate128Kbps]	freqs[50]	76	1			T119	1		T257	1		T342	2
auto[BaudRate128Kbps]	freqs[100]	231	1			T7	3		T8	2		T84	2
auto[BaudRate256Kbps]	freqs[24]	296	1			T340	3		T254	1		T158	3
auto[BaudRate256Kbps]	freqs[25]	190	1			T6	2		T251	5		T29	11
auto[BaudRate256Kbps]	freqs[48]	81	1			T9	9		T14	1		T16	1
auto[BaudRate256Kbps]	freqs[50]	64	1			T4	1		T257	1		T44	3
auto[BaudRate256Kbps]	freqs[100]	190	1			T7	1		T8	1		T84	2
auto[BaudRate1Mbps]	freqs[24]	297	1			T340	9		T176	1		T158	1
auto[BaudRate1Mbps]	freqs[25]	218	1			T6	2		T251	3		T29	19
auto[BaudRate1Mbps]	freqs[48]	96	1			T9	14		T299	1		T16	1
auto[BaudRate1Mbps]	freqs[50]	84	1			T119	1		T257	2		T44	3
auto[BaudRate1Mbps]	freqs[100]	219	1			T8	1		T84	1		T13	4
auto[BaudRate1p5Mbps]	freqs[25]	100	1			T251	2		T29	2		T152	1
auto[BaudRate1p5Mbps]	freqs[48]	107	1			T9	16		T16	2		T40	2
auto[BaudRate1p5Mbps]	freqs[50]	86	1			T119	2		T257	3		T44	2
auto[BaudRate1p5Mbps]	freqs[100]	212	1			T7	2		T28	3		T292	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded