Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	32770049	1			T1	8		T2	15657		T3	7
all_levels[1]	184734	1			T2	338		T3	5		T4	40
all_levels[2]	2235	1			T4	11		T7	2		T8	1
all_levels[3]	1111	1			T3	2		T4	2		T8	1
all_levels[4]	756	1			T4	1		T7	3		T8	4
all_levels[5]	576	1			T3	1		T4	2		T7	1
all_levels[6]	431	1			T7	1		T8	2		T9	3
all_levels[7]	354	1			T9	1		T11	1		T84	2
all_levels[8]	256	1			T4	1		T7	2		T8	3
all_levels[9]	233	1			T7	2		T8	1		T9	1
all_levels[10]	207	1			T7	2		T8	1		T9	1
all_levels[11]	196	1			T4	1		T8	3		T84	1
all_levels[12]	179	1			T7	1		T16	1		T118	3
all_levels[13]	133	1			T7	1		T34	1		T27	1
all_levels[14]	107	1			T7	1		T8	1		T84	1
all_levels[15]	140	1			T8	1		T9	2		T12	1
all_levels[16]	109	1			T8	1		T119	1		T16	1
all_levels[17]	113	1			T11	1		T12	2		T119	2
all_levels[18]	106	1			T9	1		T12	1		T16	1
all_levels[19]	83	1			T84	1		T120	1		T110	1
all_levels[20]	73	1			T12	1		T120	1		T29	1
all_levels[21]	69	1			T35	1		T121	1		T122	2
all_levels[22]	69	1			T7	2		T11	1		T123	1
all_levels[23]	52	1			T4	1		T123	4		T124	2
all_levels[24]	72	1			T4	1		T8	3		T84	1
all_levels[25]	49	1			T11	1		T12	1		T34	1
all_levels[26]	46	1			T9	1		T12	1		T29	1
all_levels[27]	54	1			T8	2		T34	1		T16	1
all_levels[28]	59	1			T125	1		T27	2		T29	2
all_levels[29]	33	1			T3	1		T110	1		T126	1
all_levels[30]	39	1			T8	1		T27	1		T29	2
all_levels[31]	35	1			T12	1		T29	1		T127	1
all_levels[32]	23	1			T128	1		T129	1		T130	1
all_levels[33]	30	1			T131	3		T46	1		T132	1
all_levels[34]	33	1			T126	1		T49	1		T133	2
all_levels[35]	20	1			T120	1		T27	1		T134	1
all_levels[36]	21	1			T29	1		T135	1		T136	1
all_levels[37]	26	1			T12	1		T137	1		T49	1
all_levels[38]	22	1			T9	1		T12	1		T119	1
all_levels[39]	7	1			T138	1		T139	1		T140	1
all_levels[40]	24	1			T135	1		T126	1		T141	2
all_levels[41]	19	1			T126	1		T132	1		T142	1
all_levels[42]	22	1			T124	1		T143	1		T132	2
all_levels[43]	23	1			T144	1		T50	1		T145	1
all_levels[44]	18	1			T4	1		T43	1		T146	1
all_levels[45]	19	1			T4	1		T119	1		T49	1
all_levels[46]	10	1			T35	1		T118	1		T27	1
all_levels[47]	10	1			T147	1		T148	1		T149	1
all_levels[48]	9	1			T12	1		T150	1		T151	1
all_levels[49]	8	1			T152	1		T153	1		T130	1
all_levels[50]	13	1			T29	1		T135	1		T154	1
all_levels[51]	11	1			T27	1		T135	2		T155	1
all_levels[52]	13	1			T136	1		T156	1		T157	1
all_levels[53]	19	1			T158	1		T50	1		T133	1
all_levels[54]	6	1			T128	1		T159	1		T160	1
all_levels[55]	9	1			T126	3		T161	1		T162	1
all_levels[56]	5	1			T163	1		T164	1		T165	1
all_levels[57]	8	1			T26	1		T166	1		T167	3
all_levels[58]	8	1			T118	1		T26	1		T154	1
all_levels[59]	13	1			T137	1		T168	1		T169	1
all_levels[60]	5	1			T35	1		T130	1		T170	2
all_levels[61]	9	1			T4	1		T171	2		T172	1
all_levels[62]	8	1			T27	1		T173	2		T174	1
all_levels[63]	6	1			T4	1		T13	1		T157	1
all_levels[64]	117	1			T3	1		T12	1		T34	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32958484

1

T2

15985

T3

11

T4

259

auto[1]

4868

1

T1

8

T2

10

T3

6

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[45] , all_levels[46]]	[auto[1]]	--	--	2
[all_levels[48] , all_levels[49]]	[auto[1]]	--	--	2
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	32765650	1			T2	15647		T3	5		T4	195
all_levels[0]	auto[1]	4399	1			T1	8		T2	10		T3	2
all_levels[1]	auto[0]	184649	1			T2	338		T3	2		T4	40
all_levels[1]	auto[1]	85	1			T3	3		T18	1		T13	1
all_levels[2]	auto[0]	2211	1			T4	11		T7	2		T8	1
all_levels[2]	auto[1]	24	1			T119	1		T13	1		T131	1
all_levels[3]	auto[0]	1086	1			T3	1		T4	2		T8	1
all_levels[3]	auto[1]	25	1			T3	1		T175	1		T176	1
all_levels[4]	auto[0]	735	1			T4	1		T7	3		T8	3
all_levels[4]	auto[1]	21	1			T8	1		T137	1		T177	2
all_levels[5]	auto[0]	552	1			T3	1		T4	2		T7	1
all_levels[5]	auto[1]	24	1			T152	2		T178	2		T179	2
all_levels[6]	auto[0]	420	1			T7	1		T8	2		T9	3
all_levels[6]	auto[1]	11	1			T34	1		T180	2		T181	2
all_levels[7]	auto[0]	338	1			T9	1		T11	1		T84	2
all_levels[7]	auto[1]	16	1			T182	1		T183	1		T130	1
all_levels[8]	auto[0]	238	1			T4	1		T7	2		T8	2
all_levels[8]	auto[1]	18	1			T8	1		T184	2		T185	1
all_levels[9]	auto[0]	224	1			T7	2		T8	1		T9	1
all_levels[9]	auto[1]	9	1			T120	1		T50	1		T186	1
all_levels[10]	auto[0]	195	1			T7	1		T8	1		T9	1
all_levels[10]	auto[1]	12	1			T7	1		T187	1		T167	2
all_levels[11]	auto[0]	176	1			T4	1		T8	2		T84	1
all_levels[11]	auto[1]	20	1			T8	1		T188	3		T124	1
all_levels[12]	auto[0]	166	1			T7	1		T16	1		T118	1
all_levels[12]	auto[1]	13	1			T118	2		T177	1		T189	1
all_levels[13]	auto[0]	127	1			T7	1		T34	1		T27	1
all_levels[13]	auto[1]	6	1			T190	1		T191	1		T192	1
all_levels[14]	auto[0]	97	1			T7	1		T8	1		T84	1
all_levels[14]	auto[1]	10	1			T193	2		T194	1		T195	3
all_levels[15]	auto[0]	126	1			T8	1		T9	2		T12	1
all_levels[15]	auto[1]	14	1			T196	1		T134	2		T197	1
all_levels[16]	auto[0]	104	1			T8	1		T119	1		T16	1
all_levels[16]	auto[1]	5	1			T198	1		T199	2		T200	1
all_levels[17]	auto[0]	98	1			T11	1		T12	1		T119	2
all_levels[17]	auto[1]	15	1			T12	1		T201	1		T202	3
all_levels[18]	auto[0]	96	1			T9	1		T12	1		T16	1
all_levels[18]	auto[1]	10	1			T203	3		T204	1		T190	2
all_levels[19]	auto[0]	81	1			T84	1		T120	1		T110	1
all_levels[19]	auto[1]	2	1			T205	1		T206	1		-	-
all_levels[20]	auto[0]	70	1			T12	1		T120	1		T29	1
all_levels[20]	auto[1]	3	1			T207	2		T208	1		-	-
all_levels[21]	auto[0]	60	1			T35	1		T121	1		T122	1
all_levels[21]	auto[1]	9	1			T122	1		T209	1		T210	2
all_levels[22]	auto[0]	64	1			T7	1		T11	1		T123	1
all_levels[22]	auto[1]	5	1			T7	1		T211	3		T212	1
all_levels[23]	auto[0]	49	1			T4	1		T123	2		T124	2
all_levels[23]	auto[1]	3	1			T123	2		T213	1		-	-
all_levels[24]	auto[0]	65	1			T4	1		T8	3		T84	1
all_levels[24]	auto[1]	7	1			T214	1		T215	1		T216	2
all_levels[25]	auto[0]	45	1			T11	1		T12	1		T34	1
all_levels[25]	auto[1]	4	1			T217	1		T218	1		T219	1
all_levels[26]	auto[0]	43	1			T9	1		T12	1		T29	1
all_levels[26]	auto[1]	3	1			T220	1		T189	1		T221	1
all_levels[27]	auto[0]	51	1			T8	2		T34	1		T16	1
all_levels[27]	auto[1]	3	1			T141	1		T207	1		T222	1
all_levels[28]	auto[0]	53	1			T125	1		T27	2		T29	2
all_levels[28]	auto[1]	6	1			T126	1		T42	1		T214	1
all_levels[29]	auto[0]	31	1			T3	1		T110	1		T126	1
all_levels[29]	auto[1]	2	1			T223	1		T224	1		-	-
all_levels[30]	auto[0]	37	1			T8	1		T27	1		T29	2
all_levels[30]	auto[1]	2	1			T206	2		-	-		-	-
all_levels[31]	auto[0]	30	1			T12	1		T29	1		T127	1
all_levels[31]	auto[1]	5	1			T225	1		T201	1		T226	1
all_levels[32]	auto[0]	22	1			T128	1		T129	1		T130	1
all_levels[32]	auto[1]	1	1			T227	1		-	-		-	-
all_levels[33]	auto[0]	25	1			T131	1		T46	1		T132	1
all_levels[33]	auto[1]	5	1			T131	2		T228	2		T192	1
all_levels[34]	auto[0]	29	1			T126	1		T49	1		T133	1
all_levels[34]	auto[1]	4	1			T133	1		T229	1		T230	2
all_levels[35]	auto[0]	19	1			T120	1		T27	1		T134	1
all_levels[35]	auto[1]	1	1			T138	1		-	-		-	-
all_levels[36]	auto[0]	18	1			T29	1		T135	1		T136	1
all_levels[36]	auto[1]	3	1			T231	2		T232	1		-	-
all_levels[37]	auto[0]	23	1			T12	1		T137	1		T49	1
all_levels[37]	auto[1]	3	1			T233	2		T234	1		-	-
all_levels[38]	auto[0]	20	1			T9	1		T12	1		T119	1
all_levels[38]	auto[1]	2	1			T235	1		T236	1		-	-
all_levels[39]	auto[0]	7	1			T138	1		T139	1		T140	1
all_levels[40]	auto[0]	15	1			T135	1		T126	1		T141	1
all_levels[40]	auto[1]	9	1			T141	1		T237	6		T238	1
all_levels[41]	auto[0]	18	1			T126	1		T132	1		T142	1
all_levels[41]	auto[1]	1	1			T104	1		-	-		-	-
all_levels[42]	auto[0]	16	1			T124	1		T143	1		T132	2
all_levels[42]	auto[1]	6	1			T231	2		T105	1		T239	3
all_levels[43]	auto[0]	21	1			T144	1		T50	1		T145	1
all_levels[43]	auto[1]	2	1			T240	1		T241	1		-	-
all_levels[44]	auto[0]	16	1			T4	1		T43	1		T146	1
all_levels[44]	auto[1]	2	1			T203	1		T242	1		-	-
all_levels[45]	auto[0]	19	1			T4	1		T119	1		T49	1
all_levels[46]	auto[0]	10	1			T35	1		T118	1		T27	1
all_levels[47]	auto[0]	7	1			T147	1		T148	1		T149	1
all_levels[47]	auto[1]	3	1			T243	2		T244	1		-	-
all_levels[48]	auto[0]	9	1			T12	1		T150	1		T151	1
all_levels[49]	auto[0]	8	1			T152	1		T153	1		T130	1
all_levels[50]	auto[0]	12	1			T29	1		T135	1		T154	1
all_levels[50]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[51]	auto[0]	11	1			T27	1		T135	2		T155	1
all_levels[52]	auto[0]	12	1			T136	1		T156	1		T157	1
all_levels[52]	auto[1]	1	1			T202	1		-	-		-	-
all_levels[53]	auto[0]	17	1			T158	1		T50	1		T133	1
all_levels[53]	auto[1]	2	1			T246	2		-	-		-	-
all_levels[54]	auto[0]	6	1			T128	1		T159	1		T160	1
all_levels[55]	auto[0]	6	1			T126	1		T161	1		T162	1
all_levels[55]	auto[1]	3	1			T126	2		T245	1		-	-
all_levels[56]	auto[0]	5	1			T163	1		T164	1		T165	1
all_levels[57]	auto[0]	6	1			T26	1		T166	1		T167	1
all_levels[57]	auto[1]	2	1			T167	2		-	-		-	-
all_levels[58]	auto[0]	8	1			T118	1		T26	1		T154	1
all_levels[59]	auto[0]	8	1			T137	1		T168	1		T169	1
all_levels[59]	auto[1]	5	1			T247	3		T248	2		-	-
all_levels[60]	auto[0]	4	1			T35	1		T130	1		T170	1
all_levels[60]	auto[1]	1	1			T170	1		-	-		-	-
all_levels[61]	auto[0]	6	1			T4	1		T171	1		T172	1
all_levels[61]	auto[1]	3	1			T171	1		T249	2		-	-
all_levels[62]	auto[0]	7	1			T27	1		T173	1		T174	1
all_levels[62]	auto[1]	1	1			T173	1		-	-		-	-
all_levels[63]	auto[0]	6	1			T4	1		T13	1		T157	1
all_levels[64]	auto[0]	101	1			T3	1		T12	1		T34	1
all_levels[64]	auto[1]	16	1			T250	2		T154	1		T213	3