Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	117712	1			T1	1		T2	61		T3	4
all_pins[1]	117712	1			T1	1		T2	61		T3	4
all_pins[2]	117712	1			T1	1		T2	61		T3	4
all_pins[3]	117712	1			T1	1		T2	61		T3	4
all_pins[4]	117712	1			T1	1		T2	61		T3	4
all_pins[5]	117712	1			T1	1		T2	61		T3	4
all_pins[6]	117712	1			T1	1		T2	61		T3	4
all_pins[7]	117712	1			T1	1		T2	61		T3	4
all_pins[8]	117712	1			T1	1		T2	61		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1013852	1			T1	9		T2	493		T3	34
values[0x1]	45556	1			T2	56		T3	2		T4	51
transitions[0x0=>0x1]	37268	1			T2	52		T3	2		T4	49
transitions[0x1=>0x0]	37074	1			T2	53		T3	2		T4	48

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	95646	1			T1	1		T2	28		T3	4
all_pins[0]	values[0x1]	22066	1			T2	33		T4	20		T5	3
all_pins[0]	transitions[0x0=>0x1]	21279	1			T2	33		T4	20		T5	3
all_pins[0]	transitions[0x1=>0x0]	1070	1			T2	1		T3	1		T9	5
all_pins[1]	values[0x0]	115855	1			T1	1		T2	60		T3	3
all_pins[1]	values[0x1]	1857	1			T2	1		T3	1		T9	10
all_pins[1]	transitions[0x0=>0x1]	1742	1			T2	1		T3	1		T9	10
all_pins[1]	transitions[0x1=>0x0]	2383	1			T2	5		T4	2		T6	6
all_pins[2]	values[0x0]	115214	1			T1	1		T2	56		T3	4
all_pins[2]	values[0x1]	2498	1			T2	5		T4	2		T6	6
all_pins[2]	transitions[0x0=>0x1]	2413	1			T2	4		T4	2		T6	6
all_pins[2]	transitions[0x1=>0x0]	234	1			T12	5		T13	1		T16	5
all_pins[3]	values[0x0]	117393	1			T1	1		T2	60		T3	4
all_pins[3]	values[0x1]	319	1			T2	1		T9	1		T12	9
all_pins[3]	transitions[0x0=>0x1]	271	1			T2	1		T9	1		T12	7
all_pins[3]	transitions[0x1=>0x0]	426	1			T2	4		T9	3		T12	2
all_pins[4]	values[0x0]	117238	1			T1	1		T2	57		T3	4
all_pins[4]	values[0x1]	474	1			T2	4		T9	3		T12	4
all_pins[4]	transitions[0x0=>0x1]	380	1			T2	4		T9	3		T12	4
all_pins[4]	transitions[0x1=>0x0]	189	1			T2	2		T12	3		T26	2
all_pins[5]	values[0x0]	117429	1			T1	1		T2	59		T3	4
all_pins[5]	values[0x1]	283	1			T2	2		T12	3		T16	3
all_pins[5]	transitions[0x0=>0x1]	227	1			T2	2		T12	3		T16	3
all_pins[5]	transitions[0x1=>0x0]	839	1			T2	4		T8	4		T9	1
all_pins[6]	values[0x0]	116817	1			T1	1		T2	57		T3	4
all_pins[6]	values[0x1]	895	1			T2	4		T8	4		T9	1
all_pins[6]	transitions[0x0=>0x1]	846	1			T2	4		T8	4		T9	1
all_pins[6]	transitions[0x1=>0x0]	322	1			T2	2		T4	8		T9	2
all_pins[7]	values[0x0]	117341	1			T1	1		T2	59		T3	4
all_pins[7]	values[0x1]	371	1			T2	2		T4	8		T9	2
all_pins[7]	transitions[0x0=>0x1]	195	1			T2	1		T4	8		T9	2
all_pins[7]	transitions[0x1=>0x0]	16617	1			T2	3		T3	1		T4	21
all_pins[8]	values[0x0]	100919	1			T1	1		T2	57		T3	3
all_pins[8]	values[0x1]	16793	1			T2	4		T3	1		T4	21
all_pins[8]	transitions[0x0=>0x1]	9915	1			T2	2		T3	1		T4	19
all_pins[8]	transitions[0x1=>0x0]	14994	1			T2	32		T4	17		T5	1