Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8055530	1			T2	23		T3	16		T4	41
all_levels[1]	2139867	1			T2	2		T6	2371		T7	24
all_levels[2]	285487	1			T2	12		T4	1		T6	2367
all_levels[3]	217328	1			T2	3		T4	196		T6	2352
all_levels[4]	661084	1			T2	1		T4	6		T5	2
all_levels[5]	215272	1			T2	1		T4	15		T6	2353
all_levels[6]	221675	1			T2	1		T6	2353		T9	202
all_levels[7]	237395	1			T2	1		T6	2355		T8	1
all_levels[8]	344657	1			T2	1		T6	2367		T8	3
all_levels[9]	214343	1			T2	3		T6	2385		T7	3
all_levels[10]	348008	1			T2	1		T5	3		T6	2576
all_levels[11]	216013	1			T2	1		T6	8548		T8	1
all_levels[12]	248048	1			T2	1		T6	1975		T9	235
all_levels[13]	271346	1			T2	1		T6	1032		T9	186
all_levels[14]	233863	1			T6	1019		T9	190		T32	31
all_levels[15]	337466	1			T2	1		T6	1033		T9	228
all_levels[16]	311900	1			T2	1		T6	1027		T9	124
all_levels[17]	761617	1			T2	3		T5	8		T6	1027
all_levels[18]	326193	1			T2	1		T6	1032		T9	306
all_levels[19]	198955	1			T2	1		T6	1033		T9	359
all_levels[20]	656158	1			T2	1		T6	1031		T9	331
all_levels[21]	253065	1			T2	3		T5	2		T6	1033
all_levels[22]	181932	1			T2	1		T6	1033		T9	484
all_levels[23]	494668	1			T2	1		T6	1030		T9	456
all_levels[24]	508355	1			T2	1		T6	1032		T9	224
all_levels[25]	323926	1			T2	2		T6	1026		T9	556
all_levels[26]	536165	1			T2	3		T6	1033		T9	565
all_levels[27]	158115	1			T5	5		T6	1033		T9	361
all_levels[28]	423624	1			T2	1		T5	2		T6	1030
all_levels[29]	515914	1			T2	2		T6	1031		T8	1
all_levels[30]	164377	1			T2	1		T5	1		T6	1028
all_levels[31]	506075	1			T2	149		T6	1105		T8	2
all_levels[32]	12394527	1			T2	15769		T3	2		T6	10210

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32958484

1

T2

15985

T3

11

T4

259

auto[1]

4464

1

T2

8

T3

7

T5

8

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8052996	1			T2	15		T3	10		T4	41
all_levels[0]	auto[1]	2534	1			T2	8		T3	6		T5	3
all_levels[1]	auto[0]	2139548	1			T2	2		T6	2371		T7	22
all_levels[1]	auto[1]	319	1			T7	2		T13	2		T37	2
all_levels[2]	auto[0]	285447	1			T2	12		T4	1		T6	2367
all_levels[2]	auto[1]	40	1			T118	2		T121	1		T127	1
all_levels[3]	auto[0]	217178	1			T2	3		T4	196		T6	2352
all_levels[3]	auto[1]	150	1			T16	20		T280	5		T30	1
all_levels[4]	auto[0]	661054	1			T2	1		T4	6		T5	2
all_levels[4]	auto[1]	30	1			T254	1		T124	2		T344	1
all_levels[5]	auto[0]	215231	1			T2	1		T4	15		T6	2353
all_levels[5]	auto[1]	41	1			T123	2		T43	2		T271	2
all_levels[6]	auto[0]	221631	1			T2	1		T6	2353		T9	202
all_levels[6]	auto[1]	44	1			T256	1		T281	3		T336	1
all_levels[7]	auto[0]	237273	1			T2	1		T6	2355		T8	1
all_levels[7]	auto[1]	122	1			T175	2		T15	25		T301	1
all_levels[8]	auto[0]	344629	1			T2	1		T6	2367		T8	3
all_levels[8]	auto[1]	28	1			T185	1		T43	2		T345	1
all_levels[9]	auto[0]	214299	1			T2	3		T6	2385		T7	2
all_levels[9]	auto[1]	44	1			T7	1		T309	4		T303	1
all_levels[10]	auto[0]	347979	1			T2	1		T5	2		T6	2576
all_levels[10]	auto[1]	29	1			T5	1		T175	1		T196	2
all_levels[11]	auto[0]	215996	1			T2	1		T6	8548		T8	1
all_levels[11]	auto[1]	17	1			T279	1		T346	2		T347	2
all_levels[12]	auto[0]	248027	1			T2	1		T6	1975		T9	235
all_levels[12]	auto[1]	21	1			T348	2		T349	1		T350	1
all_levels[13]	auto[0]	271310	1			T2	1		T6	1032		T9	186
all_levels[13]	auto[1]	36	1			T256	1		T126	1		T309	1
all_levels[14]	auto[0]	233837	1			T6	1019		T9	190		T32	31
all_levels[14]	auto[1]	26	1			T175	1		T35	2		T351	5
all_levels[15]	auto[0]	337364	1			T2	1		T6	1033		T9	228
all_levels[15]	auto[1]	102	1			T135	8		T345	1		T295	10
all_levels[16]	auto[0]	311882	1			T2	1		T6	1027		T9	124
all_levels[16]	auto[1]	18	1			T119	1		T185	2		T42	2
all_levels[17]	auto[0]	761602	1			T2	3		T5	6		T6	1027
all_levels[17]	auto[1]	15	1			T5	2		T43	1		T291	1
all_levels[18]	auto[0]	326179	1			T2	1		T6	1032		T9	306
all_levels[18]	auto[1]	14	1			T34	2		T134	1		T179	2
all_levels[19]	auto[0]	198931	1			T2	1		T6	1033		T9	359
all_levels[19]	auto[1]	24	1			T291	2		T129	1		T75	1
all_levels[20]	auto[0]	656122	1			T2	1		T6	1031		T9	331
all_levels[20]	auto[1]	36	1			T135	3		T131	1		T109	1
all_levels[21]	auto[0]	253050	1			T2	3		T5	2		T6	1033
all_levels[21]	auto[1]	15	1			T12	1		T318	2		T300	2
all_levels[22]	auto[0]	181901	1			T2	1		T6	1033		T9	484
all_levels[22]	auto[1]	31	1			T27	1		T126	1		T193	2
all_levels[23]	auto[0]	494652	1			T2	1		T6	1030		T9	456
all_levels[23]	auto[1]	16	1			T179	1		T352	4		T353	2
all_levels[24]	auto[0]	508322	1			T2	1		T6	1032		T9	224
all_levels[24]	auto[1]	33	1			T12	2		T152	2		T133	2
all_levels[25]	auto[0]	323906	1			T2	2		T6	1026		T9	556
all_levels[25]	auto[1]	20	1			T18	1		T318	2		T316	1
all_levels[26]	auto[0]	536143	1			T2	3		T6	1033		T9	565
all_levels[26]	auto[1]	22	1			T118	1		T37	1		T201	1
all_levels[27]	auto[0]	158096	1			T5	3		T6	1033		T9	361
all_levels[27]	auto[1]	19	1			T5	2		T337	1		T284	1
all_levels[28]	auto[0]	423599	1			T2	1		T5	2		T6	1030
all_levels[28]	auto[1]	25	1			T119	1		T185	2		T50	1
all_levels[29]	auto[0]	515897	1			T2	2		T6	1031		T8	1
all_levels[29]	auto[1]	17	1			T334	1		T51	1		T220	1
all_levels[30]	auto[0]	164361	1			T2	1		T5	1		T6	1028
all_levels[30]	auto[1]	16	1			T34	4		T185	1		T137	1
all_levels[31]	auto[0]	506041	1			T2	149		T6	1105		T8	2
all_levels[31]	auto[1]	34	1			T119	1		T25	1		T193	1
all_levels[32]	auto[0]	12394001	1			T2	15769		T3	1		T6	10210
all_levels[32]	auto[1]	526	1			T3	1		T8	2		T32	1