Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	821	1			T2	11		T9	7		T12	21
all_values[1]	821	1			T2	11		T9	7		T12	21
all_values[2]	821	1			T2	11		T9	7		T12	21
all_values[3]	821	1			T2	11		T9	7		T12	21
all_values[4]	821	1			T2	11		T9	7		T12	21
all_values[5]	821	1			T2	11		T9	7		T12	21
all_values[6]	821	1			T2	11		T9	7		T12	21
all_values[7]	821	1			T2	11		T9	7		T12	21
all_values[8]	821	1			T2	11		T9	7		T12	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3953

1

T2

60

T9

41

T12

108

auto[1]

3436

1

T2

39

T9

22

T12

81

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2434

1

T2

29

T9

19

T12

58

auto[1]

4955

1

T2

70

T9

44

T12

131

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4345

1

T2

54

T9

33

T12

104

auto[1]

3044

1

T2

45

T9

30

T12

85

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	255	1			T2	3		T9	4		T12	9
all_values[0]	auto[0]	auto[1]	auto[1]	229	1			T2	3		T12	6		T25	2
all_values[0]	auto[1]	auto[0]	auto[1]	200	1			T2	3		T12	4		T25	2
all_values[0]	auto[1]	auto[1]	auto[1]	137	1			T2	2		T9	3		T12	2
all_values[1]	auto[0]	auto[0]	auto[0]	250	1			T2	3		T9	2		T12	11
all_values[1]	auto[0]	auto[1]	auto[0]	244	1			T2	6		T12	6		T25	1
all_values[1]	auto[1]	auto[0]	auto[1]	176	1			T2	2		T9	2		T12	2
all_values[1]	auto[1]	auto[1]	auto[1]	151	1			T9	3		T12	2		T25	1
all_values[2]	auto[0]	auto[0]	auto[0]	166	1			T9	2		T12	2		T26	1
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T9	1		T12	1		T29	1
all_values[2]	auto[0]	auto[1]	auto[0]	164	1			T2	1		T9	1		T12	4
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T2	1		T12	2		T25	3
all_values[2]	auto[1]	auto[0]	auto[1]	191	1			T2	5		T9	1		T12	7
all_values[2]	auto[1]	auto[1]	auto[1]	160	1			T2	4		T9	2		T12	5
all_values[3]	auto[0]	auto[0]	auto[0]	183	1			T2	4		T9	1		T12	3
all_values[3]	auto[0]	auto[0]	auto[1]	77	1			T2	1		T9	3		T12	1
all_values[3]	auto[0]	auto[1]	auto[0]	157	1			T2	2		T9	1		T12	2
all_values[3]	auto[0]	auto[1]	auto[1]	83	1			T12	2		T26	1		T114	1
all_values[3]	auto[1]	auto[0]	auto[1]	192	1			T2	2		T9	1		T12	7
all_values[3]	auto[1]	auto[1]	auto[1]	129	1			T2	2		T9	1		T12	6
all_values[4]	auto[0]	auto[0]	auto[0]	164	1			T2	3		T9	1		T12	5
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T2	1		T9	1		T12	2
all_values[4]	auto[0]	auto[1]	auto[0]	140	1			T2	1		T12	1		T25	2
all_values[4]	auto[0]	auto[1]	auto[1]	80	1			T2	2		T9	1		T12	1
all_values[4]	auto[1]	auto[0]	auto[1]	196	1			T2	3		T9	1		T12	8
all_values[4]	auto[1]	auto[1]	auto[1]	158	1			T2	1		T9	3		T12	4
all_values[5]	auto[0]	auto[0]	auto[0]	170	1			T2	2		T9	5		T12	6
all_values[5]	auto[0]	auto[0]	auto[1]	74	1			T2	1		T12	1		T25	1
all_values[5]	auto[0]	auto[1]	auto[0]	146	1			T2	1		T12	4		T25	4
all_values[5]	auto[0]	auto[1]	auto[1]	83	1			T12	1		T27	1		T109	1
all_values[5]	auto[1]	auto[0]	auto[1]	180	1			T2	3		T9	2		T12	6
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T2	4		T12	3		T27	1
all_values[6]	auto[0]	auto[0]	auto[0]	213	1			T2	1		T9	2		T12	3
all_values[6]	auto[0]	auto[0]	auto[1]	76	1			T2	3		T12	1		T25	1
all_values[6]	auto[0]	auto[1]	auto[0]	142	1			T2	1		T9	2		T12	2
all_values[6]	auto[0]	auto[1]	auto[1]	74	1			T2	2		T12	4		T25	1
all_values[6]	auto[1]	auto[0]	auto[1]	188	1			T2	4		T9	3		T12	7
all_values[6]	auto[1]	auto[1]	auto[1]	128	1			T12	4		T25	1		T27	1
all_values[7]	auto[0]	auto[0]	auto[0]	160	1			T2	3		T9	2		T12	5
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T12	3		T25	2		T115	1
all_values[7]	auto[0]	auto[1]	auto[0]	135	1			T2	1		T12	4		T26	1
all_values[7]	auto[0]	auto[1]	auto[1]	89	1			T2	1		T9	1		T12	1
all_values[7]	auto[1]	auto[0]	auto[1]	194	1			T2	3		T9	3		T12	3
all_values[7]	auto[1]	auto[1]	auto[1]	158	1			T2	3		T9	1		T12	5
all_values[8]	auto[0]	auto[0]	auto[1]	242	1			T2	6		T9	3		T12	6
all_values[8]	auto[0]	auto[1]	auto[1]	241	1			T2	1		T12	5		T25	4
all_values[8]	auto[1]	auto[0]	auto[1]	168	1			T2	4		T9	1		T12	5
all_values[8]	auto[1]	auto[1]	auto[1]	170	1			T9	3		T12	5		T25	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal