Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.55


Total test records in report: 1317
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T1256 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2129492879 Jul 17 07:10:00 PM PDT 24 Jul 17 07:10:08 PM PDT 24 176799000 ps
T1257 /workspace/coverage/cover_reg_top/0.uart_intr_test.3218259468 Jul 17 07:09:38 PM PDT 24 Jul 17 07:09:40 PM PDT 24 45950485 ps
T1258 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1959177417 Jul 17 07:10:59 PM PDT 24 Jul 17 07:11:01 PM PDT 24 94860408 ps
T1259 /workspace/coverage/cover_reg_top/7.uart_csr_rw.992510610 Jul 17 07:10:01 PM PDT 24 Jul 17 07:10:08 PM PDT 24 81552464 ps
T117 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3411553730 Jul 17 07:11:00 PM PDT 24 Jul 17 07:11:03 PM PDT 24 125429453 ps
T1260 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.4228624004 Jul 17 07:09:57 PM PDT 24 Jul 17 07:10:05 PM PDT 24 18012988 ps
T1261 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2570780137 Jul 17 07:09:58 PM PDT 24 Jul 17 07:10:05 PM PDT 24 80443556 ps
T1262 /workspace/coverage/cover_reg_top/4.uart_intr_test.17903845 Jul 17 07:10:02 PM PDT 24 Jul 17 07:10:08 PM PDT 24 11300867 ps
T1263 /workspace/coverage/cover_reg_top/35.uart_intr_test.3590867455 Jul 17 07:11:03 PM PDT 24 Jul 17 07:11:09 PM PDT 24 23969181 ps
T1264 /workspace/coverage/cover_reg_top/21.uart_intr_test.3476531961 Jul 17 07:10:55 PM PDT 24 Jul 17 07:10:57 PM PDT 24 17660537 ps
T1265 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1399527257 Jul 17 07:10:00 PM PDT 24 Jul 17 07:10:08 PM PDT 24 273725105 ps
T1266 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2084825554 Jul 17 07:09:41 PM PDT 24 Jul 17 07:09:50 PM PDT 24 39633452 ps
T1267 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2944508547 Jul 17 07:10:51 PM PDT 24 Jul 17 07:10:53 PM PDT 24 318221746 ps
T1268 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2501558059 Jul 17 07:10:00 PM PDT 24 Jul 17 07:10:07 PM PDT 24 60551213 ps
T1269 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1105562428 Jul 17 07:10:00 PM PDT 24 Jul 17 07:10:06 PM PDT 24 16178401 ps
T1270 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.109766916 Jul 17 07:09:59 PM PDT 24 Jul 17 07:10:06 PM PDT 24 1310748608 ps
T1271 /workspace/coverage/cover_reg_top/47.uart_intr_test.3018310965 Jul 17 07:11:06 PM PDT 24 Jul 17 07:11:12 PM PDT 24 31793097 ps
T1272 /workspace/coverage/cover_reg_top/5.uart_intr_test.2753900206 Jul 17 07:09:54 PM PDT 24 Jul 17 07:10:03 PM PDT 24 11716284 ps
T1273 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1145700411 Jul 17 07:09:57 PM PDT 24 Jul 17 07:10:05 PM PDT 24 78038256 ps
T1274 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3234331440 Jul 17 07:10:01 PM PDT 24 Jul 17 07:10:08 PM PDT 24 49857648 ps
T1275 /workspace/coverage/cover_reg_top/25.uart_intr_test.4177120341 Jul 17 07:11:00 PM PDT 24 Jul 17 07:11:02 PM PDT 24 23451445 ps
T1276 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2734859367 Jul 17 07:11:00 PM PDT 24 Jul 17 07:11:03 PM PDT 24 34176255 ps
T1277 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3295692659 Jul 17 07:09:40 PM PDT 24 Jul 17 07:09:46 PM PDT 24 16117388 ps
T1278 /workspace/coverage/cover_reg_top/27.uart_intr_test.3184098321 Jul 17 07:11:04 PM PDT 24 Jul 17 07:11:09 PM PDT 24 16303713 ps
T1279 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2929443556 Jul 17 07:09:39 PM PDT 24 Jul 17 07:09:43 PM PDT 24 37973904 ps
T1280 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3507753306 Jul 17 07:09:41 PM PDT 24 Jul 17 07:09:49 PM PDT 24 16329984 ps
T1281 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.304371819 Jul 17 07:09:41 PM PDT 24 Jul 17 07:09:49 PM PDT 24 35357584 ps
T64 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3251425255 Jul 17 07:09:39 PM PDT 24 Jul 17 07:09:42 PM PDT 24 19207048 ps
T1282 /workspace/coverage/cover_reg_top/2.uart_tl_errors.842760952 Jul 17 07:09:39 PM PDT 24 Jul 17 07:09:44 PM PDT 24 173814310 ps
T1283 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2373757200 Jul 17 07:09:59 PM PDT 24 Jul 17 07:10:06 PM PDT 24 15780018 ps
T1284 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2517006060 Jul 17 07:11:00 PM PDT 24 Jul 17 07:11:04 PM PDT 24 89724241 ps
T1285 /workspace/coverage/cover_reg_top/44.uart_intr_test.3212046715 Jul 17 07:11:05 PM PDT 24 Jul 17 07:11:11 PM PDT 24 30423703 ps
T1286 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1689226401 Jul 17 07:09:57 PM PDT 24 Jul 17 07:10:04 PM PDT 24 40837098 ps
T1287 /workspace/coverage/cover_reg_top/16.uart_intr_test.3785863973 Jul 17 07:10:55 PM PDT 24 Jul 17 07:10:57 PM PDT 24 41134520 ps
T1288 /workspace/coverage/cover_reg_top/3.uart_intr_test.2443087458 Jul 17 07:10:01 PM PDT 24 Jul 17 07:10:08 PM PDT 24 30740110 ps
T1289 /workspace/coverage/cover_reg_top/12.uart_tl_errors.809030973 Jul 17 07:11:04 PM PDT 24 Jul 17 07:11:10 PM PDT 24 96007378 ps
T1290 /workspace/coverage/cover_reg_top/9.uart_intr_test.2974875417 Jul 17 07:09:52 PM PDT 24 Jul 17 07:10:02 PM PDT 24 40158733 ps
T65 /workspace/coverage/cover_reg_top/9.uart_csr_rw.1084527214 Jul 17 07:10:00 PM PDT 24 Jul 17 07:10:07 PM PDT 24 48573722 ps
T1291 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.399868596 Jul 17 07:10:00 PM PDT 24 Jul 17 07:10:06 PM PDT 24 17800270 ps
T1292 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1403081528 Jul 17 07:09:41 PM PDT 24 Jul 17 07:09:50 PM PDT 24 28229060 ps
T1293 /workspace/coverage/cover_reg_top/37.uart_intr_test.2707132592 Jul 17 07:11:04 PM PDT 24 Jul 17 07:11:09 PM PDT 24 68275621 ps
T66 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.714466549 Jul 17 07:10:01 PM PDT 24 Jul 17 07:10:08 PM PDT 24 29089025 ps
T1294 /workspace/coverage/cover_reg_top/11.uart_csr_rw.3154028835 Jul 17 07:10:00 PM PDT 24 Jul 17 07:10:07 PM PDT 24 17711464 ps
T1295 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2897535411 Jul 17 07:11:01 PM PDT 24 Jul 17 07:11:05 PM PDT 24 34938988 ps
T1296 /workspace/coverage/cover_reg_top/26.uart_intr_test.4034604558 Jul 17 07:10:54 PM PDT 24 Jul 17 07:10:55 PM PDT 24 16832369 ps
T1297 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1291173665 Jul 17 07:11:01 PM PDT 24 Jul 17 07:11:05 PM PDT 24 11940123 ps
T1298 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3984157816 Jul 17 07:10:02 PM PDT 24 Jul 17 07:10:08 PM PDT 24 16117408 ps
T1299 /workspace/coverage/cover_reg_top/31.uart_intr_test.368216124 Jul 17 07:10:55 PM PDT 24 Jul 17 07:10:57 PM PDT 24 26540251 ps
T1300 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2139868852 Jul 17 07:09:43 PM PDT 24 Jul 17 07:09:55 PM PDT 24 55609924 ps
T1301 /workspace/coverage/cover_reg_top/7.uart_intr_test.3750433059 Jul 17 07:09:58 PM PDT 24 Jul 17 07:10:05 PM PDT 24 59911271 ps
T1302 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.761241397 Jul 17 07:10:00 PM PDT 24 Jul 17 07:10:07 PM PDT 24 85359021 ps
T1303 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3540715428 Jul 17 07:09:52 PM PDT 24 Jul 17 07:10:01 PM PDT 24 14952528 ps
T1304 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2497439461 Jul 17 07:09:41 PM PDT 24 Jul 17 07:09:50 PM PDT 24 28462559 ps
T1305 /workspace/coverage/cover_reg_top/42.uart_intr_test.2964769048 Jul 17 07:11:03 PM PDT 24 Jul 17 07:11:07 PM PDT 24 32663185 ps
T1306 /workspace/coverage/cover_reg_top/16.uart_tl_errors.109208521 Jul 17 07:11:03 PM PDT 24 Jul 17 07:11:08 PM PDT 24 31037037 ps
T67 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.413284638 Jul 17 07:09:39 PM PDT 24 Jul 17 07:09:42 PM PDT 24 25995808 ps
T1307 /workspace/coverage/cover_reg_top/17.uart_intr_test.2332445799 Jul 17 07:11:02 PM PDT 24 Jul 17 07:11:06 PM PDT 24 15826208 ps
T1308 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3941300947 Jul 17 07:10:00 PM PDT 24 Jul 17 07:10:08 PM PDT 24 155937021 ps
T1309 /workspace/coverage/cover_reg_top/12.uart_intr_test.2931295925 Jul 17 07:10:57 PM PDT 24 Jul 17 07:10:58 PM PDT 24 12315427 ps
T1310 /workspace/coverage/cover_reg_top/15.uart_intr_test.1044167089 Jul 17 07:11:02 PM PDT 24 Jul 17 07:11:06 PM PDT 24 15206230 ps
T1311 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1797124124 Jul 17 07:09:57 PM PDT 24 Jul 17 07:10:05 PM PDT 24 28861127 ps
T1312 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3118781777 Jul 17 07:09:59 PM PDT 24 Jul 17 07:10:08 PM PDT 24 1034262929 ps
T1313 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2789284338 Jul 17 07:09:59 PM PDT 24 Jul 17 07:10:07 PM PDT 24 164005013 ps
T1314 /workspace/coverage/cover_reg_top/19.uart_intr_test.2756696124 Jul 17 07:11:00 PM PDT 24 Jul 17 07:11:03 PM PDT 24 30039512 ps
T1315 /workspace/coverage/cover_reg_top/15.uart_tl_errors.4113342554 Jul 17 07:10:55 PM PDT 24 Jul 17 07:10:57 PM PDT 24 100488466 ps
T1316 /workspace/coverage/cover_reg_top/13.uart_intr_test.2061970481 Jul 17 07:10:54 PM PDT 24 Jul 17 07:10:55 PM PDT 24 17547024 ps
T1317 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3999967910 Jul 17 07:09:58 PM PDT 24 Jul 17 07:10:05 PM PDT 24 69152418 ps

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1424173550
Short name T9
Test name
Test status
Simulation time 74686365168 ps
CPU time 354.35 seconds
Started Jul 17 05:52:10 PM PDT 24
Finished Jul 17 05:58:06 PM PDT 24
Peak memory 216464 kb
Host smart-f1ee598b-eb83-4852-8f85-6df7bcab22a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424173550 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1424173550
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3792538149
Short name T12
Test name
Test status
Simulation time 570293003082 ps
CPU time 408.13 seconds
Started Jul 17 05:52:38 PM PDT 24
Finished Jul 17 05:59:30 PM PDT 24
Peak memory 226808 kb
Host smart-077658ef-4071-45d5-bb23-e70827cda46f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792538149 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3792538149
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.115875905
Short name T27
Test name
Test status
Simulation time 58314174601 ps
CPU time 508.13 seconds
Started Jul 17 05:54:25 PM PDT 24
Finished Jul 17 06:02:54 PM PDT 24
Peak memory 216620 kb
Host smart-d50ec641-cf33-48ff-b874-fc6a40e8dccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115875905 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.115875905
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1410124527
Short name T50
Test name
Test status
Simulation time 136429089821 ps
CPU time 1068.51 seconds
Started Jul 17 05:53:16 PM PDT 24
Finished Jul 17 06:11:05 PM PDT 24
Peak memory 225988 kb
Host smart-2e6d2e5d-af29-4e8e-bfe8-3535d213467d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410124527 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1410124527
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3181994938
Short name T288
Test name
Test status
Simulation time 131330825157 ps
CPU time 1096.47 seconds
Started Jul 17 05:50:25 PM PDT 24
Finished Jul 17 06:08:43 PM PDT 24
Peak memory 199972 kb
Host smart-f43252f6-cabe-4f90-bf20-604e93969a8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3181994938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3181994938
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.540683955
Short name T109
Test name
Test status
Simulation time 536074091797 ps
CPU time 746.12 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 06:07:07 PM PDT 24
Peak memory 224872 kb
Host smart-48074eec-2c5d-4826-adb0-9bed421c6a65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540683955 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.540683955
Directory /workspace/99.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.534833329
Short name T32
Test name
Test status
Simulation time 154818224670 ps
CPU time 197.44 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:54:58 PM PDT 24
Peak memory 199980 kb
Host smart-c22936ce-47d7-4d48-b2ba-2a2babd7854a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=534833329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.534833329
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_stress_all.2665674518
Short name T134
Test name
Test status
Simulation time 255003247031 ps
CPU time 400.72 seconds
Started Jul 17 05:53:56 PM PDT 24
Finished Jul 17 06:00:38 PM PDT 24
Peak memory 199856 kb
Host smart-74eed2df-1804-422e-b9e9-abbd6781288e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665674518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2665674518
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all.2471587574
Short name T135
Test name
Test status
Simulation time 399401491268 ps
CPU time 212.07 seconds
Started Jul 17 05:51:51 PM PDT 24
Finished Jul 17 05:55:26 PM PDT 24
Peak memory 199956 kb
Host smart-0a0a6770-8fdf-4b7c-aa67-41c845a35b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471587574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2471587574
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3066876243
Short name T22
Test name
Test status
Simulation time 36405079 ps
CPU time 0.75 seconds
Started Jul 17 05:50:27 PM PDT 24
Finished Jul 17 05:50:29 PM PDT 24
Peak memory 218308 kb
Host smart-39c67c33-244b-445f-9b12-0fea07746b82
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066876243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3066876243
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_alert_test.2469244610
Short name T373
Test name
Test status
Simulation time 29854779 ps
CPU time 0.55 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:50:24 PM PDT 24
Peak memory 194012 kb
Host smart-936c8e48-68fc-43b1-ad00-f8a66fe7f655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469244610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2469244610
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2152399057
Short name T51
Test name
Test status
Simulation time 206524754341 ps
CPU time 1027.05 seconds
Started Jul 17 05:54:11 PM PDT 24
Finished Jul 17 06:11:20 PM PDT 24
Peak memory 231180 kb
Host smart-434bf1df-abeb-49a4-88f7-8eba53299f08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152399057 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2152399057
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_perf.740362367
Short name T6
Test name
Test status
Simulation time 17690215797 ps
CPU time 200.11 seconds
Started Jul 17 05:50:37 PM PDT 24
Finished Jul 17 05:53:59 PM PDT 24
Peak memory 199920 kb
Host smart-060cd91a-8f1b-4f86-96b9-92e94ea214f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740362367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.740362367
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1873088714
Short name T46
Test name
Test status
Simulation time 46964528747 ps
CPU time 369.87 seconds
Started Jul 17 05:51:23 PM PDT 24
Finished Jul 17 05:57:34 PM PDT 24
Peak memory 216340 kb
Host smart-9730afb4-2e0e-45b8-82bc-8698da78ffe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873088714 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1873088714
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1896240677
Short name T119
Test name
Test status
Simulation time 34431371841 ps
CPU time 30.49 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:51:21 PM PDT 24
Peak memory 199888 kb
Host smart-d7f72600-09d3-4667-9705-1f59ab84cb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896240677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1896240677
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1963938468
Short name T60
Test name
Test status
Simulation time 18619224 ps
CPU time 0.61 seconds
Started Jul 17 07:11:01 PM PDT 24
Finished Jul 17 07:11:05 PM PDT 24
Peak memory 196348 kb
Host smart-801d4ea3-612d-4061-ba38-55a4ccbf416c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963938468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1963938468
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1851977266
Short name T90
Test name
Test status
Simulation time 70316541 ps
CPU time 1.22 seconds
Started Jul 17 07:09:59 PM PDT 24
Finished Jul 17 07:10:06 PM PDT 24
Peak memory 200264 kb
Host smart-a5a7fde3-c67c-46fe-a823-426be871555d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851977266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1851977266
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3501790582
Short name T35
Test name
Test status
Simulation time 20619905591 ps
CPU time 21.16 seconds
Started Jul 17 05:54:54 PM PDT 24
Finished Jul 17 05:55:17 PM PDT 24
Peak memory 199940 kb
Host smart-c38e39c2-4ec5-4956-bec5-a2aab73fb8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501790582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3501790582
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3641462619
Short name T126
Test name
Test status
Simulation time 81738323353 ps
CPU time 44.17 seconds
Started Jul 17 05:55:39 PM PDT 24
Finished Jul 17 05:56:26 PM PDT 24
Peak memory 199972 kb
Host smart-c9260369-4931-4e87-a303-fba36910f8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641462619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3641462619
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2809014412
Short name T129
Test name
Test status
Simulation time 121496933066 ps
CPU time 293.16 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 05:59:22 PM PDT 24
Peak memory 199864 kb
Host smart-17ec478a-b55c-4366-bdb2-4ec8a246b03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809014412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2809014412
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.4056612355
Short name T26
Test name
Test status
Simulation time 77838114250 ps
CPU time 1719.42 seconds
Started Jul 17 05:54:22 PM PDT 24
Finished Jul 17 06:23:03 PM PDT 24
Peak memory 216320 kb
Host smart-0cab3c97-b212-49ca-9594-b2096e59d784
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056612355 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.4056612355
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3008275449
Short name T260
Test name
Test status
Simulation time 129183519934 ps
CPU time 120.13 seconds
Started Jul 17 05:51:37 PM PDT 24
Finished Jul 17 05:53:39 PM PDT 24
Peak memory 215448 kb
Host smart-bf80be9f-909e-4fc6-a073-b76c28d895c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008275449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3008275449
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.508033729
Short name T225
Test name
Test status
Simulation time 189404828682 ps
CPU time 59.12 seconds
Started Jul 17 05:52:05 PM PDT 24
Finished Jul 17 05:53:05 PM PDT 24
Peak memory 199904 kb
Host smart-734431f6-a438-4281-9088-2f8f29b50bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508033729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.508033729
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3341382988
Short name T137
Test name
Test status
Simulation time 22043425630 ps
CPU time 44.18 seconds
Started Jul 17 05:55:14 PM PDT 24
Finished Jul 17 05:55:59 PM PDT 24
Peak memory 199988 kb
Host smart-0d99d9b5-7a77-42ef-a242-aaa034ca4c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341382988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3341382988
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.4259265338
Short name T153
Test name
Test status
Simulation time 90247200181 ps
CPU time 303.34 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 05:59:46 PM PDT 24
Peak memory 216296 kb
Host smart-5222500d-b866-4662-b5cd-4157566d794a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259265338 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.4259265338
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2839594748
Short name T4
Test name
Test status
Simulation time 218636393687 ps
CPU time 166.96 seconds
Started Jul 17 05:53:58 PM PDT 24
Finished Jul 17 05:56:46 PM PDT 24
Peak memory 199848 kb
Host smart-9c69b71a-62e1-46ee-8042-9b0130256957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839594748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2839594748
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1687652044
Short name T11
Test name
Test status
Simulation time 220863784991 ps
CPU time 40.56 seconds
Started Jul 17 05:50:35 PM PDT 24
Finished Jul 17 05:51:18 PM PDT 24
Peak memory 200152 kb
Host smart-59f893ed-0a4f-486b-bbb6-a4a83c079f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687652044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1687652044
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_intr.3528207011
Short name T310
Test name
Test status
Simulation time 68433908789 ps
CPU time 32.99 seconds
Started Jul 17 05:52:33 PM PDT 24
Finished Jul 17 05:53:08 PM PDT 24
Peak memory 200148 kb
Host smart-7f79dbc6-ab84-4ee1-9465-c4ffdf8ab37f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528207011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3528207011
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2106495600
Short name T18
Test name
Test status
Simulation time 60304637537 ps
CPU time 725.64 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 06:03:11 PM PDT 24
Peak memory 216440 kb
Host smart-45ef7e0f-469d-4ddd-8526-497b86412e24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106495600 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2106495600
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.4123524478
Short name T13
Test name
Test status
Simulation time 81828202184 ps
CPU time 154.24 seconds
Started Jul 17 05:53:05 PM PDT 24
Finished Jul 17 05:55:40 PM PDT 24
Peak memory 199980 kb
Host smart-9e778e5e-7df5-4289-a240-7b793f3e4afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123524478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.4123524478
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1668201793
Short name T156
Test name
Test status
Simulation time 192690082116 ps
CPU time 81.15 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:56:03 PM PDT 24
Peak memory 199968 kb
Host smart-402a7cbb-8114-4011-adc0-6f699d9cbc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668201793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1668201793
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1072134164
Short name T261
Test name
Test status
Simulation time 182378034867 ps
CPU time 120.57 seconds
Started Jul 17 05:50:26 PM PDT 24
Finished Jul 17 05:52:28 PM PDT 24
Peak memory 199904 kb
Host smart-d3d346df-0ccc-4653-99b6-996533a36be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072134164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1072134164
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2090585110
Short name T94
Test name
Test status
Simulation time 41604173 ps
CPU time 0.87 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:48 PM PDT 24
Peak memory 199760 kb
Host smart-8d5ef90c-bd47-4c16-91dc-4dada4514716
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090585110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2090585110
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3259505744
Short name T123
Test name
Test status
Simulation time 262965767261 ps
CPU time 144.91 seconds
Started Jul 17 05:50:33 PM PDT 24
Finished Jul 17 05:52:59 PM PDT 24
Peak memory 199916 kb
Host smart-97c76fb5-3763-46df-a0c1-a05aab7d1d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259505744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3259505744
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.304719726
Short name T244
Test name
Test status
Simulation time 25902955095 ps
CPU time 39.82 seconds
Started Jul 17 05:54:54 PM PDT 24
Finished Jul 17 05:55:36 PM PDT 24
Peak memory 199816 kb
Host smart-e9518d39-87c7-4cfb-ba38-84067350ae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304719726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.304719726
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3395130185
Short name T139
Test name
Test status
Simulation time 57794802726 ps
CPU time 105.24 seconds
Started Jul 17 05:55:40 PM PDT 24
Finished Jul 17 05:57:28 PM PDT 24
Peak memory 199980 kb
Host smart-a49728e3-6b91-4fe7-abf4-3448e02798ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395130185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3395130185
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3349624042
Short name T154
Test name
Test status
Simulation time 198919211521 ps
CPU time 672.66 seconds
Started Jul 17 05:53:06 PM PDT 24
Finished Jul 17 06:04:20 PM PDT 24
Peak memory 216444 kb
Host smart-5cfcb3d1-df8a-4574-8385-2c770aef0a70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349624042 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3349624042
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1900883748
Short name T159
Test name
Test status
Simulation time 226712104226 ps
CPU time 202.66 seconds
Started Jul 17 05:53:31 PM PDT 24
Finished Jul 17 05:56:54 PM PDT 24
Peak memory 216704 kb
Host smart-d7124b1c-fa36-4558-a4e3-8ef5fb5eeb72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900883748 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1900883748
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1323584029
Short name T7
Test name
Test status
Simulation time 14757801000 ps
CPU time 22.46 seconds
Started Jul 17 05:54:25 PM PDT 24
Finished Jul 17 05:54:49 PM PDT 24
Peak memory 199576 kb
Host smart-cf1e761a-bf3a-43e6-a651-eb81752feebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323584029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1323584029
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3262264722
Short name T216
Test name
Test status
Simulation time 47955275054 ps
CPU time 79.14 seconds
Started Jul 17 05:54:38 PM PDT 24
Finished Jul 17 05:55:59 PM PDT 24
Peak memory 199944 kb
Host smart-cbfd2ba6-34c1-41db-ad37-f71aeb42a2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262264722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3262264722
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1172805600
Short name T833
Test name
Test status
Simulation time 116810820986 ps
CPU time 26.43 seconds
Started Jul 17 05:54:49 PM PDT 24
Finished Jul 17 05:55:17 PM PDT 24
Peak memory 199988 kb
Host smart-8e3ab74a-c94f-4d3a-b6dd-34ce10c7eda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172805600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1172805600
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1735435675
Short name T169
Test name
Test status
Simulation time 37074544048 ps
CPU time 18.43 seconds
Started Jul 17 05:54:38 PM PDT 24
Finished Jul 17 05:54:57 PM PDT 24
Peak memory 199980 kb
Host smart-095422ce-84d5-4afc-9a7b-7eb22b4d2fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735435675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1735435675
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.4242854568
Short name T342
Test name
Test status
Simulation time 39799443912 ps
CPU time 30.43 seconds
Started Jul 17 05:51:07 PM PDT 24
Finished Jul 17 05:51:39 PM PDT 24
Peak memory 199940 kb
Host smart-72165fc5-6f1b-4638-8182-b3da4ebf8c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242854568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4242854568
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1878979516
Short name T206
Test name
Test status
Simulation time 30073277124 ps
CPU time 45.98 seconds
Started Jul 17 05:54:42 PM PDT 24
Finished Jul 17 05:55:31 PM PDT 24
Peak memory 199916 kb
Host smart-e2e97c7f-5304-4efd-be8c-05481dc57547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878979516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1878979516
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1495167297
Short name T1108
Test name
Test status
Simulation time 192628424351 ps
CPU time 332.46 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 06:00:15 PM PDT 24
Peak memory 199956 kb
Host smart-987a785f-2e7d-4795-9b61-dc96547ef60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495167297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1495167297
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3700356664
Short name T217
Test name
Test status
Simulation time 169735435138 ps
CPU time 71.38 seconds
Started Jul 17 05:54:51 PM PDT 24
Finished Jul 17 05:56:04 PM PDT 24
Peak memory 199908 kb
Host smart-55575e26-2f68-46ca-9b57-4be92d0d716c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700356664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3700356664
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.61864244
Short name T192
Test name
Test status
Simulation time 36990773000 ps
CPU time 14.3 seconds
Started Jul 17 05:54:55 PM PDT 24
Finished Jul 17 05:55:11 PM PDT 24
Peak memory 199876 kb
Host smart-2720c4d2-ff1c-450e-ad1c-c40fcbff8be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61864244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.61864244
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.427570466
Short name T233
Test name
Test status
Simulation time 120574443117 ps
CPU time 49.8 seconds
Started Jul 17 05:55:04 PM PDT 24
Finished Jul 17 05:55:55 PM PDT 24
Peak memory 199868 kb
Host smart-4a4c1e33-6134-4787-8a22-d18cca90ff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427570466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.427570466
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1794992769
Short name T141
Test name
Test status
Simulation time 72708125051 ps
CPU time 29.22 seconds
Started Jul 17 05:55:04 PM PDT 24
Finished Jul 17 05:55:34 PM PDT 24
Peak memory 199844 kb
Host smart-de77f2f2-b5f3-4007-b7df-ba63b967b2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794992769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1794992769
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1676828497
Short name T345
Test name
Test status
Simulation time 50194112603 ps
CPU time 24.59 seconds
Started Jul 17 05:55:03 PM PDT 24
Finished Jul 17 05:55:29 PM PDT 24
Peak memory 199972 kb
Host smart-8e22efca-21d4-4d80-9da4-0a989decdf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676828497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1676828497
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.484813540
Short name T167
Test name
Test status
Simulation time 64827065172 ps
CPU time 161.5 seconds
Started Jul 17 05:55:40 PM PDT 24
Finished Jul 17 05:58:24 PM PDT 24
Peak memory 199868 kb
Host smart-d357b522-2da2-4eaa-906c-3399e3a1231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484813540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.484813540
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3763702886
Short name T783
Test name
Test status
Simulation time 350576318111 ps
CPU time 1190.18 seconds
Started Jul 17 05:53:07 PM PDT 24
Finished Jul 17 06:12:59 PM PDT 24
Peak memory 216328 kb
Host smart-40ef83ac-e93d-4ecb-89ad-4b639c8e6555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763702886 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3763702886
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.3982263014
Short name T180
Test name
Test status
Simulation time 113339598922 ps
CPU time 216.12 seconds
Started Jul 17 05:53:17 PM PDT 24
Finished Jul 17 05:56:55 PM PDT 24
Peak memory 199948 kb
Host smart-891caacd-7843-4cd2-bf4d-d8019634d65f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982263014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3982263014
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3198997690
Short name T231
Test name
Test status
Simulation time 63671450133 ps
CPU time 39.6 seconds
Started Jul 17 05:54:11 PM PDT 24
Finished Jul 17 05:54:53 PM PDT 24
Peak memory 199900 kb
Host smart-78abbfed-c023-4984-bff0-44b593d8d19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198997690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3198997690
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all.1313606197
Short name T429
Test name
Test status
Simulation time 61249047238 ps
CPU time 227.81 seconds
Started Jul 17 05:50:46 PM PDT 24
Finished Jul 17 05:54:35 PM PDT 24
Peak memory 200120 kb
Host smart-8956499a-7070-4254-b3da-8e7545a1fe86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313606197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1313606197
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2985629469
Short name T133
Test name
Test status
Simulation time 162899623947 ps
CPU time 46.13 seconds
Started Jul 17 05:54:23 PM PDT 24
Finished Jul 17 05:55:10 PM PDT 24
Peak memory 199980 kb
Host smart-32a69c26-e077-443a-bfe4-1f37a8ccc2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985629469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2985629469
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3411553730
Short name T117
Test name
Test status
Simulation time 125429453 ps
CPU time 1.31 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:03 PM PDT 24
Peak memory 200352 kb
Host smart-a0dffb9a-709e-4d05-bafb-57865521bd70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411553730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3411553730
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3143785221
Short name T203
Test name
Test status
Simulation time 18942911796 ps
CPU time 17.73 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:54:58 PM PDT 24
Peak memory 199984 kb
Host smart-e59ef362-ef72-4fc6-9626-2061143c67d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143785221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3143785221
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.668401249
Short name T171
Test name
Test status
Simulation time 36957839751 ps
CPU time 35.84 seconds
Started Jul 17 05:54:41 PM PDT 24
Finished Jul 17 05:55:20 PM PDT 24
Peak memory 199916 kb
Host smart-30e5c1c3-6228-4621-b35f-b3f2167c5d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668401249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.668401249
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.502852683
Short name T208
Test name
Test status
Simulation time 28114826291 ps
CPU time 19.38 seconds
Started Jul 17 05:54:52 PM PDT 24
Finished Jul 17 05:55:13 PM PDT 24
Peak memory 199876 kb
Host smart-77682d69-5ca1-4e95-9b9b-2bd845f86c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502852683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.502852683
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2002298639
Short name T224
Test name
Test status
Simulation time 26643383999 ps
CPU time 43.01 seconds
Started Jul 17 05:54:51 PM PDT 24
Finished Jul 17 05:55:35 PM PDT 24
Peak memory 199988 kb
Host smart-83f63667-a36d-4a58-ab71-d7c35f42b998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002298639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2002298639
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2272768989
Short name T200
Test name
Test status
Simulation time 33231480404 ps
CPU time 22.1 seconds
Started Jul 17 05:55:09 PM PDT 24
Finished Jul 17 05:55:32 PM PDT 24
Peak memory 199968 kb
Host smart-64034704-038b-40a5-bc49-196afbd9a098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272768989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2272768989
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.107118898
Short name T246
Test name
Test status
Simulation time 22301408645 ps
CPU time 18.95 seconds
Started Jul 17 05:51:41 PM PDT 24
Finished Jul 17 05:52:02 PM PDT 24
Peak memory 199984 kb
Host smart-4d608d90-4ea9-4210-9e90-079559dc71fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107118898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.107118898
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1859717252
Short name T245
Test name
Test status
Simulation time 55126060023 ps
CPU time 24.63 seconds
Started Jul 17 05:55:03 PM PDT 24
Finished Jul 17 05:55:29 PM PDT 24
Peak memory 199932 kb
Host smart-6fce09fa-0f63-4190-a1e9-5bf6f059ce14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859717252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1859717252
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.4224179563
Short name T236
Test name
Test status
Simulation time 46441540243 ps
CPU time 33.89 seconds
Started Jul 17 05:55:04 PM PDT 24
Finished Jul 17 05:55:39 PM PDT 24
Peak memory 199936 kb
Host smart-e36379f2-e781-4eda-af45-3ccce6793cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224179563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.4224179563
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3526705533
Short name T248
Test name
Test status
Simulation time 44003078770 ps
CPU time 20.14 seconds
Started Jul 17 05:55:14 PM PDT 24
Finished Jul 17 05:55:35 PM PDT 24
Peak memory 199844 kb
Host smart-f7842d3c-04cf-4ec9-a339-b28b9abe92a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526705533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3526705533
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.4177840387
Short name T104
Test name
Test status
Simulation time 26098555261 ps
CPU time 48.35 seconds
Started Jul 17 05:55:40 PM PDT 24
Finished Jul 17 05:56:31 PM PDT 24
Peak memory 199984 kb
Host smart-75214dab-0676-43ca-a446-24c767134fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177840387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.4177840387
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.4228002466
Short name T202
Test name
Test status
Simulation time 407349253248 ps
CPU time 92.39 seconds
Started Jul 17 05:52:40 PM PDT 24
Finished Jul 17 05:54:16 PM PDT 24
Peak memory 199604 kb
Host smart-1caaa09a-0062-4a11-ac63-7d2d8138747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228002466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.4228002466
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2697667333
Short name T173
Test name
Test status
Simulation time 160936990292 ps
CPU time 29.51 seconds
Started Jul 17 05:53:04 PM PDT 24
Finished Jul 17 05:53:34 PM PDT 24
Peak memory 199988 kb
Host smart-af560bfb-4a17-46ba-b37f-9d9c30baf66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697667333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2697667333
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2452315921
Short name T220
Test name
Test status
Simulation time 20545374922 ps
CPU time 37.22 seconds
Started Jul 17 05:53:17 PM PDT 24
Finished Jul 17 05:53:55 PM PDT 24
Peak memory 199952 kb
Host smart-cdeaf6f8-abc0-4b50-884b-c7bb64ae4396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452315921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2452315921
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2184959089
Short name T240
Test name
Test status
Simulation time 20124148865 ps
CPU time 116.16 seconds
Started Jul 17 05:53:42 PM PDT 24
Finished Jul 17 05:55:40 PM PDT 24
Peak memory 216232 kb
Host smart-20593410-55b2-42fc-a57c-86ab95a801ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184959089 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2184959089
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2503395109
Short name T138
Test name
Test status
Simulation time 25477808544 ps
CPU time 421.13 seconds
Started Jul 17 05:53:45 PM PDT 24
Finished Jul 17 06:00:48 PM PDT 24
Peak memory 216188 kb
Host smart-0adbd226-6ef3-4195-8588-07b90f1eb965
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503395109 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2503395109
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3258624545
Short name T170
Test name
Test status
Simulation time 10520305400 ps
CPU time 15.73 seconds
Started Jul 17 05:54:14 PM PDT 24
Finished Jul 17 05:54:31 PM PDT 24
Peak memory 199952 kb
Host smart-b2488e2e-a274-41e1-8cc6-90a538e09010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258624545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3258624545
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3174576177
Short name T227
Test name
Test status
Simulation time 16886845654 ps
CPU time 14.22 seconds
Started Jul 17 05:54:24 PM PDT 24
Finished Jul 17 05:54:39 PM PDT 24
Peak memory 199964 kb
Host smart-b8db92ce-cda4-4038-8d13-e02cfc6300ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174576177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3174576177
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.304371819
Short name T1281
Test name
Test status
Simulation time 35357584 ps
CPU time 0.77 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:49 PM PDT 24
Peak memory 197200 kb
Host smart-3484601f-b4b3-4a49-8ff4-51e91ecb715f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304371819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.304371819
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3929952320
Short name T63
Test name
Test status
Simulation time 221571067 ps
CPU time 2.18 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:45 PM PDT 24
Peak memory 198868 kb
Host smart-187ab2f9-2c25-4694-b881-88276c34cf5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929952320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3929952320
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1053615002
Short name T1234
Test name
Test status
Simulation time 20665092 ps
CPU time 0.61 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:48 PM PDT 24
Peak memory 196300 kb
Host smart-e62d74fc-60ce-4fb5-8548-b49ae856ed32
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053615002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1053615002
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3089330005
Short name T1208
Test name
Test status
Simulation time 22920443 ps
CPU time 0.73 seconds
Started Jul 17 07:09:38 PM PDT 24
Finished Jul 17 07:09:40 PM PDT 24
Peak memory 199432 kb
Host smart-eeaca72e-b22d-4cb6-bb79-5794805f60bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089330005 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3089330005
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2929443556
Short name T1279
Test name
Test status
Simulation time 37973904 ps
CPU time 0.6 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:43 PM PDT 24
Peak memory 196272 kb
Host smart-31474030-2eaf-4a41-a91b-def5aa4428bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929443556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2929443556
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3218259468
Short name T1257
Test name
Test status
Simulation time 45950485 ps
CPU time 0.54 seconds
Started Jul 17 07:09:38 PM PDT 24
Finished Jul 17 07:09:40 PM PDT 24
Peak memory 195168 kb
Host smart-d68c5790-a550-48f6-ae10-c1201ca6acae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218259468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3218259468
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2139868852
Short name T1300
Test name
Test status
Simulation time 55609924 ps
CPU time 0.62 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:55 PM PDT 24
Peak memory 196600 kb
Host smart-8eb29647-b8b9-4e80-b464-48d144ef92c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139868852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2139868852
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1310229255
Short name T1246
Test name
Test status
Simulation time 21674643 ps
CPU time 0.92 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:55 PM PDT 24
Peak memory 200676 kb
Host smart-4ff91335-38f4-4eaf-b331-c1ad5fe64fda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310229255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1310229255
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2084825554
Short name T1266
Test name
Test status
Simulation time 39633452 ps
CPU time 0.94 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:50 PM PDT 24
Peak memory 199528 kb
Host smart-69c56caa-88f6-4f61-8a53-76dec3cd709e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084825554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2084825554
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.413284638
Short name T67
Test name
Test status
Simulation time 25995808 ps
CPU time 0.65 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:42 PM PDT 24
Peak memory 195848 kb
Host smart-2a05ab2f-040e-49f0-ae0c-06d1cd52143c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413284638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.413284638
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1530832637
Short name T1194
Test name
Test status
Simulation time 77446262 ps
CPU time 1.4 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:53 PM PDT 24
Peak memory 198848 kb
Host smart-735f4615-e8f9-4608-9e92-259d5a592077
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530832637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1530832637
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2497439461
Short name T1304
Test name
Test status
Simulation time 28462559 ps
CPU time 0.57 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:50 PM PDT 24
Peak memory 196332 kb
Host smart-60dd468d-24ba-4b10-a895-a4d26e364a27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497439461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2497439461
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1403081528
Short name T1292
Test name
Test status
Simulation time 28229060 ps
CPU time 0.82 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:50 PM PDT 24
Peak memory 200720 kb
Host smart-af66cc4b-8a6c-4aa5-aacc-7db7c8789bcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403081528 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1403081528
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3295692659
Short name T1277
Test name
Test status
Simulation time 16117388 ps
CPU time 0.58 seconds
Started Jul 17 07:09:40 PM PDT 24
Finished Jul 17 07:09:46 PM PDT 24
Peak memory 196416 kb
Host smart-53268e16-3714-42a0-a079-359aa330c6b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295692659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3295692659
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3212426479
Short name T1222
Test name
Test status
Simulation time 22866138 ps
CPU time 0.63 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:51 PM PDT 24
Peak memory 195304 kb
Host smart-acbf38cc-cad6-482e-a7b1-4695a87abbb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212426479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3212426479
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3507753306
Short name T1280
Test name
Test status
Simulation time 16329984 ps
CPU time 0.72 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:49 PM PDT 24
Peak memory 196948 kb
Host smart-ba4fa310-9f61-41ce-9967-cb1a9a65c540
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507753306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3507753306
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1986167013
Short name T1239
Test name
Test status
Simulation time 434820422 ps
CPU time 1.62 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:50 PM PDT 24
Peak memory 200964 kb
Host smart-51d6cc78-d8fa-49a4-a0e8-fe1264fc4dcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986167013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1986167013
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.441652304
Short name T1187
Test name
Test status
Simulation time 130349571 ps
CPU time 1.37 seconds
Started Jul 17 07:10:01 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 200980 kb
Host smart-7350d589-394b-445a-8149-3d5c4f01b0f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441652304 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.441652304
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3984157816
Short name T1298
Test name
Test status
Simulation time 16117408 ps
CPU time 0.59 seconds
Started Jul 17 07:10:02 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 196320 kb
Host smart-1f0aac36-86da-47ad-a669-a33f212f7d3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984157816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3984157816
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3940553045
Short name T1188
Test name
Test status
Simulation time 12958391 ps
CPU time 0.58 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 195268 kb
Host smart-409c2770-23fd-4add-9b45-a8e022372c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940553045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3940553045
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.753029832
Short name T1231
Test name
Test status
Simulation time 161780770 ps
CPU time 0.73 seconds
Started Jul 17 07:09:59 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 197864 kb
Host smart-4e2ad103-fb1a-45a5-b900-ab4d28a869ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753029832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.753029832
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1432362307
Short name T1183
Test name
Test status
Simulation time 70585584 ps
CPU time 1.3 seconds
Started Jul 17 07:10:02 PM PDT 24
Finished Jul 17 07:10:09 PM PDT 24
Peak memory 200968 kb
Host smart-0d7b2563-5d65-4ceb-bbbb-b84e36a95296
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432362307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1432362307
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.761241397
Short name T1302
Test name
Test status
Simulation time 85359021 ps
CPU time 1.31 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 200184 kb
Host smart-ccc1d848-3316-4d9f-88f6-a9a21ad8bac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761241397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.761241397
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2874169672
Short name T1181
Test name
Test status
Simulation time 111702947 ps
CPU time 0.82 seconds
Started Jul 17 07:10:54 PM PDT 24
Finished Jul 17 07:10:55 PM PDT 24
Peak memory 200716 kb
Host smart-e21884a0-3ebf-4f99-9eb6-3f8c02fa9ff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874169672 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2874169672
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3154028835
Short name T1294
Test name
Test status
Simulation time 17711464 ps
CPU time 0.58 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 196236 kb
Host smart-2df8b692-6658-4798-bbb9-c91c9b9a4c89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154028835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3154028835
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2409667033
Short name T1209
Test name
Test status
Simulation time 54843984 ps
CPU time 0.58 seconds
Started Jul 17 07:10:01 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 195300 kb
Host smart-86346547-0cdd-41e0-a32f-bb94a7388fc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409667033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2409667033
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1649983045
Short name T1244
Test name
Test status
Simulation time 14961500 ps
CPU time 0.65 seconds
Started Jul 17 07:10:56 PM PDT 24
Finished Jul 17 07:10:58 PM PDT 24
Peak memory 195736 kb
Host smart-8ca0f478-d513-417a-b631-099df272e662
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649983045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1649983045
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2527393879
Short name T1185
Test name
Test status
Simulation time 136979164 ps
CPU time 1.75 seconds
Started Jul 17 07:09:59 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 200920 kb
Host smart-04cfe227-aca5-4fd0-9c29-3859895d0223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527393879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2527393879
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1812582449
Short name T85
Test name
Test status
Simulation time 250356547 ps
CPU time 0.96 seconds
Started Jul 17 07:10:01 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 199980 kb
Host smart-22bbdb77-7435-404a-81e4-420737d03e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812582449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1812582449
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1290486310
Short name T1211
Test name
Test status
Simulation time 220398334 ps
CPU time 1.13 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:04 PM PDT 24
Peak memory 200912 kb
Host smart-23998e93-b927-442c-a3cd-7fc4525a00e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290486310 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1290486310
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2991697171
Short name T1203
Test name
Test status
Simulation time 16709793 ps
CPU time 0.6 seconds
Started Jul 17 07:10:54 PM PDT 24
Finished Jul 17 07:10:55 PM PDT 24
Peak memory 196408 kb
Host smart-75c11770-2e3a-4463-b247-b180994e20e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991697171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2991697171
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2931295925
Short name T1309
Test name
Test status
Simulation time 12315427 ps
CPU time 0.55 seconds
Started Jul 17 07:10:57 PM PDT 24
Finished Jul 17 07:10:58 PM PDT 24
Peak memory 195292 kb
Host smart-187d9f36-e055-43ac-b659-4933c61b9d5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931295925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2931295925
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2006034053
Short name T1228
Test name
Test status
Simulation time 31346927 ps
CPU time 0.65 seconds
Started Jul 17 07:10:51 PM PDT 24
Finished Jul 17 07:10:52 PM PDT 24
Peak memory 196924 kb
Host smart-8d58731f-0a81-430b-b44a-2d59aadd74be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006034053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2006034053
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.809030973
Short name T1289
Test name
Test status
Simulation time 96007378 ps
CPU time 1.33 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:10 PM PDT 24
Peak memory 200932 kb
Host smart-7e7590ce-0766-4114-8c13-ca1750150b93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809030973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.809030973
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2897535411
Short name T1295
Test name
Test status
Simulation time 34938988 ps
CPU time 0.94 seconds
Started Jul 17 07:11:01 PM PDT 24
Finished Jul 17 07:11:05 PM PDT 24
Peak memory 200692 kb
Host smart-ada2d8a1-da90-4764-aabd-35f6e9c3bdd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897535411 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2897535411
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2061970481
Short name T1316
Test name
Test status
Simulation time 17547024 ps
CPU time 0.57 seconds
Started Jul 17 07:10:54 PM PDT 24
Finished Jul 17 07:10:55 PM PDT 24
Peak memory 195304 kb
Host smart-910f5d13-60c6-494b-85ec-a7ac18d011c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061970481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2061970481
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.82126265
Short name T1243
Test name
Test status
Simulation time 16729666 ps
CPU time 0.74 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:02 PM PDT 24
Peak memory 197968 kb
Host smart-c45df3c2-e557-4f5b-a3b8-a5e311548fd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82126265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_
outstanding.82126265
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3570509842
Short name T1193
Test name
Test status
Simulation time 143815136 ps
CPU time 1.55 seconds
Started Jul 17 07:10:56 PM PDT 24
Finished Jul 17 07:10:59 PM PDT 24
Peak memory 200920 kb
Host smart-b2855a6f-cb78-4f68-9aba-4733ebe23e38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570509842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3570509842
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3935024947
Short name T92
Test name
Test status
Simulation time 57359176 ps
CPU time 0.95 seconds
Started Jul 17 07:10:58 PM PDT 24
Finished Jul 17 07:11:00 PM PDT 24
Peak memory 199556 kb
Host smart-7986546a-3271-41f7-b073-13f48ea61fed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935024947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3935024947
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3436615194
Short name T1250
Test name
Test status
Simulation time 27060909 ps
CPU time 0.82 seconds
Started Jul 17 07:10:59 PM PDT 24
Finished Jul 17 07:11:02 PM PDT 24
Peak memory 200152 kb
Host smart-d6af5748-bf12-47d8-8dc7-ea73a5e5defa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436615194 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3436615194
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3604309052
Short name T1233
Test name
Test status
Simulation time 26706974 ps
CPU time 0.58 seconds
Started Jul 17 07:10:55 PM PDT 24
Finished Jul 17 07:10:57 PM PDT 24
Peak memory 196344 kb
Host smart-67d7c930-c860-4d5e-b490-ace273c4a620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604309052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3604309052
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.900939763
Short name T1253
Test name
Test status
Simulation time 40714080 ps
CPU time 0.56 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:10 PM PDT 24
Peak memory 195216 kb
Host smart-09679ac0-5b9c-4dd6-942c-0a470bcdc635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900939763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.900939763
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.59179992
Short name T78
Test name
Test status
Simulation time 14627794 ps
CPU time 0.64 seconds
Started Jul 17 07:11:02 PM PDT 24
Finished Jul 17 07:11:06 PM PDT 24
Peak memory 197316 kb
Host smart-0d88777c-fd60-40a8-ba98-cb4b6200a225
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59179992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_
outstanding.59179992
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2305936924
Short name T1204
Test name
Test status
Simulation time 32148404 ps
CPU time 1.46 seconds
Started Jul 17 07:11:01 PM PDT 24
Finished Jul 17 07:11:05 PM PDT 24
Peak memory 200880 kb
Host smart-1c06d369-7a75-4898-b499-f8743a08dbb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305936924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2305936924
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2517006060
Short name T1284
Test name
Test status
Simulation time 89724241 ps
CPU time 1.45 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:04 PM PDT 24
Peak memory 200180 kb
Host smart-4da7d7f7-7008-42ee-b85d-57d545f646af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517006060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2517006060
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.104509531
Short name T1205
Test name
Test status
Simulation time 21872634 ps
CPU time 0.76 seconds
Started Jul 17 07:10:59 PM PDT 24
Finished Jul 17 07:11:02 PM PDT 24
Peak memory 199596 kb
Host smart-04a99200-d2fc-4192-abf6-cc671205d51b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104509531 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.104509531
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1291173665
Short name T1297
Test name
Test status
Simulation time 11940123 ps
CPU time 0.57 seconds
Started Jul 17 07:11:01 PM PDT 24
Finished Jul 17 07:11:05 PM PDT 24
Peak memory 196268 kb
Host smart-b949a3bd-614a-4d1d-8db6-0865bc41a579
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291173665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1291173665
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1044167089
Short name T1310
Test name
Test status
Simulation time 15206230 ps
CPU time 0.59 seconds
Started Jul 17 07:11:02 PM PDT 24
Finished Jul 17 07:11:06 PM PDT 24
Peak memory 195392 kb
Host smart-b67db228-2b8d-48e0-b120-3aaa50cdd30a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044167089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1044167089
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3441626048
Short name T1251
Test name
Test status
Simulation time 31049713 ps
CPU time 0.76 seconds
Started Jul 17 07:10:58 PM PDT 24
Finished Jul 17 07:10:59 PM PDT 24
Peak memory 197804 kb
Host smart-8dd1efc7-e5ee-4d85-998e-c07f3b5c2182
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441626048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3441626048
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.4113342554
Short name T1315
Test name
Test status
Simulation time 100488466 ps
CPU time 1.25 seconds
Started Jul 17 07:10:55 PM PDT 24
Finished Jul 17 07:10:57 PM PDT 24
Peak memory 200920 kb
Host smart-dd387fef-27df-4792-a60b-deba44d02906
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113342554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.4113342554
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2944508547
Short name T1267
Test name
Test status
Simulation time 318221746 ps
CPU time 1.34 seconds
Started Jul 17 07:10:51 PM PDT 24
Finished Jul 17 07:10:53 PM PDT 24
Peak memory 200448 kb
Host smart-83005e99-9224-48ad-a943-27d715385685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944508547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2944508547
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2853397110
Short name T1238
Test name
Test status
Simulation time 30994054 ps
CPU time 0.62 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:07 PM PDT 24
Peak memory 198040 kb
Host smart-d1103931-a789-4b50-9875-eba1891f8c29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853397110 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2853397110
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1959177417
Short name T1258
Test name
Test status
Simulation time 94860408 ps
CPU time 0.6 seconds
Started Jul 17 07:10:59 PM PDT 24
Finished Jul 17 07:11:01 PM PDT 24
Peak memory 196492 kb
Host smart-30e01cd2-f3c5-46e8-99e9-5136d3cea132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959177417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1959177417
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3785863973
Short name T1287
Test name
Test status
Simulation time 41134520 ps
CPU time 0.55 seconds
Started Jul 17 07:10:55 PM PDT 24
Finished Jul 17 07:10:57 PM PDT 24
Peak memory 195248 kb
Host smart-3b3665c4-e395-46fc-aea1-3db9e667b887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785863973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3785863973
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1902102472
Short name T1195
Test name
Test status
Simulation time 98603262 ps
CPU time 0.77 seconds
Started Jul 17 07:11:01 PM PDT 24
Finished Jul 17 07:11:05 PM PDT 24
Peak memory 198416 kb
Host smart-496f7f99-f470-49fd-ac24-e199fe141f11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902102472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1902102472
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.109208521
Short name T1306
Test name
Test status
Simulation time 31037037 ps
CPU time 1.47 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:08 PM PDT 24
Peak memory 200928 kb
Host smart-04e3fcb3-3302-47b6-ba3e-e9cd3a4a74a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109208521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.109208521
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3652637272
Short name T116
Test name
Test status
Simulation time 79513183 ps
CPU time 0.96 seconds
Started Jul 17 07:10:59 PM PDT 24
Finished Jul 17 07:11:01 PM PDT 24
Peak memory 199640 kb
Host smart-4c8a2bbc-b477-4a59-860e-4f1a52747a45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652637272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3652637272
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2632006454
Short name T1182
Test name
Test status
Simulation time 22996148 ps
CPU time 1.07 seconds
Started Jul 17 07:10:59 PM PDT 24
Finished Jul 17 07:11:02 PM PDT 24
Peak memory 200732 kb
Host smart-6fc8846c-cbd7-4681-91f4-b7f454f5c972
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632006454 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2632006454
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3426310582
Short name T81
Test name
Test status
Simulation time 11221774 ps
CPU time 0.6 seconds
Started Jul 17 07:10:59 PM PDT 24
Finished Jul 17 07:11:00 PM PDT 24
Peak memory 196332 kb
Host smart-ffc59dfd-3434-4b94-b9bb-823498aabe7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426310582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3426310582
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2332445799
Short name T1307
Test name
Test status
Simulation time 15826208 ps
CPU time 0.57 seconds
Started Jul 17 07:11:02 PM PDT 24
Finished Jul 17 07:11:06 PM PDT 24
Peak memory 195256 kb
Host smart-a1288be4-10e2-4052-8cf4-b9cf80b0eae6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332445799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2332445799
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1842153257
Short name T1207
Test name
Test status
Simulation time 62717062 ps
CPU time 0.64 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:03 PM PDT 24
Peak memory 195308 kb
Host smart-5bd7f56d-d767-4ba0-9447-97edf9b9c7af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842153257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1842153257
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.445985745
Short name T1232
Test name
Test status
Simulation time 344647305 ps
CPU time 1.74 seconds
Started Jul 17 07:10:59 PM PDT 24
Finished Jul 17 07:11:02 PM PDT 24
Peak memory 200968 kb
Host smart-ba09bef5-3bc5-4032-9505-795901c2d199
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445985745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.445985745
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.43768882
Short name T1252
Test name
Test status
Simulation time 168829982 ps
CPU time 1.1 seconds
Started Jul 17 07:10:59 PM PDT 24
Finished Jul 17 07:11:01 PM PDT 24
Peak memory 199808 kb
Host smart-6c59b774-f6bc-40fc-939f-8c10ee2bc864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43768882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.43768882
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2734859367
Short name T1276
Test name
Test status
Simulation time 34176255 ps
CPU time 0.89 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:03 PM PDT 24
Peak memory 200752 kb
Host smart-aba34e8a-0480-4d0e-a4f4-bb8f618d5240
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734859367 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2734859367
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2198035743
Short name T61
Test name
Test status
Simulation time 58105202 ps
CPU time 0.65 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 196640 kb
Host smart-a5b88caa-5d0c-49c2-b3cb-85f34991aea9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198035743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2198035743
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2947449926
Short name T1202
Test name
Test status
Simulation time 10798324 ps
CPU time 0.62 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:07 PM PDT 24
Peak memory 195400 kb
Host smart-4f1e1f09-8d3f-4d62-a134-628b149cc819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947449926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2947449926
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3166593067
Short name T77
Test name
Test status
Simulation time 55174790 ps
CPU time 0.64 seconds
Started Jul 17 07:10:56 PM PDT 24
Finished Jul 17 07:10:58 PM PDT 24
Peak memory 196772 kb
Host smart-2c167ffd-08c1-4622-bff8-bbce687a7249
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166593067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3166593067
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3455068825
Short name T1219
Test name
Test status
Simulation time 445326724 ps
CPU time 2.19 seconds
Started Jul 17 07:11:01 PM PDT 24
Finished Jul 17 07:11:05 PM PDT 24
Peak memory 200880 kb
Host smart-9c226b09-2797-45b2-892c-2da1dfe4c041
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455068825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3455068825
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2893603099
Short name T87
Test name
Test status
Simulation time 130265115 ps
CPU time 1.34 seconds
Started Jul 17 07:11:01 PM PDT 24
Finished Jul 17 07:11:05 PM PDT 24
Peak memory 200200 kb
Host smart-8851cf02-7783-4303-92fb-2af10533078f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893603099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2893603099
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4025712413
Short name T1192
Test name
Test status
Simulation time 19791640 ps
CPU time 0.69 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 198564 kb
Host smart-cf988427-1daf-4e46-bf1a-3de4c1f569ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025712413 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.4025712413
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1656673519
Short name T62
Test name
Test status
Simulation time 32034082 ps
CPU time 0.59 seconds
Started Jul 17 07:10:55 PM PDT 24
Finished Jul 17 07:10:56 PM PDT 24
Peak memory 196324 kb
Host smart-956453bd-abe4-4f80-bb9f-ff4d7f312cae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656673519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1656673519
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2756696124
Short name T1314
Test name
Test status
Simulation time 30039512 ps
CPU time 0.58 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:03 PM PDT 24
Peak memory 195300 kb
Host smart-3d01b849-9388-4f41-8053-06667431a3ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756696124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2756696124
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1724827066
Short name T83
Test name
Test status
Simulation time 22110451 ps
CPU time 0.68 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:03 PM PDT 24
Peak memory 197552 kb
Host smart-b62e4217-858f-4ddf-a1c5-e740c53c2e12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724827066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1724827066
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1543919025
Short name T1237
Test name
Test status
Simulation time 67253680 ps
CPU time 2 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:08 PM PDT 24
Peak memory 200968 kb
Host smart-0cb62866-7eaa-487f-81a9-e761b7e2abde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543919025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1543919025
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3271462888
Short name T91
Test name
Test status
Simulation time 328228119 ps
CPU time 1.48 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:04 PM PDT 24
Peak memory 200268 kb
Host smart-b6748bae-3e88-4027-ae87-379827f0537a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271462888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3271462888
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3999967910
Short name T1317
Test name
Test status
Simulation time 69152418 ps
CPU time 0.66 seconds
Started Jul 17 07:09:58 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 195616 kb
Host smart-592a38be-c0ed-4933-958c-f81d994f0b5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999967910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3999967910
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3474463039
Short name T1236
Test name
Test status
Simulation time 182866025 ps
CPU time 1.48 seconds
Started Jul 17 07:09:59 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 198524 kb
Host smart-68f18156-c2a2-444f-aff5-59d85b2f6517
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474463039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3474463039
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3251425255
Short name T64
Test name
Test status
Simulation time 19207048 ps
CPU time 0.6 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:42 PM PDT 24
Peak memory 196316 kb
Host smart-186199c8-9867-4e93-8ac7-b950e4d93b02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251425255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3251425255
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3822799602
Short name T1191
Test name
Test status
Simulation time 42350220 ps
CPU time 0.99 seconds
Started Jul 17 07:09:57 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 200748 kb
Host smart-d85a2b24-ffa3-43ef-baf4-f1958ae2128b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822799602 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3822799602
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1605861784
Short name T1242
Test name
Test status
Simulation time 14954136 ps
CPU time 0.59 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:06 PM PDT 24
Peak memory 196340 kb
Host smart-826bb882-3908-47f1-9d17-e0cad181d461
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605861784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1605861784
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1472024935
Short name T1218
Test name
Test status
Simulation time 47718818 ps
CPU time 0.58 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:42 PM PDT 24
Peak memory 195240 kb
Host smart-d5ab582d-8fbf-44ed-93c6-0b7b0fc5ab82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472024935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1472024935
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2462774994
Short name T1240
Test name
Test status
Simulation time 93716730 ps
CPU time 0.65 seconds
Started Jul 17 07:09:58 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 196672 kb
Host smart-b2a2944a-5f18-4898-bb91-778d7755a925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462774994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2462774994
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.842760952
Short name T1282
Test name
Test status
Simulation time 173814310 ps
CPU time 1.95 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:44 PM PDT 24
Peak memory 200904 kb
Host smart-3058a328-842c-4b90-944f-85a69aede232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842760952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.842760952
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3417389647
Short name T89
Test name
Test status
Simulation time 152432861 ps
CPU time 1.2 seconds
Started Jul 17 07:09:40 PM PDT 24
Finished Jul 17 07:09:47 PM PDT 24
Peak memory 200144 kb
Host smart-bf6ac5d3-76d4-46c9-a09b-6ea54609490b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417389647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3417389647
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1135291745
Short name T1197
Test name
Test status
Simulation time 15752970 ps
CPU time 0.57 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 195216 kb
Host smart-e35f7be8-10b7-4fb3-9488-94edc3e17dd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135291745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1135291745
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3476531961
Short name T1264
Test name
Test status
Simulation time 17660537 ps
CPU time 0.59 seconds
Started Jul 17 07:10:55 PM PDT 24
Finished Jul 17 07:10:57 PM PDT 24
Peak memory 195312 kb
Host smart-1a23f246-1af9-4862-b22b-4e2634373347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476531961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3476531961
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.4079658434
Short name T1241
Test name
Test status
Simulation time 14640783 ps
CPU time 0.59 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:02 PM PDT 24
Peak memory 195212 kb
Host smart-7adda390-1ca2-48d2-9751-1d01ca402287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079658434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.4079658434
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2358276451
Short name T1196
Test name
Test status
Simulation time 33047689 ps
CPU time 0.54 seconds
Started Jul 17 07:10:54 PM PDT 24
Finished Jul 17 07:10:56 PM PDT 24
Peak memory 195248 kb
Host smart-da5b2915-3908-4128-8902-de6a93b8d74d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358276451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2358276451
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.312195804
Short name T1210
Test name
Test status
Simulation time 74001200 ps
CPU time 0.58 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:03 PM PDT 24
Peak memory 195260 kb
Host smart-ddb4c6fb-8a35-4b36-8985-98cd40ebe326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312195804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.312195804
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.4177120341
Short name T1275
Test name
Test status
Simulation time 23451445 ps
CPU time 0.59 seconds
Started Jul 17 07:11:00 PM PDT 24
Finished Jul 17 07:11:02 PM PDT 24
Peak memory 195316 kb
Host smart-336d6f89-6a4c-4703-85a6-aae50c0c1d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177120341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.4177120341
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.4034604558
Short name T1296
Test name
Test status
Simulation time 16832369 ps
CPU time 0.57 seconds
Started Jul 17 07:10:54 PM PDT 24
Finished Jul 17 07:10:55 PM PDT 24
Peak memory 195328 kb
Host smart-13439ad3-d15e-4861-9b70-9f8811999e13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034604558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.4034604558
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3184098321
Short name T1278
Test name
Test status
Simulation time 16303713 ps
CPU time 0.55 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 195316 kb
Host smart-b427fd5e-d48e-4d08-beea-875a36adaac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184098321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3184098321
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3613425490
Short name T1221
Test name
Test status
Simulation time 95176973 ps
CPU time 0.59 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:07 PM PDT 24
Peak memory 195412 kb
Host smart-d8ab5881-9eb8-4191-8286-9fb2fb002022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613425490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3613425490
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3559875769
Short name T1216
Test name
Test status
Simulation time 17027882 ps
CPU time 0.58 seconds
Started Jul 17 07:11:01 PM PDT 24
Finished Jul 17 07:11:04 PM PDT 24
Peak memory 195248 kb
Host smart-a984a8a1-caa8-4adc-afea-1ea4133df865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559875769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3559875769
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1797124124
Short name T1311
Test name
Test status
Simulation time 28861127 ps
CPU time 0.79 seconds
Started Jul 17 07:09:57 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 197148 kb
Host smart-b8df87f8-1cdc-4f7a-b3e4-c6c1d9661daf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797124124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1797124124
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3118781777
Short name T1312
Test name
Test status
Simulation time 1034262929 ps
CPU time 2.53 seconds
Started Jul 17 07:09:59 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 198756 kb
Host smart-326f6ea2-50cd-48e0-a9d7-ed1f6d4eea6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118781777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3118781777
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3540715428
Short name T1303
Test name
Test status
Simulation time 14952528 ps
CPU time 0.55 seconds
Started Jul 17 07:09:52 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 196244 kb
Host smart-24b3614e-b682-4a2a-a510-1ec2693e3d61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540715428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3540715428
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1689226401
Short name T1286
Test name
Test status
Simulation time 40837098 ps
CPU time 0.75 seconds
Started Jul 17 07:09:57 PM PDT 24
Finished Jul 17 07:10:04 PM PDT 24
Peak memory 200720 kb
Host smart-e9d9729a-ffe5-42a2-82ca-862360dd5e5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689226401 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1689226401
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1248979279
Short name T1212
Test name
Test status
Simulation time 33609246 ps
CPU time 0.59 seconds
Started Jul 17 07:09:57 PM PDT 24
Finished Jul 17 07:10:04 PM PDT 24
Peak memory 196600 kb
Host smart-a36ad6ba-3ce8-4d19-8841-9a1d64db9283
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248979279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1248979279
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2443087458
Short name T1288
Test name
Test status
Simulation time 30740110 ps
CPU time 0.59 seconds
Started Jul 17 07:10:01 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 195296 kb
Host smart-0fafb17f-54d7-4bce-bc5a-def678a403b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443087458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2443087458
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.4228624004
Short name T1260
Test name
Test status
Simulation time 18012988 ps
CPU time 0.64 seconds
Started Jul 17 07:09:57 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 195628 kb
Host smart-5719155b-086f-4d7e-b75f-3747613a2726
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228624004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.4228624004
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.505584375
Short name T1229
Test name
Test status
Simulation time 21520671 ps
CPU time 1.04 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 200976 kb
Host smart-b8ea2157-b130-4b44-a58c-0ab2d3dcb2c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505584375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.505584375
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3234331440
Short name T1274
Test name
Test status
Simulation time 49857648 ps
CPU time 1 seconds
Started Jul 17 07:10:01 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 200212 kb
Host smart-989f6c91-9a8b-4b0c-b6c4-b404512369ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234331440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3234331440
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2716550981
Short name T1184
Test name
Test status
Simulation time 83030242 ps
CPU time 0.61 seconds
Started Jul 17 07:10:58 PM PDT 24
Finished Jul 17 07:10:59 PM PDT 24
Peak memory 195028 kb
Host smart-ac5dff7c-0e47-4317-b38e-545a71b18842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716550981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2716550981
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.368216124
Short name T1299
Test name
Test status
Simulation time 26540251 ps
CPU time 0.58 seconds
Started Jul 17 07:10:55 PM PDT 24
Finished Jul 17 07:10:57 PM PDT 24
Peak memory 195208 kb
Host smart-e0607ce3-7aff-4f16-a5da-3bea848afaed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368216124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.368216124
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.90030588
Short name T1180
Test name
Test status
Simulation time 72685512 ps
CPU time 0.57 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:07 PM PDT 24
Peak memory 195316 kb
Host smart-1b6cdaee-b8cc-4a67-ba97-3870a456db85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90030588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.90030588
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2132832238
Short name T1220
Test name
Test status
Simulation time 29892630 ps
CPU time 0.55 seconds
Started Jul 17 07:11:01 PM PDT 24
Finished Jul 17 07:11:05 PM PDT 24
Peak memory 195244 kb
Host smart-636bc5f1-6381-4a64-9323-9fddac8e9a1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132832238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2132832238
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3351536059
Short name T1214
Test name
Test status
Simulation time 26618386 ps
CPU time 0.57 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:10 PM PDT 24
Peak memory 195328 kb
Host smart-3fdf3689-682c-434f-abc5-130579c94f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351536059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3351536059
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3590867455
Short name T1263
Test name
Test status
Simulation time 23969181 ps
CPU time 0.6 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 195100 kb
Host smart-dcd3745e-7922-42df-a2ee-9a0040b747e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590867455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3590867455
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.145158573
Short name T1215
Test name
Test status
Simulation time 24464522 ps
CPU time 0.56 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:07 PM PDT 24
Peak memory 195296 kb
Host smart-e66018c6-7b0e-453b-b660-74c6520780bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145158573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.145158573
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2707132592
Short name T1293
Test name
Test status
Simulation time 68275621 ps
CPU time 0.58 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 195340 kb
Host smart-a8d9008b-d502-4df0-a295-06e9aba544e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707132592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2707132592
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2553890586
Short name T1225
Test name
Test status
Simulation time 94551839 ps
CPU time 0.6 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:08 PM PDT 24
Peak memory 195316 kb
Host smart-678220bf-d8bb-4a7e-a8b2-d6a69fc82823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553890586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2553890586
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3590733972
Short name T1199
Test name
Test status
Simulation time 22798919 ps
CPU time 0.57 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:10 PM PDT 24
Peak memory 195328 kb
Host smart-115e3522-4c84-4b07-8662-fa83cf500d4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590733972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3590733972
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.714466549
Short name T66
Test name
Test status
Simulation time 29089025 ps
CPU time 0.85 seconds
Started Jul 17 07:10:01 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 197264 kb
Host smart-80807ffe-c818-4b3b-8cbb-8ff1662b5470
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714466549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.714466549
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3941300947
Short name T1308
Test name
Test status
Simulation time 155937021 ps
CPU time 1.4 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 198928 kb
Host smart-806f82bc-e1bd-4be1-b066-f715cb345148
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941300947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3941300947
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1105562428
Short name T1269
Test name
Test status
Simulation time 16178401 ps
CPU time 0.58 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:06 PM PDT 24
Peak memory 196232 kb
Host smart-79ca71a2-a137-4c3b-8091-fad2fc3576b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105562428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1105562428
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2035946112
Short name T1223
Test name
Test status
Simulation time 111274975 ps
CPU time 0.85 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:06 PM PDT 24
Peak memory 200744 kb
Host smart-a821e970-b414-4777-b860-b179ad30f61e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035946112 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2035946112
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1145700411
Short name T1273
Test name
Test status
Simulation time 78038256 ps
CPU time 0.62 seconds
Started Jul 17 07:09:57 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 197096 kb
Host smart-ffdcf755-384f-4bf9-83be-047e8133309e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145700411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1145700411
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.17903845
Short name T1262
Test name
Test status
Simulation time 11300867 ps
CPU time 0.57 seconds
Started Jul 17 07:10:02 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 195304 kb
Host smart-1a8409ae-7432-4242-b5fa-1d5c0edecafc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17903845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.17903845
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.82951365
Short name T79
Test name
Test status
Simulation time 18727053 ps
CPU time 0.62 seconds
Started Jul 17 07:09:58 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 196360 kb
Host smart-7dca9d5d-7089-41da-ab75-37f1f30eae47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82951365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_o
utstanding.82951365
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2789284338
Short name T1313
Test name
Test status
Simulation time 164005013 ps
CPU time 2.1 seconds
Started Jul 17 07:09:59 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 200944 kb
Host smart-38fb907a-cdd1-4172-86e6-e13bb57fec7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789284338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2789284338
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1489954955
Short name T86
Test name
Test status
Simulation time 79284064 ps
CPU time 1.33 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 200212 kb
Host smart-7ddf5682-44c1-452e-b503-5f40690a5a71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489954955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1489954955
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3327778130
Short name T1217
Test name
Test status
Simulation time 18210337 ps
CPU time 0.6 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:09 PM PDT 24
Peak memory 195072 kb
Host smart-60d43911-83c8-426c-a630-17997d6f0736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327778130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3327778130
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2653328416
Short name T1249
Test name
Test status
Simulation time 58321376 ps
CPU time 0.57 seconds
Started Jul 17 07:11:07 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 194516 kb
Host smart-9f5463f4-8f73-4fe0-8ecc-27dd7bc46c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653328416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2653328416
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2964769048
Short name T1305
Test name
Test status
Simulation time 32663185 ps
CPU time 0.57 seconds
Started Jul 17 07:11:03 PM PDT 24
Finished Jul 17 07:11:07 PM PDT 24
Peak memory 195300 kb
Host smart-75433c76-517f-4011-8991-91e7f811fd2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964769048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2964769048
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1945845896
Short name T1186
Test name
Test status
Simulation time 24112366 ps
CPU time 0.58 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 195228 kb
Host smart-a2c83a0b-12aa-43f5-ae4d-1b85018c3741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945845896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1945845896
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3212046715
Short name T1285
Test name
Test status
Simulation time 30423703 ps
CPU time 0.55 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:11 PM PDT 24
Peak memory 195292 kb
Host smart-6c70b561-86b3-498a-9a17-8ec210ace8e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212046715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3212046715
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3234944884
Short name T1189
Test name
Test status
Simulation time 23511142 ps
CPU time 0.59 seconds
Started Jul 17 07:11:07 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 194392 kb
Host smart-63b82da3-2a0d-4182-b9f3-138332f1bd71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234944884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3234944884
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3640313627
Short name T1230
Test name
Test status
Simulation time 54432150 ps
CPU time 0.56 seconds
Started Jul 17 07:11:05 PM PDT 24
Finished Jul 17 07:11:11 PM PDT 24
Peak memory 195272 kb
Host smart-5a03bd18-57c9-4047-84b9-34869154e26c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640313627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3640313627
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3018310965
Short name T1271
Test name
Test status
Simulation time 31793097 ps
CPU time 0.56 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 195288 kb
Host smart-4bb669b9-032c-4551-8c84-362a8e2ff02e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018310965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3018310965
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.984399957
Short name T1248
Test name
Test status
Simulation time 50355788 ps
CPU time 0.55 seconds
Started Jul 17 07:11:06 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 195344 kb
Host smart-35cce27e-fec4-4629-8f8f-9caae76c1ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984399957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.984399957
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2333153712
Short name T1247
Test name
Test status
Simulation time 30328299 ps
CPU time 0.55 seconds
Started Jul 17 07:11:04 PM PDT 24
Finished Jul 17 07:11:10 PM PDT 24
Peak memory 195208 kb
Host smart-578c5ea2-610e-4c76-b350-d76185ece751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333153712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2333153712
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1386256115
Short name T1235
Test name
Test status
Simulation time 21516279 ps
CPU time 0.74 seconds
Started Jul 17 07:10:02 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 200104 kb
Host smart-e61a9ffd-23ab-428e-826c-ae2726f40beb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386256115 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1386256115
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2145841080
Short name T82
Test name
Test status
Simulation time 59853958 ps
CPU time 0.6 seconds
Started Jul 17 07:09:55 PM PDT 24
Finished Jul 17 07:10:03 PM PDT 24
Peak memory 196408 kb
Host smart-4e745f61-ee76-4ef7-92b4-82d852fb1f9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145841080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2145841080
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2753900206
Short name T1272
Test name
Test status
Simulation time 11716284 ps
CPU time 0.58 seconds
Started Jul 17 07:09:54 PM PDT 24
Finished Jul 17 07:10:03 PM PDT 24
Peak memory 195276 kb
Host smart-075a53fb-5a26-49d8-94c5-dd6127a0d006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753900206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2753900206
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.802792011
Short name T1224
Test name
Test status
Simulation time 49224470 ps
CPU time 0.64 seconds
Started Jul 17 07:09:54 PM PDT 24
Finished Jul 17 07:10:03 PM PDT 24
Peak memory 196828 kb
Host smart-fea2c5b7-70fe-4225-862b-455637057e54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802792011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.802792011
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2300613975
Short name T1255
Test name
Test status
Simulation time 77701568 ps
CPU time 1.12 seconds
Started Jul 17 07:09:58 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 200972 kb
Host smart-0fa83401-174d-496c-a7d4-e2ab3d4e5089
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300613975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2300613975
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1038610678
Short name T95
Test name
Test status
Simulation time 54187609 ps
CPU time 1 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 199920 kb
Host smart-ee5d66ab-8f9f-4d22-99e4-393ea3e2e168
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038610678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1038610678
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2501558059
Short name T1268
Test name
Test status
Simulation time 60551213 ps
CPU time 0.65 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 198364 kb
Host smart-8a4a0063-31d6-4ee5-8ae3-530e4470fcd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501558059 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2501558059
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2373757200
Short name T1283
Test name
Test status
Simulation time 15780018 ps
CPU time 0.6 seconds
Started Jul 17 07:09:59 PM PDT 24
Finished Jul 17 07:10:06 PM PDT 24
Peak memory 196232 kb
Host smart-0a662090-a61b-49d9-802f-f64e9632d75c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373757200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2373757200
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1577425746
Short name T1226
Test name
Test status
Simulation time 44382571 ps
CPU time 0.61 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:06 PM PDT 24
Peak memory 195220 kb
Host smart-65f96910-b5fc-439d-9a60-20138c5cf495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577425746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1577425746
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1877145277
Short name T80
Test name
Test status
Simulation time 24758367 ps
CPU time 0.67 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 197488 kb
Host smart-5c35c43e-1dd1-4264-b818-5d9ea519add3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877145277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1877145277
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2403669949
Short name T1200
Test name
Test status
Simulation time 64838201 ps
CPU time 1.27 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 200956 kb
Host smart-5ce99872-bec6-49ca-a3d0-246afdd28650
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403669949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2403669949
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1399527257
Short name T1265
Test name
Test status
Simulation time 273725105 ps
CPU time 1.3 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 200164 kb
Host smart-4bf42a79-e68a-472e-9791-d01d2214301e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399527257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1399527257
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2570780137
Short name T1261
Test name
Test status
Simulation time 80443556 ps
CPU time 0.78 seconds
Started Jul 17 07:09:58 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 200744 kb
Host smart-b6eb4341-4038-4d57-853b-a48da1c1bf2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570780137 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2570780137
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.992510610
Short name T1259
Test name
Test status
Simulation time 81552464 ps
CPU time 0.6 seconds
Started Jul 17 07:10:01 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 196332 kb
Host smart-77a403f3-4f85-4610-86e4-f7e60337fcf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992510610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.992510610
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3750433059
Short name T1301
Test name
Test status
Simulation time 59911271 ps
CPU time 0.57 seconds
Started Jul 17 07:09:58 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 195296 kb
Host smart-83cdd5dc-4b3e-4c5f-a552-9c8f6c2b88ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750433059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3750433059
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2683199688
Short name T1206
Test name
Test status
Simulation time 14545234 ps
CPU time 0.62 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:06 PM PDT 24
Peak memory 196492 kb
Host smart-3c628cc3-51d3-41f0-96ad-eefac18674bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683199688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2683199688
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.842515925
Short name T1245
Test name
Test status
Simulation time 205470166 ps
CPU time 1.63 seconds
Started Jul 17 07:10:01 PM PDT 24
Finished Jul 17 07:10:09 PM PDT 24
Peak memory 200956 kb
Host smart-93a85aca-c9e7-48c8-9ef4-e1c522bd4446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842515925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.842515925
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.109766916
Short name T1270
Test name
Test status
Simulation time 1310748608 ps
CPU time 1.2 seconds
Started Jul 17 07:09:59 PM PDT 24
Finished Jul 17 07:10:06 PM PDT 24
Peak memory 200236 kb
Host smart-3a7aa24b-7ef8-46d6-9e89-220c7a862b47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109766916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.109766916
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1998010869
Short name T1201
Test name
Test status
Simulation time 64991571 ps
CPU time 0.74 seconds
Started Jul 17 07:10:01 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 200008 kb
Host smart-f01133de-88af-414e-b7ea-31667e34382e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998010869 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1998010869
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3266693705
Short name T1213
Test name
Test status
Simulation time 20494528 ps
CPU time 0.56 seconds
Started Jul 17 07:09:59 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 196292 kb
Host smart-b02cdeb6-43b7-4f8f-918d-0575af62f51b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266693705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3266693705
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3214900882
Short name T1190
Test name
Test status
Simulation time 12449321 ps
CPU time 0.58 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 195316 kb
Host smart-c8aa4087-b45f-4b7e-8a6f-8198dff37897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214900882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3214900882
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.685548185
Short name T1198
Test name
Test status
Simulation time 219827663 ps
CPU time 0.71 seconds
Started Jul 17 07:09:57 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 197664 kb
Host smart-2d258452-6bd5-44d7-ad50-868d53b6f287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685548185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.685548185
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2129492879
Short name T1256
Test name
Test status
Simulation time 176799000 ps
CPU time 1.77 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:08 PM PDT 24
Peak memory 200924 kb
Host smart-ccae3148-a45d-4a20-93e1-b56b3bf71062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129492879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2129492879
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1704923276
Short name T93
Test name
Test status
Simulation time 375379464 ps
CPU time 0.97 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 199724 kb
Host smart-d422b241-625e-4066-9238-9ea41c2c79d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704923276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1704923276
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.399868596
Short name T1291
Test name
Test status
Simulation time 17800270 ps
CPU time 0.75 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:06 PM PDT 24
Peak memory 199576 kb
Host smart-32276e4f-cf42-4470-bbc5-352f7f035166
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399868596 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.399868596
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1084527214
Short name T65
Test name
Test status
Simulation time 48573722 ps
CPU time 0.61 seconds
Started Jul 17 07:10:00 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 196656 kb
Host smart-e5e42fe1-405f-4ef5-a801-fa566a7a66ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084527214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1084527214
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2974875417
Short name T1290
Test name
Test status
Simulation time 40158733 ps
CPU time 0.61 seconds
Started Jul 17 07:09:52 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 195308 kb
Host smart-7f6cf266-a448-4fe8-aa53-7271bf611b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974875417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2974875417
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3417077554
Short name T1254
Test name
Test status
Simulation time 17046303 ps
CPU time 0.81 seconds
Started Jul 17 07:10:02 PM PDT 24
Finished Jul 17 07:10:09 PM PDT 24
Peak memory 197840 kb
Host smart-eda3c0dc-d3ea-4c99-9a65-cd8494919c30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417077554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3417077554
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3102244698
Short name T1227
Test name
Test status
Simulation time 304689452 ps
CPU time 2.63 seconds
Started Jul 17 07:09:57 PM PDT 24
Finished Jul 17 07:10:06 PM PDT 24
Peak memory 200960 kb
Host smart-5312c716-4edf-4bd3-a2fb-7a41cda00b61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102244698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3102244698
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1143116726
Short name T479
Test name
Test status
Simulation time 148605141856 ps
CPU time 19.42 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:50:43 PM PDT 24
Peak memory 200000 kb
Host smart-9eedecbe-80f4-4528-81bb-838ff237d11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143116726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1143116726
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.183272853
Short name T1130
Test name
Test status
Simulation time 26287804237 ps
CPU time 35.48 seconds
Started Jul 17 05:50:30 PM PDT 24
Finished Jul 17 05:51:07 PM PDT 24
Peak memory 199688 kb
Host smart-f1e0ecd4-8f0f-4cd4-b2db-29714addeb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183272853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.183272853
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3832271088
Short name T981
Test name
Test status
Simulation time 45085110566 ps
CPU time 34.05 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:50:57 PM PDT 24
Peak memory 199680 kb
Host smart-1b1f0406-76e6-4839-a06f-43ee74322383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832271088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3832271088
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3061158100
Short name T585
Test name
Test status
Simulation time 13764456819 ps
CPU time 21.13 seconds
Started Jul 17 05:50:27 PM PDT 24
Finished Jul 17 05:50:49 PM PDT 24
Peak memory 196460 kb
Host smart-c65b4185-b010-4aba-809b-06abb0965359
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061158100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3061158100
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_loopback.1266943255
Short name T901
Test name
Test status
Simulation time 7688360184 ps
CPU time 11.91 seconds
Started Jul 17 05:50:31 PM PDT 24
Finished Jul 17 05:50:44 PM PDT 24
Peak memory 199864 kb
Host smart-e2df4f7e-f9a6-485f-952f-5b2e4a9fe7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266943255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1266943255
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.45751646
Short name T686
Test name
Test status
Simulation time 50946658666 ps
CPU time 93.07 seconds
Started Jul 17 05:50:23 PM PDT 24
Finished Jul 17 05:51:58 PM PDT 24
Peak memory 199460 kb
Host smart-1afe5a98-83eb-4bc8-8db7-8a668a6c5fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45751646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.45751646
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2689506186
Short name T74
Test name
Test status
Simulation time 1860337672 ps
CPU time 23.6 seconds
Started Jul 17 05:50:30 PM PDT 24
Finished Jul 17 05:50:55 PM PDT 24
Peak memory 199588 kb
Host smart-5ffa293d-d75d-4f47-a8d2-93cef39b3bd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2689506186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2689506186
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3873688585
Short name T409
Test name
Test status
Simulation time 6622020403 ps
CPU time 15.87 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:50:39 PM PDT 24
Peak memory 197756 kb
Host smart-5ab0785a-feb0-40a4-a174-900bccc2cbfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3873688585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3873688585
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.16978207
Short name T721
Test name
Test status
Simulation time 323044829259 ps
CPU time 516.04 seconds
Started Jul 17 05:50:25 PM PDT 24
Finished Jul 17 05:59:03 PM PDT 24
Peak memory 199924 kb
Host smart-1b333ea4-a808-4d35-9cb5-25ae00318950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16978207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.16978207
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.437824517
Short name T610
Test name
Test status
Simulation time 2313695570 ps
CPU time 4.23 seconds
Started Jul 17 05:50:23 PM PDT 24
Finished Jul 17 05:50:29 PM PDT 24
Peak memory 195396 kb
Host smart-71a36ead-c8e7-43b8-badc-f3af598dd654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437824517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.437824517
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.4046633682
Short name T763
Test name
Test status
Simulation time 853047617 ps
CPU time 1.78 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:50:26 PM PDT 24
Peak memory 198428 kb
Host smart-0a2af941-6891-4092-81ee-de81ee302181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046633682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.4046633682
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3880083223
Short name T16
Test name
Test status
Simulation time 164908339385 ps
CPU time 136.64 seconds
Started Jul 17 05:50:27 PM PDT 24
Finished Jul 17 05:52:45 PM PDT 24
Peak memory 199960 kb
Host smart-3c4c2a40-ae39-4f53-b066-051dbdde05f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880083223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3880083223
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.938564254
Short name T820
Test name
Test status
Simulation time 93197592425 ps
CPU time 1571.35 seconds
Started Jul 17 05:50:23 PM PDT 24
Finished Jul 17 06:16:36 PM PDT 24
Peak memory 224836 kb
Host smart-2e1b70ef-35d1-48e2-bfd9-6e998fa196fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938564254 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.938564254
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1099557854
Short name T449
Test name
Test status
Simulation time 6876633517 ps
CPU time 16.67 seconds
Started Jul 17 05:50:25 PM PDT 24
Finished Jul 17 05:50:43 PM PDT 24
Peak memory 199824 kb
Host smart-82acb7d2-8ad1-451b-baf3-22aa78671e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099557854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1099557854
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_alert_test.489120577
Short name T805
Test name
Test status
Simulation time 12388104 ps
CPU time 0.55 seconds
Started Jul 17 05:50:33 PM PDT 24
Finished Jul 17 05:50:36 PM PDT 24
Peak memory 195236 kb
Host smart-233d753e-faf8-460c-a6f9-b535db81dba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489120577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.489120577
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2675352778
Short name T423
Test name
Test status
Simulation time 124549075382 ps
CPU time 95.17 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:51:58 PM PDT 24
Peak memory 199904 kb
Host smart-5b4544de-54de-43b8-8e9d-66aba6b3f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675352778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2675352778
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.4281694916
Short name T797
Test name
Test status
Simulation time 92369813074 ps
CPU time 31.96 seconds
Started Jul 17 05:50:24 PM PDT 24
Finished Jul 17 05:50:58 PM PDT 24
Peak memory 199864 kb
Host smart-ab5e4d73-4bf2-4813-9efb-e206525846dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281694916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.4281694916
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2817752600
Short name T831
Test name
Test status
Simulation time 30985582618 ps
CPU time 12.59 seconds
Started Jul 17 05:50:26 PM PDT 24
Finished Jul 17 05:50:40 PM PDT 24
Peak memory 199896 kb
Host smart-977072f1-c526-4c15-b539-a8209336d979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817752600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2817752600
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2148240546
Short name T628
Test name
Test status
Simulation time 48054943551 ps
CPU time 71.32 seconds
Started Jul 17 05:50:24 PM PDT 24
Finished Jul 17 05:51:37 PM PDT 24
Peak memory 199852 kb
Host smart-3f0aeab7-7b43-4651-bbbf-6eb012b14ae9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148240546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2148240546
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1557782305
Short name T457
Test name
Test status
Simulation time 105885927077 ps
CPU time 449.94 seconds
Started Jul 17 05:50:37 PM PDT 24
Finished Jul 17 05:58:08 PM PDT 24
Peak memory 199900 kb
Host smart-dd551b98-60b8-4861-babe-ef691c8b1740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557782305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1557782305
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2505253028
Short name T371
Test name
Test status
Simulation time 4080630769 ps
CPU time 7.06 seconds
Started Jul 17 05:50:23 PM PDT 24
Finished Jul 17 05:50:32 PM PDT 24
Peak memory 198568 kb
Host smart-872924f7-d525-4c5c-8236-ed9bd88ace0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505253028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2505253028
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.4169143264
Short name T416
Test name
Test status
Simulation time 45344409882 ps
CPU time 37.46 seconds
Started Jul 17 05:50:30 PM PDT 24
Finished Jul 17 05:51:09 PM PDT 24
Peak memory 200044 kb
Host smart-4b2fa73f-a4c3-4602-9985-a3effe12afd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169143264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.4169143264
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2618719615
Short name T609
Test name
Test status
Simulation time 1296333635 ps
CPU time 1.06 seconds
Started Jul 17 05:50:23 PM PDT 24
Finished Jul 17 05:50:26 PM PDT 24
Peak memory 195780 kb
Host smart-20682eef-485c-4b24-9816-4a63be149df1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618719615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2618719615
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2575614849
Short name T1170
Test name
Test status
Simulation time 107577777886 ps
CPU time 74.8 seconds
Started Jul 17 05:50:23 PM PDT 24
Finished Jul 17 05:51:39 PM PDT 24
Peak memory 199980 kb
Host smart-3374da7a-52fd-4c85-b305-3f13814ef34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575614849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2575614849
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2927409772
Short name T883
Test name
Test status
Simulation time 1758733945 ps
CPU time 1.34 seconds
Started Jul 17 05:50:27 PM PDT 24
Finished Jul 17 05:50:30 PM PDT 24
Peak memory 195392 kb
Host smart-26fee6a4-ec14-4d4b-8f81-43cab7ea0ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927409772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2927409772
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3160549744
Short name T97
Test name
Test status
Simulation time 202077844 ps
CPU time 0.79 seconds
Started Jul 17 05:50:34 PM PDT 24
Finished Jul 17 05:50:36 PM PDT 24
Peak memory 218376 kb
Host smart-898d6b9a-f2a7-46f2-b56b-f405980cdb3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160549744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3160549744
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1329007224
Short name T365
Test name
Test status
Simulation time 480792700 ps
CPU time 1.54 seconds
Started Jul 17 05:50:23 PM PDT 24
Finished Jul 17 05:50:26 PM PDT 24
Peak memory 198572 kb
Host smart-9181ceb3-a1f7-49f8-b84d-c20b25b4f051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329007224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1329007224
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3197921467
Short name T195
Test name
Test status
Simulation time 203242674146 ps
CPU time 446.27 seconds
Started Jul 17 05:50:35 PM PDT 24
Finished Jul 17 05:58:03 PM PDT 24
Peak memory 215604 kb
Host smart-71c86f5f-afbf-42ba-9058-c095f22326d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197921467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3197921467
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3359669948
Short name T1059
Test name
Test status
Simulation time 73574594765 ps
CPU time 543.48 seconds
Started Jul 17 05:50:34 PM PDT 24
Finished Jul 17 05:59:40 PM PDT 24
Peak memory 216720 kb
Host smart-fd73cd9f-9fc2-4173-8b2b-33b863ce9016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359669948 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3359669948
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3443095259
Short name T688
Test name
Test status
Simulation time 3250761527 ps
CPU time 2.06 seconds
Started Jul 17 05:50:29 PM PDT 24
Finished Jul 17 05:50:33 PM PDT 24
Peak memory 198492 kb
Host smart-51a97825-375d-4a5a-bae9-7cd2b4e0644e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443095259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3443095259
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.867809982
Short name T824
Test name
Test status
Simulation time 97969298052 ps
CPU time 17.75 seconds
Started Jul 17 05:50:30 PM PDT 24
Finished Jul 17 05:50:49 PM PDT 24
Peak memory 199536 kb
Host smart-270193b0-c261-41bf-8920-c3c3bd753b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867809982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.867809982
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3571502285
Short name T385
Test name
Test status
Simulation time 13781286 ps
CPU time 0.58 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 05:51:06 PM PDT 24
Peak memory 195444 kb
Host smart-d26407a6-da46-4534-ab9c-6c3c9d2dcd9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571502285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3571502285
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2326553970
Short name T608
Test name
Test status
Simulation time 20208406989 ps
CPU time 33.99 seconds
Started Jul 17 05:51:05 PM PDT 24
Finished Jul 17 05:51:41 PM PDT 24
Peak memory 199980 kb
Host smart-e860a988-e18e-4950-9576-c6c956e8b09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326553970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2326553970
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1760525972
Short name T454
Test name
Test status
Simulation time 71951497722 ps
CPU time 8.92 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 05:51:14 PM PDT 24
Peak memory 198504 kb
Host smart-bb69af0b-5886-49d5-96a3-6c5054d5f0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760525972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1760525972
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3826259480
Short name T774
Test name
Test status
Simulation time 100302627394 ps
CPU time 159.47 seconds
Started Jul 17 05:51:06 PM PDT 24
Finished Jul 17 05:53:48 PM PDT 24
Peak memory 199944 kb
Host smart-03542431-8fb9-4461-bf5e-87599810f40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826259480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3826259480
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1582903947
Short name T738
Test name
Test status
Simulation time 37538229594 ps
CPU time 15.7 seconds
Started Jul 17 05:51:05 PM PDT 24
Finished Jul 17 05:51:23 PM PDT 24
Peak memory 199756 kb
Host smart-d96959a2-d3b6-4b73-a864-a8586d6f0f92
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582903947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1582903947
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2829722298
Short name T866
Test name
Test status
Simulation time 112208880032 ps
CPU time 253.26 seconds
Started Jul 17 05:51:07 PM PDT 24
Finished Jul 17 05:55:22 PM PDT 24
Peak memory 199960 kb
Host smart-e505b6e8-a3a2-4230-b0ee-785bbfdb9ce1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2829722298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2829722298
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1768200932
Short name T71
Test name
Test status
Simulation time 1613419285 ps
CPU time 1.44 seconds
Started Jul 17 05:51:07 PM PDT 24
Finished Jul 17 05:51:10 PM PDT 24
Peak memory 197416 kb
Host smart-f4922291-cd2c-45d0-a3f0-06e74af58355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768200932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1768200932
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2970933020
Short name T68
Test name
Test status
Simulation time 18665423696 ps
CPU time 27.39 seconds
Started Jul 17 05:51:07 PM PDT 24
Finished Jul 17 05:51:37 PM PDT 24
Peak memory 200048 kb
Host smart-9c4a4398-2b73-4ac2-8cb1-4bfc270228f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970933020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2970933020
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.1084835466
Short name T1022
Test name
Test status
Simulation time 12941932710 ps
CPU time 649.24 seconds
Started Jul 17 05:51:07 PM PDT 24
Finished Jul 17 06:01:59 PM PDT 24
Peak memory 199892 kb
Host smart-fd64645f-2154-47cd-9c61-77204255c93a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1084835466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1084835466
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3001853848
Short name T391
Test name
Test status
Simulation time 1698627503 ps
CPU time 1.94 seconds
Started Jul 17 05:51:05 PM PDT 24
Finished Jul 17 05:51:10 PM PDT 24
Peak memory 198328 kb
Host smart-6b237c6c-d51b-4d5c-9958-fdd8cbcff4ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001853848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3001853848
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.458617038
Short name T49
Test name
Test status
Simulation time 27985108044 ps
CPU time 22.02 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 05:51:27 PM PDT 24
Peak memory 199884 kb
Host smart-c5be9e11-3af9-4b5b-b165-2d7f9674e12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458617038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.458617038
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1542361589
Short name T930
Test name
Test status
Simulation time 5509824889 ps
CPU time 3.11 seconds
Started Jul 17 05:51:01 PM PDT 24
Finished Jul 17 05:51:05 PM PDT 24
Peak memory 196328 kb
Host smart-e634188c-4b26-4b57-b639-b0f387b9b54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542361589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1542361589
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3772721528
Short name T851
Test name
Test status
Simulation time 6069711679 ps
CPU time 27.3 seconds
Started Jul 17 05:51:04 PM PDT 24
Finished Jul 17 05:51:34 PM PDT 24
Peak memory 199960 kb
Host smart-1cb89f93-78dc-4cc9-9f99-0871d61725c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772721528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3772721528
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.3110816914
Short name T1053
Test name
Test status
Simulation time 441142389345 ps
CPU time 637.85 seconds
Started Jul 17 05:51:07 PM PDT 24
Finished Jul 17 06:01:47 PM PDT 24
Peak memory 199856 kb
Host smart-ea21581d-811c-43c7-9269-59cb277bc0ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110816914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3110816914
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1273083769
Short name T843
Test name
Test status
Simulation time 96447656816 ps
CPU time 392.63 seconds
Started Jul 17 05:51:07 PM PDT 24
Finished Jul 17 05:57:42 PM PDT 24
Peak memory 216480 kb
Host smart-4c9c4cee-ce40-41b3-8134-a1e6cf3863d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273083769 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1273083769
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.645867693
Short name T434
Test name
Test status
Simulation time 688427666 ps
CPU time 2.01 seconds
Started Jul 17 05:51:04 PM PDT 24
Finished Jul 17 05:51:09 PM PDT 24
Peak memory 198576 kb
Host smart-5edf8fae-5e38-4d65-b341-27aef3ed7608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645867693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.645867693
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3509642424
Short name T258
Test name
Test status
Simulation time 335076111424 ps
CPU time 69.59 seconds
Started Jul 17 05:51:08 PM PDT 24
Finished Jul 17 05:52:20 PM PDT 24
Peak memory 199944 kb
Host smart-60e24aa2-9c58-4b8e-91e7-b0ff903d72c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509642424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3509642424
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1787573794
Short name T969
Test name
Test status
Simulation time 97818759510 ps
CPU time 79.79 seconds
Started Jul 17 05:54:41 PM PDT 24
Finished Jul 17 05:56:04 PM PDT 24
Peak memory 199984 kb
Host smart-432e52aa-ac38-4d08-93cd-9adf5ee90ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787573794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1787573794
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3822285457
Short name T232
Test name
Test status
Simulation time 15296347418 ps
CPU time 24.79 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:55:07 PM PDT 24
Peak memory 199980 kb
Host smart-66071ae6-6339-405f-b42a-8d82096ddb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822285457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3822285457
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2961467405
Short name T932
Test name
Test status
Simulation time 8468501723 ps
CPU time 14.86 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 05:54:57 PM PDT 24
Peak memory 199972 kb
Host smart-f13d4776-5a40-4593-aec3-cd283fcf9b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961467405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2961467405
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.4078121902
Short name T1151
Test name
Test status
Simulation time 34252523108 ps
CPU time 27.82 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:55:10 PM PDT 24
Peak memory 199916 kb
Host smart-a0c93f29-e574-4ea1-ab3e-36157fdc251a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078121902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.4078121902
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2463439490
Short name T751
Test name
Test status
Simulation time 89264223983 ps
CPU time 37.33 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 05:55:21 PM PDT 24
Peak memory 199880 kb
Host smart-6fbc9e14-c354-4b4b-bea6-a51c5855e7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463439490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2463439490
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3319649095
Short name T337
Test name
Test status
Simulation time 188534349320 ps
CPU time 66.51 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 05:55:50 PM PDT 24
Peak memory 199932 kb
Host smart-09b68bcf-215a-48d0-88b5-c5294e7bb5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319649095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3319649095
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.831084552
Short name T234
Test name
Test status
Simulation time 34183536894 ps
CPU time 14.6 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 05:54:58 PM PDT 24
Peak memory 199956 kb
Host smart-a1067a8c-192a-4de4-9c0c-6245cb23d6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831084552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.831084552
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.4198420807
Short name T218
Test name
Test status
Simulation time 10961841944 ps
CPU time 15.9 seconds
Started Jul 17 05:54:45 PM PDT 24
Finished Jul 17 05:55:02 PM PDT 24
Peak memory 199876 kb
Host smart-4e084b5d-abba-42db-8404-1b4a28434e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198420807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4198420807
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.490308965
Short name T896
Test name
Test status
Simulation time 128310408 ps
CPU time 0.55 seconds
Started Jul 17 05:51:14 PM PDT 24
Finished Jul 17 05:51:17 PM PDT 24
Peak memory 194744 kb
Host smart-8240199a-3e01-43a0-ab2c-e75b074acc7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490308965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.490308965
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2790464189
Short name T273
Test name
Test status
Simulation time 151440310340 ps
CPU time 223.91 seconds
Started Jul 17 05:51:07 PM PDT 24
Finished Jul 17 05:54:53 PM PDT 24
Peak memory 199964 kb
Host smart-78285adc-c226-46e0-95b8-5e24b25060ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790464189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2790464189
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1861649776
Short name T749
Test name
Test status
Simulation time 128919320942 ps
CPU time 53.18 seconds
Started Jul 17 05:51:05 PM PDT 24
Finished Jul 17 05:52:01 PM PDT 24
Peak memory 199980 kb
Host smart-92f9c679-7f23-482f-a765-7809f47ba782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861649776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1861649776
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1951542309
Short name T673
Test name
Test status
Simulation time 26820373784 ps
CPU time 25.26 seconds
Started Jul 17 05:51:07 PM PDT 24
Finished Jul 17 05:51:35 PM PDT 24
Peak memory 199932 kb
Host smart-28fc18e7-fe72-400e-91b6-d1edf7331c1e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951542309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1951542309
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3148206458
Short name T443
Test name
Test status
Simulation time 80914629295 ps
CPU time 616.64 seconds
Started Jul 17 05:51:16 PM PDT 24
Finished Jul 17 06:01:35 PM PDT 24
Peak memory 199912 kb
Host smart-07e0ee13-7ef7-46dc-8bcf-1e690fc1dbc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148206458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3148206458
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1927139217
Short name T912
Test name
Test status
Simulation time 7844054724 ps
CPU time 7.4 seconds
Started Jul 17 05:51:16 PM PDT 24
Finished Jul 17 05:51:25 PM PDT 24
Peak memory 198664 kb
Host smart-40b39406-827e-4ef1-b012-753d441d8dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927139217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1927139217
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.227419402
Short name T940
Test name
Test status
Simulation time 86892812891 ps
CPU time 72.82 seconds
Started Jul 17 05:51:12 PM PDT 24
Finished Jul 17 05:52:26 PM PDT 24
Peak memory 208300 kb
Host smart-43267a37-0571-4ace-bc2a-690160eae431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227419402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.227419402
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2504922880
Short name T687
Test name
Test status
Simulation time 10338611073 ps
CPU time 587.24 seconds
Started Jul 17 05:51:16 PM PDT 24
Finished Jul 17 06:01:06 PM PDT 24
Peak memory 199832 kb
Host smart-09e29d4b-774a-443c-8abf-bba1edc1a1f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2504922880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2504922880
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3695553450
Short name T855
Test name
Test status
Simulation time 2758139772 ps
CPU time 26.14 seconds
Started Jul 17 05:51:05 PM PDT 24
Finished Jul 17 05:51:34 PM PDT 24
Peak memory 198196 kb
Host smart-551beb8e-26d9-4456-968f-15f908b444a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3695553450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3695553450
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.335346293
Short name T979
Test name
Test status
Simulation time 29003617753 ps
CPU time 46.03 seconds
Started Jul 17 05:51:16 PM PDT 24
Finished Jul 17 05:52:05 PM PDT 24
Peak memory 199912 kb
Host smart-5550a527-86d2-4574-aa44-d8bfefe88642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335346293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.335346293
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.641064858
Short name T1154
Test name
Test status
Simulation time 83762164070 ps
CPU time 128.2 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 05:53:25 PM PDT 24
Peak memory 195716 kb
Host smart-e81e5008-7503-4c7c-a03b-114f3a7814d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641064858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.641064858
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.354753407
Short name T741
Test name
Test status
Simulation time 5864848489 ps
CPU time 15.94 seconds
Started Jul 17 05:51:06 PM PDT 24
Finished Jul 17 05:51:25 PM PDT 24
Peak memory 199820 kb
Host smart-3857f16e-df00-49b5-afa9-f2449268c295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354753407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.354753407
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.932050700
Short name T530
Test name
Test status
Simulation time 181804462176 ps
CPU time 244.94 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 05:55:22 PM PDT 24
Peak memory 199916 kb
Host smart-bde5601c-7868-4cc9-9a32-776daad6d659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932050700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.932050700
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2479414450
Short name T569
Test name
Test status
Simulation time 198734639974 ps
CPU time 739.99 seconds
Started Jul 17 05:51:13 PM PDT 24
Finished Jul 17 06:03:33 PM PDT 24
Peak memory 216460 kb
Host smart-6e160b44-c3c1-4b2e-90b7-3c6660fddf40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479414450 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2479414450
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.660573462
Short name T269
Test name
Test status
Simulation time 6287279770 ps
CPU time 18.71 seconds
Started Jul 17 05:51:16 PM PDT 24
Finished Jul 17 05:51:37 PM PDT 24
Peak memory 199696 kb
Host smart-48ff2388-9d8d-4414-9238-9d193e030f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660573462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.660573462
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2543149736
Short name T953
Test name
Test status
Simulation time 9034997885 ps
CPU time 9.86 seconds
Started Jul 17 05:51:07 PM PDT 24
Finished Jul 17 05:51:19 PM PDT 24
Peak memory 198356 kb
Host smart-af92cf09-2259-43a9-a206-787e74ae44c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543149736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2543149736
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.215759534
Short name T701
Test name
Test status
Simulation time 322712503369 ps
CPU time 33.77 seconds
Started Jul 17 05:54:41 PM PDT 24
Finished Jul 17 05:55:18 PM PDT 24
Peak memory 199892 kb
Host smart-b63213e3-f354-4d44-a049-6bdb3c0f16df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215759534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.215759534
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3325688327
Short name T642
Test name
Test status
Simulation time 46312574053 ps
CPU time 71.79 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 05:55:55 PM PDT 24
Peak memory 199856 kb
Host smart-84576486-ebab-4648-85a2-cd8b44a4ce45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325688327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3325688327
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1572536157
Short name T179
Test name
Test status
Simulation time 18565915497 ps
CPU time 31.29 seconds
Started Jul 17 05:54:38 PM PDT 24
Finished Jul 17 05:55:11 PM PDT 24
Peak memory 199972 kb
Host smart-0e80a268-8c27-4832-975e-8c954dd9f4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572536157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1572536157
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.4022470697
Short name T1027
Test name
Test status
Simulation time 113518962121 ps
CPU time 463.57 seconds
Started Jul 17 05:54:41 PM PDT 24
Finished Jul 17 06:02:28 PM PDT 24
Peak memory 199864 kb
Host smart-9c35fd96-7923-4ef6-93b0-4eeeb27f32ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022470697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4022470697
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2394342623
Short name T1060
Test name
Test status
Simulation time 60433903870 ps
CPU time 133.79 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:56:55 PM PDT 24
Peak memory 199980 kb
Host smart-ec88b6c7-24d1-4fa6-94fb-65eb6ee8a467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394342623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2394342623
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2917754165
Short name T689
Test name
Test status
Simulation time 180378530730 ps
CPU time 241.21 seconds
Started Jul 17 05:54:43 PM PDT 24
Finished Jul 17 05:58:46 PM PDT 24
Peak memory 199940 kb
Host smart-08fde57a-d215-42e0-8c86-8a3516ce505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917754165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2917754165
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.282275095
Short name T252
Test name
Test status
Simulation time 18249111757 ps
CPU time 8.87 seconds
Started Jul 17 05:54:43 PM PDT 24
Finished Jul 17 05:54:54 PM PDT 24
Peak memory 199920 kb
Host smart-3ae76b55-06a5-4799-833a-6716cc3b1080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282275095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.282275095
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3861715101
Short name T675
Test name
Test status
Simulation time 61037315397 ps
CPU time 85.24 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:56:06 PM PDT 24
Peak memory 199840 kb
Host smart-69d84a61-6fd6-4386-952b-0589f3f032cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861715101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3861715101
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2194886968
Short name T1163
Test name
Test status
Simulation time 113961905527 ps
CPU time 84.77 seconds
Started Jul 17 05:54:41 PM PDT 24
Finished Jul 17 05:56:09 PM PDT 24
Peak memory 199800 kb
Host smart-c48d31b4-3e5c-4c44-a5d5-6782a2dd2c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194886968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2194886968
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1011298944
Short name T1014
Test name
Test status
Simulation time 42144168 ps
CPU time 0.62 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 05:51:17 PM PDT 24
Peak memory 195584 kb
Host smart-c6c7e941-1455-4b8f-a445-84da20e63eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011298944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1011298944
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3060810819
Short name T728
Test name
Test status
Simulation time 59183123568 ps
CPU time 92.42 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 05:52:50 PM PDT 24
Peak memory 199976 kb
Host smart-f762218e-f330-4f05-af12-d2f75c00ee4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060810819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3060810819
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2004018588
Short name T778
Test name
Test status
Simulation time 153708181505 ps
CPU time 215.67 seconds
Started Jul 17 05:51:14 PM PDT 24
Finished Jul 17 05:54:50 PM PDT 24
Peak memory 199864 kb
Host smart-b3eeefde-f408-41c1-9ea9-2a3e9b0baddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004018588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2004018588
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.153403808
Short name T439
Test name
Test status
Simulation time 49520098993 ps
CPU time 78.15 seconds
Started Jul 17 05:51:14 PM PDT 24
Finished Jul 17 05:52:34 PM PDT 24
Peak memory 199872 kb
Host smart-d90b7bac-03c2-4781-b5bd-2c869d4c18e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153403808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.153403808
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.4052875993
Short name T992
Test name
Test status
Simulation time 511292423693 ps
CPU time 726.34 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 06:03:24 PM PDT 24
Peak memory 199064 kb
Host smart-022f6182-c052-4ce4-a691-4cd44c78c3a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052875993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.4052875993
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2489186923
Short name T1025
Test name
Test status
Simulation time 135168635378 ps
CPU time 1277.84 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 06:12:34 PM PDT 24
Peak memory 199848 kb
Host smart-fe527669-5b84-448f-85a5-4ee0478c849c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489186923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2489186923
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3995463468
Short name T425
Test name
Test status
Simulation time 1607003715 ps
CPU time 2.17 seconds
Started Jul 17 05:51:14 PM PDT 24
Finished Jul 17 05:51:18 PM PDT 24
Peak memory 197728 kb
Host smart-16be990a-4c29-448d-b4ce-26a51377ca8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995463468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3995463468
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2682270650
Short name T634
Test name
Test status
Simulation time 44129347624 ps
CPU time 173.9 seconds
Started Jul 17 05:51:13 PM PDT 24
Finished Jul 17 05:54:08 PM PDT 24
Peak memory 198900 kb
Host smart-6913eef8-9802-4c70-812b-86a6dd1599df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682270650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2682270650
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1186629075
Short name T272
Test name
Test status
Simulation time 15417706059 ps
CPU time 833.6 seconds
Started Jul 17 05:51:17 PM PDT 24
Finished Jul 17 06:05:13 PM PDT 24
Peak memory 199820 kb
Host smart-66b4fd4f-0d45-422a-beb9-9550ac0adf58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1186629075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1186629075
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1956359211
Short name T976
Test name
Test status
Simulation time 6754286871 ps
CPU time 58.69 seconds
Started Jul 17 05:51:13 PM PDT 24
Finished Jul 17 05:52:12 PM PDT 24
Peak memory 198064 kb
Host smart-e3e9c4dc-6537-4d98-bc76-c55935ff34f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956359211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1956359211
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.355547504
Short name T428
Test name
Test status
Simulation time 47149374306 ps
CPU time 41.73 seconds
Started Jul 17 05:51:19 PM PDT 24
Finished Jul 17 05:52:03 PM PDT 24
Peak memory 199948 kb
Host smart-9dc6dbc1-1f40-4e0f-a5d6-9ada44734929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355547504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.355547504
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1413283198
Short name T1175
Test name
Test status
Simulation time 5793967405 ps
CPU time 2.41 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 05:51:19 PM PDT 24
Peak memory 196672 kb
Host smart-b891aa8c-bbfe-45d9-8d6c-6500e51cb4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413283198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1413283198
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2090501550
Short name T1176
Test name
Test status
Simulation time 6055839965 ps
CPU time 17.3 seconds
Started Jul 17 05:51:16 PM PDT 24
Finished Jul 17 05:51:35 PM PDT 24
Peak memory 199844 kb
Host smart-76e80c24-7489-4459-8830-18e3894faea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090501550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2090501550
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1733655564
Short name T702
Test name
Test status
Simulation time 251732324325 ps
CPU time 544.58 seconds
Started Jul 17 05:51:14 PM PDT 24
Finished Jul 17 06:00:19 PM PDT 24
Peak memory 199992 kb
Host smart-2df39d37-6830-470e-8aff-ca757c46f139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733655564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1733655564
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2603302700
Short name T107
Test name
Test status
Simulation time 72527313664 ps
CPU time 185.02 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:54:26 PM PDT 24
Peak memory 208276 kb
Host smart-bb3848cc-3314-49eb-9667-476968069f4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603302700 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2603302700
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1794934726
Short name T45
Test name
Test status
Simulation time 839274427 ps
CPU time 2.57 seconds
Started Jul 17 05:51:17 PM PDT 24
Finished Jul 17 05:51:22 PM PDT 24
Peak memory 198872 kb
Host smart-e6686b31-daae-46ac-8ec4-648e93a3bab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794934726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1794934726
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1003373436
Short name T915
Test name
Test status
Simulation time 133235153389 ps
CPU time 45.98 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 05:52:03 PM PDT 24
Peak memory 199964 kb
Host smart-8f65eb17-8238-47b0-828f-f94be0c73069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003373436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1003373436
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3710571243
Short name T921
Test name
Test status
Simulation time 147973329626 ps
CPU time 28.47 seconds
Started Jul 17 05:54:41 PM PDT 24
Finished Jul 17 05:55:13 PM PDT 24
Peak memory 199952 kb
Host smart-2cbfa129-d3ff-48a4-b266-471bda07a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710571243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3710571243
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1205969868
Short name T850
Test name
Test status
Simulation time 122067388357 ps
CPU time 42.63 seconds
Started Jul 17 05:54:41 PM PDT 24
Finished Jul 17 05:55:27 PM PDT 24
Peak memory 199960 kb
Host smart-31bd0d44-f35a-449f-894c-497982e1149a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205969868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1205969868
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1082664938
Short name T1156
Test name
Test status
Simulation time 85895592674 ps
CPU time 47.28 seconds
Started Jul 17 05:54:42 PM PDT 24
Finished Jul 17 05:55:32 PM PDT 24
Peak memory 200000 kb
Host smart-bc269741-c5f7-4427-a66a-59e46190fb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082664938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1082664938
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1063409506
Short name T787
Test name
Test status
Simulation time 24945922303 ps
CPU time 39.05 seconds
Started Jul 17 05:54:42 PM PDT 24
Finished Jul 17 05:55:24 PM PDT 24
Peak memory 199988 kb
Host smart-2c2ca18d-cffe-4e6b-8ce1-670f2b4f269b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063409506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1063409506
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.432101967
Short name T196
Test name
Test status
Simulation time 33768980972 ps
CPU time 79.03 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:56:00 PM PDT 24
Peak memory 199968 kb
Host smart-75202721-8d36-4ec7-a437-4ea3a3e2cc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432101967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.432101967
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3473210395
Short name T250
Test name
Test status
Simulation time 70178742889 ps
CPU time 26.31 seconds
Started Jul 17 05:54:41 PM PDT 24
Finished Jul 17 05:55:10 PM PDT 24
Peak memory 199676 kb
Host smart-3f43b703-f5f0-4295-8211-35511ded2bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473210395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3473210395
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2777837822
Short name T1179
Test name
Test status
Simulation time 117906600996 ps
CPU time 261.63 seconds
Started Jul 17 05:54:41 PM PDT 24
Finished Jul 17 05:59:06 PM PDT 24
Peak memory 199728 kb
Host smart-437008ea-298d-4ed0-a96d-1abad5a28fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777837822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2777837822
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1777603760
Short name T553
Test name
Test status
Simulation time 122360325866 ps
CPU time 58.38 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 05:55:42 PM PDT 24
Peak memory 199844 kb
Host smart-c3e2b33f-0376-4907-9257-2a90879fcd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777603760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1777603760
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3488236176
Short name T547
Test name
Test status
Simulation time 28186576 ps
CPU time 0.58 seconds
Started Jul 17 05:51:16 PM PDT 24
Finished Jul 17 05:51:19 PM PDT 24
Peak memory 195292 kb
Host smart-0eefec0f-2139-4bbd-9fd9-3f00936cc74c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488236176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3488236176
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3041479541
Short name T503
Test name
Test status
Simulation time 191206026800 ps
CPU time 275.23 seconds
Started Jul 17 05:51:13 PM PDT 24
Finished Jul 17 05:55:49 PM PDT 24
Peak memory 199908 kb
Host smart-52ed656d-8fec-4dd0-991b-a9841f6e2466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041479541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3041479541
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1305472576
Short name T791
Test name
Test status
Simulation time 138448858784 ps
CPU time 67.42 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:52:28 PM PDT 24
Peak memory 199932 kb
Host smart-5a2f688c-d6b7-4e17-b18a-0737a261130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305472576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1305472576
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.432215330
Short name T779
Test name
Test status
Simulation time 23126152325 ps
CPU time 40.15 seconds
Started Jul 17 05:51:10 PM PDT 24
Finished Jul 17 05:51:51 PM PDT 24
Peak memory 200112 kb
Host smart-227ecf93-31d2-46c8-bea3-4e97f4fd69d2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432215330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.432215330
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3735246157
Short name T762
Test name
Test status
Simulation time 84165669335 ps
CPU time 166.54 seconds
Started Jul 17 05:51:16 PM PDT 24
Finished Jul 17 05:54:04 PM PDT 24
Peak memory 199812 kb
Host smart-049747cd-f7f0-486a-8dd4-456ca32e8612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3735246157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3735246157
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3702441953
Short name T359
Test name
Test status
Simulation time 9167543326 ps
CPU time 15.83 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:51:36 PM PDT 24
Peak memory 199868 kb
Host smart-0503be71-fe5a-421b-b63f-ed35a91f886e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702441953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3702441953
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1622719652
Short name T1012
Test name
Test status
Simulation time 33155850538 ps
CPU time 67.53 seconds
Started Jul 17 05:51:14 PM PDT 24
Finished Jul 17 05:52:23 PM PDT 24
Peak memory 199540 kb
Host smart-25c57db5-2a69-4c7f-90f4-d947334e6296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622719652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1622719652
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2668580285
Short name T1132
Test name
Test status
Simulation time 18156922315 ps
CPU time 248.22 seconds
Started Jul 17 05:51:14 PM PDT 24
Finished Jul 17 05:55:23 PM PDT 24
Peak memory 199928 kb
Host smart-9952a434-8d97-4447-939c-754bbc59a45e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668580285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2668580285
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.490105987
Short name T793
Test name
Test status
Simulation time 7091786374 ps
CPU time 67.74 seconds
Started Jul 17 05:51:14 PM PDT 24
Finished Jul 17 05:52:24 PM PDT 24
Peak memory 198860 kb
Host smart-bcc39c1a-7422-4f5f-9284-92aeb62ab3ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=490105987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.490105987
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.971299418
Short name T492
Test name
Test status
Simulation time 88827350922 ps
CPU time 57.33 seconds
Started Jul 17 05:51:12 PM PDT 24
Finished Jul 17 05:52:09 PM PDT 24
Peak memory 199820 kb
Host smart-7ba6d4e0-28aa-46d2-97d9-1ded9cd07d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971299418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.971299418
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2031943797
Short name T654
Test name
Test status
Simulation time 1728727397 ps
CPU time 1.99 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 05:51:19 PM PDT 24
Peak memory 195576 kb
Host smart-5933b2e0-0b50-4f61-959b-f3612b9f6e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031943797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2031943797
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3062980606
Short name T327
Test name
Test status
Simulation time 480580819 ps
CPU time 1.75 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 05:51:18 PM PDT 24
Peak memory 198684 kb
Host smart-b757d175-65df-4dee-b5ab-61ba18de5ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062980606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3062980606
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2522019663
Short name T330
Test name
Test status
Simulation time 173792172605 ps
CPU time 93.6 seconds
Started Jul 17 05:51:16 PM PDT 24
Finished Jul 17 05:52:51 PM PDT 24
Peak memory 199948 kb
Host smart-03c5c576-736e-4ac8-81b1-2cb40f42890b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522019663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2522019663
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1637313624
Short name T931
Test name
Test status
Simulation time 2622033541 ps
CPU time 2.16 seconds
Started Jul 17 05:51:16 PM PDT 24
Finished Jul 17 05:51:20 PM PDT 24
Peak memory 198908 kb
Host smart-2c1b2f5a-5377-45f7-be87-4848da91560b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637313624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1637313624
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2007366380
Short name T660
Test name
Test status
Simulation time 104200907432 ps
CPU time 57.19 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 05:52:14 PM PDT 24
Peak memory 199952 kb
Host smart-095d8764-9db1-47b5-9183-3ff6e3e5901b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007366380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2007366380
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1229408703
Short name T328
Test name
Test status
Simulation time 3948124009 ps
CPU time 6.41 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 05:54:50 PM PDT 24
Peak memory 199696 kb
Host smart-442396fd-b3ea-42b4-9a81-fa4ff36a1b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229408703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1229408703
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2846487958
Short name T998
Test name
Test status
Simulation time 148272888807 ps
CPU time 108.29 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 05:56:32 PM PDT 24
Peak memory 199816 kb
Host smart-87aeef32-8d11-4236-add7-efdc0061bf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846487958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2846487958
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2122651272
Short name T861
Test name
Test status
Simulation time 159936834168 ps
CPU time 25.55 seconds
Started Jul 17 05:54:41 PM PDT 24
Finished Jul 17 05:55:10 PM PDT 24
Peak memory 199628 kb
Host smart-b0aa0f06-dd8a-42b4-9240-e58af68e8404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122651272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2122651272
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.102177006
Short name T1103
Test name
Test status
Simulation time 57776819326 ps
CPU time 100.37 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:56:22 PM PDT 24
Peak memory 199928 kb
Host smart-617190af-c8ab-4e79-bbd1-f358a676febe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102177006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.102177006
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.4233156714
Short name T175
Test name
Test status
Simulation time 14422746210 ps
CPU time 23.35 seconds
Started Jul 17 05:54:43 PM PDT 24
Finished Jul 17 05:55:09 PM PDT 24
Peak memory 199976 kb
Host smart-9666aa20-06ac-415c-a588-f1b745d4e2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233156714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.4233156714
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2347091341
Short name T160
Test name
Test status
Simulation time 63970550996 ps
CPU time 35.23 seconds
Started Jul 17 05:54:42 PM PDT 24
Finished Jul 17 05:55:20 PM PDT 24
Peak memory 199836 kb
Host smart-690918cf-0b45-423f-82ba-662dd37a6c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347091341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2347091341
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2704845287
Short name T801
Test name
Test status
Simulation time 126630267436 ps
CPU time 189.98 seconds
Started Jul 17 05:54:55 PM PDT 24
Finished Jul 17 05:58:06 PM PDT 24
Peak memory 199864 kb
Host smart-36cd32a6-d22a-4d84-89c3-4c1ea98a151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704845287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2704845287
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1548240410
Short name T704
Test name
Test status
Simulation time 83080740743 ps
CPU time 25.41 seconds
Started Jul 17 05:54:50 PM PDT 24
Finished Jul 17 05:55:17 PM PDT 24
Peak memory 199856 kb
Host smart-8cb04a8a-64e9-4589-bb0d-01c1ac804a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548240410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1548240410
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.682679075
Short name T360
Test name
Test status
Simulation time 49183331 ps
CPU time 0.57 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:51:21 PM PDT 24
Peak memory 195300 kb
Host smart-0fbfb606-4ebc-41b3-b48e-8c965f320c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682679075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.682679075
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.4286309888
Short name T658
Test name
Test status
Simulation time 84262312079 ps
CPU time 21.33 seconds
Started Jul 17 05:51:13 PM PDT 24
Finished Jul 17 05:51:36 PM PDT 24
Peak memory 199960 kb
Host smart-26476f5f-210a-4f88-bd26-02dd488f8855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286309888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.4286309888
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1917040209
Short name T413
Test name
Test status
Simulation time 243897374909 ps
CPU time 141.41 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 05:53:39 PM PDT 24
Peak memory 199776 kb
Host smart-8f0d1297-d832-45e6-8afd-78fc822c1308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917040209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1917040209
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2533192555
Short name T782
Test name
Test status
Simulation time 9121038241 ps
CPU time 15.78 seconds
Started Jul 17 05:51:14 PM PDT 24
Finished Jul 17 05:51:31 PM PDT 24
Peak memory 199708 kb
Host smart-8c0668bc-f6a2-4b93-879a-0ad80df1de81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533192555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2533192555
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2140719833
Short name T113
Test name
Test status
Simulation time 79506005982 ps
CPU time 35.21 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:51:56 PM PDT 24
Peak memory 199972 kb
Host smart-4588e3c6-4ff5-485d-bc9b-95b3a59b6657
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140719833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2140719833
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1606874170
Short name T674
Test name
Test status
Simulation time 49770376895 ps
CPU time 299.6 seconds
Started Jul 17 05:51:29 PM PDT 24
Finished Jul 17 05:56:30 PM PDT 24
Peak memory 199964 kb
Host smart-37d5b466-8ad2-4918-9ff6-283cf3182bd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606874170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1606874170
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.292587543
Short name T374
Test name
Test status
Simulation time 9988000993 ps
CPU time 20.16 seconds
Started Jul 17 05:51:19 PM PDT 24
Finished Jul 17 05:51:41 PM PDT 24
Peak memory 199968 kb
Host smart-47914c59-5bb2-4859-a99e-06fc52baf818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292587543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.292587543
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1790037819
Short name T334
Test name
Test status
Simulation time 19866723681 ps
CPU time 30.16 seconds
Started Jul 17 05:51:17 PM PDT 24
Finished Jul 17 05:51:49 PM PDT 24
Peak memory 199992 kb
Host smart-e84a6a99-fa98-4d62-89fa-c9da1204ad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790037819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1790037819
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2985594350
Short name T821
Test name
Test status
Simulation time 14024341535 ps
CPU time 846.49 seconds
Started Jul 17 05:51:14 PM PDT 24
Finished Jul 17 06:05:22 PM PDT 24
Peak memory 199988 kb
Host smart-b30b07bb-6c88-48b7-8fb2-61c26d24757a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985594350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2985594350
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2824552428
Short name T361
Test name
Test status
Simulation time 4710613772 ps
CPU time 7.6 seconds
Started Jul 17 05:51:21 PM PDT 24
Finished Jul 17 05:51:29 PM PDT 24
Peak memory 198728 kb
Host smart-9f082b10-f285-4e01-bc5a-258ed0431d19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2824552428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2824552428
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.60651743
Short name T475
Test name
Test status
Simulation time 135699270479 ps
CPU time 402.03 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:58:02 PM PDT 24
Peak memory 199928 kb
Host smart-bbc39d2a-8aa7-4069-815a-6fca78c8c030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60651743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.60651743
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1495137025
Short name T691
Test name
Test status
Simulation time 2747636424 ps
CPU time 1.65 seconds
Started Jul 17 05:51:17 PM PDT 24
Finished Jul 17 05:51:21 PM PDT 24
Peak memory 195616 kb
Host smart-0d644d0d-9bff-4d17-b6ef-9b8a7d43140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495137025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1495137025
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.951703192
Short name T491
Test name
Test status
Simulation time 443022636 ps
CPU time 2.62 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:51:24 PM PDT 24
Peak memory 199576 kb
Host smart-398b9c66-76ae-4d42-a13d-35773bf290bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951703192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.951703192
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1201278189
Short name T497
Test name
Test status
Simulation time 822752935633 ps
CPU time 389.43 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:57:50 PM PDT 24
Peak memory 208368 kb
Host smart-5da69350-e8a3-4772-b32a-d7c0cc44431d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201278189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1201278189
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2421626985
Short name T752
Test name
Test status
Simulation time 56231592217 ps
CPU time 143.64 seconds
Started Jul 17 05:51:17 PM PDT 24
Finished Jul 17 05:53:44 PM PDT 24
Peak memory 210996 kb
Host smart-c24f0b3c-abc2-431d-950f-6cf4bc3fe41c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421626985 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2421626985
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2156551136
Short name T274
Test name
Test status
Simulation time 1155404284 ps
CPU time 2.48 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:51:23 PM PDT 24
Peak memory 198720 kb
Host smart-02b95d78-70f7-461c-a6fc-46c88a2431d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156551136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2156551136
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3625840060
Short name T881
Test name
Test status
Simulation time 33525865142 ps
CPU time 11.36 seconds
Started Jul 17 05:51:17 PM PDT 24
Finished Jul 17 05:51:31 PM PDT 24
Peak memory 197872 kb
Host smart-c520730c-a280-4aac-b891-61c3f2ba834a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625840060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3625840060
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.264303812
Short name T256
Test name
Test status
Simulation time 20596297747 ps
CPU time 13.55 seconds
Started Jul 17 05:54:51 PM PDT 24
Finished Jul 17 05:55:06 PM PDT 24
Peak memory 199992 kb
Host smart-8682c03a-eae1-4e22-a68c-2f61282e2495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264303812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.264303812
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3099492565
Short name T713
Test name
Test status
Simulation time 156548733920 ps
CPU time 91 seconds
Started Jul 17 05:54:50 PM PDT 24
Finished Jul 17 05:56:23 PM PDT 24
Peak memory 199896 kb
Host smart-9348c97f-4859-4111-8574-f32f71c042e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099492565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3099492565
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.753020676
Short name T799
Test name
Test status
Simulation time 23308535127 ps
CPU time 53.7 seconds
Started Jul 17 05:54:53 PM PDT 24
Finished Jul 17 05:55:48 PM PDT 24
Peak memory 199976 kb
Host smart-3b311ab8-a22e-47da-b8dc-c7784d33f180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753020676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.753020676
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.271202592
Short name T75
Test name
Test status
Simulation time 227251965325 ps
CPU time 16.51 seconds
Started Jul 17 05:54:51 PM PDT 24
Finished Jul 17 05:55:10 PM PDT 24
Peak memory 199248 kb
Host smart-3d2c34a3-4aa0-4833-87c1-c7e43fc1249e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271202592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.271202592
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2380654178
Short name T291
Test name
Test status
Simulation time 140308891975 ps
CPU time 133.2 seconds
Started Jul 17 05:54:50 PM PDT 24
Finished Jul 17 05:57:04 PM PDT 24
Peak memory 199992 kb
Host smart-83e2c9d3-eaa8-47a7-8a7a-71f20827274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380654178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2380654178
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.4093161801
Short name T1164
Test name
Test status
Simulation time 49819437563 ps
CPU time 18.3 seconds
Started Jul 17 05:54:54 PM PDT 24
Finished Jul 17 05:55:14 PM PDT 24
Peak memory 199868 kb
Host smart-2ec79087-18a8-407d-acbe-c1ae48ed695c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093161801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.4093161801
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2442123446
Short name T754
Test name
Test status
Simulation time 22023052853 ps
CPU time 34.59 seconds
Started Jul 17 05:54:47 PM PDT 24
Finished Jul 17 05:55:22 PM PDT 24
Peak memory 199940 kb
Host smart-af375e48-074a-4554-82ee-78d6200af97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442123446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2442123446
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1214108839
Short name T1042
Test name
Test status
Simulation time 8999319971 ps
CPU time 13.58 seconds
Started Jul 17 05:55:06 PM PDT 24
Finished Jul 17 05:55:21 PM PDT 24
Peak memory 198792 kb
Host smart-aaca9fe5-d666-441c-8468-034b6d85607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214108839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1214108839
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1098544189
Short name T810
Test name
Test status
Simulation time 158838969 ps
CPU time 0.54 seconds
Started Jul 17 05:51:15 PM PDT 24
Finished Jul 17 05:51:17 PM PDT 24
Peak memory 195268 kb
Host smart-14c1c86f-bdb1-4aa0-a4a4-18e7ca1f9291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098544189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1098544189
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.684148540
Short name T307
Test name
Test status
Simulation time 115842506706 ps
CPU time 58.96 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:52:20 PM PDT 24
Peak memory 199696 kb
Host smart-94788969-55b0-46f5-9185-6f8cbbe1f84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684148540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.684148540
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2478219863
Short name T561
Test name
Test status
Simulation time 35205816037 ps
CPU time 27.75 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:51:48 PM PDT 24
Peak memory 199988 kb
Host smart-8137be5f-8897-4d2c-8947-00d5732e1730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478219863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2478219863
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.219492573
Short name T695
Test name
Test status
Simulation time 129765455694 ps
CPU time 115.97 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:53:16 PM PDT 24
Peak memory 199932 kb
Host smart-85b56540-8084-48e6-9533-5ce099f9d38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219492573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.219492573
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2679725896
Short name T15
Test name
Test status
Simulation time 39802263324 ps
CPU time 7.57 seconds
Started Jul 17 05:51:19 PM PDT 24
Finished Jul 17 05:51:29 PM PDT 24
Peak memory 199924 kb
Host smart-f98822ce-8e0c-4479-bea4-9aadbd7f106a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679725896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2679725896
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.4118373263
Short name T672
Test name
Test status
Simulation time 294580046409 ps
CPU time 217.48 seconds
Started Jul 17 05:51:21 PM PDT 24
Finished Jul 17 05:54:59 PM PDT 24
Peak memory 199900 kb
Host smart-13e9892c-2131-47eb-853f-4dc597ba3ea9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4118373263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.4118373263
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3367701286
Short name T900
Test name
Test status
Simulation time 5397225557 ps
CPU time 17.07 seconds
Started Jul 17 05:51:19 PM PDT 24
Finished Jul 17 05:51:38 PM PDT 24
Peak memory 198996 kb
Host smart-c048a042-8ce5-4485-8a76-2a9a852f4ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367701286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3367701286
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2841766055
Short name T349
Test name
Test status
Simulation time 5796113676 ps
CPU time 7.24 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:51:28 PM PDT 24
Peak memory 194476 kb
Host smart-7397c91e-618c-4ebb-9afe-91274686133b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841766055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2841766055
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2853618485
Short name T830
Test name
Test status
Simulation time 11817161666 ps
CPU time 105.69 seconds
Started Jul 17 05:51:17 PM PDT 24
Finished Jul 17 05:53:06 PM PDT 24
Peak memory 199956 kb
Host smart-37c52f81-dc81-4b93-a90d-93221b24a67c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853618485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2853618485
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.172406249
Short name T720
Test name
Test status
Simulation time 6159655079 ps
CPU time 26.71 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:51:47 PM PDT 24
Peak memory 199292 kb
Host smart-565d9cae-9293-428d-a286-2304c6b9fd3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172406249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.172406249
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2848271590
Short name T441
Test name
Test status
Simulation time 109092766400 ps
CPU time 265.18 seconds
Started Jul 17 05:51:21 PM PDT 24
Finished Jul 17 05:55:47 PM PDT 24
Peak memory 199912 kb
Host smart-40d997cf-a3f6-46d8-bd02-f62a9d71df2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848271590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2848271590
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1664362276
Short name T1122
Test name
Test status
Simulation time 3849089052 ps
CPU time 6.16 seconds
Started Jul 17 05:51:21 PM PDT 24
Finished Jul 17 05:51:28 PM PDT 24
Peak memory 196212 kb
Host smart-5d5596c1-7d39-415b-ad9b-a442b408d03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664362276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1664362276
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3613804350
Short name T563
Test name
Test status
Simulation time 652011862 ps
CPU time 1.8 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:51:22 PM PDT 24
Peak memory 198336 kb
Host smart-bd6093ff-f08a-48cb-8629-675ed50bfa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613804350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3613804350
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1718406660
Short name T999
Test name
Test status
Simulation time 39300309138 ps
CPU time 20.38 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:51:41 PM PDT 24
Peak memory 199812 kb
Host smart-a84898a6-c851-42f6-b7df-c4bac4ce0e99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718406660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1718406660
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.103780630
Short name T678
Test name
Test status
Simulation time 268052077746 ps
CPU time 501.24 seconds
Started Jul 17 05:51:16 PM PDT 24
Finished Jul 17 05:59:39 PM PDT 24
Peak memory 224800 kb
Host smart-0253faab-6b1c-4fcb-9727-259cbb703b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103780630 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.103780630
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3842848168
Short name T970
Test name
Test status
Simulation time 826828779 ps
CPU time 1.92 seconds
Started Jul 17 05:51:22 PM PDT 24
Finished Jul 17 05:51:24 PM PDT 24
Peak memory 198716 kb
Host smart-30a5f412-6531-4d28-9d7e-105f6298d986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842848168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3842848168
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.204575178
Short name T663
Test name
Test status
Simulation time 23904744144 ps
CPU time 10.15 seconds
Started Jul 17 05:51:18 PM PDT 24
Finished Jul 17 05:51:31 PM PDT 24
Peak memory 199528 kb
Host smart-2b573f07-6539-474a-b893-f1df1764e57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204575178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.204575178
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.890726455
Short name T210
Test name
Test status
Simulation time 115287467498 ps
CPU time 263.85 seconds
Started Jul 17 05:54:55 PM PDT 24
Finished Jul 17 05:59:20 PM PDT 24
Peak memory 199920 kb
Host smart-36d6c3a7-f97a-40e1-85f6-eb948f34ec95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890726455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.890726455
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.397886593
Short name T1097
Test name
Test status
Simulation time 35281712068 ps
CPU time 13.84 seconds
Started Jul 17 05:54:54 PM PDT 24
Finished Jul 17 05:55:10 PM PDT 24
Peak memory 199916 kb
Host smart-45b6bd64-89de-4260-a827-c04a65fc716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397886593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.397886593
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2269847439
Short name T353
Test name
Test status
Simulation time 62210141216 ps
CPU time 29.52 seconds
Started Jul 17 05:54:50 PM PDT 24
Finished Jul 17 05:55:20 PM PDT 24
Peak memory 199920 kb
Host smart-ff1b7d70-a1f0-4dbe-aaa2-40e2e7dfea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269847439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2269847439
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2445381585
Short name T1100
Test name
Test status
Simulation time 212483930585 ps
CPU time 125.66 seconds
Started Jul 17 05:54:51 PM PDT 24
Finished Jul 17 05:56:59 PM PDT 24
Peak memory 199916 kb
Host smart-601ef987-643b-4adf-9036-76c531513dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445381585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2445381585
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2496593627
Short name T290
Test name
Test status
Simulation time 62964764685 ps
CPU time 133.45 seconds
Started Jul 17 05:54:54 PM PDT 24
Finished Jul 17 05:57:10 PM PDT 24
Peak memory 199872 kb
Host smart-d958368e-91fa-4473-a412-7a009b80e8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496593627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2496593627
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1219910356
Short name T987
Test name
Test status
Simulation time 125762581431 ps
CPU time 44.46 seconds
Started Jul 17 05:54:51 PM PDT 24
Finished Jul 17 05:55:37 PM PDT 24
Peak memory 199916 kb
Host smart-6e4c010e-d31f-4172-980e-a298c20d37b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219910356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1219910356
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2022032460
Short name T773
Test name
Test status
Simulation time 10399345637 ps
CPU time 5.2 seconds
Started Jul 17 05:54:51 PM PDT 24
Finished Jul 17 05:54:57 PM PDT 24
Peak memory 199928 kb
Host smart-ef56245a-2bad-4cf8-a131-90489765bf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022032460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2022032460
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3736408889
Short name T1004
Test name
Test status
Simulation time 13723971623 ps
CPU time 22.76 seconds
Started Jul 17 05:54:55 PM PDT 24
Finished Jul 17 05:55:19 PM PDT 24
Peak memory 199948 kb
Host smart-9915134c-1d37-4025-9efa-5af1bba76ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736408889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3736408889
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2800660961
Short name T581
Test name
Test status
Simulation time 7922595428 ps
CPU time 18.99 seconds
Started Jul 17 05:54:50 PM PDT 24
Finished Jul 17 05:55:11 PM PDT 24
Peak memory 199892 kb
Host smart-474469c5-b96b-40c5-829b-0d66dfe75984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800660961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2800660961
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3417893532
Short name T825
Test name
Test status
Simulation time 12468991 ps
CPU time 0.58 seconds
Started Jul 17 05:51:25 PM PDT 24
Finished Jul 17 05:51:28 PM PDT 24
Peak memory 195464 kb
Host smart-d1e22a7b-d6fd-41d4-9d00-45306814a7a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417893532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3417893532
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3713116014
Short name T849
Test name
Test status
Simulation time 145984858488 ps
CPU time 70.91 seconds
Started Jul 17 05:51:17 PM PDT 24
Finished Jul 17 05:52:31 PM PDT 24
Peak memory 200000 kb
Host smart-56e32afc-70f2-48e7-87e2-caaefba69e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713116014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3713116014
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2862199442
Short name T146
Test name
Test status
Simulation time 59920614250 ps
CPU time 30.23 seconds
Started Jul 17 05:51:25 PM PDT 24
Finished Jul 17 05:51:57 PM PDT 24
Peak memory 199936 kb
Host smart-3f27c939-d460-4e2e-9b40-88416a4ee924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862199442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2862199442
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1331543862
Short name T188
Test name
Test status
Simulation time 18998313498 ps
CPU time 9.4 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:51:38 PM PDT 24
Peak memory 199864 kb
Host smart-a2be2d4e-6b61-4ea4-9ede-d278f5ffc309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331543862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1331543862
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3757855420
Short name T1062
Test name
Test status
Simulation time 18329556717 ps
CPU time 8.72 seconds
Started Jul 17 05:51:25 PM PDT 24
Finished Jul 17 05:51:36 PM PDT 24
Peak memory 198684 kb
Host smart-8324711d-9e94-4cf5-82a4-47f371b8af90
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757855420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3757855420
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.997545818
Short name T268
Test name
Test status
Simulation time 127908250361 ps
CPU time 1047.81 seconds
Started Jul 17 05:51:28 PM PDT 24
Finished Jul 17 06:08:58 PM PDT 24
Peak memory 199956 kb
Host smart-ae0924f1-0e68-4070-bbd6-b609b0112e0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997545818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.997545818
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2239837653
Short name T354
Test name
Test status
Simulation time 60081288 ps
CPU time 0.7 seconds
Started Jul 17 05:51:30 PM PDT 24
Finished Jul 17 05:51:32 PM PDT 24
Peak memory 195872 kb
Host smart-13c9fe64-61c7-42df-874b-0a4bf6fdee8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239837653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2239837653
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1201626578
Short name T499
Test name
Test status
Simulation time 7352571244 ps
CPU time 7.36 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:51:36 PM PDT 24
Peak memory 199784 kb
Host smart-df0794c2-132e-49bf-9d20-8ef3969ab499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201626578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1201626578
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2453774120
Short name T1172
Test name
Test status
Simulation time 8311031106 ps
CPU time 491.54 seconds
Started Jul 17 05:51:25 PM PDT 24
Finished Jul 17 05:59:39 PM PDT 24
Peak memory 199892 kb
Host smart-7f3d9877-5af7-4eb9-8647-526d14d10095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453774120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2453774120
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.876671311
Short name T716
Test name
Test status
Simulation time 3775347941 ps
CPU time 6.39 seconds
Started Jul 17 05:51:32 PM PDT 24
Finished Jul 17 05:51:40 PM PDT 24
Peak memory 198200 kb
Host smart-16913946-91d1-43b8-9d21-1320a9674e6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=876671311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.876671311
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3395904333
Short name T620
Test name
Test status
Simulation time 118955461314 ps
CPU time 62.94 seconds
Started Jul 17 05:51:32 PM PDT 24
Finished Jul 17 05:52:37 PM PDT 24
Peak memory 199980 kb
Host smart-359d6a0c-9f9a-4f57-a2b9-f5f78588bf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395904333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3395904333
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1668473237
Short name T293
Test name
Test status
Simulation time 3515556619 ps
CPU time 6.16 seconds
Started Jul 17 05:51:27 PM PDT 24
Finished Jul 17 05:51:35 PM PDT 24
Peak memory 196216 kb
Host smart-967dc782-77b1-4557-81ad-c9cef807bed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668473237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1668473237
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.787475021
Short name T1008
Test name
Test status
Simulation time 6180382443 ps
CPU time 21.9 seconds
Started Jul 17 05:51:17 PM PDT 24
Finished Jul 17 05:51:41 PM PDT 24
Peak memory 199312 kb
Host smart-e9a44a4c-babb-40ca-a19d-9bb343b3632c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787475021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.787475021
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3400893903
Short name T1084
Test name
Test status
Simulation time 124388829456 ps
CPU time 245.14 seconds
Started Jul 17 05:51:31 PM PDT 24
Finished Jul 17 05:55:37 PM PDT 24
Peak memory 199864 kb
Host smart-90b6c197-f84e-47b8-8da7-5d2be61b7bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400893903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3400893903
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2151226973
Short name T989
Test name
Test status
Simulation time 102384102463 ps
CPU time 298.75 seconds
Started Jul 17 05:51:24 PM PDT 24
Finished Jul 17 05:56:25 PM PDT 24
Peak memory 216792 kb
Host smart-63da5153-98c9-4b76-bf49-eabe8edc5421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151226973 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2151226973
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.587651851
Short name T748
Test name
Test status
Simulation time 2976512059 ps
CPU time 2.09 seconds
Started Jul 17 05:51:32 PM PDT 24
Finished Jul 17 05:51:36 PM PDT 24
Peak memory 198588 kb
Host smart-2826350e-b623-412e-96c0-b5413ba3b23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587651851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.587651851
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1627108796
Short name T575
Test name
Test status
Simulation time 75751242707 ps
CPU time 48.29 seconds
Started Jul 17 05:51:14 PM PDT 24
Finished Jul 17 05:52:03 PM PDT 24
Peak memory 199928 kb
Host smart-efc1ff21-25fe-4a11-bda0-34bb5b851cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627108796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1627108796
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2187921348
Short name T871
Test name
Test status
Simulation time 102477189617 ps
CPU time 87.01 seconds
Started Jul 17 05:54:55 PM PDT 24
Finished Jul 17 05:56:24 PM PDT 24
Peak memory 199928 kb
Host smart-257e9544-a484-40be-8847-c1da531ac855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187921348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2187921348
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2100204231
Short name T242
Test name
Test status
Simulation time 44725328800 ps
CPU time 21.52 seconds
Started Jul 17 05:54:50 PM PDT 24
Finished Jul 17 05:55:12 PM PDT 24
Peak memory 199936 kb
Host smart-3c80ac55-8d11-48f6-92bb-955664c396c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100204231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2100204231
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3073319780
Short name T1065
Test name
Test status
Simulation time 119596644382 ps
CPU time 110.37 seconds
Started Jul 17 05:54:48 PM PDT 24
Finished Jul 17 05:56:39 PM PDT 24
Peak memory 199924 kb
Host smart-4c13e5f4-1bd0-4be3-82dd-755631850141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073319780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3073319780
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1714419187
Short name T165
Test name
Test status
Simulation time 94090645458 ps
CPU time 38.62 seconds
Started Jul 17 05:54:54 PM PDT 24
Finished Jul 17 05:55:33 PM PDT 24
Peak memory 199840 kb
Host smart-5ed9379d-1d3d-4a13-9731-dd8b6d716894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714419187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1714419187
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3869418935
Short name T3
Test name
Test status
Simulation time 53014365971 ps
CPU time 14.44 seconds
Started Jul 17 05:54:54 PM PDT 24
Finished Jul 17 05:55:10 PM PDT 24
Peak memory 199916 kb
Host smart-08589eb4-7fd0-4058-b686-9d5fb553e624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869418935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3869418935
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2074910928
Short name T725
Test name
Test status
Simulation time 17971223298 ps
CPU time 25.91 seconds
Started Jul 17 05:54:55 PM PDT 24
Finished Jul 17 05:55:23 PM PDT 24
Peak memory 199972 kb
Host smart-8241f5a5-978c-467d-9eb3-1994c5a00dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074910928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2074910928
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2171556158
Short name T368
Test name
Test status
Simulation time 22115440364 ps
CPU time 10.01 seconds
Started Jul 17 05:54:56 PM PDT 24
Finished Jul 17 05:55:07 PM PDT 24
Peak memory 198148 kb
Host smart-6ccd473c-0fd3-43e4-9bd7-a8dea31a88cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171556158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2171556158
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2122800551
Short name T1160
Test name
Test status
Simulation time 20052294219 ps
CPU time 14.17 seconds
Started Jul 17 05:54:55 PM PDT 24
Finished Jul 17 05:55:11 PM PDT 24
Peak memory 199940 kb
Host smart-a485726d-a223-479c-ae6f-b467768b8218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122800551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2122800551
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.650170864
Short name T238
Test name
Test status
Simulation time 137387646800 ps
CPU time 48.26 seconds
Started Jul 17 05:54:53 PM PDT 24
Finished Jul 17 05:55:42 PM PDT 24
Peak memory 199812 kb
Host smart-88b514db-c6d1-4421-a1b9-14b0065dceb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650170864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.650170864
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.4252868817
Short name T399
Test name
Test status
Simulation time 39265813 ps
CPU time 0.59 seconds
Started Jul 17 05:51:24 PM PDT 24
Finished Jul 17 05:51:26 PM PDT 24
Peak memory 195300 kb
Host smart-593d6278-2e7f-4d7e-b9b5-7731602d62eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252868817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.4252868817
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1596617309
Short name T527
Test name
Test status
Simulation time 23859241332 ps
CPU time 37.55 seconds
Started Jul 17 05:51:24 PM PDT 24
Finished Jul 17 05:52:04 PM PDT 24
Peak memory 199908 kb
Host smart-7fc941bd-a90e-4b3c-97a8-2173170c5e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596617309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1596617309
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.773863820
Short name T679
Test name
Test status
Simulation time 61139137861 ps
CPU time 62.23 seconds
Started Jul 17 05:51:28 PM PDT 24
Finished Jul 17 05:52:32 PM PDT 24
Peak memory 199832 kb
Host smart-c168cfb2-d29c-4fa9-8375-b2ac8eb71588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773863820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.773863820
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2641276683
Short name T177
Test name
Test status
Simulation time 115156358311 ps
CPU time 170.56 seconds
Started Jul 17 05:51:23 PM PDT 24
Finished Jul 17 05:54:15 PM PDT 24
Peak memory 200172 kb
Host smart-f0a42d20-843b-402e-967d-2a74577b3e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641276683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2641276683
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.4263990646
Short name T502
Test name
Test status
Simulation time 35118522834 ps
CPU time 56.28 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:52:25 PM PDT 24
Peak memory 198812 kb
Host smart-4b917286-be66-4533-82c8-679dd1764bd1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263990646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.4263990646
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2974627813
Short name T490
Test name
Test status
Simulation time 72734580753 ps
CPU time 580.74 seconds
Started Jul 17 05:51:25 PM PDT 24
Finished Jul 17 06:01:08 PM PDT 24
Peak memory 199852 kb
Host smart-657e1fb7-9913-4288-9829-94276720bcee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974627813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2974627813
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.656255658
Short name T662
Test name
Test status
Simulation time 1676043493 ps
CPU time 1.74 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:51:30 PM PDT 24
Peak memory 198416 kb
Host smart-016d7896-cdb4-4fb0-83f3-785c3b056516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656255658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.656255658
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.111710422
Short name T1051
Test name
Test status
Simulation time 151913097933 ps
CPU time 67.86 seconds
Started Jul 17 05:51:31 PM PDT 24
Finished Jul 17 05:52:41 PM PDT 24
Peak memory 200160 kb
Host smart-c5e7c46e-21cd-40bc-bb0c-264ee51be0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111710422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.111710422
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.4228187142
Short name T911
Test name
Test status
Simulation time 10269732438 ps
CPU time 122.63 seconds
Started Jul 17 05:51:40 PM PDT 24
Finished Jul 17 05:53:45 PM PDT 24
Peak memory 199960 kb
Host smart-1f872910-867c-4c9f-bcbe-7659729e8882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228187142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4228187142
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2819178121
Short name T1104
Test name
Test status
Simulation time 2972507071 ps
CPU time 11.26 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:51:39 PM PDT 24
Peak memory 199060 kb
Host smart-ec100a4b-2c7d-4662-85e6-2d8e59d41bbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2819178121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2819178121
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1526244793
Short name T865
Test name
Test status
Simulation time 42331914313 ps
CPU time 69.64 seconds
Started Jul 17 05:51:28 PM PDT 24
Finished Jul 17 05:52:40 PM PDT 24
Peak memory 199920 kb
Host smart-7b421055-0da3-4546-9405-6432dcd115a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526244793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1526244793
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4007419050
Short name T411
Test name
Test status
Simulation time 32800742746 ps
CPU time 18.95 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:51:48 PM PDT 24
Peak memory 196040 kb
Host smart-5b3686d6-ea17-44fa-8530-7c8fff84316d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007419050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4007419050
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.622599458
Short name T1078
Test name
Test status
Simulation time 6072278940 ps
CPU time 18.96 seconds
Started Jul 17 05:51:40 PM PDT 24
Finished Jul 17 05:52:01 PM PDT 24
Peak memory 199232 kb
Host smart-5becac5c-33e3-4e46-b5ff-cce41580e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622599458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.622599458
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1867993606
Short name T174
Test name
Test status
Simulation time 138723035012 ps
CPU time 96.4 seconds
Started Jul 17 05:51:23 PM PDT 24
Finished Jul 17 05:53:01 PM PDT 24
Peak memory 199912 kb
Host smart-5c187062-bf8f-4bd5-9f94-1bae554ec16d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867993606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1867993606
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3147120167
Short name T531
Test name
Test status
Simulation time 3919427525 ps
CPU time 1.47 seconds
Started Jul 17 05:51:25 PM PDT 24
Finished Jul 17 05:51:29 PM PDT 24
Peak memory 199080 kb
Host smart-b9b0c50c-8612-4098-9d5d-2c7338588629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147120167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3147120167
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1773341480
Short name T909
Test name
Test status
Simulation time 57497532757 ps
CPU time 167.38 seconds
Started Jul 17 05:51:25 PM PDT 24
Finished Jul 17 05:54:15 PM PDT 24
Peak memory 199904 kb
Host smart-d1070d71-aa96-49b2-912f-a23c49394286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773341480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1773341480
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.4202391117
Short name T301
Test name
Test status
Simulation time 10408549189 ps
CPU time 14.18 seconds
Started Jul 17 05:54:54 PM PDT 24
Finished Jul 17 05:55:10 PM PDT 24
Peak memory 199568 kb
Host smart-36d69346-7f97-4bc9-82ff-ae7dfac93856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202391117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.4202391117
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1179596085
Short name T309
Test name
Test status
Simulation time 25909235625 ps
CPU time 14.25 seconds
Started Jul 17 05:54:54 PM PDT 24
Finished Jul 17 05:55:10 PM PDT 24
Peak memory 199860 kb
Host smart-933c418f-6653-4d5c-bc16-bea2e79cf767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179596085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1179596085
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2992358370
Short name T1085
Test name
Test status
Simulation time 120433087632 ps
CPU time 161.12 seconds
Started Jul 17 05:54:49 PM PDT 24
Finished Jul 17 05:57:30 PM PDT 24
Peak memory 199984 kb
Host smart-de1e2dcb-3e03-41df-85a6-86a4996f6b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992358370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2992358370
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.497836022
Short name T331
Test name
Test status
Simulation time 39061320436 ps
CPU time 43.1 seconds
Started Jul 17 05:54:54 PM PDT 24
Finished Jul 17 05:55:39 PM PDT 24
Peak memory 200000 kb
Host smart-8f5b2ec0-8714-4272-94c1-823c7791c1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497836022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.497836022
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2877388405
Short name T239
Test name
Test status
Simulation time 167204877689 ps
CPU time 62.66 seconds
Started Jul 17 05:54:55 PM PDT 24
Finished Jul 17 05:55:59 PM PDT 24
Peak memory 199928 kb
Host smart-50e0e387-4372-411c-a50c-343ce9aab466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877388405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2877388405
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3637840362
Short name T185
Test name
Test status
Simulation time 47692487134 ps
CPU time 64.14 seconds
Started Jul 17 05:54:55 PM PDT 24
Finished Jul 17 05:56:01 PM PDT 24
Peak memory 199988 kb
Host smart-dcf87116-15a8-4f9c-a32e-7406726ada3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637840362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3637840362
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1476385905
Short name T303
Test name
Test status
Simulation time 29267264028 ps
CPU time 43.54 seconds
Started Jul 17 05:54:54 PM PDT 24
Finished Jul 17 05:55:40 PM PDT 24
Peak memory 199808 kb
Host smart-84fb8c26-ebb6-4cc9-9c5c-f317bdb01b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476385905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1476385905
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3774625013
Short name T476
Test name
Test status
Simulation time 23326634 ps
CPU time 0.54 seconds
Started Jul 17 05:51:28 PM PDT 24
Finished Jul 17 05:51:31 PM PDT 24
Peak memory 195576 kb
Host smart-4c9a887f-c015-4c81-ae62-951aa23e268e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774625013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3774625013
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1219504742
Short name T769
Test name
Test status
Simulation time 176978714760 ps
CPU time 231.31 seconds
Started Jul 17 05:51:23 PM PDT 24
Finished Jul 17 05:55:16 PM PDT 24
Peak memory 199976 kb
Host smart-e2948383-1600-484a-a452-ab0612c71d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219504742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1219504742
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.4116062915
Short name T461
Test name
Test status
Simulation time 32811612502 ps
CPU time 48.21 seconds
Started Jul 17 05:51:24 PM PDT 24
Finished Jul 17 05:52:14 PM PDT 24
Peak memory 199796 kb
Host smart-611054dc-ba68-4850-abb6-e4fa4308ca41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116062915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.4116062915
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2008775278
Short name T1044
Test name
Test status
Simulation time 103711831507 ps
CPU time 28.61 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:51:58 PM PDT 24
Peak memory 199864 kb
Host smart-1c81b8a5-2193-4cf6-91a8-b4028ec2d6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008775278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2008775278
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1025996507
Short name T112
Test name
Test status
Simulation time 337616592092 ps
CPU time 462.7 seconds
Started Jul 17 05:51:32 PM PDT 24
Finished Jul 17 05:59:17 PM PDT 24
Peak memory 197784 kb
Host smart-895ec9f2-6704-4243-b583-cbac42dec3b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025996507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1025996507
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3339843671
Short name T1165
Test name
Test status
Simulation time 75339459590 ps
CPU time 386.35 seconds
Started Jul 17 05:51:25 PM PDT 24
Finished Jul 17 05:57:54 PM PDT 24
Peak memory 199852 kb
Host smart-266b56ee-9ef1-47bb-857b-bd0fff87f04a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3339843671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3339843671
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.4134256726
Short name T341
Test name
Test status
Simulation time 4761406268 ps
CPU time 5.55 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:51:34 PM PDT 24
Peak memory 197796 kb
Host smart-9e0ffbfc-87a6-4f62-8955-ed7107a6ae29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134256726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.4134256726
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2672766712
Short name T262
Test name
Test status
Simulation time 171516239513 ps
CPU time 111.74 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:53:20 PM PDT 24
Peak memory 199264 kb
Host smart-14791dfb-3de2-412a-843e-6e501362c155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672766712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2672766712
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1874010141
Short name T586
Test name
Test status
Simulation time 19611151598 ps
CPU time 240.97 seconds
Started Jul 17 05:51:24 PM PDT 24
Finished Jul 17 05:55:26 PM PDT 24
Peak memory 199992 kb
Host smart-98234aff-f402-42be-8198-364024eb8fca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1874010141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1874010141
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2767927604
Short name T629
Test name
Test status
Simulation time 3173478680 ps
CPU time 28.67 seconds
Started Jul 17 05:51:27 PM PDT 24
Finished Jul 17 05:51:58 PM PDT 24
Peak memory 198200 kb
Host smart-9c2160c3-176e-4f92-89da-ac4f3e833ffc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767927604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2767927604
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2224573916
Short name T875
Test name
Test status
Simulation time 27308355279 ps
CPU time 19.74 seconds
Started Jul 17 05:51:40 PM PDT 24
Finished Jul 17 05:52:02 PM PDT 24
Peak memory 199928 kb
Host smart-f3ab255d-ffae-4539-bd1a-a64bc2c157fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224573916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2224573916
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2555122763
Short name T929
Test name
Test status
Simulation time 41354651259 ps
CPU time 4.31 seconds
Started Jul 17 05:51:30 PM PDT 24
Finished Jul 17 05:51:36 PM PDT 24
Peak memory 195716 kb
Host smart-a43e9a48-209b-4b10-b438-57b3d5cd62f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555122763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2555122763
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3826315933
Short name T973
Test name
Test status
Simulation time 528686334 ps
CPU time 1.48 seconds
Started Jul 17 05:51:40 PM PDT 24
Finished Jul 17 05:51:44 PM PDT 24
Peak memory 198304 kb
Host smart-e1075fef-1dca-4dea-89bc-58de399daf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826315933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3826315933
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3444104129
Short name T1035
Test name
Test status
Simulation time 130332318657 ps
CPU time 428.49 seconds
Started Jul 17 05:51:40 PM PDT 24
Finished Jul 17 05:58:51 PM PDT 24
Peak memory 199864 kb
Host smart-790c717a-fefe-4ede-bdaf-dd81bf1cd2cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444104129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3444104129
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.282035489
Short name T29
Test name
Test status
Simulation time 80250426821 ps
CPU time 238.97 seconds
Started Jul 17 05:51:40 PM PDT 24
Finished Jul 17 05:55:41 PM PDT 24
Peak memory 215208 kb
Host smart-6789126b-30d8-496c-96ae-7d0594eff7a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282035489 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.282035489
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3873283814
Short name T1142
Test name
Test status
Simulation time 7387803254 ps
CPU time 7.6 seconds
Started Jul 17 05:51:32 PM PDT 24
Finished Jul 17 05:51:41 PM PDT 24
Peak memory 199600 kb
Host smart-8a6126ee-391c-4a3a-874e-5bb6b8bf903c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873283814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3873283814
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2759309773
Short name T593
Test name
Test status
Simulation time 37506684963 ps
CPU time 20.18 seconds
Started Jul 17 05:51:31 PM PDT 24
Finished Jul 17 05:51:53 PM PDT 24
Peak memory 199960 kb
Host smart-15f16115-c4dd-4c49-b74f-48e2201da7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759309773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2759309773
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2634249444
Short name T488
Test name
Test status
Simulation time 97992170197 ps
CPU time 147.91 seconds
Started Jul 17 05:54:48 PM PDT 24
Finished Jul 17 05:57:16 PM PDT 24
Peak memory 200108 kb
Host smart-17338b89-c71d-4fab-9bb1-7401954323a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634249444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2634249444
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3812897788
Short name T867
Test name
Test status
Simulation time 56988414496 ps
CPU time 25.29 seconds
Started Jul 17 05:54:56 PM PDT 24
Finished Jul 17 05:55:23 PM PDT 24
Peak memory 199988 kb
Host smart-0721c491-45c7-4e69-b0aa-c99da63c51c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812897788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3812897788
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1202428580
Short name T118
Test name
Test status
Simulation time 4425185719 ps
CPU time 7.56 seconds
Started Jul 17 05:54:54 PM PDT 24
Finished Jul 17 05:55:04 PM PDT 24
Peak memory 198852 kb
Host smart-2a016908-518d-41a7-b4b5-ca3142b66728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202428580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1202428580
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3110783818
Short name T34
Test name
Test status
Simulation time 30873411434 ps
CPU time 24.77 seconds
Started Jul 17 05:54:53 PM PDT 24
Finished Jul 17 05:55:19 PM PDT 24
Peak memory 199968 kb
Host smart-fd2fa850-7e02-47e7-b35a-a82d52b163a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110783818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3110783818
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1117120940
Short name T415
Test name
Test status
Simulation time 80953705899 ps
CPU time 293.12 seconds
Started Jul 17 05:54:53 PM PDT 24
Finished Jul 17 05:59:47 PM PDT 24
Peak memory 199924 kb
Host smart-3e90e58f-071b-46ee-a704-bc7f3d12eb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117120940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1117120940
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1821822006
Short name T789
Test name
Test status
Simulation time 89544590527 ps
CPU time 33.89 seconds
Started Jul 17 05:55:04 PM PDT 24
Finished Jul 17 05:55:39 PM PDT 24
Peak memory 199968 kb
Host smart-8e39c550-de6c-4dcf-a3a0-9af8eec02e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821822006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1821822006
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3841032706
Short name T128
Test name
Test status
Simulation time 95177947560 ps
CPU time 217 seconds
Started Jul 17 05:55:05 PM PDT 24
Finished Jul 17 05:58:43 PM PDT 24
Peak memory 199868 kb
Host smart-e5a7039d-9938-428d-b249-f7b413c2a80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841032706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3841032706
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3390992125
Short name T5
Test name
Test status
Simulation time 60560655013 ps
CPU time 86.86 seconds
Started Jul 17 05:55:04 PM PDT 24
Finished Jul 17 05:56:33 PM PDT 24
Peak memory 199992 kb
Host smart-f18982ec-877b-4acb-904f-9837d8982877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390992125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3390992125
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2936822171
Short name T759
Test name
Test status
Simulation time 37016935 ps
CPU time 0.55 seconds
Started Jul 17 05:51:31 PM PDT 24
Finished Jul 17 05:51:33 PM PDT 24
Peak memory 195580 kb
Host smart-130e6399-2c5f-4294-941e-12b165a22ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936822171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2936822171
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.944770021
Short name T802
Test name
Test status
Simulation time 72735438979 ps
CPU time 30.3 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:51:58 PM PDT 24
Peak memory 199660 kb
Host smart-bfad9e55-fb03-4c7e-b9ed-af4803727c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944770021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.944770021
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.4045585629
Short name T589
Test name
Test status
Simulation time 37023316748 ps
CPU time 30 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:51:58 PM PDT 24
Peak memory 199884 kb
Host smart-58b84ccb-9962-41be-b805-be331e526df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045585629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.4045585629
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2371713224
Short name T229
Test name
Test status
Simulation time 47342622436 ps
CPU time 32.8 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:52:01 PM PDT 24
Peak memory 199908 kb
Host smart-6bebe642-450f-4731-aa1b-d46ef63eef0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371713224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2371713224
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2337554635
Short name T582
Test name
Test status
Simulation time 66426271347 ps
CPU time 90.35 seconds
Started Jul 17 05:51:25 PM PDT 24
Finished Jul 17 05:52:57 PM PDT 24
Peak memory 198948 kb
Host smart-31a127bb-8fbe-4d1d-93fa-28b0eceb68ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337554635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2337554635
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.4277357191
Short name T947
Test name
Test status
Simulation time 292782128224 ps
CPU time 376.08 seconds
Started Jul 17 05:58:54 PM PDT 24
Finished Jul 17 06:05:11 PM PDT 24
Peak memory 199892 kb
Host smart-5eae2d5a-6f6f-4c1b-aea2-501131022d80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277357191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.4277357191
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2880067488
Short name T387
Test name
Test status
Simulation time 121106841 ps
CPU time 0.95 seconds
Started Jul 17 05:51:23 PM PDT 24
Finished Jul 17 05:51:25 PM PDT 24
Peak memory 197588 kb
Host smart-cb971d79-c557-46a1-b526-db71631ff83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880067488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2880067488
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1303532923
Short name T567
Test name
Test status
Simulation time 25558492407 ps
CPU time 49.84 seconds
Started Jul 17 05:51:31 PM PDT 24
Finished Jul 17 05:52:23 PM PDT 24
Peak memory 199032 kb
Host smart-b8dcea6f-3fe3-43fc-ac2c-83dbffa100b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303532923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1303532923
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.191841417
Short name T470
Test name
Test status
Simulation time 10040346669 ps
CPU time 441.66 seconds
Started Jul 17 05:51:28 PM PDT 24
Finished Jul 17 05:58:52 PM PDT 24
Peak memory 199900 kb
Host smart-97c52046-a132-4381-bce2-fbaea756778d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=191841417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.191841417
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1375371834
Short name T1000
Test name
Test status
Simulation time 2970519531 ps
CPU time 19.92 seconds
Started Jul 17 05:51:25 PM PDT 24
Finished Jul 17 05:51:47 PM PDT 24
Peak memory 199124 kb
Host smart-a8147885-49b6-4cf0-b3ab-648e24f7f323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375371834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1375371834
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1692998911
Short name T163
Test name
Test status
Simulation time 51666558708 ps
CPU time 38.85 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:52:08 PM PDT 24
Peak memory 199916 kb
Host smart-580909ba-1a68-46d7-83e2-13047aa1382f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692998911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1692998911
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3257240248
Short name T693
Test name
Test status
Simulation time 5808006212 ps
CPU time 3.23 seconds
Started Jul 17 05:51:28 PM PDT 24
Finished Jul 17 05:51:33 PM PDT 24
Peak memory 196000 kb
Host smart-78bd46c7-ae77-46c1-a0f5-f4b37c181f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257240248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3257240248
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3910662173
Short name T645
Test name
Test status
Simulation time 907297874 ps
CPU time 2.48 seconds
Started Jul 17 05:51:40 PM PDT 24
Finished Jul 17 05:51:45 PM PDT 24
Peak memory 198648 kb
Host smart-511d838b-eac8-4b98-a539-a05e66e51277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910662173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3910662173
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1029273868
Short name T967
Test name
Test status
Simulation time 153942444785 ps
CPU time 73.06 seconds
Started Jul 17 05:51:28 PM PDT 24
Finished Jul 17 05:52:43 PM PDT 24
Peak memory 200084 kb
Host smart-cf80ed82-22ef-431f-8077-09918089170d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029273868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1029273868
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.4046162614
Short name T1123
Test name
Test status
Simulation time 54523501706 ps
CPU time 613.34 seconds
Started Jul 17 05:51:30 PM PDT 24
Finished Jul 17 06:01:45 PM PDT 24
Peak memory 224804 kb
Host smart-a9d22907-25a6-47e5-9e0c-e93db3fcc5cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046162614 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4046162614
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.509258765
Short name T412
Test name
Test status
Simulation time 7468522339 ps
CPU time 12.83 seconds
Started Jul 17 05:51:25 PM PDT 24
Finished Jul 17 05:51:40 PM PDT 24
Peak memory 199964 kb
Host smart-b49dd346-0e27-4b49-b237-daedb875e576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509258765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.509258765
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.991819037
Short name T951
Test name
Test status
Simulation time 38095061093 ps
CPU time 59.88 seconds
Started Jul 17 05:51:26 PM PDT 24
Finished Jul 17 05:52:29 PM PDT 24
Peak memory 199856 kb
Host smart-11f15e9e-04b2-4f97-b3f7-65dc73b6a5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991819037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.991819037
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1792803422
Short name T1052
Test name
Test status
Simulation time 10819913426 ps
CPU time 20.75 seconds
Started Jul 17 05:55:04 PM PDT 24
Finished Jul 17 05:55:26 PM PDT 24
Peak memory 199840 kb
Host smart-78b75925-8295-4f14-80fd-4458b0d5fe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792803422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1792803422
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2204143140
Short name T347
Test name
Test status
Simulation time 8210660081 ps
CPU time 13.62 seconds
Started Jul 17 05:55:03 PM PDT 24
Finished Jul 17 05:55:18 PM PDT 24
Peak memory 199772 kb
Host smart-9f33b38a-b006-42f5-abe1-db6c79f5d48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204143140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2204143140
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3575033987
Short name T548
Test name
Test status
Simulation time 116134115742 ps
CPU time 81.18 seconds
Started Jul 17 05:55:08 PM PDT 24
Finished Jul 17 05:56:30 PM PDT 24
Peak memory 199640 kb
Host smart-bb1bca27-5809-48b9-87af-b9982eb75fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575033987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3575033987
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1715427415
Short name T707
Test name
Test status
Simulation time 16111633641 ps
CPU time 30.88 seconds
Started Jul 17 05:55:04 PM PDT 24
Finished Jul 17 05:55:36 PM PDT 24
Peak memory 199904 kb
Host smart-2f6bd27e-6cab-4130-af10-aa3ef79997ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715427415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1715427415
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.626633312
Short name T513
Test name
Test status
Simulation time 19515963077 ps
CPU time 18.63 seconds
Started Jul 17 05:55:02 PM PDT 24
Finished Jul 17 05:55:21 PM PDT 24
Peak memory 199988 kb
Host smart-b1dc5444-95ea-4e41-aa3a-7cedbe1a25c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626633312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.626633312
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.4204340540
Short name T597
Test name
Test status
Simulation time 20650342027 ps
CPU time 39.94 seconds
Started Jul 17 05:55:09 PM PDT 24
Finished Jul 17 05:55:49 PM PDT 24
Peak memory 199972 kb
Host smart-1148c234-feaa-4597-b403-826996d369b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204340540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.4204340540
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3116664737
Short name T784
Test name
Test status
Simulation time 45661314390 ps
CPU time 19.33 seconds
Started Jul 17 05:55:04 PM PDT 24
Finished Jul 17 05:55:25 PM PDT 24
Peak memory 199972 kb
Host smart-3599f31d-3488-4d89-a064-aff40838dff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116664737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3116664737
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3744306856
Short name T1115
Test name
Test status
Simulation time 18092175194 ps
CPU time 27.6 seconds
Started Jul 17 05:55:02 PM PDT 24
Finished Jul 17 05:55:30 PM PDT 24
Peak memory 199888 kb
Host smart-b33441af-663b-40df-9836-553261fde88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744306856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3744306856
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2460636662
Short name T43
Test name
Test status
Simulation time 40776829206 ps
CPU time 16.06 seconds
Started Jul 17 05:55:03 PM PDT 24
Finished Jul 17 05:55:20 PM PDT 24
Peak memory 199600 kb
Host smart-97afb8ac-5500-4e44-a970-666619dd2080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460636662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2460636662
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3018565553
Short name T494
Test name
Test status
Simulation time 94395609206 ps
CPU time 75.52 seconds
Started Jul 17 05:55:08 PM PDT 24
Finished Jul 17 05:56:25 PM PDT 24
Peak memory 199896 kb
Host smart-b763cf5c-46b0-4b9f-a8ec-5c7faf8f87ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018565553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3018565553
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1887555193
Short name T404
Test name
Test status
Simulation time 24610495 ps
CPU time 0.56 seconds
Started Jul 17 05:50:36 PM PDT 24
Finished Jul 17 05:50:38 PM PDT 24
Peak memory 195268 kb
Host smart-47dcf9df-6613-4330-acc6-43659c1ea71b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887555193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1887555193
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.722575025
Short name T944
Test name
Test status
Simulation time 101682176935 ps
CPU time 161.16 seconds
Started Jul 17 05:50:35 PM PDT 24
Finished Jul 17 05:53:18 PM PDT 24
Peak memory 199840 kb
Host smart-9c3086b7-7d63-4d5e-ad01-873239931ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722575025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.722575025
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3337505773
Short name T121
Test name
Test status
Simulation time 16496891362 ps
CPU time 28.67 seconds
Started Jul 17 05:50:38 PM PDT 24
Finished Jul 17 05:51:08 PM PDT 24
Peak memory 199964 kb
Host smart-b57e2f18-54ee-435d-b3d1-686cefc81209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337505773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3337505773
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2466525518
Short name T440
Test name
Test status
Simulation time 13255794128 ps
CPU time 20.11 seconds
Started Jul 17 05:50:34 PM PDT 24
Finished Jul 17 05:50:56 PM PDT 24
Peak memory 196844 kb
Host smart-b99298f7-0c8b-42e3-b267-c7f42706502a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466525518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2466525518
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1601898499
Short name T965
Test name
Test status
Simulation time 89125665991 ps
CPU time 302.84 seconds
Started Jul 17 05:50:34 PM PDT 24
Finished Jul 17 05:55:38 PM PDT 24
Peak memory 199896 kb
Host smart-fd9a8897-eee9-48e2-a4c4-ae3e18f8c9e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1601898499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1601898499
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3177766657
Short name T388
Test name
Test status
Simulation time 3796165483 ps
CPU time 3.63 seconds
Started Jul 17 05:50:34 PM PDT 24
Finished Jul 17 05:50:40 PM PDT 24
Peak memory 198812 kb
Host smart-f65e9c77-6f1e-4639-800d-3f595bb86afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177766657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3177766657
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1375354204
Short name T711
Test name
Test status
Simulation time 14165071813 ps
CPU time 10.99 seconds
Started Jul 17 05:50:34 PM PDT 24
Finished Jul 17 05:50:47 PM PDT 24
Peak memory 194612 kb
Host smart-179450c0-151a-4ee1-941a-543ae5656003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375354204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1375354204
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2238912089
Short name T670
Test name
Test status
Simulation time 6870154291 ps
CPU time 352.07 seconds
Started Jul 17 05:50:39 PM PDT 24
Finished Jul 17 05:56:33 PM PDT 24
Peak memory 200180 kb
Host smart-066a223e-93ab-443c-b7db-415df2714c5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2238912089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2238912089
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.808554973
Short name T948
Test name
Test status
Simulation time 1482774338 ps
CPU time 6.03 seconds
Started Jul 17 05:50:39 PM PDT 24
Finished Jul 17 05:50:47 PM PDT 24
Peak memory 198108 kb
Host smart-3aa1b1ff-8502-46c6-9524-840e8f4135af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808554973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.808554973
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3387595946
Short name T414
Test name
Test status
Simulation time 14276571445 ps
CPU time 8.67 seconds
Started Jul 17 05:50:36 PM PDT 24
Finished Jul 17 05:50:46 PM PDT 24
Peak memory 199948 kb
Host smart-8f1ac680-9ed3-4754-830b-fe8c7c7b39be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387595946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3387595946
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1607366958
Short name T882
Test name
Test status
Simulation time 3789748665 ps
CPU time 6.42 seconds
Started Jul 17 05:50:34 PM PDT 24
Finished Jul 17 05:50:41 PM PDT 24
Peak memory 196228 kb
Host smart-2d563fc4-7e59-488a-b16c-bccaa9ef68ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607366958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1607366958
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.153076348
Short name T23
Test name
Test status
Simulation time 69933472 ps
CPU time 0.83 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:50:49 PM PDT 24
Peak memory 218212 kb
Host smart-2556edfc-9a1c-4959-aa23-0b83243c74bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153076348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.153076348
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1139955034
Short name T895
Test name
Test status
Simulation time 110637287 ps
CPU time 0.92 seconds
Started Jul 17 05:50:33 PM PDT 24
Finished Jul 17 05:50:35 PM PDT 24
Peak memory 197448 kb
Host smart-df625e8c-0c96-47ae-8509-89e95f1682bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139955034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1139955034
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.908494653
Short name T826
Test name
Test status
Simulation time 98963736732 ps
CPU time 44.13 seconds
Started Jul 17 05:50:34 PM PDT 24
Finished Jul 17 05:51:20 PM PDT 24
Peak memory 200064 kb
Host smart-702abcc2-fbb9-443b-82e9-5e8fe748e52c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908494653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.908494653
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3815882357
Short name T800
Test name
Test status
Simulation time 56739263142 ps
CPU time 609.31 seconds
Started Jul 17 05:50:39 PM PDT 24
Finished Jul 17 06:00:51 PM PDT 24
Peak memory 216500 kb
Host smart-a1a9aead-c4c3-4ba2-8124-1834991a342b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815882357 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3815882357
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2181334338
Short name T599
Test name
Test status
Simulation time 3385923099 ps
CPU time 3.06 seconds
Started Jul 17 05:50:35 PM PDT 24
Finished Jul 17 05:50:40 PM PDT 24
Peak memory 199192 kb
Host smart-976b314e-c650-41e2-a5ba-6c7380d04814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181334338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2181334338
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1554816062
Short name T1043
Test name
Test status
Simulation time 44447572383 ps
CPU time 64.97 seconds
Started Jul 17 05:50:37 PM PDT 24
Finished Jul 17 05:51:43 PM PDT 24
Peak memory 199908 kb
Host smart-18f6d37a-b659-4ae8-9e4a-be049cd9d515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554816062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1554816062
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.155164587
Short name T20
Test name
Test status
Simulation time 66006795 ps
CPU time 0.56 seconds
Started Jul 17 05:51:39 PM PDT 24
Finished Jul 17 05:51:42 PM PDT 24
Peak memory 194484 kb
Host smart-58d363e5-c134-4350-97f9-38f0d2ffeb20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155164587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.155164587
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1473436389
Short name T493
Test name
Test status
Simulation time 114755069629 ps
CPU time 191.78 seconds
Started Jul 17 05:51:37 PM PDT 24
Finished Jul 17 05:54:51 PM PDT 24
Peak memory 199936 kb
Host smart-dc6fd818-c158-4a5b-9802-bbe57fe53873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473436389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1473436389
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.600132358
Short name T308
Test name
Test status
Simulation time 216611304604 ps
CPU time 23.37 seconds
Started Jul 17 05:51:36 PM PDT 24
Finished Jul 17 05:52:00 PM PDT 24
Peak memory 199664 kb
Host smart-53d0551d-30f4-4222-8b4a-9ec9c3e1b2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600132358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.600132358
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.1675814686
Short name T1024
Test name
Test status
Simulation time 8606581964 ps
CPU time 8.07 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:51:48 PM PDT 24
Peak memory 197716 kb
Host smart-815c96cf-18ee-4925-90ec-50f94e7de07d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675814686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1675814686
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2279312461
Short name T669
Test name
Test status
Simulation time 309810809077 ps
CPU time 259.2 seconds
Started Jul 17 05:51:40 PM PDT 24
Finished Jul 17 05:56:02 PM PDT 24
Peak memory 199956 kb
Host smart-84f4bca5-92f7-49f7-9469-ffc3a873c72d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2279312461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2279312461
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.4255247191
Short name T1119
Test name
Test status
Simulation time 3571810247 ps
CPU time 3.58 seconds
Started Jul 17 05:51:35 PM PDT 24
Finished Jul 17 05:51:40 PM PDT 24
Peak memory 198196 kb
Host smart-a0562611-9275-49c7-932e-9de0b948d0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255247191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.4255247191
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.4287020150
Short name T1113
Test name
Test status
Simulation time 7240977012 ps
CPU time 99.64 seconds
Started Jul 17 05:51:39 PM PDT 24
Finished Jul 17 05:53:22 PM PDT 24
Peak memory 199752 kb
Host smart-d1ba6907-52ed-4671-a054-2a31dbb65ba3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4287020150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.4287020150
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2989603032
Short name T1033
Test name
Test status
Simulation time 2116080069 ps
CPU time 3.33 seconds
Started Jul 17 05:51:36 PM PDT 24
Finished Jul 17 05:51:41 PM PDT 24
Peak memory 198060 kb
Host smart-815991ba-7f98-4d47-93d8-6751ae25c1c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2989603032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2989603032
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.498034699
Short name T950
Test name
Test status
Simulation time 140281535759 ps
CPU time 230.14 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:55:31 PM PDT 24
Peak memory 199880 kb
Host smart-a0cd4411-f934-4a93-ac37-207bf9b7d8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498034699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.498034699
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.4201381191
Short name T848
Test name
Test status
Simulation time 2777932554 ps
CPU time 1.59 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:51:43 PM PDT 24
Peak memory 196424 kb
Host smart-83bc8fff-4b64-4216-9171-527b11543cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201381191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.4201381191
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.4127170906
Short name T397
Test name
Test status
Simulation time 146821518 ps
CPU time 0.72 seconds
Started Jul 17 05:51:31 PM PDT 24
Finished Jul 17 05:51:34 PM PDT 24
Peak memory 196956 kb
Host smart-4aecbdc3-3d07-42f7-9e01-42df6c4c0006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127170906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.4127170906
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3946203196
Short name T480
Test name
Test status
Simulation time 157903672173 ps
CPU time 47.63 seconds
Started Jul 17 05:51:39 PM PDT 24
Finished Jul 17 05:52:30 PM PDT 24
Peak memory 199692 kb
Host smart-d2bb4a26-a7df-441f-ab79-82477bfff0e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946203196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3946203196
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2164443166
Short name T2
Test name
Test status
Simulation time 38873537466 ps
CPU time 190.42 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:54:51 PM PDT 24
Peak memory 216412 kb
Host smart-5ad2ba97-dcb8-4f4b-ab1f-e3b0accbfa5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164443166 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2164443166
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2938275812
Short name T304
Test name
Test status
Simulation time 8616975254 ps
CPU time 8.02 seconds
Started Jul 17 05:51:36 PM PDT 24
Finished Jul 17 05:51:46 PM PDT 24
Peak memory 199964 kb
Host smart-4463989d-c1ae-423a-a5bd-1d03a1b148a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938275812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2938275812
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3744943673
Short name T927
Test name
Test status
Simulation time 41063004967 ps
CPU time 15.89 seconds
Started Jul 17 05:51:40 PM PDT 24
Finished Jul 17 05:51:58 PM PDT 24
Peak memory 197628 kb
Host smart-e75c286a-4f9e-44a4-a937-90f08f135252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744943673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3744943673
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2049340895
Short name T228
Test name
Test status
Simulation time 126505971222 ps
CPU time 26.59 seconds
Started Jul 17 05:55:02 PM PDT 24
Finished Jul 17 05:55:30 PM PDT 24
Peak memory 199864 kb
Host smart-3f555bff-9676-4a99-bed1-f5f273098b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049340895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2049340895
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.362172193
Short name T318
Test name
Test status
Simulation time 161900576535 ps
CPU time 242.4 seconds
Started Jul 17 05:55:04 PM PDT 24
Finished Jul 17 05:59:07 PM PDT 24
Peak memory 199908 kb
Host smart-17d8eb94-2d54-4233-85d5-d18c0457ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362172193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.362172193
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2397245505
Short name T172
Test name
Test status
Simulation time 41921353564 ps
CPU time 21.6 seconds
Started Jul 17 05:55:03 PM PDT 24
Finished Jul 17 05:55:25 PM PDT 24
Peak memory 199988 kb
Host smart-9ba576c2-3238-48f1-b910-7e6a18ee25f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397245505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2397245505
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.532722900
Short name T1120
Test name
Test status
Simulation time 72430906849 ps
CPU time 29.89 seconds
Started Jul 17 05:55:05 PM PDT 24
Finished Jul 17 05:55:37 PM PDT 24
Peak memory 199932 kb
Host smart-32792c41-dd4f-4efc-9e58-07c94083b487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532722900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.532722900
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1198526273
Short name T122
Test name
Test status
Simulation time 39643322679 ps
CPU time 64.21 seconds
Started Jul 17 05:55:03 PM PDT 24
Finished Jul 17 05:56:08 PM PDT 24
Peak memory 199940 kb
Host smart-e5fa98ac-b7fe-4e99-b946-4f9e298ec775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198526273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1198526273
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1303020209
Short name T960
Test name
Test status
Simulation time 20893699705 ps
CPU time 12.19 seconds
Started Jul 17 05:55:09 PM PDT 24
Finished Jul 17 05:55:22 PM PDT 24
Peak memory 199992 kb
Host smart-8ca87531-084c-4824-af02-2ba3421d34a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303020209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1303020209
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2411405832
Short name T1112
Test name
Test status
Simulation time 93947754421 ps
CPU time 22.85 seconds
Started Jul 17 05:55:04 PM PDT 24
Finished Jul 17 05:55:28 PM PDT 24
Peak memory 199920 kb
Host smart-dde1cd1a-718a-4fe9-8d09-7ab009dd7b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411405832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2411405832
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.484281659
Short name T692
Test name
Test status
Simulation time 30759193260 ps
CPU time 51.99 seconds
Started Jul 17 05:55:05 PM PDT 24
Finished Jul 17 05:55:59 PM PDT 24
Peak memory 199928 kb
Host smart-02e4fbdc-4fbc-44db-a906-bec93e3e2e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484281659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.484281659
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1979277825
Short name T847
Test name
Test status
Simulation time 42207619 ps
CPU time 0.6 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:51:41 PM PDT 24
Peak memory 195588 kb
Host smart-21262ace-a8dc-4ac6-92f2-55c14216619c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979277825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1979277825
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1619145312
Short name T1071
Test name
Test status
Simulation time 57787164292 ps
CPU time 23.68 seconds
Started Jul 17 05:51:40 PM PDT 24
Finished Jul 17 05:52:06 PM PDT 24
Peak memory 199904 kb
Host smart-32f79987-6eec-4285-a63c-78b14ff1ec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619145312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1619145312
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1256492658
Short name T270
Test name
Test status
Simulation time 21158201772 ps
CPU time 48.12 seconds
Started Jul 17 05:51:37 PM PDT 24
Finished Jul 17 05:52:26 PM PDT 24
Peak memory 199920 kb
Host smart-0bbc8c8f-5963-4dc1-bdd6-2ac876021238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256492658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1256492658
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1714162851
Short name T957
Test name
Test status
Simulation time 24720952329 ps
CPU time 11.96 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:51:53 PM PDT 24
Peak memory 199916 kb
Host smart-a122d715-5451-47dd-afff-e8cf4ac57e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714162851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1714162851
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2778738984
Short name T573
Test name
Test status
Simulation time 7841947316 ps
CPU time 16.06 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:51:58 PM PDT 24
Peak memory 199864 kb
Host smart-afb010da-4f50-4893-841b-e0b33f2be03e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778738984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2778738984
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_loopback.2846127193
Short name T356
Test name
Test status
Simulation time 2652641460 ps
CPU time 1.3 seconds
Started Jul 17 05:51:37 PM PDT 24
Finished Jul 17 05:51:40 PM PDT 24
Peak memory 196372 kb
Host smart-41376bfb-5d32-4e78-8423-259a177abeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846127193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2846127193
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3213055972
Short name T854
Test name
Test status
Simulation time 147524911305 ps
CPU time 31.42 seconds
Started Jul 17 05:51:36 PM PDT 24
Finished Jul 17 05:52:09 PM PDT 24
Peak memory 208332 kb
Host smart-f73c4fa6-aee7-485a-888e-b416c9fe8652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213055972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3213055972
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.144310434
Short name T39
Test name
Test status
Simulation time 3123016403 ps
CPU time 145.27 seconds
Started Jul 17 05:51:42 PM PDT 24
Finished Jul 17 05:54:09 PM PDT 24
Peak memory 199980 kb
Host smart-04f008bb-d2f0-4766-95a7-c151f6c89534
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=144310434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.144310434
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2523379810
Short name T474
Test name
Test status
Simulation time 1863171714 ps
CPU time 8.05 seconds
Started Jul 17 05:51:37 PM PDT 24
Finished Jul 17 05:51:47 PM PDT 24
Peak memory 198536 kb
Host smart-67ff6a4c-45c6-464f-8579-db608caedd6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523379810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2523379810
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1838128528
Short name T557
Test name
Test status
Simulation time 52647873024 ps
CPU time 25.49 seconds
Started Jul 17 05:51:39 PM PDT 24
Finished Jul 17 05:52:07 PM PDT 24
Peak memory 199956 kb
Host smart-e2fdabff-8c5a-4a5f-b7a0-83ca1a966a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838128528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1838128528
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.741606205
Short name T421
Test name
Test status
Simulation time 40030866063 ps
CPU time 23.99 seconds
Started Jul 17 05:51:37 PM PDT 24
Finished Jul 17 05:52:02 PM PDT 24
Peak memory 196060 kb
Host smart-21428b07-f2f6-467e-8328-c7ba32eb17d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741606205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.741606205
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3472300995
Short name T1126
Test name
Test status
Simulation time 863848592 ps
CPU time 0.94 seconds
Started Jul 17 05:51:37 PM PDT 24
Finished Jul 17 05:51:39 PM PDT 24
Peak memory 199104 kb
Host smart-9d33c6d3-f9d1-43bb-a149-0e76bf5613e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472300995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3472300995
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1585403779
Short name T130
Test name
Test status
Simulation time 305310419019 ps
CPU time 778.16 seconds
Started Jul 17 05:51:40 PM PDT 24
Finished Jul 17 06:04:41 PM PDT 24
Peak memory 199952 kb
Host smart-24c39823-fd24-4421-82c2-76844f6467c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585403779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1585403779
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1925258897
Short name T925
Test name
Test status
Simulation time 66518697748 ps
CPU time 189 seconds
Started Jul 17 05:51:35 PM PDT 24
Finished Jul 17 05:54:45 PM PDT 24
Peak memory 216444 kb
Host smart-2b6650ae-5976-4123-aa31-79a4f1d4b29e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925258897 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1925258897
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1388418491
Short name T665
Test name
Test status
Simulation time 1437784634 ps
CPU time 2.84 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:51:43 PM PDT 24
Peak memory 199592 kb
Host smart-38f13b7f-1011-4858-8775-e3ee402028ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388418491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1388418491
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3165936044
Short name T740
Test name
Test status
Simulation time 17953715411 ps
CPU time 29.21 seconds
Started Jul 17 05:51:39 PM PDT 24
Finished Jul 17 05:52:12 PM PDT 24
Peak memory 199888 kb
Host smart-433ac4b6-d5a0-43a0-9102-794f70b65234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165936044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3165936044
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3433769157
Short name T523
Test name
Test status
Simulation time 28614088462 ps
CPU time 41.44 seconds
Started Jul 17 05:55:03 PM PDT 24
Finished Jul 17 05:55:45 PM PDT 24
Peak memory 199912 kb
Host smart-97ce5836-4537-4335-95cb-bb06d816b459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433769157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3433769157
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.501796779
Short name T1136
Test name
Test status
Simulation time 23709519562 ps
CPU time 37.38 seconds
Started Jul 17 05:55:08 PM PDT 24
Finished Jul 17 05:55:47 PM PDT 24
Peak memory 199976 kb
Host smart-802d4595-29ea-43fb-ae40-ab74cd879648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501796779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.501796779
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3657960954
Short name T977
Test name
Test status
Simulation time 234215930507 ps
CPU time 25.8 seconds
Started Jul 17 05:55:03 PM PDT 24
Finished Jul 17 05:55:29 PM PDT 24
Peak memory 199976 kb
Host smart-25865cda-7c38-4a51-b16b-bf57b76558e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657960954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3657960954
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2436836166
Short name T625
Test name
Test status
Simulation time 20768938420 ps
CPU time 16.97 seconds
Started Jul 17 05:55:06 PM PDT 24
Finished Jul 17 05:55:24 PM PDT 24
Peak memory 199844 kb
Host smart-a29e6fc7-32e6-4dda-aeb8-1597caeca0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436836166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2436836166
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1851764727
Short name T922
Test name
Test status
Simulation time 88639823403 ps
CPU time 127.63 seconds
Started Jul 17 05:55:05 PM PDT 24
Finished Jul 17 05:57:14 PM PDT 24
Peak memory 199892 kb
Host smart-816f025c-4ae2-4b27-8e49-792781e67db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851764727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1851764727
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1681988188
Short name T873
Test name
Test status
Simulation time 42330672738 ps
CPU time 8.43 seconds
Started Jul 17 05:55:17 PM PDT 24
Finished Jul 17 05:55:26 PM PDT 24
Peak memory 199844 kb
Host smart-581f3eea-964f-42ae-b197-2f821c4d646e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681988188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1681988188
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2946912239
Short name T1138
Test name
Test status
Simulation time 42033635711 ps
CPU time 33.14 seconds
Started Jul 17 05:55:14 PM PDT 24
Finished Jul 17 05:55:48 PM PDT 24
Peak memory 199912 kb
Host smart-dc129f2a-7466-4cf7-aa3b-a5c9d7d62195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946912239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2946912239
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1774437469
Short name T755
Test name
Test status
Simulation time 20251651461 ps
CPU time 24.6 seconds
Started Jul 17 05:55:14 PM PDT 24
Finished Jul 17 05:55:39 PM PDT 24
Peak memory 199928 kb
Host smart-7f32f662-c012-4675-894a-97c8da0c3ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774437469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1774437469
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3740336339
Short name T473
Test name
Test status
Simulation time 42246596 ps
CPU time 0.56 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:51:56 PM PDT 24
Peak memory 194640 kb
Host smart-c4bc6885-8961-4be6-aab3-1a39b6af225c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740336339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3740336339
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1868275207
Short name T807
Test name
Test status
Simulation time 214753171997 ps
CPU time 32.27 seconds
Started Jul 17 05:51:39 PM PDT 24
Finished Jul 17 05:52:14 PM PDT 24
Peak memory 199972 kb
Host smart-a79f2bab-edf6-4f94-8d6b-a1a097b74eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868275207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1868275207
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.4133925659
Short name T110
Test name
Test status
Simulation time 90998720896 ps
CPU time 34.2 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:52:15 PM PDT 24
Peak memory 199952 kb
Host smart-7676ebba-8eba-4f7a-9ef6-37b3882f718e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133925659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4133925659
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.4167186169
Short name T205
Test name
Test status
Simulation time 16158202251 ps
CPU time 30.62 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:52:12 PM PDT 24
Peak memory 199924 kb
Host smart-8adba88b-57c7-46e5-bdba-b071f7761c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167186169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.4167186169
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1329277038
Short name T295
Test name
Test status
Simulation time 40782035225 ps
CPU time 65.12 seconds
Started Jul 17 05:51:51 PM PDT 24
Finished Jul 17 05:52:59 PM PDT 24
Peak memory 199952 kb
Host smart-9ae91753-d467-46fe-9073-6ac753a85878
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329277038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1329277038
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3949908609
Short name T278
Test name
Test status
Simulation time 91244324468 ps
CPU time 407.93 seconds
Started Jul 17 05:51:51 PM PDT 24
Finished Jul 17 05:58:42 PM PDT 24
Peak memory 199984 kb
Host smart-6d820682-adca-4806-bdbc-6d17d55d1f44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949908609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3949908609
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.674419676
Short name T1148
Test name
Test status
Simulation time 310885936 ps
CPU time 1.05 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:51:56 PM PDT 24
Peak memory 195388 kb
Host smart-5d3e287c-f364-4b04-b745-da8033bd6265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674419676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.674419676
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.307186599
Short name T1150
Test name
Test status
Simulation time 143987227260 ps
CPU time 72.22 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:53:07 PM PDT 24
Peak memory 200092 kb
Host smart-86c33eec-3eab-454c-befb-e631d8f7802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307186599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.307186599
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2451727366
Short name T906
Test name
Test status
Simulation time 20487376198 ps
CPU time 201.5 seconds
Started Jul 17 05:51:53 PM PDT 24
Finished Jul 17 05:55:18 PM PDT 24
Peak memory 199956 kb
Host smart-6288b9e9-c8c0-4c3c-8493-86043124e235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451727366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2451727366
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.231195562
Short name T945
Test name
Test status
Simulation time 2562536254 ps
CPU time 4.41 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:51:45 PM PDT 24
Peak memory 198224 kb
Host smart-e3d19f09-87b5-4888-848b-ae17fd38e12c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231195562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.231195562
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.538683976
Short name T709
Test name
Test status
Simulation time 166268681145 ps
CPU time 339.74 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:57:35 PM PDT 24
Peak memory 199920 kb
Host smart-2424727d-cc3a-4b66-ada7-cc3f5437a951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538683976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.538683976
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1900002616
Short name T505
Test name
Test status
Simulation time 2529740634 ps
CPU time 1.12 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:51:56 PM PDT 24
Peak memory 195932 kb
Host smart-d3cb1d76-043a-4e7a-87b9-3ff6b0ea224f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900002616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1900002616
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3426146890
Short name T485
Test name
Test status
Simulation time 5859889092 ps
CPU time 8.63 seconds
Started Jul 17 05:51:38 PM PDT 24
Finished Jul 17 05:51:49 PM PDT 24
Peak memory 199796 kb
Host smart-8aad6dba-33ba-485c-bb6f-660f5f27aab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426146890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3426146890
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2704216460
Short name T321
Test name
Test status
Simulation time 63528836845 ps
CPU time 108.1 seconds
Started Jul 17 05:51:51 PM PDT 24
Finished Jul 17 05:53:41 PM PDT 24
Peak memory 199968 kb
Host smart-48e594d2-0a09-426b-a63f-2adaaf8f4518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704216460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2704216460
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2848344009
Short name T697
Test name
Test status
Simulation time 95961063667 ps
CPU time 304.88 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:57:00 PM PDT 24
Peak memory 215248 kb
Host smart-f634005d-48b3-499f-87bb-82e15d8f0559
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848344009 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2848344009
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1430911035
Short name T275
Test name
Test status
Simulation time 6524416868 ps
CPU time 22.76 seconds
Started Jul 17 05:51:50 PM PDT 24
Finished Jul 17 05:52:14 PM PDT 24
Peak memory 199676 kb
Host smart-53469f28-f3e1-4ff5-a2eb-27c4ffe72668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430911035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1430911035
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1147384998
Short name T712
Test name
Test status
Simulation time 16225898482 ps
CPU time 13.28 seconds
Started Jul 17 05:51:41 PM PDT 24
Finished Jul 17 05:51:56 PM PDT 24
Peak memory 199896 kb
Host smart-513f33a6-bc23-4130-a978-ef1a2276eb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147384998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1147384998
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1763162707
Short name T222
Test name
Test status
Simulation time 73337078769 ps
CPU time 106.37 seconds
Started Jul 17 05:55:14 PM PDT 24
Finished Jul 17 05:57:01 PM PDT 24
Peak memory 199896 kb
Host smart-33463654-ffad-4e57-9b38-8842e4a3d16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763162707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1763162707
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.4249397102
Short name T351
Test name
Test status
Simulation time 14532134586 ps
CPU time 10.16 seconds
Started Jul 17 05:55:14 PM PDT 24
Finished Jul 17 05:55:25 PM PDT 24
Peak memory 199532 kb
Host smart-8cdd5a4a-058c-498a-a98d-07072b975916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249397102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.4249397102
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3232238682
Short name T839
Test name
Test status
Simulation time 171180335780 ps
CPU time 101.81 seconds
Started Jul 17 05:55:16 PM PDT 24
Finished Jul 17 05:56:59 PM PDT 24
Peak memory 199868 kb
Host smart-f63742b5-a590-4b67-be50-dc3f18978d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232238682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3232238682
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.4094624326
Short name T194
Test name
Test status
Simulation time 14261500878 ps
CPU time 23.37 seconds
Started Jul 17 05:55:15 PM PDT 24
Finished Jul 17 05:55:40 PM PDT 24
Peak memory 199928 kb
Host smart-1fc5ed74-4bf1-49b5-8c06-c8c3670df0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094624326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.4094624326
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3064442642
Short name T1079
Test name
Test status
Simulation time 91298333076 ps
CPU time 126.87 seconds
Started Jul 17 05:55:15 PM PDT 24
Finished Jul 17 05:57:23 PM PDT 24
Peak memory 199820 kb
Host smart-9899e269-5726-4ebe-8d8f-64588067d41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064442642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3064442642
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1630383770
Short name T860
Test name
Test status
Simulation time 81802393547 ps
CPU time 135.99 seconds
Started Jul 17 05:55:16 PM PDT 24
Finished Jul 17 05:57:34 PM PDT 24
Peak memory 199972 kb
Host smart-4f293f03-80a8-41dc-9b70-a6a5febea2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630383770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1630383770
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2311530436
Short name T994
Test name
Test status
Simulation time 138507045079 ps
CPU time 50.67 seconds
Started Jul 17 05:55:11 PM PDT 24
Finished Jul 17 05:56:02 PM PDT 24
Peak memory 199884 kb
Host smart-cd76e012-cba3-4e6a-ac5d-654e73be7596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311530436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2311530436
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3672692401
Short name T616
Test name
Test status
Simulation time 126578927578 ps
CPU time 23.16 seconds
Started Jul 17 05:55:15 PM PDT 24
Finished Jul 17 05:55:40 PM PDT 24
Peak memory 199500 kb
Host smart-479e5c6d-c6d5-4d95-bfad-2f816f688953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672692401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3672692401
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.879486053
Short name T757
Test name
Test status
Simulation time 117029936897 ps
CPU time 90.19 seconds
Started Jul 17 05:55:15 PM PDT 24
Finished Jul 17 05:56:46 PM PDT 24
Peak memory 199992 kb
Host smart-4c4228a8-7180-4ba2-9769-c11df02b1a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879486053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.879486053
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2421148512
Short name T590
Test name
Test status
Simulation time 12220481 ps
CPU time 0.55 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:51:56 PM PDT 24
Peak memory 195588 kb
Host smart-6311b4d1-6de6-47f2-9eb6-6dfa72fa42bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421148512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2421148512
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.706021221
Short name T1034
Test name
Test status
Simulation time 149356627355 ps
CPU time 104.72 seconds
Started Jul 17 05:51:51 PM PDT 24
Finished Jul 17 05:53:39 PM PDT 24
Peak memory 200008 kb
Host smart-356500dc-2a1a-4b96-b26a-7a9bcac08610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706021221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.706021221
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3653634289
Short name T703
Test name
Test status
Simulation time 17872215278 ps
CPU time 13.84 seconds
Started Jul 17 05:51:50 PM PDT 24
Finished Jul 17 05:52:06 PM PDT 24
Peak memory 199584 kb
Host smart-95c9376a-1375-4631-812c-26ae20e01947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653634289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3653634289
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1561689512
Short name T223
Test name
Test status
Simulation time 154755655268 ps
CPU time 125.19 seconds
Started Jul 17 05:51:50 PM PDT 24
Finished Jul 17 05:53:57 PM PDT 24
Peak memory 199880 kb
Host smart-575d1625-0b31-4b09-9a50-78ed720bba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561689512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1561689512
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.718652295
Short name T955
Test name
Test status
Simulation time 261612321318 ps
CPU time 430.58 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:59:06 PM PDT 24
Peak memory 199824 kb
Host smart-eed427b1-ecce-436b-8ad0-2818694ceba2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718652295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.718652295
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2815993591
Short name T417
Test name
Test status
Simulation time 126018189043 ps
CPU time 249.34 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:56:05 PM PDT 24
Peak memory 199764 kb
Host smart-0f427b06-1669-4288-ab45-92c62f10058c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815993591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2815993591
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3506934277
Short name T1116
Test name
Test status
Simulation time 3371843950 ps
CPU time 1.13 seconds
Started Jul 17 05:51:53 PM PDT 24
Finished Jul 17 05:51:57 PM PDT 24
Peak memory 196040 kb
Host smart-68c14d4c-dda2-491f-bf3e-3f976085a02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506934277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3506934277
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3977612432
Short name T323
Test name
Test status
Simulation time 96858575479 ps
CPU time 38.82 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:52:34 PM PDT 24
Peak memory 200080 kb
Host smart-57f08fbd-4399-4b11-9540-0a2bd725217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977612432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3977612432
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.101113696
Short name T621
Test name
Test status
Simulation time 10011176675 ps
CPU time 363.39 seconds
Started Jul 17 05:51:51 PM PDT 24
Finished Jul 17 05:57:57 PM PDT 24
Peak memory 199908 kb
Host smart-fda4baf3-0262-4a65-b351-480c922c1cce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=101113696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.101113696
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.715506386
Short name T515
Test name
Test status
Simulation time 3256180701 ps
CPU time 6.23 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:52:02 PM PDT 24
Peak memory 198184 kb
Host smart-ead05599-3b4d-40cc-99bf-6e29b40a48ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=715506386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.715506386
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3033057164
Short name T946
Test name
Test status
Simulation time 63202376905 ps
CPU time 97.84 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:53:33 PM PDT 24
Peak memory 199924 kb
Host smart-5980c581-da37-43d6-9f17-47490d530bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033057164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3033057164
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1623902203
Short name T306
Test name
Test status
Simulation time 3787138088 ps
CPU time 1.81 seconds
Started Jul 17 05:51:51 PM PDT 24
Finished Jul 17 05:51:56 PM PDT 24
Peak memory 196160 kb
Host smart-551e9683-c966-4055-aff8-d9597f1f3a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623902203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1623902203
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4288926118
Short name T1146
Test name
Test status
Simulation time 6253771930 ps
CPU time 19.6 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:52:15 PM PDT 24
Peak memory 199348 kb
Host smart-3ad46f3e-680b-47f0-b177-fc27357a21ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288926118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4288926118
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.850161380
Short name T537
Test name
Test status
Simulation time 58876199852 ps
CPU time 317.51 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:57:13 PM PDT 24
Peak memory 216700 kb
Host smart-d5d73796-8b81-41ed-98cd-47d9cfd2db5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850161380 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.850161380
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.717954807
Short name T664
Test name
Test status
Simulation time 863899451 ps
CPU time 2.32 seconds
Started Jul 17 05:51:53 PM PDT 24
Finished Jul 17 05:51:58 PM PDT 24
Peak memory 199888 kb
Host smart-9683892a-73c2-4f03-9965-143d3c69d340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717954807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.717954807
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.735954655
Short name T667
Test name
Test status
Simulation time 1875972677 ps
CPU time 2.03 seconds
Started Jul 17 05:51:51 PM PDT 24
Finished Jul 17 05:51:56 PM PDT 24
Peak memory 197916 kb
Host smart-d6e1833b-574f-4eec-acfa-152b3858101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735954655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.735954655
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1425183563
Short name T512
Test name
Test status
Simulation time 6756284952 ps
CPU time 10.46 seconds
Started Jul 17 05:55:16 PM PDT 24
Finished Jul 17 05:55:27 PM PDT 24
Peak memory 199652 kb
Host smart-086c7530-81c1-40d0-a805-3b27b0a97f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425183563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1425183563
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1863144313
Short name T219
Test name
Test status
Simulation time 162043601437 ps
CPU time 33.49 seconds
Started Jul 17 05:55:17 PM PDT 24
Finished Jul 17 05:55:51 PM PDT 24
Peak memory 199928 kb
Host smart-fd02ba85-883e-4745-b5d4-2784938d5a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863144313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1863144313
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.627334285
Short name T191
Test name
Test status
Simulation time 134084157949 ps
CPU time 493.35 seconds
Started Jul 17 05:55:12 PM PDT 24
Finished Jul 17 06:03:27 PM PDT 24
Peak memory 199980 kb
Host smart-4586dcf9-dacc-45f1-bcac-c270ddfda00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627334285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.627334285
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.4246049247
Short name T936
Test name
Test status
Simulation time 44687868305 ps
CPU time 27.18 seconds
Started Jul 17 05:55:16 PM PDT 24
Finished Jul 17 05:55:45 PM PDT 24
Peak memory 199824 kb
Host smart-f30c9d11-e367-4c7c-96ce-0d4ded6e34b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246049247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.4246049247
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1162520139
Short name T37
Test name
Test status
Simulation time 85285574781 ps
CPU time 178.23 seconds
Started Jul 17 05:55:13 PM PDT 24
Finished Jul 17 05:58:13 PM PDT 24
Peak memory 199916 kb
Host smart-a3b7dcc9-d878-4634-9db2-c280734b633d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162520139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1162520139
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3251603941
Short name T724
Test name
Test status
Simulation time 9820011517 ps
CPU time 8.93 seconds
Started Jul 17 05:55:15 PM PDT 24
Finished Jul 17 05:55:25 PM PDT 24
Peak memory 199996 kb
Host smart-778a2174-cfc8-45d5-8b42-ffac229b54ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251603941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3251603941
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.4009703214
Short name T600
Test name
Test status
Simulation time 213870152196 ps
CPU time 82.35 seconds
Started Jul 17 05:55:26 PM PDT 24
Finished Jul 17 05:56:50 PM PDT 24
Peak memory 199952 kb
Host smart-424cd03d-5186-4b95-be01-b72c2fc1391b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009703214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.4009703214
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.739027846
Short name T124
Test name
Test status
Simulation time 60788420675 ps
CPU time 161.94 seconds
Started Jul 17 05:55:27 PM PDT 24
Finished Jul 17 05:58:10 PM PDT 24
Peak memory 199944 kb
Host smart-a0490fc3-cae5-402a-837f-25773bb8d5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739027846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.739027846
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2872792954
Short name T212
Test name
Test status
Simulation time 158490474428 ps
CPU time 63.12 seconds
Started Jul 17 05:55:27 PM PDT 24
Finished Jul 17 05:56:31 PM PDT 24
Peak memory 199980 kb
Host smart-62c33801-af1d-4bb4-bcfb-32a1dae2b08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872792954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2872792954
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1282269402
Short name T469
Test name
Test status
Simulation time 16948606 ps
CPU time 0.53 seconds
Started Jul 17 05:52:06 PM PDT 24
Finished Jul 17 05:52:08 PM PDT 24
Peak memory 194716 kb
Host smart-b52a4a4d-49f5-4ab9-84d2-5d5277c5019d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282269402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1282269402
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.617654463
Short name T84
Test name
Test status
Simulation time 55890932641 ps
CPU time 84.94 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:53:20 PM PDT 24
Peak memory 199904 kb
Host smart-df039bd5-048b-4867-b187-a588b016a316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617654463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.617654463
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3691861892
Short name T298
Test name
Test status
Simulation time 133087395262 ps
CPU time 104.68 seconds
Started Jul 17 05:51:51 PM PDT 24
Finished Jul 17 05:53:39 PM PDT 24
Peak memory 199916 kb
Host smart-7fb79dc2-1d49-4d53-b726-aad9a59dad5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691861892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3691861892
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1221444066
Short name T864
Test name
Test status
Simulation time 73628817195 ps
CPU time 103.81 seconds
Started Jul 17 05:51:50 PM PDT 24
Finished Jul 17 05:53:36 PM PDT 24
Peak memory 199764 kb
Host smart-c410af4a-2be1-4b9c-ad9d-4b719f69695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221444066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1221444066
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.685712843
Short name T375
Test name
Test status
Simulation time 61268518475 ps
CPU time 42.47 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:52:37 PM PDT 24
Peak memory 199912 kb
Host smart-175b727b-6d1b-4569-b3cd-024baad7ce4f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685712843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.685712843
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2056014918
Short name T403
Test name
Test status
Simulation time 202243292742 ps
CPU time 296.24 seconds
Started Jul 17 05:52:05 PM PDT 24
Finished Jul 17 05:57:02 PM PDT 24
Peak memory 199860 kb
Host smart-13674a2b-05c2-44b2-b078-c08718fbd307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056014918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2056014918
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1358386120
Short name T1003
Test name
Test status
Simulation time 310617789 ps
CPU time 0.83 seconds
Started Jul 17 05:52:05 PM PDT 24
Finished Jul 17 05:52:08 PM PDT 24
Peak memory 196808 kb
Host smart-70523a97-9681-4d03-90da-dee0ba6586fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358386120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1358386120
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3904521747
Short name T781
Test name
Test status
Simulation time 25859023050 ps
CPU time 45.47 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:52:41 PM PDT 24
Peak memory 200092 kb
Host smart-c2ad22b2-b843-49ba-9bff-6e411fa2a506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904521747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3904521747
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3851913709
Short name T598
Test name
Test status
Simulation time 25575558662 ps
CPU time 307.44 seconds
Started Jul 17 05:52:06 PM PDT 24
Finished Jul 17 05:57:16 PM PDT 24
Peak memory 199132 kb
Host smart-56999787-f682-4b48-8358-42e46de6bf8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3851913709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3851913709
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.401153006
Short name T462
Test name
Test status
Simulation time 2218570167 ps
CPU time 11.32 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:52:07 PM PDT 24
Peak memory 198144 kb
Host smart-61e0f8d9-a17e-41bb-857f-1f2d1eb9d2cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401153006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.401153006
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2066976188
Short name T100
Test name
Test status
Simulation time 27287805277 ps
CPU time 25.57 seconds
Started Jul 17 05:52:09 PM PDT 24
Finished Jul 17 05:52:37 PM PDT 24
Peak memory 199980 kb
Host smart-a622c2df-8677-4c65-9e2b-b3bd4e44ca6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066976188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2066976188
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1489627337
Short name T1131
Test name
Test status
Simulation time 3912765911 ps
CPU time 3.02 seconds
Started Jul 17 05:52:10 PM PDT 24
Finished Jul 17 05:52:14 PM PDT 24
Peak memory 196412 kb
Host smart-338e126b-69ab-45d3-b641-76f0e69eaec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489627337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1489627337
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1534142412
Short name T1173
Test name
Test status
Simulation time 869555904 ps
CPU time 2.09 seconds
Started Jul 17 05:51:52 PM PDT 24
Finished Jul 17 05:51:57 PM PDT 24
Peak memory 198988 kb
Host smart-b59c4447-6e64-49bc-be03-0c78487a88c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534142412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1534142412
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2743892081
Short name T910
Test name
Test status
Simulation time 96013019112 ps
CPU time 184.62 seconds
Started Jul 17 05:52:02 PM PDT 24
Finished Jul 17 05:55:07 PM PDT 24
Peak memory 199932 kb
Host smart-b63f8c58-9dfe-4101-b104-be14822cdb6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743892081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2743892081
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3232962769
Short name T877
Test name
Test status
Simulation time 66739816687 ps
CPU time 204.06 seconds
Started Jul 17 05:52:05 PM PDT 24
Finished Jul 17 05:55:30 PM PDT 24
Peak memory 215932 kb
Host smart-b69879d9-b3af-48f2-84a7-020fffe46034
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232962769 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3232962769
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2636089837
Short name T908
Test name
Test status
Simulation time 1050869307 ps
CPU time 1.43 seconds
Started Jul 17 05:52:11 PM PDT 24
Finished Jul 17 05:52:14 PM PDT 24
Peak memory 198940 kb
Host smart-c85f945c-5ef8-4da8-b63b-9df130ab4fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636089837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2636089837
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2772164524
Short name T776
Test name
Test status
Simulation time 20558534790 ps
CPU time 7.58 seconds
Started Jul 17 05:51:51 PM PDT 24
Finished Jul 17 05:52:02 PM PDT 24
Peak memory 199248 kb
Host smart-3d53ec30-6cb8-4d66-b361-abf19a5f0980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772164524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2772164524
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2062244954
Short name T120
Test name
Test status
Simulation time 52961670426 ps
CPU time 13.2 seconds
Started Jul 17 05:55:27 PM PDT 24
Finished Jul 17 05:55:42 PM PDT 24
Peak memory 199952 kb
Host smart-21e4b7b1-1375-46fa-b0b2-fd06ab42dbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062244954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2062244954
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3217278102
Short name T247
Test name
Test status
Simulation time 111189248833 ps
CPU time 37.91 seconds
Started Jul 17 05:55:28 PM PDT 24
Finished Jul 17 05:56:07 PM PDT 24
Peak memory 199908 kb
Host smart-5241271a-3bae-40e7-98eb-da179a6fd040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217278102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3217278102
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1926119773
Short name T859
Test name
Test status
Simulation time 181238864876 ps
CPU time 175.71 seconds
Started Jul 17 05:55:27 PM PDT 24
Finished Jul 17 05:58:25 PM PDT 24
Peak memory 199920 kb
Host smart-ec994ecc-9ee2-4d76-8af4-11d5174504ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926119773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1926119773
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.826243380
Short name T529
Test name
Test status
Simulation time 117821178680 ps
CPU time 67.62 seconds
Started Jul 17 05:55:27 PM PDT 24
Finished Jul 17 05:56:36 PM PDT 24
Peak memory 199944 kb
Host smart-ef278df5-6b5d-46b1-9d86-48e33cfe33a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826243380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.826243380
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2986829295
Short name T1041
Test name
Test status
Simulation time 83584782809 ps
CPU time 27.76 seconds
Started Jul 17 05:55:26 PM PDT 24
Finished Jul 17 05:55:55 PM PDT 24
Peak memory 199776 kb
Host smart-e7bd7497-4eff-48e7-a12a-2076d33bfc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986829295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2986829295
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1172913013
Short name T1133
Test name
Test status
Simulation time 49741364749 ps
CPU time 24.39 seconds
Started Jul 17 05:55:27 PM PDT 24
Finished Jul 17 05:55:53 PM PDT 24
Peak memory 199744 kb
Host smart-0003309d-fd52-4aa6-998c-39e7e64bcb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172913013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1172913013
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2618219104
Short name T184
Test name
Test status
Simulation time 41929749341 ps
CPU time 33.95 seconds
Started Jul 17 05:55:26 PM PDT 24
Finished Jul 17 05:56:01 PM PDT 24
Peak memory 199892 kb
Host smart-d4d4eeb7-3817-455b-9fe2-863843de24e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618219104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2618219104
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.4004824832
Short name T623
Test name
Test status
Simulation time 82261175846 ps
CPU time 205.33 seconds
Started Jul 17 05:55:27 PM PDT 24
Finished Jul 17 05:58:54 PM PDT 24
Peak memory 199864 kb
Host smart-d9c1ed14-1dad-4289-8e4a-2e902d50847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004824832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.4004824832
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2578477193
Short name T209
Test name
Test status
Simulation time 52309761872 ps
CPU time 81.95 seconds
Started Jul 17 05:55:27 PM PDT 24
Finished Jul 17 05:56:50 PM PDT 24
Peak memory 199940 kb
Host smart-201bd655-9eeb-47a4-a236-c8d5a2615c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578477193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2578477193
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1055235810
Short name T346
Test name
Test status
Simulation time 32760809286 ps
CPU time 15.73 seconds
Started Jul 17 05:55:27 PM PDT 24
Finished Jul 17 05:55:44 PM PDT 24
Peak memory 199820 kb
Host smart-5529ee54-cc39-4d34-8c67-3f3fc3c72f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055235810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1055235810
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3177047775
Short name T730
Test name
Test status
Simulation time 16643536 ps
CPU time 0.57 seconds
Started Jul 17 05:52:07 PM PDT 24
Finished Jul 17 05:52:10 PM PDT 24
Peak memory 194956 kb
Host smart-984d3437-6ced-4a65-9d4f-17ebbc7ffb14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177047775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3177047775
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1931341404
Short name T655
Test name
Test status
Simulation time 232467076434 ps
CPU time 77.77 seconds
Started Jul 17 05:52:04 PM PDT 24
Finished Jul 17 05:53:23 PM PDT 24
Peak memory 199964 kb
Host smart-4b640a9a-f98d-480f-ab7a-5f76f137e983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931341404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1931341404
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3678271747
Short name T1058
Test name
Test status
Simulation time 35775830704 ps
CPU time 25.31 seconds
Started Jul 17 05:52:07 PM PDT 24
Finished Jul 17 05:52:34 PM PDT 24
Peak memory 199436 kb
Host smart-6a978e41-9621-42f2-aa73-4a6c9206fec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678271747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3678271747
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_intr.4234480056
Short name T870
Test name
Test status
Simulation time 40081550609 ps
CPU time 16.07 seconds
Started Jul 17 05:52:09 PM PDT 24
Finished Jul 17 05:52:28 PM PDT 24
Peak memory 199944 kb
Host smart-fa9a265e-27c7-48ab-b40f-feba361badc1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234480056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4234480056
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.998109413
Short name T1155
Test name
Test status
Simulation time 62046208452 ps
CPU time 551.27 seconds
Started Jul 17 05:52:04 PM PDT 24
Finished Jul 17 06:01:16 PM PDT 24
Peak memory 199920 kb
Host smart-9588ed8a-97c9-47d2-bac2-e1060d3d911f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=998109413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.998109413
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2464065789
Short name T651
Test name
Test status
Simulation time 3675465436 ps
CPU time 2.8 seconds
Started Jul 17 05:52:06 PM PDT 24
Finished Jul 17 05:52:11 PM PDT 24
Peak memory 197788 kb
Host smart-41432ec3-dc62-4668-85df-51d7745bf30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464065789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2464065789
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3219442004
Short name T41
Test name
Test status
Simulation time 10018094007 ps
CPU time 4.27 seconds
Started Jul 17 05:52:06 PM PDT 24
Finished Jul 17 05:52:12 PM PDT 24
Peak memory 194472 kb
Host smart-89c5957b-783a-46ee-a678-79808e6e0f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219442004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3219442004
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3992469261
Short name T622
Test name
Test status
Simulation time 15100396552 ps
CPU time 806.18 seconds
Started Jul 17 05:52:04 PM PDT 24
Finished Jul 17 06:05:31 PM PDT 24
Peak memory 199924 kb
Host smart-e8dd989e-b6e4-4b96-ae06-f652c9a41b64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3992469261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3992469261
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3439919647
Short name T554
Test name
Test status
Simulation time 3375851031 ps
CPU time 12.28 seconds
Started Jul 17 05:52:09 PM PDT 24
Finished Jul 17 05:52:23 PM PDT 24
Peak memory 198136 kb
Host smart-ddfd696a-3b7a-46d0-b401-2e7078326f6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439919647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3439919647
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.4142069631
Short name T555
Test name
Test status
Simulation time 80235244573 ps
CPU time 85.21 seconds
Started Jul 17 05:52:07 PM PDT 24
Finished Jul 17 05:53:35 PM PDT 24
Peak memory 199828 kb
Host smart-00d10f91-2927-4b04-a4bd-23382958d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142069631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.4142069631
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1523886906
Short name T1026
Test name
Test status
Simulation time 2887601845 ps
CPU time 4.33 seconds
Started Jul 17 05:52:06 PM PDT 24
Finished Jul 17 05:52:13 PM PDT 24
Peak memory 196436 kb
Host smart-147662a2-d336-491e-9f77-bf00071402e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523886906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1523886906
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1472594528
Short name T942
Test name
Test status
Simulation time 934445227 ps
CPU time 4.65 seconds
Started Jul 17 05:52:03 PM PDT 24
Finished Jul 17 05:52:09 PM PDT 24
Peak memory 198584 kb
Host smart-6a67389b-8d9c-4a9a-a440-3a48aa9cc9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472594528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1472594528
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.992980897
Short name T207
Test name
Test status
Simulation time 50381236055 ps
CPU time 64.47 seconds
Started Jul 17 05:52:11 PM PDT 24
Finished Jul 17 05:53:17 PM PDT 24
Peak memory 199688 kb
Host smart-c9fe2801-e673-401a-b6d9-ea68ea552886
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992980897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.992980897
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.175329005
Short name T1145
Test name
Test status
Simulation time 6771211490 ps
CPU time 18.99 seconds
Started Jul 17 05:52:06 PM PDT 24
Finished Jul 17 05:52:26 PM PDT 24
Peak memory 199252 kb
Host smart-87476a41-3a44-49b0-9369-c8d766e58675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175329005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.175329005
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3505260738
Short name T986
Test name
Test status
Simulation time 117437379013 ps
CPU time 100.32 seconds
Started Jul 17 05:52:09 PM PDT 24
Finished Jul 17 05:53:52 PM PDT 24
Peak memory 199972 kb
Host smart-75fd05e7-3f44-451b-a956-75511377654e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505260738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3505260738
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1046388738
Short name T281
Test name
Test status
Simulation time 93318332577 ps
CPU time 29.1 seconds
Started Jul 17 05:55:27 PM PDT 24
Finished Jul 17 05:55:58 PM PDT 24
Peak memory 199940 kb
Host smart-ff39d00f-71e9-4cbe-82ad-847b7623dd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046388738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1046388738
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3329291784
Short name T540
Test name
Test status
Simulation time 106117642948 ps
CPU time 44.57 seconds
Started Jul 17 05:55:26 PM PDT 24
Finished Jul 17 05:56:11 PM PDT 24
Peak memory 199460 kb
Host smart-513b7d91-c7b6-4831-bfc0-57dda4f72d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329291784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3329291784
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.281620526
Short name T226
Test name
Test status
Simulation time 115158256478 ps
CPU time 161.65 seconds
Started Jul 17 05:55:28 PM PDT 24
Finished Jul 17 05:58:11 PM PDT 24
Peak memory 199832 kb
Host smart-968f24d5-6ba6-4d5e-b35b-298e38837c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281620526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.281620526
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3475416103
Short name T732
Test name
Test status
Simulation time 68267849854 ps
CPU time 24.99 seconds
Started Jul 17 05:55:28 PM PDT 24
Finished Jul 17 05:55:54 PM PDT 24
Peak memory 199864 kb
Host smart-986996b3-3b67-4db6-aa58-0760abf498f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475416103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3475416103
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.986888922
Short name T514
Test name
Test status
Simulation time 10722081409 ps
CPU time 22.38 seconds
Started Jul 17 05:55:26 PM PDT 24
Finished Jul 17 05:55:50 PM PDT 24
Peak memory 199980 kb
Host smart-0617a9c1-b944-45f4-97df-650f3d51632b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986888922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.986888922
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.530411910
Short name T594
Test name
Test status
Simulation time 120205037572 ps
CPU time 74.31 seconds
Started Jul 17 05:55:28 PM PDT 24
Finished Jul 17 05:56:44 PM PDT 24
Peak memory 199928 kb
Host smart-fa36dec5-b2ed-4349-b0a5-272c43a5c778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530411910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.530411910
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.506038534
Short name T832
Test name
Test status
Simulation time 102091772556 ps
CPU time 118.57 seconds
Started Jul 17 05:55:27 PM PDT 24
Finished Jul 17 05:57:28 PM PDT 24
Peak memory 199928 kb
Host smart-4ce21470-5233-4ab8-9938-352a9d8a1579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506038534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.506038534
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1336713609
Short name T816
Test name
Test status
Simulation time 74745268747 ps
CPU time 85.9 seconds
Started Jul 17 05:55:29 PM PDT 24
Finished Jul 17 05:56:56 PM PDT 24
Peak memory 199964 kb
Host smart-48ec15be-a461-4f7b-8a3f-f51b908a3d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336713609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1336713609
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3082634258
Short name T344
Test name
Test status
Simulation time 113693846706 ps
CPU time 76.91 seconds
Started Jul 17 05:55:28 PM PDT 24
Finished Jul 17 05:56:46 PM PDT 24
Peak memory 199828 kb
Host smart-a4f317c7-23ab-4f0c-bf3f-2f4332fd8d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082634258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3082634258
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2010626301
Short name T506
Test name
Test status
Simulation time 25941076621 ps
CPU time 38.14 seconds
Started Jul 17 05:55:27 PM PDT 24
Finished Jul 17 05:56:07 PM PDT 24
Peak memory 199864 kb
Host smart-9e9648e7-dbba-4393-a58d-48ed6cfb8b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010626301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2010626301
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3518961391
Short name T841
Test name
Test status
Simulation time 11766688 ps
CPU time 0.54 seconds
Started Jul 17 05:52:07 PM PDT 24
Finished Jul 17 05:52:10 PM PDT 24
Peak memory 194972 kb
Host smart-92c9aa98-e4ab-46f1-87aa-3db2bcab97c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518961391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3518961391
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3318015976
Short name T733
Test name
Test status
Simulation time 133438433208 ps
CPU time 253.82 seconds
Started Jul 17 05:52:07 PM PDT 24
Finished Jul 17 05:56:23 PM PDT 24
Peak memory 199912 kb
Host smart-425f083c-84c1-42bc-829c-f44ba8ffcb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318015976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3318015976
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2708285332
Short name T815
Test name
Test status
Simulation time 254415973623 ps
CPU time 87.54 seconds
Started Jul 17 05:52:05 PM PDT 24
Finished Jul 17 05:53:33 PM PDT 24
Peak memory 199792 kb
Host smart-802efb8b-7d80-4ef0-8749-110456855297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708285332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2708285332
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.962230136
Short name T292
Test name
Test status
Simulation time 20367627368 ps
CPU time 41.34 seconds
Started Jul 17 05:52:07 PM PDT 24
Finished Jul 17 05:52:50 PM PDT 24
Peak memory 199908 kb
Host smart-ab213c56-3c3b-48e2-8744-fb04f48813fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962230136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.962230136
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1341576555
Short name T1143
Test name
Test status
Simulation time 15671557302 ps
CPU time 27.64 seconds
Started Jul 17 05:52:07 PM PDT 24
Finished Jul 17 05:52:37 PM PDT 24
Peak memory 199864 kb
Host smart-4d4370ce-f277-45c1-a4e6-144b2c4882da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341576555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1341576555
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.182469167
Short name T405
Test name
Test status
Simulation time 191390849844 ps
CPU time 192.74 seconds
Started Jul 17 05:52:07 PM PDT 24
Finished Jul 17 05:55:22 PM PDT 24
Peak memory 199880 kb
Host smart-759ac388-37b4-4806-9233-70601b2fe7d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=182469167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.182469167
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1614638271
Short name T466
Test name
Test status
Simulation time 835970784 ps
CPU time 1.01 seconds
Started Jul 17 05:52:06 PM PDT 24
Finished Jul 17 05:52:08 PM PDT 24
Peak memory 196028 kb
Host smart-e3ab655a-32ca-4a1e-b421-9da9ade05b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614638271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1614638271
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1093733538
Short name T828
Test name
Test status
Simulation time 200775002799 ps
CPU time 41.41 seconds
Started Jul 17 05:52:04 PM PDT 24
Finished Jul 17 05:52:47 PM PDT 24
Peak memory 200180 kb
Host smart-5466a60f-ffe8-46b0-83b3-b67390822a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093733538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1093733538
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3363513001
Short name T1076
Test name
Test status
Simulation time 12955557657 ps
CPU time 610.22 seconds
Started Jul 17 05:52:05 PM PDT 24
Finished Jul 17 06:02:17 PM PDT 24
Peak memory 199964 kb
Host smart-f530588d-7180-41ca-93bb-cbc9ebc5e37a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3363513001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3363513001
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3036604410
Short name T524
Test name
Test status
Simulation time 7294104285 ps
CPU time 69.14 seconds
Started Jul 17 05:52:05 PM PDT 24
Finished Jul 17 05:53:16 PM PDT 24
Peak memory 198108 kb
Host smart-3a585a7a-2569-4a76-bc4b-a3440eced4ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3036604410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3036604410
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2124144269
Short name T168
Test name
Test status
Simulation time 23731742694 ps
CPU time 37.57 seconds
Started Jul 17 05:52:08 PM PDT 24
Finished Jul 17 05:52:47 PM PDT 24
Peak memory 199836 kb
Host smart-77e7e990-c1b8-4821-9d9e-bcaf27ab67b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124144269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2124144269
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2627969044
Short name T974
Test name
Test status
Simulation time 3451130590 ps
CPU time 1.21 seconds
Started Jul 17 05:52:05 PM PDT 24
Finished Jul 17 05:52:08 PM PDT 24
Peak memory 195968 kb
Host smart-8b76ee1d-4183-4048-96cb-70eaa6ac0b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627969044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2627969044
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1891361591
Short name T715
Test name
Test status
Simulation time 311840461 ps
CPU time 1.51 seconds
Started Jul 17 05:52:20 PM PDT 24
Finished Jul 17 05:52:22 PM PDT 24
Peak memory 198700 kb
Host smart-62dec8c0-a9bf-4a49-ad84-4f88d157838a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891361591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1891361591
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2572730942
Short name T350
Test name
Test status
Simulation time 336668824501 ps
CPU time 181.54 seconds
Started Jul 17 05:52:00 PM PDT 24
Finished Jul 17 05:55:02 PM PDT 24
Peak memory 208604 kb
Host smart-01ae9f61-b92e-46d5-aa0e-395a00eee1be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572730942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2572730942
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.908721746
Short name T615
Test name
Test status
Simulation time 106405905297 ps
CPU time 443.42 seconds
Started Jul 17 05:52:09 PM PDT 24
Finished Jul 17 05:59:35 PM PDT 24
Peak memory 216624 kb
Host smart-f970f236-20ba-4eec-b459-7166fe8fccb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908721746 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.908721746
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2690773267
Short name T322
Test name
Test status
Simulation time 7548707708 ps
CPU time 13.45 seconds
Started Jul 17 05:52:04 PM PDT 24
Finished Jul 17 05:52:18 PM PDT 24
Peak memory 199140 kb
Host smart-38a4c435-e05e-4f76-a179-a5bbb3c9e9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690773267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2690773267
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.4075691452
Short name T1110
Test name
Test status
Simulation time 9331255022 ps
CPU time 17.5 seconds
Started Jul 17 05:52:05 PM PDT 24
Finished Jul 17 05:52:24 PM PDT 24
Peak memory 199964 kb
Host smart-a0aa92b3-91e5-4957-acb2-a7214d3c5e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075691452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.4075691452
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1663314980
Short name T183
Test name
Test status
Simulation time 53563128094 ps
CPU time 51.67 seconds
Started Jul 17 05:55:26 PM PDT 24
Finished Jul 17 05:56:19 PM PDT 24
Peak memory 199976 kb
Host smart-03252b84-f9e8-4e5e-85a9-3f6d4d7fb861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663314980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1663314980
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.279173201
Short name T685
Test name
Test status
Simulation time 22057081637 ps
CPU time 26.48 seconds
Started Jul 17 05:55:28 PM PDT 24
Finished Jul 17 05:55:56 PM PDT 24
Peak memory 199788 kb
Host smart-be474c25-1e55-4fc8-9d60-74eafa1c304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279173201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.279173201
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1913486350
Short name T384
Test name
Test status
Simulation time 11013263068 ps
CPU time 4.74 seconds
Started Jul 17 05:55:28 PM PDT 24
Finished Jul 17 05:55:34 PM PDT 24
Peak memory 198936 kb
Host smart-e667d830-043e-4208-b629-e66579bcf6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913486350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1913486350
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3291232116
Short name T708
Test name
Test status
Simulation time 18553232936 ps
CPU time 29.36 seconds
Started Jul 17 05:55:26 PM PDT 24
Finished Jul 17 05:55:57 PM PDT 24
Peak memory 199952 kb
Host smart-e0b3ab2b-1c2c-4e1e-9733-5ebede7c00f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291232116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3291232116
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3831648068
Short name T596
Test name
Test status
Simulation time 344315396082 ps
CPU time 322.05 seconds
Started Jul 17 05:55:39 PM PDT 24
Finished Jul 17 06:01:03 PM PDT 24
Peak memory 199892 kb
Host smart-ffac4a29-8d1e-432e-bbe5-816d34d74cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831648068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3831648068
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1682919901
Short name T1075
Test name
Test status
Simulation time 132190214110 ps
CPU time 231.7 seconds
Started Jul 17 05:55:39 PM PDT 24
Finished Jul 17 05:59:33 PM PDT 24
Peak memory 199932 kb
Host smart-b1758fd3-9d2c-4627-b7a6-e479ec47d875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682919901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1682919901
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2657389450
Short name T1009
Test name
Test status
Simulation time 129405694481 ps
CPU time 177.55 seconds
Started Jul 17 05:55:39 PM PDT 24
Finished Jul 17 05:58:38 PM PDT 24
Peak memory 199976 kb
Host smart-adb0e5dc-c59e-458e-be32-d96c5bcc6efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657389450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2657389450
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1987419140
Short name T204
Test name
Test status
Simulation time 97313343222 ps
CPU time 42.41 seconds
Started Jul 17 05:55:40 PM PDT 24
Finished Jul 17 05:56:25 PM PDT 24
Peak memory 199588 kb
Host smart-d2816233-e198-453b-8b96-af04398da717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987419140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1987419140
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2381564769
Short name T140
Test name
Test status
Simulation time 48136504982 ps
CPU time 227.61 seconds
Started Jul 17 05:55:38 PM PDT 24
Finished Jul 17 05:59:28 PM PDT 24
Peak memory 199896 kb
Host smart-82e99dd2-52f0-43e0-acef-d6d2da594489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381564769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2381564769
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1593672945
Short name T996
Test name
Test status
Simulation time 34950138789 ps
CPU time 15.73 seconds
Started Jul 17 05:55:39 PM PDT 24
Finished Jul 17 05:55:56 PM PDT 24
Peak memory 199596 kb
Host smart-6b30ed2d-a2b2-42c1-9cec-8548904d55ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593672945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1593672945
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.50705039
Short name T394
Test name
Test status
Simulation time 32420358 ps
CPU time 0.54 seconds
Started Jul 17 05:52:24 PM PDT 24
Finished Jul 17 05:52:28 PM PDT 24
Peak memory 195292 kb
Host smart-4460ce92-141b-445d-9cea-6aa11bf0a481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50705039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.50705039
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3543320641
Short name T549
Test name
Test status
Simulation time 117546535000 ps
CPU time 51 seconds
Started Jul 17 05:52:09 PM PDT 24
Finished Jul 17 05:53:02 PM PDT 24
Peak memory 199928 kb
Host smart-7c4ee17c-3a85-439b-ae08-ccd680e08ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543320641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3543320641
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.377179732
Short name T905
Test name
Test status
Simulation time 107774865991 ps
CPU time 14.34 seconds
Started Jul 17 05:52:07 PM PDT 24
Finished Jul 17 05:52:24 PM PDT 24
Peak memory 199936 kb
Host smart-477146ef-c667-492b-a320-6990abd76952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377179732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.377179732
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2074256287
Short name T142
Test name
Test status
Simulation time 103976817267 ps
CPU time 156.2 seconds
Started Jul 17 05:52:05 PM PDT 24
Finished Jul 17 05:54:42 PM PDT 24
Peak memory 199860 kb
Host smart-90a612f8-85b3-4118-96aa-3edc3a2845ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074256287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2074256287
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3322913145
Short name T333
Test name
Test status
Simulation time 143764322749 ps
CPU time 133.01 seconds
Started Jul 17 05:52:06 PM PDT 24
Finished Jul 17 05:54:20 PM PDT 24
Peak memory 196100 kb
Host smart-05c60b0a-0944-4477-92d5-d874496b3c64
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322913145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3322913145
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.4270278995
Short name T619
Test name
Test status
Simulation time 65687561613 ps
CPU time 75.28 seconds
Started Jul 17 05:52:24 PM PDT 24
Finished Jul 17 05:53:43 PM PDT 24
Peak memory 199908 kb
Host smart-ae6d8c14-8b4a-43b8-b848-d3389d0a3eb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270278995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.4270278995
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2021379313
Short name T677
Test name
Test status
Simulation time 5325773028 ps
CPU time 4.99 seconds
Started Jul 17 05:52:22 PM PDT 24
Finished Jul 17 05:52:29 PM PDT 24
Peak memory 198376 kb
Host smart-d5649913-ef22-42f1-a207-b4dc8a0a3986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021379313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2021379313
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3444564612
Short name T481
Test name
Test status
Simulation time 11337700843 ps
CPU time 15 seconds
Started Jul 17 05:52:09 PM PDT 24
Finished Jul 17 05:52:26 PM PDT 24
Peak memory 196496 kb
Host smart-c688883b-4054-4cb9-bbae-4e8916130981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444564612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3444564612
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.674795377
Short name T427
Test name
Test status
Simulation time 6686404752 ps
CPU time 299.78 seconds
Started Jul 17 05:52:20 PM PDT 24
Finished Jul 17 05:57:21 PM PDT 24
Peak memory 199980 kb
Host smart-009a3506-f738-48bc-a65e-564c7283584e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=674795377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.674795377
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.2345989325
Short name T571
Test name
Test status
Simulation time 6800213857 ps
CPU time 58.94 seconds
Started Jul 17 05:52:08 PM PDT 24
Finished Jul 17 05:53:09 PM PDT 24
Peak memory 198728 kb
Host smart-67cfc5a1-e141-42b0-8e23-1d2287c68f29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345989325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2345989325
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3263480768
Short name T550
Test name
Test status
Simulation time 79320098078 ps
CPU time 154.48 seconds
Started Jul 17 05:52:06 PM PDT 24
Finished Jul 17 05:54:42 PM PDT 24
Peak memory 199948 kb
Host smart-24427052-ccf0-4d49-9a78-4a540f7367e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263480768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3263480768
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1751241096
Short name T377
Test name
Test status
Simulation time 3054421735 ps
CPU time 1.88 seconds
Started Jul 17 05:52:07 PM PDT 24
Finished Jul 17 05:52:11 PM PDT 24
Peak memory 196484 kb
Host smart-592e580e-3953-4c4a-a9eb-5c2d3082023a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751241096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1751241096
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.673024185
Short name T935
Test name
Test status
Simulation time 738528567 ps
CPU time 3.45 seconds
Started Jul 17 05:52:06 PM PDT 24
Finished Jul 17 05:52:12 PM PDT 24
Peak memory 199756 kb
Host smart-f5b5f18d-623c-49b8-8ad1-17ec3830240d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673024185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.673024185
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.2577161138
Short name T1040
Test name
Test status
Simulation time 239325557098 ps
CPU time 289.73 seconds
Started Jul 17 05:52:22 PM PDT 24
Finished Jul 17 05:57:15 PM PDT 24
Peak memory 199952 kb
Host smart-285c43a5-e599-49d5-a08f-cbdff536908e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577161138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2577161138
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.4269207279
Short name T53
Test name
Test status
Simulation time 56322019034 ps
CPU time 181.38 seconds
Started Jul 17 05:52:25 PM PDT 24
Finished Jul 17 05:55:29 PM PDT 24
Peak memory 210944 kb
Host smart-6cf2d4c1-b032-4a7b-b5e7-bc13b65568d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269207279 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.4269207279
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1733302315
Short name T991
Test name
Test status
Simulation time 360595420 ps
CPU time 1.32 seconds
Started Jul 17 05:52:24 PM PDT 24
Finished Jul 17 05:52:28 PM PDT 24
Peak memory 197856 kb
Host smart-74ea0f15-bb48-4d0f-ac4a-6a688f173882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733302315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1733302315
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.641095123
Short name T455
Test name
Test status
Simulation time 49457701354 ps
CPU time 20.3 seconds
Started Jul 17 05:52:06 PM PDT 24
Finished Jul 17 05:52:29 PM PDT 24
Peak memory 199900 kb
Host smart-13f477e9-18fe-4273-b110-6d3ff7baec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641095123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.641095123
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.429692656
Short name T885
Test name
Test status
Simulation time 113846214839 ps
CPU time 180.26 seconds
Started Jul 17 05:55:39 PM PDT 24
Finished Jul 17 05:58:41 PM PDT 24
Peak memory 199980 kb
Host smart-bca98ac8-0aeb-43b6-886b-0641392dafdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429692656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.429692656
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2031569984
Short name T1153
Test name
Test status
Simulation time 79518847961 ps
CPU time 120.27 seconds
Started Jul 17 05:55:41 PM PDT 24
Finished Jul 17 05:57:43 PM PDT 24
Peak memory 199976 kb
Host smart-e4954e64-3fed-471c-96f2-8b24af93effe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031569984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2031569984
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.4024601611
Short name T904
Test name
Test status
Simulation time 19679498052 ps
CPU time 17.45 seconds
Started Jul 17 05:55:39 PM PDT 24
Finished Jul 17 05:55:59 PM PDT 24
Peak memory 199896 kb
Host smart-1a549a56-c400-4092-a951-dae322693e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024601611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.4024601611
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1694678058
Short name T182
Test name
Test status
Simulation time 59080881794 ps
CPU time 103.53 seconds
Started Jul 17 05:55:41 PM PDT 24
Finished Jul 17 05:57:27 PM PDT 24
Peak memory 199976 kb
Host smart-9012f422-dcae-4014-b73b-e309dd36881b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694678058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1694678058
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2623581559
Short name T445
Test name
Test status
Simulation time 144851144732 ps
CPU time 73.43 seconds
Started Jul 17 05:55:41 PM PDT 24
Finished Jul 17 05:56:56 PM PDT 24
Peak memory 199924 kb
Host smart-5b4d5491-5b49-40b0-8b63-fc491d8bd599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623581559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2623581559
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1323593030
Short name T916
Test name
Test status
Simulation time 56705272422 ps
CPU time 142.54 seconds
Started Jul 17 05:55:40 PM PDT 24
Finished Jul 17 05:58:05 PM PDT 24
Peak memory 200000 kb
Host smart-d5039fed-1b87-43e0-82bb-d6668b6987ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323593030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1323593030
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2534307326
Short name T591
Test name
Test status
Simulation time 37019066860 ps
CPU time 33.82 seconds
Started Jul 17 05:55:39 PM PDT 24
Finished Jul 17 05:56:16 PM PDT 24
Peak memory 199896 kb
Host smart-6743c045-5257-4336-bc1c-e496c63fc225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534307326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2534307326
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.4100277369
Short name T215
Test name
Test status
Simulation time 46792252991 ps
CPU time 30.38 seconds
Started Jul 17 05:55:39 PM PDT 24
Finished Jul 17 05:56:12 PM PDT 24
Peak memory 199832 kb
Host smart-895c3c25-b7cb-4843-84c2-4e5a47a68b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100277369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.4100277369
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1538649122
Short name T588
Test name
Test status
Simulation time 23196132 ps
CPU time 0.55 seconds
Started Jul 17 05:52:22 PM PDT 24
Finished Jul 17 05:52:26 PM PDT 24
Peak memory 194204 kb
Host smart-e378297f-a3ff-4c13-9117-d4bb5e25fa31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538649122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1538649122
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1113911293
Short name T570
Test name
Test status
Simulation time 39535906266 ps
CPU time 40.61 seconds
Started Jul 17 05:52:24 PM PDT 24
Finished Jul 17 05:53:08 PM PDT 24
Peak memory 199976 kb
Host smart-9c0af264-800c-48b1-9020-5433ab061a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113911293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1113911293
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.999898520
Short name T145
Test name
Test status
Simulation time 186693159072 ps
CPU time 75.27 seconds
Started Jul 17 05:52:20 PM PDT 24
Finished Jul 17 05:53:36 PM PDT 24
Peak memory 199776 kb
Host smart-02336dbe-a736-4056-94b6-74fd552e2ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999898520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.999898520
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1979796209
Short name T1080
Test name
Test status
Simulation time 15393821306 ps
CPU time 26.37 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 05:52:52 PM PDT 24
Peak memory 199684 kb
Host smart-cb060b9b-4e61-43f0-8314-2baa5ad05897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979796209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1979796209
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1926547842
Short name T335
Test name
Test status
Simulation time 128256110943 ps
CPU time 53.28 seconds
Started Jul 17 05:52:24 PM PDT 24
Finished Jul 17 05:53:20 PM PDT 24
Peak memory 198952 kb
Host smart-3aee03d3-2e33-4f2e-88ea-6eb8caa780ed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926547842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1926547842
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1861318121
Short name T44
Test name
Test status
Simulation time 110065393765 ps
CPU time 513.75 seconds
Started Jul 17 05:52:21 PM PDT 24
Finished Jul 17 06:00:56 PM PDT 24
Peak memory 199912 kb
Host smart-70cb8453-f5ce-4443-bbf2-fd53581e7387
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1861318121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1861318121
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2607086335
Short name T431
Test name
Test status
Simulation time 247603634 ps
CPU time 0.81 seconds
Started Jul 17 05:52:24 PM PDT 24
Finished Jul 17 05:52:28 PM PDT 24
Peak memory 195372 kb
Host smart-038301d5-144b-4551-b47b-43bedf6c0bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607086335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2607086335
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.506815541
Short name T1124
Test name
Test status
Simulation time 24872171771 ps
CPU time 9.59 seconds
Started Jul 17 05:52:22 PM PDT 24
Finished Jul 17 05:52:34 PM PDT 24
Peak memory 195928 kb
Host smart-804d7608-f718-4e7b-9dcf-862bfe6616df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506815541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.506815541
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1392617276
Short name T1054
Test name
Test status
Simulation time 4501501263 ps
CPU time 99.15 seconds
Started Jul 17 05:52:22 PM PDT 24
Finished Jul 17 05:54:03 PM PDT 24
Peak memory 199800 kb
Host smart-077d9402-8fa8-4cd3-ad55-8cfdd2e837cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392617276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1392617276
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2510745148
Short name T556
Test name
Test status
Simulation time 4932915225 ps
CPU time 12.71 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 05:52:39 PM PDT 24
Peak memory 199092 kb
Host smart-ae55135b-c856-4276-8a9a-6a10aa82b5b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510745148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2510745148
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2563934039
Short name T166
Test name
Test status
Simulation time 60946338457 ps
CPU time 33.69 seconds
Started Jul 17 05:52:22 PM PDT 24
Finished Jul 17 05:52:59 PM PDT 24
Peak memory 200092 kb
Host smart-563aadb3-e66e-46e1-83c8-0c6aee21a62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563934039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2563934039
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1415337673
Short name T362
Test name
Test status
Simulation time 1657806892 ps
CPU time 1.22 seconds
Started Jul 17 05:52:21 PM PDT 24
Finished Jul 17 05:52:23 PM PDT 24
Peak memory 195428 kb
Host smart-a1997e30-1672-46d9-939c-347432cc6188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415337673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1415337673
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1162563364
Short name T770
Test name
Test status
Simulation time 132009564 ps
CPU time 0.8 seconds
Started Jul 17 05:52:21 PM PDT 24
Finished Jul 17 05:52:24 PM PDT 24
Peak memory 197108 kb
Host smart-038eadeb-1a54-4871-af83-b5cc9882b809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162563364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1162563364
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.722598488
Short name T617
Test name
Test status
Simulation time 348834766033 ps
CPU time 838 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 06:06:25 PM PDT 24
Peak memory 208288 kb
Host smart-f0dcb28b-992e-4b39-a320-63aa8d43dbb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722598488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.722598488
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2664722995
Short name T28
Test name
Test status
Simulation time 31664488155 ps
CPU time 280 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 05:57:07 PM PDT 24
Peak memory 216496 kb
Host smart-2308b071-fb09-4005-a56a-382f6588057d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664722995 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2664722995
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.327821200
Short name T840
Test name
Test status
Simulation time 618498486 ps
CPU time 1.36 seconds
Started Jul 17 05:52:21 PM PDT 24
Finished Jul 17 05:52:23 PM PDT 24
Peak memory 197908 kb
Host smart-18d9ab5c-b6db-4777-8a61-f5bf38e9d7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327821200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.327821200
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2809862838
Short name T914
Test name
Test status
Simulation time 202571220246 ps
CPU time 70.23 seconds
Started Jul 17 05:52:24 PM PDT 24
Finished Jul 17 05:53:37 PM PDT 24
Peak memory 199988 kb
Host smart-bffb2e72-b393-4881-ab6d-dd5fa478c550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809862838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2809862838
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.4286749285
Short name T237
Test name
Test status
Simulation time 44626383567 ps
CPU time 29.88 seconds
Started Jul 17 05:55:39 PM PDT 24
Finished Jul 17 05:56:12 PM PDT 24
Peak memory 199992 kb
Host smart-0f40cd7f-ad93-4a3e-b7c6-c4a56fa79b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286749285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.4286749285
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2493224486
Short name T102
Test name
Test status
Simulation time 14584944803 ps
CPU time 28.19 seconds
Started Jul 17 05:55:40 PM PDT 24
Finished Jul 17 05:56:10 PM PDT 24
Peak memory 199904 kb
Host smart-bcc8ade3-eaa4-402a-bdf0-469636ea0186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493224486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2493224486
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1575614869
Short name T902
Test name
Test status
Simulation time 45321045631 ps
CPU time 74.56 seconds
Started Jul 17 05:55:37 PM PDT 24
Finished Jul 17 05:56:52 PM PDT 24
Peak memory 199972 kb
Host smart-30528dc7-b7da-4f60-8a87-063ba8cb5062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575614869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1575614869
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.4141586017
Short name T230
Test name
Test status
Simulation time 35075641836 ps
CPU time 13.6 seconds
Started Jul 17 05:55:41 PM PDT 24
Finished Jul 17 05:55:56 PM PDT 24
Peak memory 199928 kb
Host smart-d10ec1c6-cb38-4b39-9bc8-0ac86476e05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141586017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.4141586017
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.5618656
Short name T1140
Test name
Test status
Simulation time 29456202011 ps
CPU time 41.58 seconds
Started Jul 17 05:55:39 PM PDT 24
Finished Jul 17 05:56:23 PM PDT 24
Peak memory 200012 kb
Host smart-288032c4-8c94-45b3-98e3-e3bd867529eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5618656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.5618656
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1685580704
Short name T42
Test name
Test status
Simulation time 69560634718 ps
CPU time 26.62 seconds
Started Jul 17 05:56:06 PM PDT 24
Finished Jul 17 05:56:33 PM PDT 24
Peak memory 199972 kb
Host smart-8cde2b2a-ecce-451c-997e-e855acb99290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685580704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1685580704
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2005776418
Short name T876
Test name
Test status
Simulation time 39069162434 ps
CPU time 17.94 seconds
Started Jul 17 05:55:41 PM PDT 24
Finished Jul 17 05:56:01 PM PDT 24
Peak memory 199940 kb
Host smart-5ecdceb9-e7d9-487b-b803-019155c53186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005776418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2005776418
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1299390618
Short name T803
Test name
Test status
Simulation time 37929788628 ps
CPU time 42.56 seconds
Started Jul 17 05:55:40 PM PDT 24
Finished Jul 17 05:56:25 PM PDT 24
Peak memory 199920 kb
Host smart-375685de-f341-4e93-ada7-0adbc8b4556b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299390618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1299390618
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.4278085771
Short name T433
Test name
Test status
Simulation time 12740308 ps
CPU time 0.52 seconds
Started Jul 17 05:52:21 PM PDT 24
Finished Jul 17 05:52:23 PM PDT 24
Peak memory 195208 kb
Host smart-315932c1-d16e-410a-a712-6a985c13ab68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278085771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.4278085771
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1984169660
Short name T450
Test name
Test status
Simulation time 159678689326 ps
CPU time 123.11 seconds
Started Jul 17 05:52:21 PM PDT 24
Finished Jul 17 05:54:26 PM PDT 24
Peak memory 199840 kb
Host smart-b3d350a3-ea14-44ac-a8af-d50e8d30d2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984169660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1984169660
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.395346665
Short name T143
Test name
Test status
Simulation time 97152356402 ps
CPU time 29.57 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 05:52:56 PM PDT 24
Peak memory 199848 kb
Host smart-f27cb46f-a3f1-4e4f-849b-74ee20d38ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395346665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.395346665
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.680159359
Short name T897
Test name
Test status
Simulation time 248435304449 ps
CPU time 181.85 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 05:55:28 PM PDT 24
Peak memory 199964 kb
Host smart-8819c9f9-680c-43b1-886c-55e162208d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680159359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.680159359
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.4187081275
Short name T1056
Test name
Test status
Simulation time 19422357896 ps
CPU time 5.57 seconds
Started Jul 17 05:52:25 PM PDT 24
Finished Jul 17 05:52:33 PM PDT 24
Peak memory 199872 kb
Host smart-0c10740a-ab98-4ff8-ba90-46a19b2d8726
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187081275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.4187081275
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2809125453
Short name T744
Test name
Test status
Simulation time 165137499903 ps
CPU time 1484.16 seconds
Started Jul 17 05:52:17 PM PDT 24
Finished Jul 17 06:17:02 PM PDT 24
Peak memory 199928 kb
Host smart-56ad5968-1f0b-4577-8d73-c6b172c21108
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809125453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2809125453
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1753944276
Short name T1015
Test name
Test status
Simulation time 8796098170 ps
CPU time 5.86 seconds
Started Jul 17 05:52:24 PM PDT 24
Finished Jul 17 05:52:33 PM PDT 24
Peak memory 199388 kb
Host smart-7bd6f432-d40d-4d5d-a69c-e2ee00e8b0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753944276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1753944276
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2447845262
Short name T1099
Test name
Test status
Simulation time 144583920157 ps
CPU time 66.43 seconds
Started Jul 17 05:52:27 PM PDT 24
Finished Jul 17 05:53:35 PM PDT 24
Peak memory 199800 kb
Host smart-2adc1add-707c-43d8-b97b-409aba6b0ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447845262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2447845262
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2866701347
Short name T907
Test name
Test status
Simulation time 3483866209 ps
CPU time 189.2 seconds
Started Jul 17 05:52:22 PM PDT 24
Finished Jul 17 05:55:35 PM PDT 24
Peak memory 199980 kb
Host smart-4f5692ef-632a-4a63-8465-2041350e7f0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2866701347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2866701347
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.295160349
Short name T386
Test name
Test status
Simulation time 4008740273 ps
CPU time 17.42 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 05:52:43 PM PDT 24
Peak memory 198312 kb
Host smart-f33071cf-aedf-401c-a785-8bd5c1dbe65b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=295160349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.295160349
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.897442599
Short name T640
Test name
Test status
Simulation time 129815684926 ps
CPU time 202.3 seconds
Started Jul 17 05:52:21 PM PDT 24
Finished Jul 17 05:55:44 PM PDT 24
Peak memory 199612 kb
Host smart-a5b5368c-fab7-420d-990e-86937b5e373f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897442599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.897442599
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2985212963
Short name T296
Test name
Test status
Simulation time 4499329646 ps
CPU time 1.73 seconds
Started Jul 17 05:52:24 PM PDT 24
Finished Jul 17 05:52:29 PM PDT 24
Peak memory 196028 kb
Host smart-e668ddb0-33e2-4107-877b-cdb8dc72ab93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985212963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2985212963
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1422472260
Short name T392
Test name
Test status
Simulation time 6099547045 ps
CPU time 16.74 seconds
Started Jul 17 05:52:22 PM PDT 24
Finished Jul 17 05:52:42 PM PDT 24
Peak memory 199972 kb
Host smart-a3147cc4-c418-4ef8-b829-03f8aeebd57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422472260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1422472260
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2389076879
Short name T559
Test name
Test status
Simulation time 318254012227 ps
CPU time 811.82 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 06:05:58 PM PDT 24
Peak memory 200160 kb
Host smart-5b416217-fd1a-434d-9dce-a60c9ab32821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389076879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2389076879
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3941789289
Short name T1098
Test name
Test status
Simulation time 25318413999 ps
CPU time 427.03 seconds
Started Jul 17 05:52:22 PM PDT 24
Finished Jul 17 05:59:32 PM PDT 24
Peak memory 215704 kb
Host smart-e27c4d09-b8bc-4efe-8062-81b89521f7ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941789289 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3941789289
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1452709235
Short name T886
Test name
Test status
Simulation time 506532758 ps
CPU time 1.91 seconds
Started Jul 17 05:52:24 PM PDT 24
Finished Jul 17 05:52:29 PM PDT 24
Peak memory 198300 kb
Host smart-a54faf46-b6df-4898-a113-54c939e61015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452709235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1452709235
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2094257471
Short name T1137
Test name
Test status
Simulation time 27528514327 ps
CPU time 11.57 seconds
Started Jul 17 05:52:22 PM PDT 24
Finished Jul 17 05:52:35 PM PDT 24
Peak memory 199980 kb
Host smart-3265622e-b730-4e8f-8711-0963e262fb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094257471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2094257471
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.4107974736
Short name T568
Test name
Test status
Simulation time 34521489685 ps
CPU time 14.58 seconds
Started Jul 17 05:55:41 PM PDT 24
Finished Jul 17 05:55:57 PM PDT 24
Peak memory 199348 kb
Host smart-8fde2c7c-149a-4c75-952d-5ad0789ac11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107974736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.4107974736
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1725481060
Short name T982
Test name
Test status
Simulation time 265070529750 ps
CPU time 33.02 seconds
Started Jul 17 05:55:40 PM PDT 24
Finished Jul 17 05:56:16 PM PDT 24
Peak memory 199924 kb
Host smart-f73cbfe0-7634-4bdf-a02c-304bc5bbcf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725481060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1725481060
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.4054073784
Short name T379
Test name
Test status
Simulation time 31123288238 ps
CPU time 9.81 seconds
Started Jul 17 05:55:40 PM PDT 24
Finished Jul 17 05:55:52 PM PDT 24
Peak memory 199868 kb
Host smart-7e5e6971-6fdf-4f81-bfa7-2a1f01ba4e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054073784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4054073784
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2745071774
Short name T539
Test name
Test status
Simulation time 88672093405 ps
CPU time 157.94 seconds
Started Jul 17 05:55:37 PM PDT 24
Finished Jul 17 05:58:16 PM PDT 24
Peak memory 199940 kb
Host smart-0c2f15e5-2373-4aa0-bee9-c0635771de0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745071774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2745071774
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3797511148
Short name T1077
Test name
Test status
Simulation time 57675726580 ps
CPU time 14.88 seconds
Started Jul 17 05:55:42 PM PDT 24
Finished Jul 17 05:55:58 PM PDT 24
Peak memory 199928 kb
Host smart-2cf79888-56fd-452f-8e4f-b38c81345fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797511148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3797511148
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3014261049
Short name T152
Test name
Test status
Simulation time 52923492932 ps
CPU time 25.6 seconds
Started Jul 17 05:55:37 PM PDT 24
Finished Jul 17 05:56:04 PM PDT 24
Peak memory 200168 kb
Host smart-25ae0e97-0b48-481e-8cc6-6127d7084038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014261049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3014261049
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1796944314
Short name T1020
Test name
Test status
Simulation time 48735800893 ps
CPU time 38.5 seconds
Started Jul 17 05:55:38 PM PDT 24
Finished Jul 17 05:56:17 PM PDT 24
Peak memory 199900 kb
Host smart-d419d5d9-2c20-44b4-90ef-62911f017328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796944314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1796944314
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.646260324
Short name T1045
Test name
Test status
Simulation time 34770631751 ps
CPU time 15.9 seconds
Started Jul 17 05:55:40 PM PDT 24
Finished Jul 17 05:55:58 PM PDT 24
Peak memory 199916 kb
Host smart-68ba391d-f54a-4d7c-ba47-1a7e59ba2620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646260324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.646260324
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3606400826
Short name T198
Test name
Test status
Simulation time 39638124507 ps
CPU time 52.27 seconds
Started Jul 17 05:55:54 PM PDT 24
Finished Jul 17 05:56:47 PM PDT 24
Peak memory 199952 kb
Host smart-9788669a-819b-4a6c-8c8c-5ef42ccd5709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606400826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3606400826
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3319371747
Short name T1069
Test name
Test status
Simulation time 60383645885 ps
CPU time 41.68 seconds
Started Jul 17 05:55:54 PM PDT 24
Finished Jul 17 05:56:37 PM PDT 24
Peak memory 199840 kb
Host smart-f088d767-479c-47a8-99d4-74e45b3d3c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319371747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3319371747
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1122393936
Short name T814
Test name
Test status
Simulation time 15413936 ps
CPU time 0.59 seconds
Started Jul 17 05:50:39 PM PDT 24
Finished Jul 17 05:50:42 PM PDT 24
Peak memory 195208 kb
Host smart-9427348f-d298-4eed-a054-af94eb9748a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122393936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1122393936
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1328216434
Short name T459
Test name
Test status
Simulation time 48097203102 ps
CPU time 79.03 seconds
Started Jul 17 05:50:40 PM PDT 24
Finished Jul 17 05:52:01 PM PDT 24
Peak memory 199872 kb
Host smart-2da1df26-4acb-4fd9-a0c0-30b0f48dd57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328216434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1328216434
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1957915591
Short name T644
Test name
Test status
Simulation time 22523836644 ps
CPU time 22.09 seconds
Started Jul 17 05:50:36 PM PDT 24
Finished Jul 17 05:51:00 PM PDT 24
Peak memory 199764 kb
Host smart-f1aff5d6-bff9-4c47-bd5e-bb0ef3760479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957915591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1957915591
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_intr.231097078
Short name T836
Test name
Test status
Simulation time 26988405101 ps
CPU time 14.79 seconds
Started Jul 17 05:50:40 PM PDT 24
Finished Jul 17 05:50:56 PM PDT 24
Peak memory 199832 kb
Host smart-660af2a1-dc28-4563-b030-4193b5dee517
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231097078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.231097078
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1839793838
Short name T251
Test name
Test status
Simulation time 174501916545 ps
CPU time 493.92 seconds
Started Jul 17 05:50:33 PM PDT 24
Finished Jul 17 05:58:49 PM PDT 24
Peak memory 199832 kb
Host smart-1f0d60f8-c377-4b6d-b522-39bd280d5e2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839793838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1839793838
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.527421855
Short name T464
Test name
Test status
Simulation time 4398917496 ps
CPU time 3.48 seconds
Started Jul 17 05:50:35 PM PDT 24
Finished Jul 17 05:50:40 PM PDT 24
Peak memory 199196 kb
Host smart-95823454-7718-4c67-96ba-eb99f1b1f899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527421855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.527421855
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.639076975
Short name T282
Test name
Test status
Simulation time 129801607355 ps
CPU time 531.24 seconds
Started Jul 17 05:50:40 PM PDT 24
Finished Jul 17 05:59:33 PM PDT 24
Peak memory 200308 kb
Host smart-d1f13863-2dd5-4f20-8e5a-9ee2520107e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639076975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.639076975
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3189901097
Short name T471
Test name
Test status
Simulation time 38685790844 ps
CPU time 1797.35 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 06:20:47 PM PDT 24
Peak memory 199956 kb
Host smart-8eed81c6-1ea8-4e3c-8ca2-8fad728b924f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189901097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3189901097
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3884610125
Short name T794
Test name
Test status
Simulation time 6029521846 ps
CPU time 49.69 seconds
Started Jul 17 05:50:46 PM PDT 24
Finished Jul 17 05:51:37 PM PDT 24
Peak memory 199200 kb
Host smart-0a574aa2-e3db-419a-9172-00bc7f9e9e7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884610125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3884610125
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.151565551
Short name T743
Test name
Test status
Simulation time 48407766932 ps
CPU time 19.52 seconds
Started Jul 17 05:50:33 PM PDT 24
Finished Jul 17 05:50:54 PM PDT 24
Peak memory 199896 kb
Host smart-9a63f803-efc1-4a71-a6f7-60c9100ab287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151565551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.151565551
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3888549841
Short name T892
Test name
Test status
Simulation time 3179271925 ps
CPU time 5.89 seconds
Started Jul 17 05:50:34 PM PDT 24
Finished Jul 17 05:50:41 PM PDT 24
Peak memory 196476 kb
Host smart-d7e536df-05e7-467a-aabc-8c6dfaefd566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888549841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3888549841
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2461226972
Short name T24
Test name
Test status
Simulation time 32404992 ps
CPU time 0.78 seconds
Started Jul 17 05:50:39 PM PDT 24
Finished Jul 17 05:50:41 PM PDT 24
Peak memory 218260 kb
Host smart-4c6321e6-d7fd-416a-a685-8c0ebfdbb615
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461226972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2461226972
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3503603460
Short name T1127
Test name
Test status
Simulation time 6084904505 ps
CPU time 12.29 seconds
Started Jul 17 05:50:35 PM PDT 24
Finished Jul 17 05:50:49 PM PDT 24
Peak memory 199968 kb
Host smart-1f9605c1-4197-4e89-a163-9a54b9974a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503603460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3503603460
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3899531830
Short name T964
Test name
Test status
Simulation time 120232641483 ps
CPU time 84.8 seconds
Started Jul 17 05:50:36 PM PDT 24
Finished Jul 17 05:52:03 PM PDT 24
Peak memory 200100 kb
Host smart-76cc29a9-5474-482b-87f8-04251b51e82c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899531830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3899531830
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2120688519
Short name T852
Test name
Test status
Simulation time 5333155135 ps
CPU time 57.41 seconds
Started Jul 17 05:50:34 PM PDT 24
Finished Jul 17 05:51:32 PM PDT 24
Peak memory 216272 kb
Host smart-071a7376-2ca7-40a1-8395-4bd42b13c02e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120688519 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2120688519
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2531427497
Short name T919
Test name
Test status
Simulation time 481640873 ps
CPU time 1.92 seconds
Started Jul 17 05:50:36 PM PDT 24
Finished Jul 17 05:50:40 PM PDT 24
Peak memory 198272 kb
Host smart-cbbc74eb-9b6f-4411-8bd2-cf7054fb2f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531427497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2531427497
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2824543698
Short name T809
Test name
Test status
Simulation time 5495767968 ps
CPU time 8.47 seconds
Started Jul 17 05:50:37 PM PDT 24
Finished Jul 17 05:50:47 PM PDT 24
Peak memory 199916 kb
Host smart-4da5279a-e9f8-4f81-a14a-8e5ca3639647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824543698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2824543698
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3963223159
Short name T646
Test name
Test status
Simulation time 23281957 ps
CPU time 0.56 seconds
Started Jul 17 05:52:34 PM PDT 24
Finished Jul 17 05:52:36 PM PDT 24
Peak memory 195304 kb
Host smart-65562807-322a-4228-9fb7-b34fb5875cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963223159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3963223159
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2668013381
Short name T993
Test name
Test status
Simulation time 38371334661 ps
CPU time 62.52 seconds
Started Jul 17 05:52:21 PM PDT 24
Finished Jul 17 05:53:26 PM PDT 24
Peak memory 199920 kb
Host smart-e5ef248b-6ed0-43cc-bcab-46ed6ccdca3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668013381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2668013381
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1504786171
Short name T858
Test name
Test status
Simulation time 22908902517 ps
CPU time 49.56 seconds
Started Jul 17 05:52:24 PM PDT 24
Finished Jul 17 05:53:17 PM PDT 24
Peak memory 199828 kb
Host smart-8d56bb7d-848a-4cf3-acbe-9c9bf549a6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504786171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1504786171
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2318564438
Short name T131
Test name
Test status
Simulation time 36069293362 ps
CPU time 166.73 seconds
Started Jul 17 05:52:20 PM PDT 24
Finished Jul 17 05:55:07 PM PDT 24
Peak memory 199908 kb
Host smart-58047ce4-f051-4c11-9e82-e8265909e2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318564438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2318564438
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2689533881
Short name T343
Test name
Test status
Simulation time 39135486651 ps
CPU time 7.23 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 05:52:33 PM PDT 24
Peak memory 199884 kb
Host smart-c0952d36-4045-4a25-892d-7e659379974d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689533881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2689533881
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.917413064
Short name T294
Test name
Test status
Simulation time 160409209091 ps
CPU time 272.98 seconds
Started Jul 17 05:52:21 PM PDT 24
Finished Jul 17 05:56:56 PM PDT 24
Peak memory 199920 kb
Host smart-add0e9d9-2ca4-4687-a62c-62416c55db7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917413064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.917413064
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1088679891
Short name T420
Test name
Test status
Simulation time 1636418360 ps
CPU time 2.12 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 05:52:28 PM PDT 24
Peak memory 199608 kb
Host smart-9129c5f8-9e47-4e05-b1ed-8ea67f5914b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088679891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1088679891
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.723709138
Short name T1063
Test name
Test status
Simulation time 2254492157 ps
CPU time 3.92 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 05:52:30 PM PDT 24
Peak memory 199876 kb
Host smart-d6632e73-2259-4d37-83de-45df01d4ed8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723709138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.723709138
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2656298900
Short name T602
Test name
Test status
Simulation time 6118234937 ps
CPU time 97.36 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 05:54:04 PM PDT 24
Peak memory 200004 kb
Host smart-e76385a0-d94c-49a8-8d32-64d366ed1a78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656298900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2656298900
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2287874256
Short name T1134
Test name
Test status
Simulation time 6610819312 ps
CPU time 13.26 seconds
Started Jul 17 05:52:21 PM PDT 24
Finished Jul 17 05:52:36 PM PDT 24
Peak memory 198964 kb
Host smart-a4b1c1d6-704e-4387-84a6-e18ef4d74c70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287874256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2287874256
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2102217557
Short name T822
Test name
Test status
Simulation time 151363986207 ps
CPU time 63.28 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 05:53:29 PM PDT 24
Peak memory 199964 kb
Host smart-de0cf126-9874-4972-9a33-319045e29e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102217557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2102217557
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3542012139
Short name T990
Test name
Test status
Simulation time 3906656955 ps
CPU time 3.44 seconds
Started Jul 17 05:52:21 PM PDT 24
Finished Jul 17 05:52:26 PM PDT 24
Peak memory 196704 kb
Host smart-414392d7-a320-4378-8fe8-f16cfc8c3dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542012139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3542012139
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.4122293345
Short name T577
Test name
Test status
Simulation time 631341680 ps
CPU time 2.35 seconds
Started Jul 17 05:52:20 PM PDT 24
Finished Jul 17 05:52:24 PM PDT 24
Peak memory 199868 kb
Host smart-b0b2e449-ffa4-47b5-a842-89cafdacdb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122293345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.4122293345
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.715828106
Short name T266
Test name
Test status
Simulation time 118234329454 ps
CPU time 160.51 seconds
Started Jul 17 05:52:38 PM PDT 24
Finished Jul 17 05:55:23 PM PDT 24
Peak memory 199640 kb
Host smart-aae818fd-7c99-47f8-be76-239eb546c377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715828106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.715828106
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.2994968788
Short name T650
Test name
Test status
Simulation time 135973265910 ps
CPU time 597.9 seconds
Started Jul 17 05:52:22 PM PDT 24
Finished Jul 17 06:02:22 PM PDT 24
Peak memory 224912 kb
Host smart-6e66dc95-2f5d-4cb6-821c-06cef1ad2687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994968788 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.2994968788
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3889246014
Short name T1081
Test name
Test status
Simulation time 7231101571 ps
CPU time 9.49 seconds
Started Jul 17 05:52:23 PM PDT 24
Finished Jul 17 05:52:35 PM PDT 24
Peak memory 199852 kb
Host smart-819cc03f-b523-4b52-a6ff-21d96037f2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889246014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3889246014
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3091855744
Short name T656
Test name
Test status
Simulation time 52385302304 ps
CPU time 107.97 seconds
Started Jul 17 05:52:25 PM PDT 24
Finished Jul 17 05:54:16 PM PDT 24
Peak memory 199840 kb
Host smart-42cbf42a-aeef-4680-91c5-822823b72b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091855744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3091855744
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.528661900
Short name T546
Test name
Test status
Simulation time 52210180 ps
CPU time 0.55 seconds
Started Jul 17 05:52:35 PM PDT 24
Finished Jul 17 05:52:38 PM PDT 24
Peak memory 194952 kb
Host smart-e9a55c09-e684-4b76-8185-91b77716a229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528661900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.528661900
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.965737414
Short name T893
Test name
Test status
Simulation time 40018119063 ps
CPU time 63.82 seconds
Started Jul 17 05:52:33 PM PDT 24
Finished Jul 17 05:53:38 PM PDT 24
Peak memory 199996 kb
Host smart-d764dfb9-f296-4114-b089-3da4d0c10358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965737414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.965737414
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3125167876
Short name T136
Test name
Test status
Simulation time 18316571945 ps
CPU time 16.17 seconds
Started Jul 17 05:52:40 PM PDT 24
Finished Jul 17 05:53:00 PM PDT 24
Peak memory 199832 kb
Host smart-032b68b7-c9e8-4192-bff3-6b4ad76ae16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125167876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3125167876
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2958591088
Short name T149
Test name
Test status
Simulation time 46951367395 ps
CPU time 118.72 seconds
Started Jul 17 05:52:36 PM PDT 24
Finished Jul 17 05:54:37 PM PDT 24
Peak memory 199908 kb
Host smart-a507c57f-05f2-49bf-9e26-5a4a44356eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958591088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2958591088
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1768383742
Short name T988
Test name
Test status
Simulation time 95505220855 ps
CPU time 332.19 seconds
Started Jul 17 05:52:36 PM PDT 24
Finished Jul 17 05:58:11 PM PDT 24
Peak memory 199760 kb
Host smart-98d8d034-a296-4080-a741-ce68674a62ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768383742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1768383742
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3030805144
Short name T949
Test name
Test status
Simulation time 39696218 ps
CPU time 0.58 seconds
Started Jul 17 05:52:33 PM PDT 24
Finished Jul 17 05:52:34 PM PDT 24
Peak memory 195672 kb
Host smart-a1b68a24-04c8-4554-8f87-d384a618780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030805144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3030805144
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.2095392403
Short name T696
Test name
Test status
Simulation time 15272130412 ps
CPU time 847.21 seconds
Started Jul 17 05:52:40 PM PDT 24
Finished Jul 17 06:06:51 PM PDT 24
Peak memory 199696 kb
Host smart-7e79dff8-7f12-4b3a-aff6-06ff013bd3c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095392403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2095392403
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.184569067
Short name T487
Test name
Test status
Simulation time 5377808362 ps
CPU time 43.83 seconds
Started Jul 17 05:52:34 PM PDT 24
Finished Jul 17 05:53:19 PM PDT 24
Peak memory 199388 kb
Host smart-e021fa22-7559-40be-a7bb-db8954c791c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=184569067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.184569067
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3772933735
Short name T545
Test name
Test status
Simulation time 127608789217 ps
CPU time 368.54 seconds
Started Jul 17 05:52:34 PM PDT 24
Finished Jul 17 05:58:45 PM PDT 24
Peak memory 199828 kb
Host smart-34c88b09-1ab9-4fac-bea3-c23c0587e5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772933735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3772933735
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.4108866112
Short name T775
Test name
Test status
Simulation time 3322901839 ps
CPU time 2.89 seconds
Started Jul 17 05:52:39 PM PDT 24
Finished Jul 17 05:52:46 PM PDT 24
Peak memory 195880 kb
Host smart-e9ca0c2c-2b64-4823-9f9d-69ccccaa3341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108866112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4108866112
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1093332769
Short name T442
Test name
Test status
Simulation time 913382822 ps
CPU time 2.07 seconds
Started Jul 17 05:52:35 PM PDT 24
Finished Jul 17 05:52:39 PM PDT 24
Peak memory 198276 kb
Host smart-87d1ea6a-5ebc-4f6e-a1b7-f7eeefa3be07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093332769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1093332769
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2589406116
Short name T551
Test name
Test status
Simulation time 241997376932 ps
CPU time 231.98 seconds
Started Jul 17 05:52:36 PM PDT 24
Finished Jul 17 05:56:31 PM PDT 24
Peak memory 199956 kb
Host smart-764b6db0-5ba6-48a3-93d1-34eda1771018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589406116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2589406116
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.4012812040
Short name T918
Test name
Test status
Simulation time 39025687215 ps
CPU time 700.22 seconds
Started Jul 17 05:52:40 PM PDT 24
Finished Jul 17 06:04:24 PM PDT 24
Peak memory 216272 kb
Host smart-cc1d5192-1861-418c-931f-9067b8afd6b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012812040 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.4012812040
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3098216421
Short name T661
Test name
Test status
Simulation time 572703886 ps
CPU time 2.28 seconds
Started Jul 17 05:52:36 PM PDT 24
Finished Jul 17 05:52:42 PM PDT 24
Peak memory 198964 kb
Host smart-576fd43c-6f2a-4b68-83bd-f0a8b4f17857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098216421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3098216421
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1947911912
Short name T489
Test name
Test status
Simulation time 45303560573 ps
CPU time 59.7 seconds
Started Jul 17 05:52:37 PM PDT 24
Finished Jul 17 05:53:40 PM PDT 24
Peak memory 199624 kb
Host smart-7c759ca1-e6f7-4bec-8080-cbfa159e259b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947911912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1947911912
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1984775298
Short name T734
Test name
Test status
Simulation time 59272063 ps
CPU time 0.54 seconds
Started Jul 17 05:52:38 PM PDT 24
Finished Jul 17 05:52:43 PM PDT 24
Peak memory 194192 kb
Host smart-2d0f8d3e-3e80-4dda-89ce-25aa5bf9dd95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984775298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1984775298
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3714238382
Short name T576
Test name
Test status
Simulation time 73150803724 ps
CPU time 27.41 seconds
Started Jul 17 05:52:41 PM PDT 24
Finished Jul 17 05:53:12 PM PDT 24
Peak memory 199868 kb
Host smart-c0cdccf1-f45a-49c5-87dd-b6a436905f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714238382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3714238382
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1961340773
Short name T765
Test name
Test status
Simulation time 15564942422 ps
CPU time 26.95 seconds
Started Jul 17 05:52:35 PM PDT 24
Finished Jul 17 05:53:05 PM PDT 24
Peak memory 200000 kb
Host smart-74b53461-d99e-4ebf-a425-93be454d25aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961340773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1961340773
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1040503300
Short name T666
Test name
Test status
Simulation time 125688461388 ps
CPU time 99.8 seconds
Started Jul 17 05:52:36 PM PDT 24
Finished Jul 17 05:54:20 PM PDT 24
Peak memory 199852 kb
Host smart-10d538f6-ca90-4b23-ab8a-511492c95736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040503300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1040503300
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3454895224
Short name T637
Test name
Test status
Simulation time 21203198355 ps
CPU time 9.1 seconds
Started Jul 17 05:52:30 PM PDT 24
Finished Jul 17 05:52:40 PM PDT 24
Peak memory 198628 kb
Host smart-3160def6-0824-4988-ae26-88333affd4b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454895224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3454895224
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1678446462
Short name T101
Test name
Test status
Simulation time 92113297396 ps
CPU time 470.65 seconds
Started Jul 17 05:52:37 PM PDT 24
Finished Jul 17 06:00:32 PM PDT 24
Peak memory 199904 kb
Host smart-347ed236-f618-4a0b-9d22-53b0372e9566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678446462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1678446462
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2517203638
Short name T648
Test name
Test status
Simulation time 3925341380 ps
CPU time 6.27 seconds
Started Jul 17 05:52:41 PM PDT 24
Finished Jul 17 05:52:51 PM PDT 24
Peak memory 195756 kb
Host smart-c2b2dd44-4865-4da7-af2c-19121ff70254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517203638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2517203638
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3292252498
Short name T1117
Test name
Test status
Simulation time 26559903672 ps
CPU time 35.66 seconds
Started Jul 17 05:52:36 PM PDT 24
Finished Jul 17 05:53:15 PM PDT 24
Peak memory 200120 kb
Host smart-6d059e97-edc6-4b2a-9cd9-8f2e61598f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292252498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3292252498
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3510383311
Short name T378
Test name
Test status
Simulation time 10401974629 ps
CPU time 613.71 seconds
Started Jul 17 05:52:34 PM PDT 24
Finished Jul 17 06:02:49 PM PDT 24
Peak memory 200012 kb
Host smart-f2f9c5f6-88e3-4bae-aa9e-223a97a5f08a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510383311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3510383311
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1605697980
Short name T1152
Test name
Test status
Simulation time 1499082493 ps
CPU time 3.11 seconds
Started Jul 17 05:52:35 PM PDT 24
Finished Jul 17 05:52:40 PM PDT 24
Peak memory 198604 kb
Host smart-222b2ab9-7966-4a65-a6dd-8e254c71459f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605697980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1605697980
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.702769632
Short name T777
Test name
Test status
Simulation time 57732956903 ps
CPU time 21.99 seconds
Started Jul 17 05:52:36 PM PDT 24
Finished Jul 17 05:53:01 PM PDT 24
Peak memory 199796 kb
Host smart-8a4eccc5-2133-4a23-882d-30173dae8e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702769632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.702769632
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2539547620
Short name T1177
Test name
Test status
Simulation time 44129772071 ps
CPU time 27.24 seconds
Started Jul 17 05:52:34 PM PDT 24
Finished Jul 17 05:53:03 PM PDT 24
Peak memory 196168 kb
Host smart-b9672a09-c2d9-4d28-ae49-19c63aa31dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539547620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2539547620
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2045364613
Short name T558
Test name
Test status
Simulation time 5363325979 ps
CPU time 16.93 seconds
Started Jul 17 05:52:37 PM PDT 24
Finished Jul 17 05:52:57 PM PDT 24
Peak memory 198680 kb
Host smart-3d91b527-f204-4675-bc07-a882e080570b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045364613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2045364613
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.473048252
Short name T984
Test name
Test status
Simulation time 252362146129 ps
CPU time 434.13 seconds
Started Jul 17 05:52:35 PM PDT 24
Finished Jul 17 05:59:53 PM PDT 24
Peak memory 199948 kb
Host smart-14a5b067-d6f2-4f46-910e-f552698cefbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473048252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.473048252
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.4177246110
Short name T103
Test name
Test status
Simulation time 137283187374 ps
CPU time 673.22 seconds
Started Jul 17 05:52:41 PM PDT 24
Finished Jul 17 06:03:58 PM PDT 24
Peak memory 210732 kb
Host smart-0d5fb964-1835-475d-9726-3a9c3f7711e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177246110 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.4177246110
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2647847444
Short name T1070
Test name
Test status
Simulation time 1603002325 ps
CPU time 2.82 seconds
Started Jul 17 05:52:34 PM PDT 24
Finished Jul 17 05:52:39 PM PDT 24
Peak memory 199796 kb
Host smart-6426edaa-412d-4274-a1ae-e5df622fbacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647847444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2647847444
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3239853748
Short name T426
Test name
Test status
Simulation time 56364493338 ps
CPU time 96.42 seconds
Started Jul 17 05:52:36 PM PDT 24
Finished Jul 17 05:54:16 PM PDT 24
Peak memory 199968 kb
Host smart-fe405086-131b-44ef-89ca-2d6ad13441a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239853748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3239853748
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3507152925
Short name T1086
Test name
Test status
Simulation time 26409929 ps
CPU time 0.59 seconds
Started Jul 17 05:52:42 PM PDT 24
Finished Jul 17 05:52:45 PM PDT 24
Peak memory 195160 kb
Host smart-675e7241-e1be-48d1-8899-8591159559cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507152925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3507152925
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.672894461
Short name T508
Test name
Test status
Simulation time 26336542643 ps
CPU time 40.73 seconds
Started Jul 17 05:52:35 PM PDT 24
Finished Jul 17 05:53:18 PM PDT 24
Peak memory 199920 kb
Host smart-f6a95070-de9d-4a71-969e-931d89b3c863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672894461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.672894461
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1275321138
Short name T319
Test name
Test status
Simulation time 43800033534 ps
CPU time 64.85 seconds
Started Jul 17 05:52:34 PM PDT 24
Finished Jul 17 05:53:41 PM PDT 24
Peak memory 199776 kb
Host smart-9c3735c5-f568-4e2d-bb3d-6246a9e1fb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275321138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1275321138
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.385855862
Short name T1074
Test name
Test status
Simulation time 44505515628 ps
CPU time 40.79 seconds
Started Jul 17 05:52:38 PM PDT 24
Finished Jul 17 05:53:23 PM PDT 24
Peak memory 199660 kb
Host smart-686da661-fbe6-4430-b57d-99777071fc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385855862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.385855862
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3817823830
Short name T17
Test name
Test status
Simulation time 43117682030 ps
CPU time 35.41 seconds
Started Jul 17 05:52:41 PM PDT 24
Finished Jul 17 05:53:20 PM PDT 24
Peak memory 199044 kb
Host smart-09758f17-7a56-42db-8489-d0aaacfaf3b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817823830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3817823830
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3575422303
Short name T286
Test name
Test status
Simulation time 152019038002 ps
CPU time 768.57 seconds
Started Jul 17 05:52:42 PM PDT 24
Finished Jul 17 06:05:33 PM PDT 24
Peak memory 199928 kb
Host smart-3d0105b2-fec3-4924-9330-71a09a5fa5b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575422303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3575422303
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.4003600673
Short name T844
Test name
Test status
Simulation time 5720977909 ps
CPU time 6.37 seconds
Started Jul 17 05:52:40 PM PDT 24
Finished Jul 17 05:52:50 PM PDT 24
Peak memory 198736 kb
Host smart-4e37051b-5ddd-49ed-b322-8084af45d79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003600673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.4003600673
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2807382580
Short name T954
Test name
Test status
Simulation time 72206183418 ps
CPU time 80.52 seconds
Started Jul 17 05:52:39 PM PDT 24
Finished Jul 17 05:54:03 PM PDT 24
Peak memory 200068 kb
Host smart-f6afb6fe-9baa-432b-99cf-b057b6d75fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807382580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2807382580
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2118831536
Short name T652
Test name
Test status
Simulation time 25185584338 ps
CPU time 145.51 seconds
Started Jul 17 05:52:37 PM PDT 24
Finished Jul 17 05:55:06 PM PDT 24
Peak memory 199988 kb
Host smart-4a0a5043-63bc-4e9c-8e70-53d1e026942b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2118831536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2118831536
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1479152415
Short name T624
Test name
Test status
Simulation time 3683994369 ps
CPU time 26.6 seconds
Started Jul 17 05:52:35 PM PDT 24
Finished Jul 17 05:53:04 PM PDT 24
Peak memory 198164 kb
Host smart-b348c54c-dce8-4e05-b83e-cd8c22f27ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479152415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1479152415
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1908930159
Short name T1094
Test name
Test status
Simulation time 9329968665 ps
CPU time 13.92 seconds
Started Jul 17 05:52:35 PM PDT 24
Finished Jul 17 05:52:52 PM PDT 24
Peak memory 199416 kb
Host smart-f874e333-f3db-4673-a866-89a947f6ec6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908930159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1908930159
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2111928818
Short name T1047
Test name
Test status
Simulation time 2855636161 ps
CPU time 4.91 seconds
Started Jul 17 05:52:37 PM PDT 24
Finished Jul 17 05:52:45 PM PDT 24
Peak memory 195420 kb
Host smart-1eed864b-ee93-4811-9b5c-307ebdb796e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111928818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2111928818
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.311507360
Short name T534
Test name
Test status
Simulation time 491308740 ps
CPU time 1.92 seconds
Started Jul 17 05:52:35 PM PDT 24
Finished Jul 17 05:52:39 PM PDT 24
Peak memory 198924 kb
Host smart-fc9d4a0a-ed9b-4c10-87c7-08b786b9ddf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311507360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.311507360
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.4274370598
Short name T641
Test name
Test status
Simulation time 103646146778 ps
CPU time 36.27 seconds
Started Jul 17 05:52:41 PM PDT 24
Finished Jul 17 05:53:21 PM PDT 24
Peak memory 199824 kb
Host smart-5e79c3cf-fd8b-4040-b64f-b186115147f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274370598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.4274370598
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3535978203
Short name T745
Test name
Test status
Simulation time 948086179 ps
CPU time 2.44 seconds
Started Jul 17 05:52:39 PM PDT 24
Finished Jul 17 05:52:45 PM PDT 24
Peak memory 198456 kb
Host smart-1f9fbae1-260c-4266-818e-ca2f46193d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535978203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3535978203
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1904755617
Short name T311
Test name
Test status
Simulation time 51943787187 ps
CPU time 73.5 seconds
Started Jul 17 05:52:38 PM PDT 24
Finished Jul 17 05:53:56 PM PDT 24
Peak memory 199848 kb
Host smart-dd3cc636-9290-40ee-ab3e-2e1376f5ebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904755617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1904755617
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1132578435
Short name T827
Test name
Test status
Simulation time 13352703 ps
CPU time 0.55 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:52:56 PM PDT 24
Peak memory 194772 kb
Host smart-9719f64c-792b-4089-8b39-e82ed556ce9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132578435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1132578435
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1974065113
Short name T389
Test name
Test status
Simulation time 49195901921 ps
CPU time 87.48 seconds
Started Jul 17 05:52:40 PM PDT 24
Finished Jul 17 05:54:11 PM PDT 24
Peak memory 199872 kb
Host smart-b40788fa-64e3-42f6-b35e-91b3c370c45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974065113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1974065113
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.119052824
Short name T1105
Test name
Test status
Simulation time 112950654875 ps
CPU time 94.84 seconds
Started Jul 17 05:52:40 PM PDT 24
Finished Jul 17 05:54:18 PM PDT 24
Peak memory 199924 kb
Host smart-2aab68a0-3b81-47f8-aeb8-de1c312389e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119052824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.119052824
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_intr.726663381
Short name T408
Test name
Test status
Simulation time 179228346243 ps
CPU time 63.81 seconds
Started Jul 17 05:52:44 PM PDT 24
Finished Jul 17 05:53:49 PM PDT 24
Peak memory 198332 kb
Host smart-cc1a636c-62d5-4709-9f7d-fec8b379879d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726663381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.726663381
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2857727352
Short name T396
Test name
Test status
Simulation time 64074107000 ps
CPU time 475.56 seconds
Started Jul 17 05:52:56 PM PDT 24
Finished Jul 17 06:00:53 PM PDT 24
Peak memory 199896 kb
Host smart-3e35586b-9e90-4b57-8187-3b3fac5b6b12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857727352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2857727352
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.4049694327
Short name T592
Test name
Test status
Simulation time 4484309316 ps
CPU time 10.83 seconds
Started Jul 17 05:52:42 PM PDT 24
Finished Jul 17 05:52:55 PM PDT 24
Peak memory 199924 kb
Host smart-29b546c9-1152-49b9-903f-fac1b28d5edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049694327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.4049694327
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1705366891
Short name T390
Test name
Test status
Simulation time 72027004135 ps
CPU time 58.18 seconds
Started Jul 17 05:52:42 PM PDT 24
Finished Jul 17 05:53:43 PM PDT 24
Peak memory 199952 kb
Host smart-a9c10cdb-b422-489f-ac65-14e3173eeff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705366891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1705366891
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.114566817
Short name T806
Test name
Test status
Simulation time 17582310632 ps
CPU time 191.01 seconds
Started Jul 17 05:52:51 PM PDT 24
Finished Jul 17 05:56:03 PM PDT 24
Peak memory 199984 kb
Host smart-c43edf97-1d5f-43a5-9cef-d247dc7ccb71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114566817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.114566817
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.4213667957
Short name T1114
Test name
Test status
Simulation time 3677577731 ps
CPU time 27.63 seconds
Started Jul 17 05:52:35 PM PDT 24
Finished Jul 17 05:53:06 PM PDT 24
Peak memory 197996 kb
Host smart-8ae97a89-b4c3-445d-b990-71660e6abd0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213667957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.4213667957
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.227023974
Short name T971
Test name
Test status
Simulation time 11123545148 ps
CPU time 19.8 seconds
Started Jul 17 05:52:40 PM PDT 24
Finished Jul 17 05:53:04 PM PDT 24
Peak memory 199580 kb
Host smart-e0559334-ab18-41f2-b1ac-d763506bc337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227023974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.227023974
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.200218203
Short name T401
Test name
Test status
Simulation time 2828579862 ps
CPU time 1.83 seconds
Started Jul 17 05:52:40 PM PDT 24
Finished Jul 17 05:52:45 PM PDT 24
Peak memory 195920 kb
Host smart-6ef75c98-adca-4050-9871-8204d9cb592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200218203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.200218203
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3311406355
Short name T1039
Test name
Test status
Simulation time 757540958 ps
CPU time 1.63 seconds
Started Jul 17 05:52:33 PM PDT 24
Finished Jul 17 05:52:36 PM PDT 24
Peak memory 198496 kb
Host smart-0c64d283-82be-4046-b808-59802fc7fd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311406355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3311406355
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.4207240076
Short name T682
Test name
Test status
Simulation time 84054381111 ps
CPU time 104.58 seconds
Started Jul 17 05:52:53 PM PDT 24
Finished Jul 17 05:54:39 PM PDT 24
Peak memory 199896 kb
Host smart-c5fc66e8-1e2e-445b-8099-cbef63e05e37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207240076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.4207240076
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3201302169
Short name T58
Test name
Test status
Simulation time 116607303546 ps
CPU time 202.16 seconds
Started Jul 17 05:52:53 PM PDT 24
Finished Jul 17 05:56:17 PM PDT 24
Peak memory 216652 kb
Host smart-2c906155-98d6-40a3-aee3-6320aa6b0250
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201302169 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3201302169
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2059799087
Short name T1046
Test name
Test status
Simulation time 1728670817 ps
CPU time 1.9 seconds
Started Jul 17 05:59:02 PM PDT 24
Finished Jul 17 05:59:05 PM PDT 24
Peak memory 198672 kb
Host smart-11e4f3be-3d2f-477d-88c5-695b925b0394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059799087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2059799087
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1100477553
Short name T325
Test name
Test status
Simulation time 42735715333 ps
CPU time 64.19 seconds
Started Jul 17 05:52:37 PM PDT 24
Finished Jul 17 05:53:45 PM PDT 24
Peak memory 199972 kb
Host smart-7ad1bf34-0d99-4887-9e2a-476199983992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100477553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1100477553
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1697545839
Short name T668
Test name
Test status
Simulation time 43770587 ps
CPU time 0.56 seconds
Started Jul 17 05:52:52 PM PDT 24
Finished Jul 17 05:52:53 PM PDT 24
Peak memory 195304 kb
Host smart-b42d22b1-e5fe-478a-966d-1e26a31b4940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697545839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1697545839
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1932144938
Short name T162
Test name
Test status
Simulation time 150711180004 ps
CPU time 18.44 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:53:15 PM PDT 24
Peak memory 199904 kb
Host smart-715f5ebe-4bcf-4b7d-a63c-35acd0a0dc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932144938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1932144938
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3790231111
Short name T312
Test name
Test status
Simulation time 64142226528 ps
CPU time 117.17 seconds
Started Jul 17 05:52:57 PM PDT 24
Finished Jul 17 05:54:55 PM PDT 24
Peak memory 199928 kb
Host smart-a2423ed6-9e9c-4ce4-8c44-60b31c285c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790231111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3790231111
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1255439078
Short name T526
Test name
Test status
Simulation time 46399995258 ps
CPU time 23.43 seconds
Started Jul 17 05:52:56 PM PDT 24
Finished Jul 17 05:53:21 PM PDT 24
Peak memory 199984 kb
Host smart-bf8abc24-42da-42a5-befa-daf0ffa2c951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255439078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1255439078
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.593043837
Short name T111
Test name
Test status
Simulation time 39243659140 ps
CPU time 59.25 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:53:55 PM PDT 24
Peak memory 199936 kb
Host smart-6f918c39-2e0e-47cb-8c35-6129bbed7dbd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593043837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.593043837
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.653759710
Short name T1171
Test name
Test status
Simulation time 178167583789 ps
CPU time 97.99 seconds
Started Jul 17 05:52:55 PM PDT 24
Finished Jul 17 05:54:35 PM PDT 24
Peak memory 199964 kb
Host smart-891273c2-0b0e-4200-b8f6-4c84849d30f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=653759710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.653759710
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3755760867
Short name T1048
Test name
Test status
Simulation time 8236218418 ps
CPU time 8.82 seconds
Started Jul 17 05:52:55 PM PDT 24
Finished Jul 17 05:53:06 PM PDT 24
Peak memory 199772 kb
Host smart-48cf526a-ffc3-41ce-9003-86490d27bb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755760867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3755760867
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2617459144
Short name T868
Test name
Test status
Simulation time 17822145189 ps
CPU time 24.81 seconds
Started Jul 17 05:52:52 PM PDT 24
Finished Jul 17 05:53:18 PM PDT 24
Peak memory 200140 kb
Host smart-4fa635b1-6249-4ec1-bbd6-01763475beae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617459144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2617459144
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.4214656549
Short name T611
Test name
Test status
Simulation time 2983851643 ps
CPU time 44.04 seconds
Started Jul 17 05:52:53 PM PDT 24
Finished Jul 17 05:53:38 PM PDT 24
Peak memory 199844 kb
Host smart-ee29ff46-9f1d-442e-b5e3-247191ce6913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4214656549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.4214656549
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.789265694
Short name T574
Test name
Test status
Simulation time 2850549658 ps
CPU time 15.64 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:53:12 PM PDT 24
Peak memory 198396 kb
Host smart-9c7ad8a2-4693-4cee-be51-8f489829dd6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789265694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.789265694
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2073342621
Short name T837
Test name
Test status
Simulation time 26126213197 ps
CPU time 41.63 seconds
Started Jul 17 05:52:52 PM PDT 24
Finished Jul 17 05:53:34 PM PDT 24
Peak memory 199892 kb
Host smart-59a3f8a0-2f29-46ec-b03a-10a6bcb01f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073342621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2073342621
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3411561279
Short name T267
Test name
Test status
Simulation time 5956051812 ps
CPU time 10.4 seconds
Started Jul 17 05:52:56 PM PDT 24
Finished Jul 17 05:53:08 PM PDT 24
Peak memory 196376 kb
Host smart-c386e561-0cfb-47a4-b706-6910d84518d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411561279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3411561279
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3982012968
Short name T735
Test name
Test status
Simulation time 578869989 ps
CPU time 1.51 seconds
Started Jul 17 05:52:57 PM PDT 24
Finished Jul 17 05:53:00 PM PDT 24
Peak memory 198788 kb
Host smart-b95d2c9d-c470-4c23-8c6c-1a8e6d84c690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982012968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3982012968
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.436716504
Short name T284
Test name
Test status
Simulation time 150562965407 ps
CPU time 230.61 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:56:46 PM PDT 24
Peak memory 200012 kb
Host smart-2ff907be-196a-462e-9c82-eb53fe444215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436716504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.436716504
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3819833903
Short name T750
Test name
Test status
Simulation time 56176357248 ps
CPU time 372.32 seconds
Started Jul 17 05:52:53 PM PDT 24
Finished Jul 17 05:59:07 PM PDT 24
Peak memory 216400 kb
Host smart-3ae4808d-8316-49fd-aa60-bc6dc8d3d604
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819833903 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3819833903
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1725909320
Short name T14
Test name
Test status
Simulation time 550414525 ps
CPU time 1.69 seconds
Started Jul 17 05:52:56 PM PDT 24
Finished Jul 17 05:52:59 PM PDT 24
Peak memory 199712 kb
Host smart-901c3bfb-b23d-4b7d-9cb1-8e3f2f21c5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725909320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1725909320
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.4146189700
Short name T880
Test name
Test status
Simulation time 65836129142 ps
CPU time 25.72 seconds
Started Jul 17 05:52:53 PM PDT 24
Finished Jul 17 05:53:20 PM PDT 24
Peak memory 199940 kb
Host smart-15ef8da8-6146-4955-9e36-678260d1597d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146189700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.4146189700
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2051967874
Short name T889
Test name
Test status
Simulation time 13823150 ps
CPU time 0.55 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:52:56 PM PDT 24
Peak memory 195316 kb
Host smart-15979661-4bc7-4e4a-9b0d-fc3a9e754f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051967874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2051967874
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.814331984
Short name T125
Test name
Test status
Simulation time 85427262206 ps
CPU time 12.58 seconds
Started Jul 17 05:52:57 PM PDT 24
Finished Jul 17 05:53:11 PM PDT 24
Peak memory 199908 kb
Host smart-75b654bc-bc92-49a0-9cf6-39f10f71df44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814331984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.814331984
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2085819034
Short name T363
Test name
Test status
Simulation time 58533260073 ps
CPU time 27.86 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:53:24 PM PDT 24
Peak memory 199896 kb
Host smart-92eb8a77-4b22-4c08-9e06-afa6a9d5c037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085819034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2085819034
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1755573246
Short name T178
Test name
Test status
Simulation time 209225216162 ps
CPU time 89.57 seconds
Started Jul 17 05:52:56 PM PDT 24
Finished Jul 17 05:54:27 PM PDT 24
Peak memory 199816 kb
Host smart-0af25752-fc02-4be9-b28a-30ea6f118f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755573246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1755573246
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3822171946
Short name T320
Test name
Test status
Simulation time 406863110995 ps
CPU time 405.21 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:59:40 PM PDT 24
Peak memory 200116 kb
Host smart-53e2ff71-5495-45b6-b801-9e15d20463fd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822171946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3822171946
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2508634152
Short name T369
Test name
Test status
Simulation time 37787287827 ps
CPU time 249.51 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:57:06 PM PDT 24
Peak memory 199928 kb
Host smart-917b8621-fc16-4f6c-9d72-e69e2a4dba54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508634152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2508634152
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.427357677
Short name T961
Test name
Test status
Simulation time 5418562738 ps
CPU time 5.55 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:53:02 PM PDT 24
Peak memory 199844 kb
Host smart-043f7c5b-1b44-46d7-bd6d-59a9094a492e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427357677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.427357677
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3891437722
Short name T263
Test name
Test status
Simulation time 143531520813 ps
CPU time 278.79 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:57:35 PM PDT 24
Peak memory 208304 kb
Host smart-b0793f66-8a74-4b35-b69d-d54f110ee447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891437722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3891437722
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2660776315
Short name T486
Test name
Test status
Simulation time 4428340810 ps
CPU time 275.74 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:57:32 PM PDT 24
Peak memory 199976 kb
Host smart-82155687-a836-4a6e-9aeb-ee3a65401b5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660776315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2660776315
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.4294066237
Short name T1001
Test name
Test status
Simulation time 6080636559 ps
CPU time 56.76 seconds
Started Jul 17 05:52:53 PM PDT 24
Finished Jul 17 05:53:50 PM PDT 24
Peak memory 198200 kb
Host smart-c250f5fc-7c03-43bc-8b18-346706e47764
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294066237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.4294066237
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.903226343
Short name T148
Test name
Test status
Simulation time 35025706677 ps
CPU time 45.13 seconds
Started Jul 17 05:52:55 PM PDT 24
Finished Jul 17 05:53:42 PM PDT 24
Peak memory 199928 kb
Host smart-c96db431-e3ce-41be-a4b3-bf6cdeb35d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903226343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.903226343
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2972305742
Short name T817
Test name
Test status
Simulation time 4686441686 ps
CPU time 8.13 seconds
Started Jul 17 05:52:57 PM PDT 24
Finished Jul 17 05:53:06 PM PDT 24
Peak memory 196696 kb
Host smart-e5a53d4c-d870-4d17-a259-af575cf63376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972305742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2972305742
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.668725347
Short name T647
Test name
Test status
Simulation time 909666196 ps
CPU time 1.93 seconds
Started Jul 17 05:52:53 PM PDT 24
Finished Jul 17 05:52:56 PM PDT 24
Peak memory 198548 kb
Host smart-febdc8d4-ab86-4a69-8fe1-0386183bb79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668725347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.668725347
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.335775939
Short name T249
Test name
Test status
Simulation time 593309336997 ps
CPU time 180.81 seconds
Started Jul 17 05:52:53 PM PDT 24
Finished Jul 17 05:55:56 PM PDT 24
Peak memory 208364 kb
Host smart-1234bd35-b849-45e2-ab52-bf0e3fb5f6f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335775939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.335775939
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1829080888
Short name T243
Test name
Test status
Simulation time 190756736509 ps
CPU time 893.85 seconds
Started Jul 17 05:52:56 PM PDT 24
Finished Jul 17 06:07:52 PM PDT 24
Peak memory 230728 kb
Host smart-14bb8555-16ed-41f5-9f9b-cfd8c83fc8a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829080888 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1829080888
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3734880221
Short name T898
Test name
Test status
Simulation time 1370894599 ps
CPU time 3.03 seconds
Started Jul 17 05:52:55 PM PDT 24
Finished Jul 17 05:53:00 PM PDT 24
Peak memory 198320 kb
Host smart-0dd3e7aa-1c27-45b0-ad79-5313bcc470cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734880221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3734880221
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.542444810
Short name T798
Test name
Test status
Simulation time 118769170118 ps
CPU time 278.67 seconds
Started Jul 17 05:52:53 PM PDT 24
Finished Jul 17 05:57:33 PM PDT 24
Peak memory 199896 kb
Host smart-515b6fc5-d40a-4221-a5a8-81aef683bcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542444810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.542444810
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.821845726
Short name T21
Test name
Test status
Simulation time 42804687 ps
CPU time 0.57 seconds
Started Jul 17 05:53:05 PM PDT 24
Finished Jul 17 05:53:07 PM PDT 24
Peak memory 195524 kb
Host smart-b944e88e-2555-452f-94c7-ab18c1fd8b7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821845726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.821845726
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1614148230
Short name T583
Test name
Test status
Simulation time 64268792659 ps
CPU time 8.77 seconds
Started Jul 17 05:52:57 PM PDT 24
Finished Jul 17 05:53:07 PM PDT 24
Peak memory 199832 kb
Host smart-171cb635-9f1c-42bc-8378-71d909ada7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614148230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1614148230
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1203500793
Short name T659
Test name
Test status
Simulation time 123670714168 ps
CPU time 49.94 seconds
Started Jul 17 05:52:55 PM PDT 24
Finished Jul 17 05:53:47 PM PDT 24
Peak memory 199920 kb
Host smart-4e786ba2-b420-4d94-9ec8-8bb3704cf466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203500793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1203500793
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.4057966645
Short name T1036
Test name
Test status
Simulation time 16734686473 ps
CPU time 27.94 seconds
Started Jul 17 05:52:54 PM PDT 24
Finished Jul 17 05:53:23 PM PDT 24
Peak memory 199924 kb
Host smart-19ac5d5f-33b5-40a7-b378-54374adc8cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057966645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4057966645
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2864407379
Short name T418
Test name
Test status
Simulation time 32642910607 ps
CPU time 35.97 seconds
Started Jul 17 05:52:56 PM PDT 24
Finished Jul 17 05:53:33 PM PDT 24
Peak memory 199872 kb
Host smart-52b2c8a9-4721-443f-bc4a-84d481e792f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864407379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2864407379
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1574543291
Short name T1091
Test name
Test status
Simulation time 126997529739 ps
CPU time 591.82 seconds
Started Jul 17 05:53:04 PM PDT 24
Finished Jul 17 06:02:57 PM PDT 24
Peak memory 199964 kb
Host smart-1c295341-aaa7-41dd-9504-864b7ccfa610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574543291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1574543291
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2427790381
Short name T393
Test name
Test status
Simulation time 9538740584 ps
CPU time 17.74 seconds
Started Jul 17 05:52:53 PM PDT 24
Finished Jul 17 05:53:12 PM PDT 24
Peak memory 199940 kb
Host smart-c1976aee-7ca6-4cd3-9726-35341f8984cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427790381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2427790381
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3195748032
Short name T419
Test name
Test status
Simulation time 11135709205 ps
CPU time 14.3 seconds
Started Jul 17 05:52:56 PM PDT 24
Finished Jul 17 05:53:12 PM PDT 24
Peak memory 200044 kb
Host smart-28f229e3-3296-4e90-896d-55eced5c1eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195748032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3195748032
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.920537926
Short name T259
Test name
Test status
Simulation time 17156228789 ps
CPU time 812.33 seconds
Started Jul 17 05:53:11 PM PDT 24
Finished Jul 17 06:06:44 PM PDT 24
Peak memory 199820 kb
Host smart-e22d7958-4c2e-4a32-9c40-1296ab14a9b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920537926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.920537926
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2729436523
Short name T366
Test name
Test status
Simulation time 6950353560 ps
CPU time 16.29 seconds
Started Jul 17 05:52:55 PM PDT 24
Finished Jul 17 05:53:13 PM PDT 24
Peak memory 198936 kb
Host smart-ce3449d0-d91a-46a6-9eb3-927177d83eef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2729436523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2729436523
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3433568114
Short name T430
Test name
Test status
Simulation time 162981501681 ps
CPU time 372.48 seconds
Started Jul 17 05:52:57 PM PDT 24
Finished Jul 17 05:59:11 PM PDT 24
Peak memory 199792 kb
Host smart-1ac4ea9c-1e46-4be7-a75e-cd85ca9b2049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433568114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3433568114
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1084675343
Short name T472
Test name
Test status
Simulation time 2553199267 ps
CPU time 4.35 seconds
Started Jul 17 05:52:56 PM PDT 24
Finished Jul 17 05:53:02 PM PDT 24
Peak memory 196444 kb
Host smart-4a7ccb90-f875-4e24-9a23-b8bfac196fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084675343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1084675343
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3826918008
Short name T618
Test name
Test status
Simulation time 465218064 ps
CPU time 1.25 seconds
Started Jul 17 05:52:53 PM PDT 24
Finished Jul 17 05:52:56 PM PDT 24
Peak memory 198960 kb
Host smart-4840be72-98e6-4091-abf9-12666f3b9196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826918008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3826918008
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3134151789
Short name T818
Test name
Test status
Simulation time 53944829480 ps
CPU time 102.18 seconds
Started Jul 17 05:53:05 PM PDT 24
Finished Jul 17 05:54:48 PM PDT 24
Peak memory 199872 kb
Host smart-1d9c3a41-642c-4585-a704-0fce6673be72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134151789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3134151789
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.834025430
Short name T1082
Test name
Test status
Simulation time 1893915155 ps
CPU time 1.85 seconds
Started Jul 17 05:52:58 PM PDT 24
Finished Jul 17 05:53:01 PM PDT 24
Peak memory 198372 kb
Host smart-ed95081b-6384-4d38-81b2-9eb648403168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834025430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.834025430
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2128934879
Short name T501
Test name
Test status
Simulation time 99355216387 ps
CPU time 46.66 seconds
Started Jul 17 05:52:49 PM PDT 24
Finished Jul 17 05:53:37 PM PDT 24
Peak memory 200184 kb
Host smart-cdfa6a5a-e283-4d21-9f97-7287b7ffdc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128934879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2128934879
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3924242317
Short name T804
Test name
Test status
Simulation time 13211046 ps
CPU time 0.56 seconds
Started Jul 17 05:53:06 PM PDT 24
Finished Jul 17 05:53:08 PM PDT 24
Peak memory 195548 kb
Host smart-07fe5822-7d05-4a4f-a925-da0c39fd2d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924242317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3924242317
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3809445422
Short name T1174
Test name
Test status
Simulation time 76135655771 ps
CPU time 17.13 seconds
Started Jul 17 05:53:08 PM PDT 24
Finished Jul 17 05:53:26 PM PDT 24
Peak memory 199972 kb
Host smart-6249fad1-451e-41ab-8601-09f0b95f72aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809445422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3809445422
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1913045569
Short name T796
Test name
Test status
Simulation time 127233150858 ps
CPU time 40.75 seconds
Started Jul 17 05:53:07 PM PDT 24
Finished Jul 17 05:53:49 PM PDT 24
Peak memory 199848 kb
Host smart-e31afb26-0131-4942-bace-07e11816f271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913045569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1913045569
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_intr.3708698774
Short name T1167
Test name
Test status
Simulation time 42430373146 ps
CPU time 70.42 seconds
Started Jul 17 05:53:09 PM PDT 24
Finished Jul 17 05:54:20 PM PDT 24
Peak memory 199948 kb
Host smart-543d8ec4-102c-4e6a-b5c9-60fafc26252c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708698774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3708698774
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.280665091
Short name T983
Test name
Test status
Simulation time 58368148862 ps
CPU time 110.56 seconds
Started Jul 17 05:53:07 PM PDT 24
Finished Jul 17 05:54:59 PM PDT 24
Peak memory 199920 kb
Host smart-77a35480-3a0c-40df-a3ce-77ba8289f9a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280665091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.280665091
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3677509487
Short name T358
Test name
Test status
Simulation time 7178489201 ps
CPU time 4.26 seconds
Started Jul 17 05:53:06 PM PDT 24
Finished Jul 17 05:53:11 PM PDT 24
Peak memory 198100 kb
Host smart-9d8ed9da-ac94-463f-8c8a-fdda3bf7123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677509487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3677509487
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.505303094
Short name T444
Test name
Test status
Simulation time 19739105979 ps
CPU time 29.68 seconds
Started Jul 17 05:53:05 PM PDT 24
Finished Jul 17 05:53:36 PM PDT 24
Peak memory 198192 kb
Host smart-1ca85607-382b-4527-9766-221274d0e7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505303094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.505303094
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.32643143
Short name T70
Test name
Test status
Simulation time 11840669739 ps
CPU time 169.24 seconds
Started Jul 17 05:53:06 PM PDT 24
Finished Jul 17 05:55:57 PM PDT 24
Peak memory 199884 kb
Host smart-fbf0f593-55e2-448b-8d75-6a3af8d29f3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=32643143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.32643143
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2541578170
Short name T533
Test name
Test status
Simulation time 5835847266 ps
CPU time 52.66 seconds
Started Jul 17 05:53:09 PM PDT 24
Finished Jul 17 05:54:03 PM PDT 24
Peak memory 197292 kb
Host smart-cfe8ec86-d2aa-4da2-82d9-fe2b9efae329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2541578170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2541578170
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.4203234635
Short name T564
Test name
Test status
Simulation time 23255712492 ps
CPU time 28 seconds
Started Jul 17 05:53:08 PM PDT 24
Finished Jul 17 05:53:37 PM PDT 24
Peak memory 199944 kb
Host smart-2b400edd-f4f0-417e-92d9-6b7873eded31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203234635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.4203234635
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1331850820
Short name T468
Test name
Test status
Simulation time 1595470113 ps
CPU time 2.85 seconds
Started Jul 17 05:53:10 PM PDT 24
Finished Jul 17 05:53:14 PM PDT 24
Peak memory 195364 kb
Host smart-fe98986d-5d66-4aeb-9e4b-c1901f6f0564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331850820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1331850820
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2192488178
Short name T963
Test name
Test status
Simulation time 283971881 ps
CPU time 1.44 seconds
Started Jul 17 05:53:11 PM PDT 24
Finished Jul 17 05:53:13 PM PDT 24
Peak memory 198364 kb
Host smart-5c190cc8-d77f-46e8-b35e-35e37dbec82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192488178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2192488178
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1259452126
Short name T943
Test name
Test status
Simulation time 908679580485 ps
CPU time 484.32 seconds
Started Jul 17 05:53:09 PM PDT 24
Finished Jul 17 06:01:15 PM PDT 24
Peak memory 216172 kb
Host smart-68892cbd-335a-4e4c-ac00-d559540e357d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259452126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1259452126
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.448287866
Short name T59
Test name
Test status
Simulation time 70175220230 ps
CPU time 805.88 seconds
Started Jul 17 05:53:05 PM PDT 24
Finished Jul 17 06:06:32 PM PDT 24
Peak memory 216432 kb
Host smart-55362e1e-65f9-4b45-90fe-54b5aeb3205a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448287866 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.448287866
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3829768802
Short name T36
Test name
Test status
Simulation time 8128793436 ps
CPU time 1.62 seconds
Started Jul 17 05:53:04 PM PDT 24
Finished Jul 17 05:53:07 PM PDT 24
Peak memory 199948 kb
Host smart-c0bcd83c-a140-4827-a167-6388aad58200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829768802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3829768802
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3460479796
Short name T680
Test name
Test status
Simulation time 74284003932 ps
CPU time 113.63 seconds
Started Jul 17 05:53:10 PM PDT 24
Finished Jul 17 05:55:05 PM PDT 24
Peak memory 199872 kb
Host smart-5d27ba50-f173-48b2-9309-bf6a057f5bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460479796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3460479796
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2214015220
Short name T19
Test name
Test status
Simulation time 21283999 ps
CPU time 0.56 seconds
Started Jul 17 05:53:07 PM PDT 24
Finished Jul 17 05:53:09 PM PDT 24
Peak memory 194748 kb
Host smart-bf596320-de0f-4852-9e37-d659c1661a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214015220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2214015220
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.693959553
Short name T329
Test name
Test status
Simulation time 39503886242 ps
CPU time 42.56 seconds
Started Jul 17 05:53:08 PM PDT 24
Finished Jul 17 05:53:52 PM PDT 24
Peak memory 199988 kb
Host smart-a3612f38-a5be-4309-9b3b-733ef02de69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693959553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.693959553
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.654223169
Short name T846
Test name
Test status
Simulation time 17796634382 ps
CPU time 29.53 seconds
Started Jul 17 05:53:06 PM PDT 24
Finished Jul 17 05:53:37 PM PDT 24
Peak memory 199728 kb
Host smart-dd46ae74-1cb6-40c7-a8e8-c1ce1637d192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654223169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.654223169
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1624966285
Short name T1095
Test name
Test status
Simulation time 65797426533 ps
CPU time 62.56 seconds
Started Jul 17 05:53:03 PM PDT 24
Finished Jul 17 05:54:07 PM PDT 24
Peak memory 199868 kb
Host smart-f37a6f83-52fb-4bc6-99ed-83e8ac01f5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624966285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1624966285
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1068263906
Short name T507
Test name
Test status
Simulation time 16339497793 ps
CPU time 14.05 seconds
Started Jul 17 05:53:09 PM PDT 24
Finished Jul 17 05:53:25 PM PDT 24
Peak memory 199896 kb
Host smart-9390ff7c-f97e-417b-8de4-ac353218289b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068263906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1068263906
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2630396393
Short name T962
Test name
Test status
Simulation time 51350762996 ps
CPU time 169.68 seconds
Started Jul 17 05:53:06 PM PDT 24
Finished Jul 17 05:55:57 PM PDT 24
Peak memory 199964 kb
Host smart-953b0fd7-1ae1-4c1c-83ff-a33cb65a80ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630396393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2630396393
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.760055499
Short name T842
Test name
Test status
Simulation time 2603747630 ps
CPU time 5.07 seconds
Started Jul 17 05:53:06 PM PDT 24
Finished Jul 17 05:53:12 PM PDT 24
Peak memory 198636 kb
Host smart-f10b0993-1448-4545-9145-5f70e69e83a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760055499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.760055499
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1912503065
Short name T643
Test name
Test status
Simulation time 85619389173 ps
CPU time 49.46 seconds
Started Jul 17 05:53:09 PM PDT 24
Finished Jul 17 05:54:00 PM PDT 24
Peak memory 207324 kb
Host smart-42a5879e-8006-4e7b-8d73-f7cc3d444f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912503065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1912503065
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1754695296
Short name T903
Test name
Test status
Simulation time 15831756293 ps
CPU time 120.74 seconds
Started Jul 17 05:53:08 PM PDT 24
Finished Jul 17 05:55:10 PM PDT 24
Peak memory 199900 kb
Host smart-b8395749-ae13-42fc-ac37-e434114ee9d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1754695296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1754695296
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2635525878
Short name T31
Test name
Test status
Simulation time 3069360452 ps
CPU time 4.39 seconds
Started Jul 17 05:53:05 PM PDT 24
Finished Jul 17 05:53:10 PM PDT 24
Peak memory 198964 kb
Host smart-141756ce-2fab-455a-8594-e4ab6a2bf5ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2635525878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2635525878
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1457744703
Short name T959
Test name
Test status
Simulation time 151642251226 ps
CPU time 42.62 seconds
Started Jul 17 05:53:07 PM PDT 24
Finished Jul 17 05:53:51 PM PDT 24
Peak memory 199980 kb
Host smart-62043199-ca8c-4cef-a2d5-502a461e3bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457744703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1457744703
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1254257151
Short name T1029
Test name
Test status
Simulation time 1809386155 ps
CPU time 1.22 seconds
Started Jul 17 05:53:09 PM PDT 24
Finished Jul 17 05:53:11 PM PDT 24
Peak memory 195336 kb
Host smart-2556ca5e-2efd-4ada-98c1-e1961d8f4474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254257151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1254257151
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2004854585
Short name T780
Test name
Test status
Simulation time 511631317 ps
CPU time 2.45 seconds
Started Jul 17 05:53:07 PM PDT 24
Finished Jul 17 05:53:11 PM PDT 24
Peak memory 199576 kb
Host smart-49cafda5-efe6-4be3-bb62-256f6a208fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004854585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2004854585
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2139686838
Short name T437
Test name
Test status
Simulation time 166666579312 ps
CPU time 257.57 seconds
Started Jul 17 05:53:04 PM PDT 24
Finished Jul 17 05:57:23 PM PDT 24
Peak memory 199948 kb
Host smart-a32f03ea-8921-4c00-904a-423d33c43168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139686838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2139686838
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1393714157
Short name T48
Test name
Test status
Simulation time 5949509986 ps
CPU time 15.31 seconds
Started Jul 17 05:53:09 PM PDT 24
Finished Jul 17 05:53:26 PM PDT 24
Peak memory 199840 kb
Host smart-a8809687-606f-4c3c-adb4-571d9c77845b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393714157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1393714157
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.366713209
Short name T1141
Test name
Test status
Simulation time 117228612053 ps
CPU time 44.65 seconds
Started Jul 17 05:53:05 PM PDT 24
Finished Jul 17 05:53:51 PM PDT 24
Peak memory 199964 kb
Host smart-8df2099b-0e8e-4ade-a416-c9842577f4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366713209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.366713209
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3100252339
Short name T33
Test name
Test status
Simulation time 13843998 ps
CPU time 0.53 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:50:50 PM PDT 24
Peak memory 194264 kb
Host smart-08b3afdd-5cbf-4bae-a410-77ce29186c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100252339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3100252339
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3477669910
Short name T894
Test name
Test status
Simulation time 69411750281 ps
CPU time 105.36 seconds
Started Jul 17 05:50:46 PM PDT 24
Finished Jul 17 05:52:32 PM PDT 24
Peak memory 199916 kb
Host smart-c9449980-480c-42ae-81cf-d77a26b2a7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477669910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3477669910
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1298827242
Short name T302
Test name
Test status
Simulation time 93233937881 ps
CPU time 165.78 seconds
Started Jul 17 05:50:33 PM PDT 24
Finished Jul 17 05:53:19 PM PDT 24
Peak memory 199920 kb
Host smart-f4c832f5-06b7-4615-9428-7b8994e90f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298827242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1298827242
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2607937945
Short name T300
Test name
Test status
Simulation time 85637080202 ps
CPU time 35.75 seconds
Started Jul 17 05:50:33 PM PDT 24
Finished Jul 17 05:51:11 PM PDT 24
Peak memory 199964 kb
Host smart-2f9888f4-8ec8-4169-90a2-b015a5a3778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607937945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2607937945
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1109883488
Short name T280
Test name
Test status
Simulation time 21716298179 ps
CPU time 10.18 seconds
Started Jul 17 05:50:33 PM PDT 24
Finished Jul 17 05:50:44 PM PDT 24
Peak memory 199480 kb
Host smart-0be5939d-4406-4281-a3ee-26ae8555c36c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109883488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1109883488
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3589844566
Short name T398
Test name
Test status
Simulation time 103732304599 ps
CPU time 887.93 seconds
Started Jul 17 05:50:39 PM PDT 24
Finished Jul 17 06:05:29 PM PDT 24
Peak memory 200068 kb
Host smart-0b43176a-d145-4332-a9ae-beab22c8a84f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589844566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3589844566
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2868106043
Short name T340
Test name
Test status
Simulation time 6902234300 ps
CPU time 5.12 seconds
Started Jul 17 05:50:40 PM PDT 24
Finished Jul 17 05:50:47 PM PDT 24
Peak memory 199724 kb
Host smart-734a7ecd-f54f-4806-8aad-364132be6dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868106043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2868106043
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3065109121
Short name T772
Test name
Test status
Simulation time 20976784922 ps
CPU time 29.62 seconds
Started Jul 17 05:50:41 PM PDT 24
Finished Jul 17 05:51:12 PM PDT 24
Peak memory 199088 kb
Host smart-838e08e9-beb7-4ff1-9b76-8076ea6f88d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065109121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3065109121
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.4245689878
Short name T40
Test name
Test status
Simulation time 21114470954 ps
CPU time 422.21 seconds
Started Jul 17 05:50:34 PM PDT 24
Finished Jul 17 05:57:39 PM PDT 24
Peak memory 199904 kb
Host smart-48aada21-ad55-45fa-9161-7ee707b99118
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4245689878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.4245689878
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.280827884
Short name T1162
Test name
Test status
Simulation time 4378651034 ps
CPU time 37.48 seconds
Started Jul 17 05:50:46 PM PDT 24
Finished Jul 17 05:51:25 PM PDT 24
Peak memory 198040 kb
Host smart-8bfef0b7-f586-4bc4-bcbf-997953caacad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280827884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.280827884
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.6093602
Short name T277
Test name
Test status
Simulation time 114813267256 ps
CPU time 82.68 seconds
Started Jul 17 05:50:36 PM PDT 24
Finished Jul 17 05:52:00 PM PDT 24
Peak memory 199904 kb
Host smart-6002bc05-f118-447e-96c5-fcdd8995abe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6093602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.6093602
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3125639512
Short name T657
Test name
Test status
Simulation time 1494259916 ps
CPU time 3.02 seconds
Started Jul 17 05:50:35 PM PDT 24
Finished Jul 17 05:50:40 PM PDT 24
Peak memory 195552 kb
Host smart-53965bac-fdc3-4816-a349-184fce6e00cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125639512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3125639512
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.868500153
Short name T96
Test name
Test status
Simulation time 90747356 ps
CPU time 0.85 seconds
Started Jul 17 05:50:37 PM PDT 24
Finished Jul 17 05:50:40 PM PDT 24
Peak memory 218256 kb
Host smart-77ef0a47-2115-4754-891b-044ab0d5d7bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868500153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.868500153
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.770376192
Short name T835
Test name
Test status
Simulation time 653065517 ps
CPU time 2.69 seconds
Started Jul 17 05:50:36 PM PDT 24
Finished Jul 17 05:50:40 PM PDT 24
Peak memory 198768 kb
Host smart-ea5b2ea9-e8d7-4733-9dbc-968ef7b3b1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770376192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.770376192
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.101046717
Short name T484
Test name
Test status
Simulation time 314028444843 ps
CPU time 104.5 seconds
Started Jul 17 05:50:33 PM PDT 24
Finished Jul 17 05:52:18 PM PDT 24
Peak memory 199964 kb
Host smart-ed93e20a-672c-4df8-bd59-c23bd19000a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101046717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.101046717
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2939498169
Short name T114
Test name
Test status
Simulation time 43671486631 ps
CPU time 949.51 seconds
Started Jul 17 05:50:35 PM PDT 24
Finished Jul 17 06:06:27 PM PDT 24
Peak memory 224792 kb
Host smart-99bb111a-5a8e-4929-9ba6-45b671ff799d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939498169 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2939498169
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1745986432
Short name T917
Test name
Test status
Simulation time 7144142370 ps
CPU time 5.25 seconds
Started Jul 17 05:50:46 PM PDT 24
Finished Jul 17 05:50:52 PM PDT 24
Peak memory 199280 kb
Host smart-0a8f127f-1200-442f-903c-fc1b08888131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745986432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1745986432
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3128711476
Short name T887
Test name
Test status
Simulation time 72809819093 ps
CPU time 149.67 seconds
Started Jul 17 05:50:35 PM PDT 24
Finished Jul 17 05:53:06 PM PDT 24
Peak memory 199300 kb
Host smart-70703a38-3d67-42ee-b554-6c1a3de9fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128711476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3128711476
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2967183963
Short name T978
Test name
Test status
Simulation time 25173909 ps
CPU time 0.56 seconds
Started Jul 17 05:53:06 PM PDT 24
Finished Jul 17 05:53:08 PM PDT 24
Peak memory 195296 kb
Host smart-453c01f3-f745-4a1d-aec1-5fe509d234ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967183963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2967183963
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.500855407
Short name T432
Test name
Test status
Simulation time 36078320268 ps
CPU time 54.39 seconds
Started Jul 17 05:53:07 PM PDT 24
Finished Jul 17 05:54:03 PM PDT 24
Peak memory 199852 kb
Host smart-0f98d847-149f-4361-9e17-08c010658a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500855407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.500855407
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.931177220
Short name T878
Test name
Test status
Simulation time 70023299558 ps
CPU time 104.19 seconds
Started Jul 17 05:53:09 PM PDT 24
Finished Jul 17 05:54:55 PM PDT 24
Peak memory 199908 kb
Host smart-f177ec55-f301-44a3-95ee-08dc570c5e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931177220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.931177220
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_intr.3204984083
Short name T496
Test name
Test status
Simulation time 13685403630 ps
CPU time 17.97 seconds
Started Jul 17 05:53:11 PM PDT 24
Finished Jul 17 05:53:29 PM PDT 24
Peak memory 196500 kb
Host smart-187735c4-2237-4fbf-8b4a-91fe90a29e53
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204984083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3204984083
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3708276426
Short name T452
Test name
Test status
Simulation time 89258747102 ps
CPU time 681.49 seconds
Started Jul 17 05:53:07 PM PDT 24
Finished Jul 17 06:04:30 PM PDT 24
Peak memory 199908 kb
Host smart-8cc1039e-dbe4-483b-8583-277770d8819c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3708276426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3708276426
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3862790096
Short name T819
Test name
Test status
Simulation time 7509739197 ps
CPU time 12.34 seconds
Started Jul 17 05:53:09 PM PDT 24
Finished Jul 17 05:53:23 PM PDT 24
Peak memory 200064 kb
Host smart-38db5b94-cf26-4f6c-b038-d4e36a3b85fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862790096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3862790096
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.3971817432
Short name T683
Test name
Test status
Simulation time 49704126772 ps
CPU time 76.24 seconds
Started Jul 17 05:53:12 PM PDT 24
Finished Jul 17 05:54:29 PM PDT 24
Peak memory 200016 kb
Host smart-8af027de-3eba-4212-9783-5086e3de7201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971817432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3971817432
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.593622738
Short name T1157
Test name
Test status
Simulation time 15157044520 ps
CPU time 750.84 seconds
Started Jul 17 05:53:11 PM PDT 24
Finished Jul 17 06:05:43 PM PDT 24
Peak memory 199828 kb
Host smart-6fdb63d9-7f09-404a-8ddd-ee5d512e7f31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593622738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.593622738
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3180780875
Short name T10
Test name
Test status
Simulation time 7210441612 ps
CPU time 29.46 seconds
Started Jul 17 05:53:08 PM PDT 24
Finished Jul 17 05:53:38 PM PDT 24
Peak memory 199936 kb
Host smart-7fbbeb3d-1dca-42a7-a5b2-df48e76844aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3180780875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3180780875
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.716165388
Short name T1055
Test name
Test status
Simulation time 85529500413 ps
CPU time 17.67 seconds
Started Jul 17 05:53:12 PM PDT 24
Finished Jul 17 05:53:30 PM PDT 24
Peak memory 199844 kb
Host smart-72cd1864-ce42-48fe-b506-4dcb7e3241e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716165388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.716165388
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.238139618
Short name T913
Test name
Test status
Simulation time 33941463391 ps
CPU time 13.76 seconds
Started Jul 17 05:53:11 PM PDT 24
Finished Jul 17 05:53:26 PM PDT 24
Peak memory 196144 kb
Host smart-2374d71f-ecc0-4112-b1aa-4e4cdf927f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238139618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.238139618
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2856573803
Short name T1049
Test name
Test status
Simulation time 97088316 ps
CPU time 0.84 seconds
Started Jul 17 05:53:04 PM PDT 24
Finished Jul 17 05:53:06 PM PDT 24
Peak memory 198128 kb
Host smart-dc0aa02a-e608-4ed9-9cbb-a81f58098ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856573803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2856573803
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.572249343
Short name T132
Test name
Test status
Simulation time 223473829397 ps
CPU time 181.47 seconds
Started Jul 17 05:53:09 PM PDT 24
Finished Jul 17 05:56:12 PM PDT 24
Peak memory 200064 kb
Host smart-5c16d5f4-1298-4118-b25c-17e0366ba2d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572249343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.572249343
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3134740654
Short name T76
Test name
Test status
Simulation time 63420265686 ps
CPU time 560.53 seconds
Started Jul 17 05:53:08 PM PDT 24
Finished Jul 17 06:02:30 PM PDT 24
Peak memory 216504 kb
Host smart-4ad82acd-aa51-48cb-bfc4-5dcc37c26d0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134740654 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3134740654
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.587607631
Short name T766
Test name
Test status
Simulation time 6305206574 ps
CPU time 17.36 seconds
Started Jul 17 05:53:09 PM PDT 24
Finished Jul 17 05:53:28 PM PDT 24
Peak memory 200004 kb
Host smart-2752b312-eb12-43d9-af77-8e332318e365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587607631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.587607631
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1049131206
Short name T863
Test name
Test status
Simulation time 86970330764 ps
CPU time 38.36 seconds
Started Jul 17 05:53:08 PM PDT 24
Finished Jul 17 05:53:47 PM PDT 24
Peak memory 199960 kb
Host smart-0d120610-b549-4494-b9d4-7cd82096ca38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049131206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1049131206
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2571076454
Short name T966
Test name
Test status
Simulation time 17426429 ps
CPU time 0.54 seconds
Started Jul 17 05:53:13 PM PDT 24
Finished Jul 17 05:53:14 PM PDT 24
Peak memory 194964 kb
Host smart-4cd77655-d2db-4607-9ef4-ccaebdf1100c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571076454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2571076454
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.872673966
Short name T1023
Test name
Test status
Simulation time 309354709895 ps
CPU time 31.63 seconds
Started Jul 17 05:53:17 PM PDT 24
Finished Jul 17 05:53:50 PM PDT 24
Peak memory 199928 kb
Host smart-ce5676e7-5640-445a-a688-ab1423fac1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872673966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.872673966
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.60435445
Short name T500
Test name
Test status
Simulation time 53147877418 ps
CPU time 50.29 seconds
Started Jul 17 05:53:17 PM PDT 24
Finished Jul 17 05:54:09 PM PDT 24
Peak memory 199952 kb
Host smart-eae58719-9d98-4f5c-b891-7ae00fec1f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60435445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.60435445
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3449763007
Short name T316
Test name
Test status
Simulation time 39633037264 ps
CPU time 32.91 seconds
Started Jul 17 05:53:22 PM PDT 24
Finished Jul 17 05:53:55 PM PDT 24
Peak memory 199968 kb
Host smart-c52cd1f5-fe0c-4fa6-a932-691e1ef86d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449763007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3449763007
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1138843852
Short name T1057
Test name
Test status
Simulation time 104542832852 ps
CPU time 99.7 seconds
Started Jul 17 05:53:20 PM PDT 24
Finished Jul 17 05:55:01 PM PDT 24
Peak memory 199964 kb
Host smart-4a630318-03b9-4133-9383-3329ffe92df6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138843852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1138843852
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1231578539
Short name T511
Test name
Test status
Simulation time 150743729853 ps
CPU time 1087.83 seconds
Started Jul 17 05:53:17 PM PDT 24
Finished Jul 17 06:11:26 PM PDT 24
Peak memory 199960 kb
Host smart-e9de2773-1253-426e-bc8b-42dc1c179798
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231578539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1231578539
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1003035046
Short name T1050
Test name
Test status
Simulation time 979550236 ps
CPU time 1.42 seconds
Started Jul 17 05:53:19 PM PDT 24
Finished Jul 17 05:53:21 PM PDT 24
Peak memory 196120 kb
Host smart-075a285a-b221-4f73-a59b-7382f24cdeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003035046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1003035046
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.970319211
Short name T795
Test name
Test status
Simulation time 153576041794 ps
CPU time 212.25 seconds
Started Jul 17 05:53:18 PM PDT 24
Finished Jul 17 05:56:52 PM PDT 24
Peak memory 200136 kb
Host smart-7f831ffd-0021-413b-af4d-fc25b76f4f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970319211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.970319211
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1390806781
Short name T1013
Test name
Test status
Simulation time 5313786926 ps
CPU time 90.31 seconds
Started Jul 17 05:53:18 PM PDT 24
Finished Jul 17 05:54:50 PM PDT 24
Peak memory 199848 kb
Host smart-16783b4c-4d54-4c90-9751-007e70e7e2e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390806781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1390806781
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1339449101
Short name T376
Test name
Test status
Simulation time 2705690453 ps
CPU time 14.92 seconds
Started Jul 17 05:53:16 PM PDT 24
Finished Jul 17 05:53:32 PM PDT 24
Peak memory 198344 kb
Host smart-ebd57592-6a1d-4c4e-913d-fa4f1aa66916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1339449101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1339449101
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.761868477
Short name T1038
Test name
Test status
Simulation time 59144712642 ps
CPU time 36.62 seconds
Started Jul 17 05:53:18 PM PDT 24
Finished Jul 17 05:53:56 PM PDT 24
Peak memory 199896 kb
Host smart-93c758fc-24bc-45aa-ab18-4b2e156ff72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761868477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.761868477
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.892112943
Short name T853
Test name
Test status
Simulation time 5219476204 ps
CPU time 8.53 seconds
Started Jul 17 05:53:17 PM PDT 24
Finished Jul 17 05:53:27 PM PDT 24
Peak memory 196060 kb
Host smart-7c082c03-f7c7-4006-a570-200c0cd20c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892112943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.892112943
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3536885736
Short name T699
Test name
Test status
Simulation time 5911825690 ps
CPU time 9.83 seconds
Started Jul 17 05:53:18 PM PDT 24
Finished Jul 17 05:53:29 PM PDT 24
Peak memory 199964 kb
Host smart-82a27107-7ba6-49af-a74d-71ff95aaa2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536885736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3536885736
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2449161598
Short name T1061
Test name
Test status
Simulation time 132149238049 ps
CPU time 450.46 seconds
Started Jul 17 05:53:24 PM PDT 24
Finished Jul 17 06:00:55 PM PDT 24
Peak memory 216420 kb
Host smart-381e01ef-b790-4a48-8d07-129026428b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449161598 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2449161598
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1896599730
Short name T968
Test name
Test status
Simulation time 16715539445 ps
CPU time 15.17 seconds
Started Jul 17 05:53:20 PM PDT 24
Finished Jul 17 05:53:36 PM PDT 24
Peak memory 199876 kb
Host smart-512927be-f3d6-4068-b976-b99cc5a98c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896599730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1896599730
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1043894982
Short name T934
Test name
Test status
Simulation time 66432252560 ps
CPU time 148.58 seconds
Started Jul 17 05:53:17 PM PDT 24
Finished Jul 17 05:55:47 PM PDT 24
Peak memory 199972 kb
Host smart-29419d43-a6ec-4689-bc4f-a5b12bad816e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043894982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1043894982
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1512581444
Short name T1169
Test name
Test status
Simulation time 43819894 ps
CPU time 0.6 seconds
Started Jul 17 05:53:18 PM PDT 24
Finished Jul 17 05:53:20 PM PDT 24
Peak memory 194960 kb
Host smart-a4f28904-a5fc-4f65-937e-e8747f897af9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512581444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1512581444
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2898074557
Short name T1128
Test name
Test status
Simulation time 100001093101 ps
CPU time 39.02 seconds
Started Jul 17 05:53:20 PM PDT 24
Finished Jul 17 05:54:00 PM PDT 24
Peak memory 199860 kb
Host smart-925d8d44-6953-409e-9166-20b5d84b1f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898074557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2898074557
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1402704690
Short name T482
Test name
Test status
Simulation time 18525142609 ps
CPU time 27.83 seconds
Started Jul 17 05:53:23 PM PDT 24
Finished Jul 17 05:53:51 PM PDT 24
Peak memory 199180 kb
Host smart-9ff25ab0-8f08-4f66-a3b3-53abc045a5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402704690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1402704690
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_intr.3948601201
Short name T1083
Test name
Test status
Simulation time 52476812081 ps
CPU time 21.07 seconds
Started Jul 17 05:53:20 PM PDT 24
Finished Jul 17 05:53:42 PM PDT 24
Peak memory 199320 kb
Host smart-187b1290-6e8f-4138-907a-69a8759008d5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948601201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3948601201
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2804517630
Short name T920
Test name
Test status
Simulation time 164493743607 ps
CPU time 372.98 seconds
Started Jul 17 05:53:19 PM PDT 24
Finished Jul 17 05:59:34 PM PDT 24
Peak memory 199904 kb
Host smart-1f9afa19-d350-49b1-a59a-d68e94ff19f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804517630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2804517630
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1361852066
Short name T566
Test name
Test status
Simulation time 6683023199 ps
CPU time 12.51 seconds
Started Jul 17 05:53:17 PM PDT 24
Finished Jul 17 05:53:31 PM PDT 24
Peak memory 199896 kb
Host smart-3550a7fe-02c3-4c0f-9d17-70d0c236e8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361852066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1361852066
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3733593540
Short name T1006
Test name
Test status
Simulation time 107622258848 ps
CPU time 50.66 seconds
Started Jul 17 05:53:16 PM PDT 24
Finished Jul 17 05:54:08 PM PDT 24
Peak memory 198964 kb
Host smart-e47d47a3-ee8e-40d2-b645-7b41ab4aa9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733593540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3733593540
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2114809626
Short name T756
Test name
Test status
Simulation time 14785415560 ps
CPU time 426.71 seconds
Started Jul 17 05:53:17 PM PDT 24
Finished Jul 17 06:00:25 PM PDT 24
Peak memory 199916 kb
Host smart-3f56231b-0788-4c24-b4a1-c9bcad2a290c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2114809626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2114809626
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.16069245
Short name T872
Test name
Test status
Simulation time 7081716967 ps
CPU time 4.11 seconds
Started Jul 17 05:53:16 PM PDT 24
Finished Jul 17 05:53:22 PM PDT 24
Peak memory 198708 kb
Host smart-91526377-4f21-45d2-a99d-c3556162bcf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16069245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.16069245
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2923943302
Short name T632
Test name
Test status
Simulation time 147059395470 ps
CPU time 96.05 seconds
Started Jul 17 05:53:18 PM PDT 24
Finished Jul 17 05:54:55 PM PDT 24
Peak memory 199976 kb
Host smart-4ce438ad-cea3-4205-b130-6d4bdb59cd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923943302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2923943302
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4089062214
Short name T541
Test name
Test status
Simulation time 40664742089 ps
CPU time 5.81 seconds
Started Jul 17 05:53:17 PM PDT 24
Finished Jul 17 05:53:25 PM PDT 24
Peak memory 196412 kb
Host smart-85fe5850-3b45-4483-b6fc-780e0877a702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089062214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4089062214
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.843902494
Short name T985
Test name
Test status
Simulation time 5991447553 ps
CPU time 11.47 seconds
Started Jul 17 05:53:18 PM PDT 24
Finished Jul 17 05:53:31 PM PDT 24
Peak memory 199668 kb
Host smart-1d15627a-25db-4001-adf7-4ea206718300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843902494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.843902494
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1026782203
Short name T723
Test name
Test status
Simulation time 282219509551 ps
CPU time 231.13 seconds
Started Jul 17 05:53:20 PM PDT 24
Finished Jul 17 05:57:12 PM PDT 24
Peak memory 215772 kb
Host smart-22052f7d-7808-4877-a895-c8bced12ac53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026782203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1026782203
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.618927188
Short name T410
Test name
Test status
Simulation time 6265086490 ps
CPU time 22.67 seconds
Started Jul 17 05:53:23 PM PDT 24
Finished Jul 17 05:53:46 PM PDT 24
Peak memory 199920 kb
Host smart-e583beeb-6699-4d45-a7c9-f6cfd860f727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618927188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.618927188
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1512980643
Short name T972
Test name
Test status
Simulation time 75720179822 ps
CPU time 216.62 seconds
Started Jul 17 05:53:16 PM PDT 24
Finished Jul 17 05:56:53 PM PDT 24
Peak memory 199932 kb
Host smart-c091b06d-ee3c-47ec-9a8c-6c2dcb13fd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512980643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1512980643
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1129784728
Short name T1093
Test name
Test status
Simulation time 33489791 ps
CPU time 0.56 seconds
Started Jul 17 05:53:36 PM PDT 24
Finished Jul 17 05:53:37 PM PDT 24
Peak memory 195588 kb
Host smart-0d6622b7-8db3-4a3c-9f31-b285dac0cbaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129784728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1129784728
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.552759299
Short name T525
Test name
Test status
Simulation time 63944727260 ps
CPU time 49.9 seconds
Started Jul 17 05:53:19 PM PDT 24
Finished Jul 17 05:54:11 PM PDT 24
Peak memory 199924 kb
Host smart-1576362a-9a73-42b5-a589-8c36683fa7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552759299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.552759299
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.413567464
Short name T158
Test name
Test status
Simulation time 26014183574 ps
CPU time 9.45 seconds
Started Jul 17 05:53:17 PM PDT 24
Finished Jul 17 05:53:28 PM PDT 24
Peak memory 199360 kb
Host smart-71172fe7-2621-47c4-9dc0-1a5b2e82048d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413567464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.413567464
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1549552875
Short name T8
Test name
Test status
Simulation time 56230665194 ps
CPU time 94.2 seconds
Started Jul 17 05:53:17 PM PDT 24
Finished Jul 17 05:54:53 PM PDT 24
Peak memory 199928 kb
Host smart-b0a3b441-ffc1-4dd6-bd64-85d5792971e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549552875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1549552875
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2304942311
Short name T926
Test name
Test status
Simulation time 12048020926 ps
CPU time 18.75 seconds
Started Jul 17 05:53:19 PM PDT 24
Finished Jul 17 05:53:39 PM PDT 24
Peak memory 199512 kb
Host smart-abd75fa6-4553-4134-9049-487b771d76ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304942311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2304942311
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3286180238
Short name T458
Test name
Test status
Simulation time 131030692250 ps
CPU time 990.31 seconds
Started Jul 17 05:53:29 PM PDT 24
Finished Jul 17 06:10:01 PM PDT 24
Peak memory 199924 kb
Host smart-ebe07471-a15c-4619-ab51-5d14b3498d07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286180238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3286180238
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3416608207
Short name T580
Test name
Test status
Simulation time 6251219964 ps
CPU time 10.88 seconds
Started Jul 17 05:53:29 PM PDT 24
Finished Jul 17 05:53:41 PM PDT 24
Peak memory 199812 kb
Host smart-1b898ffd-155d-466c-b60d-e41034008bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416608207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3416608207
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1283114397
Short name T584
Test name
Test status
Simulation time 56784338411 ps
CPU time 101.71 seconds
Started Jul 17 05:53:18 PM PDT 24
Finished Jul 17 05:55:01 PM PDT 24
Peak memory 199360 kb
Host smart-ab2b927b-8122-4afe-82cb-f551a991aac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283114397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1283114397
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2504476594
Short name T72
Test name
Test status
Simulation time 20017813135 ps
CPU time 187.95 seconds
Started Jul 17 05:53:36 PM PDT 24
Finished Jul 17 05:56:44 PM PDT 24
Peak memory 199968 kb
Host smart-b45b66b2-bdb4-464b-965d-bfeb8dcb2547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2504476594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2504476594
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1345755447
Short name T402
Test name
Test status
Simulation time 3620420389 ps
CPU time 28.37 seconds
Started Jul 17 05:53:16 PM PDT 24
Finished Jul 17 05:53:45 PM PDT 24
Peak memory 197912 kb
Host smart-8a8c755f-43aa-4f78-9ccb-b56dadbacce5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345755447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1345755447
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.72114830
Short name T543
Test name
Test status
Simulation time 30857935697 ps
CPU time 42.17 seconds
Started Jul 17 05:53:23 PM PDT 24
Finished Jul 17 05:54:06 PM PDT 24
Peak memory 199844 kb
Host smart-e550b7f1-dd98-4cb4-8064-069f169745b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72114830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.72114830
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1818705510
Short name T890
Test name
Test status
Simulation time 31539043907 ps
CPU time 45.48 seconds
Started Jul 17 05:53:24 PM PDT 24
Finished Jul 17 05:54:10 PM PDT 24
Peak memory 196680 kb
Host smart-5759d868-983a-48b4-b95a-9581e07cad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818705510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1818705510
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.686302616
Short name T980
Test name
Test status
Simulation time 6069428407 ps
CPU time 18.82 seconds
Started Jul 17 05:53:22 PM PDT 24
Finished Jul 17 05:53:42 PM PDT 24
Peak memory 199748 kb
Host smart-8cf0383c-e156-45e0-a15f-21d9f782fcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686302616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.686302616
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1619574890
Short name T460
Test name
Test status
Simulation time 430316660256 ps
CPU time 1390.2 seconds
Started Jul 17 05:53:37 PM PDT 24
Finished Jul 17 06:16:48 PM PDT 24
Peak memory 199972 kb
Host smart-e7ceb1db-67ae-4a1d-ab9e-c6607a87faa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619574890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1619574890
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2183610221
Short name T718
Test name
Test status
Simulation time 101358356416 ps
CPU time 1020.29 seconds
Started Jul 17 05:53:29 PM PDT 24
Finished Jul 17 06:10:30 PM PDT 24
Peak memory 216644 kb
Host smart-bee9a8fc-ba37-4f83-bda5-e25e31f9fdf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183610221 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2183610221
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1322332738
Short name T370
Test name
Test status
Simulation time 18929944904 ps
CPU time 2.76 seconds
Started Jul 17 05:53:35 PM PDT 24
Finished Jul 17 05:53:39 PM PDT 24
Peak memory 199520 kb
Host smart-24bccbed-1254-4505-bf26-6c016faa37b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322332738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1322332738
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3341863236
Short name T521
Test name
Test status
Simulation time 10554339094 ps
CPU time 8.37 seconds
Started Jul 17 05:53:16 PM PDT 24
Finished Jul 17 05:53:25 PM PDT 24
Peak memory 198072 kb
Host smart-928985c7-f6e4-4a13-b58f-6bc506e6b8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341863236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3341863236
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.212539562
Short name T638
Test name
Test status
Simulation time 13812545 ps
CPU time 0.57 seconds
Started Jul 17 05:53:29 PM PDT 24
Finished Jul 17 05:53:31 PM PDT 24
Peak memory 195548 kb
Host smart-5355d96d-46d7-4dda-9a91-55e8a68ed23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212539562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.212539562
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.4206387949
Short name T786
Test name
Test status
Simulation time 57934063300 ps
CPU time 13.63 seconds
Started Jul 17 05:53:30 PM PDT 24
Finished Jul 17 05:53:44 PM PDT 24
Peak memory 199980 kb
Host smart-deec6bf8-5157-4ad4-af4d-61f9a16792b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206387949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4206387949
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1014797504
Short name T264
Test name
Test status
Simulation time 117212562299 ps
CPU time 148.69 seconds
Started Jul 17 05:53:36 PM PDT 24
Finished Jul 17 05:56:06 PM PDT 24
Peak memory 199884 kb
Host smart-901c2aa1-8e9b-454a-aa3b-a906bcbc48e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014797504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1014797504
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2133123647
Short name T315
Test name
Test status
Simulation time 22030180516 ps
CPU time 9.47 seconds
Started Jul 17 05:53:29 PM PDT 24
Finished Jul 17 05:53:40 PM PDT 24
Peak memory 199988 kb
Host smart-c5bb8913-a166-4b59-8157-751de13d4911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133123647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2133123647
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1674102841
Short name T879
Test name
Test status
Simulation time 210770114801 ps
CPU time 370.54 seconds
Started Jul 17 05:53:29 PM PDT 24
Finished Jul 17 05:59:40 PM PDT 24
Peak memory 199896 kb
Host smart-4c4d3858-dbb0-493c-87d0-61bd59b4c849
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674102841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1674102841
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.4174331006
Short name T811
Test name
Test status
Simulation time 274136358274 ps
CPU time 368.86 seconds
Started Jul 17 05:53:29 PM PDT 24
Finished Jul 17 05:59:39 PM PDT 24
Peak memory 199900 kb
Host smart-ee0e45c6-3538-4d74-9e90-6d61be270dfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4174331006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.4174331006
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2199542138
Short name T939
Test name
Test status
Simulation time 4086910602 ps
CPU time 2.55 seconds
Started Jul 17 05:53:37 PM PDT 24
Finished Jul 17 05:53:41 PM PDT 24
Peak memory 197740 kb
Host smart-3d6e0e23-1ac2-40d3-8895-4c9f39826c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199542138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2199542138
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.381447060
Short name T382
Test name
Test status
Simulation time 293544017922 ps
CPU time 129.63 seconds
Started Jul 17 05:53:30 PM PDT 24
Finished Jul 17 05:55:41 PM PDT 24
Peak memory 208132 kb
Host smart-e072dda3-d2cf-4953-aa45-5086762d1363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381447060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.381447060
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2547495664
Short name T257
Test name
Test status
Simulation time 2862814788 ps
CPU time 81.55 seconds
Started Jul 17 05:53:28 PM PDT 24
Finished Jul 17 05:54:50 PM PDT 24
Peak memory 199820 kb
Host smart-e560b86c-d433-4603-832d-924fe6863dba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2547495664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2547495664
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1823306137
Short name T367
Test name
Test status
Simulation time 3056106328 ps
CPU time 11.7 seconds
Started Jul 17 05:53:30 PM PDT 24
Finished Jul 17 05:53:42 PM PDT 24
Peak memory 198172 kb
Host smart-464f0132-2373-4315-ac1f-6843b8bfc2c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823306137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1823306137
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2338017710
Short name T1089
Test name
Test status
Simulation time 16878999652 ps
CPU time 10.67 seconds
Started Jul 17 05:53:37 PM PDT 24
Finished Jul 17 05:53:48 PM PDT 24
Peak memory 199960 kb
Host smart-fbdc9621-5f90-4cd3-a497-0b04e9000d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338017710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2338017710
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3500621748
Short name T605
Test name
Test status
Simulation time 1706336177 ps
CPU time 2.95 seconds
Started Jul 17 05:53:37 PM PDT 24
Finished Jul 17 05:53:41 PM PDT 24
Peak memory 195376 kb
Host smart-dc972ad9-2248-4444-933e-d54fc890340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500621748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3500621748
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2872025521
Short name T1037
Test name
Test status
Simulation time 450431389 ps
CPU time 2.14 seconds
Started Jul 17 05:53:36 PM PDT 24
Finished Jul 17 05:53:39 PM PDT 24
Peak memory 198696 kb
Host smart-b1b5801e-1391-4eca-bba6-be1578cd3396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872025521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2872025521
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3693230032
Short name T265
Test name
Test status
Simulation time 127866631536 ps
CPU time 436.15 seconds
Started Jul 17 05:53:36 PM PDT 24
Finished Jul 17 06:00:53 PM PDT 24
Peak memory 200280 kb
Host smart-f1ed500a-a2f4-4559-8b91-3259bc56c1a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693230032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3693230032
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2525625058
Short name T1139
Test name
Test status
Simulation time 2097055015 ps
CPU time 2.55 seconds
Started Jul 17 05:53:37 PM PDT 24
Finished Jul 17 05:53:41 PM PDT 24
Peak memory 198824 kb
Host smart-1ceb96ec-87e7-40c9-ba3b-995d94418423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525625058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2525625058
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2414601854
Short name T790
Test name
Test status
Simulation time 128064048216 ps
CPU time 45.84 seconds
Started Jul 17 05:53:30 PM PDT 24
Finished Jul 17 05:54:17 PM PDT 24
Peak memory 199788 kb
Host smart-c0822a9c-fdf0-4995-8dcf-b351b8e854a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414601854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2414601854
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2702127227
Short name T813
Test name
Test status
Simulation time 176034682 ps
CPU time 0.57 seconds
Started Jul 17 05:53:45 PM PDT 24
Finished Jul 17 05:53:47 PM PDT 24
Peak memory 195584 kb
Host smart-201868d2-1b40-44cd-9ade-698c467475d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702127227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2702127227
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.214867494
Short name T874
Test name
Test status
Simulation time 41097182296 ps
CPU time 17.33 seconds
Started Jul 17 05:53:31 PM PDT 24
Finished Jul 17 05:53:49 PM PDT 24
Peak memory 199924 kb
Host smart-a6ec47fa-f583-4eb0-a376-377d52fced56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214867494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.214867494
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2530177612
Short name T289
Test name
Test status
Simulation time 239567296273 ps
CPU time 352.74 seconds
Started Jul 17 05:53:36 PM PDT 24
Finished Jul 17 05:59:30 PM PDT 24
Peak memory 199988 kb
Host smart-8dbc011c-7565-4292-81d8-c63dc701084f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530177612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2530177612
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.4110546102
Short name T739
Test name
Test status
Simulation time 50562880322 ps
CPU time 49.86 seconds
Started Jul 17 05:53:36 PM PDT 24
Finished Jul 17 05:54:27 PM PDT 24
Peak memory 199988 kb
Host smart-d6285b1a-eb4b-4850-a673-0897cdc9bf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110546102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.4110546102
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.735797370
Short name T635
Test name
Test status
Simulation time 9828866345 ps
CPU time 14.11 seconds
Started Jul 17 05:53:30 PM PDT 24
Finished Jul 17 05:53:45 PM PDT 24
Peak memory 198124 kb
Host smart-2b739ec2-8a63-45cb-867a-1cbd4890c294
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735797370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.735797370
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.961897455
Short name T572
Test name
Test status
Simulation time 137908264547 ps
CPU time 249.84 seconds
Started Jul 17 05:53:43 PM PDT 24
Finished Jul 17 05:57:55 PM PDT 24
Peak memory 199892 kb
Host smart-e05f7a10-2e90-4f24-8de2-7c40c0d8e6f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961897455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.961897455
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.696799171
Short name T406
Test name
Test status
Simulation time 4523026145 ps
CPU time 9.35 seconds
Started Jul 17 05:53:44 PM PDT 24
Finished Jul 17 05:53:55 PM PDT 24
Peak memory 199568 kb
Host smart-2afa03dd-b89e-4e53-a27c-b862096eba2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696799171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.696799171
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3988298120
Short name T613
Test name
Test status
Simulation time 9368651363 ps
CPU time 15.5 seconds
Started Jul 17 05:53:29 PM PDT 24
Finished Jul 17 05:53:45 PM PDT 24
Peak memory 194964 kb
Host smart-a5ccaeda-1be7-4dba-9a58-3e378b46d26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988298120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3988298120
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.4073640313
Short name T792
Test name
Test status
Simulation time 20191407150 ps
CPU time 1196.56 seconds
Started Jul 17 05:53:42 PM PDT 24
Finished Jul 17 06:13:40 PM PDT 24
Peak memory 199924 kb
Host smart-9cd148f4-e5d8-48a3-99b4-e296120706d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073640313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.4073640313
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.4176514604
Short name T364
Test name
Test status
Simulation time 6936160714 ps
CPU time 61.41 seconds
Started Jul 17 05:53:28 PM PDT 24
Finished Jul 17 05:54:30 PM PDT 24
Peak memory 199424 kb
Host smart-76b5a730-d7db-4a1a-a4d7-3f0028a751a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4176514604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.4176514604
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.348996963
Short name T636
Test name
Test status
Simulation time 20111686299 ps
CPU time 31.42 seconds
Started Jul 17 05:53:42 PM PDT 24
Finished Jul 17 05:54:15 PM PDT 24
Peak memory 199964 kb
Host smart-4dc1a045-721c-4372-8952-61be508a9280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348996963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.348996963
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.4097082054
Short name T1166
Test name
Test status
Simulation time 3238128229 ps
CPU time 5.49 seconds
Started Jul 17 05:53:45 PM PDT 24
Finished Jul 17 05:53:52 PM PDT 24
Peak memory 196160 kb
Host smart-5933ce5f-b70c-4094-a9be-ca40c251af77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097082054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4097082054
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1184547597
Short name T862
Test name
Test status
Simulation time 842717623 ps
CPU time 5.54 seconds
Started Jul 17 05:53:32 PM PDT 24
Finished Jul 17 05:53:38 PM PDT 24
Peak memory 198724 kb
Host smart-4d8b7b8e-3614-41fe-8559-3d0630286b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184547597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1184547597
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.4270015285
Short name T157
Test name
Test status
Simulation time 129882070818 ps
CPU time 380.03 seconds
Started Jul 17 05:53:43 PM PDT 24
Finished Jul 17 06:00:05 PM PDT 24
Peak memory 199968 kb
Host smart-415c297f-fded-4174-b770-1ee8277837ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270015285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.4270015285
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2192163864
Short name T436
Test name
Test status
Simulation time 2320957777 ps
CPU time 2.65 seconds
Started Jul 17 05:53:43 PM PDT 24
Finished Jul 17 05:53:47 PM PDT 24
Peak memory 198588 kb
Host smart-d77d1ec7-1f2a-434d-8d97-e85cfe94a7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192163864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2192163864
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.332377407
Short name T287
Test name
Test status
Simulation time 87206646928 ps
CPU time 151.18 seconds
Started Jul 17 05:53:36 PM PDT 24
Finished Jul 17 05:56:08 PM PDT 24
Peak memory 199936 kb
Host smart-25ae6d2e-1827-4a5c-a833-3247ea887ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332377407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.332377407
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.4015675803
Short name T98
Test name
Test status
Simulation time 11614967 ps
CPU time 0.59 seconds
Started Jul 17 05:53:43 PM PDT 24
Finished Jul 17 05:53:45 PM PDT 24
Peak memory 194476 kb
Host smart-4c658dbe-a2cc-4f06-bc2c-6c97238f6d89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015675803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4015675803
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3572268625
Short name T144
Test name
Test status
Simulation time 122811428286 ps
CPU time 103.46 seconds
Started Jul 17 05:53:43 PM PDT 24
Finished Jul 17 05:55:28 PM PDT 24
Peak memory 199924 kb
Host smart-05eab36a-029d-4c02-a265-1997e405beca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572268625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3572268625
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1549897449
Short name T760
Test name
Test status
Simulation time 203854831475 ps
CPU time 194.99 seconds
Started Jul 17 05:53:43 PM PDT 24
Finished Jul 17 05:57:00 PM PDT 24
Peak memory 199936 kb
Host smart-7925c3f1-679b-427a-8c6c-71ffde0931fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549897449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1549897449
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3977653313
Short name T176
Test name
Test status
Simulation time 62158926557 ps
CPU time 23.22 seconds
Started Jul 17 05:53:47 PM PDT 24
Finished Jul 17 05:54:12 PM PDT 24
Peak memory 199012 kb
Host smart-e8aadf7f-a402-4bf3-b9f3-ba2fbcfe3373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977653313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3977653313
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.4010384305
Short name T562
Test name
Test status
Simulation time 32370745517 ps
CPU time 50.55 seconds
Started Jul 17 05:53:42 PM PDT 24
Finished Jul 17 05:54:34 PM PDT 24
Peak memory 199912 kb
Host smart-df485a0c-e33d-4bdc-9abb-b92a76bf3f22
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010384305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.4010384305
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2634353535
Short name T719
Test name
Test status
Simulation time 208030735597 ps
CPU time 558.17 seconds
Started Jul 17 05:53:42 PM PDT 24
Finished Jul 17 06:03:01 PM PDT 24
Peak memory 199852 kb
Host smart-1e981e02-b47c-4bcf-ae75-18c3cd9caaae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634353535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2634353535
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1549831594
Short name T448
Test name
Test status
Simulation time 4173215839 ps
CPU time 4.17 seconds
Started Jul 17 05:53:42 PM PDT 24
Finished Jul 17 05:53:47 PM PDT 24
Peak memory 197232 kb
Host smart-0f30d29c-8a86-4a4b-9889-0fbaf8530139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549831594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1549831594
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.355364293
Short name T997
Test name
Test status
Simulation time 32989665523 ps
CPU time 9.8 seconds
Started Jul 17 05:53:44 PM PDT 24
Finished Jul 17 05:53:56 PM PDT 24
Peak memory 199876 kb
Host smart-94674e12-6555-44b6-a296-ebc4dbf263f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355364293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.355364293
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1047059663
Short name T601
Test name
Test status
Simulation time 12732079459 ps
CPU time 624.8 seconds
Started Jul 17 05:53:45 PM PDT 24
Finished Jul 17 06:04:11 PM PDT 24
Peak memory 200132 kb
Host smart-c90a782b-fa2b-4209-9afa-64646c094b43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1047059663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1047059663
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3244636529
Short name T758
Test name
Test status
Simulation time 2135326920 ps
CPU time 3.74 seconds
Started Jul 17 05:53:42 PM PDT 24
Finished Jul 17 05:53:46 PM PDT 24
Peak memory 198196 kb
Host smart-83418c30-6982-42fe-a486-75bcc0a648cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244636529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3244636529
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3254583363
Short name T438
Test name
Test status
Simulation time 5548504769 ps
CPU time 8.98 seconds
Started Jul 17 05:53:42 PM PDT 24
Finished Jul 17 05:53:53 PM PDT 24
Peak memory 199808 kb
Host smart-9d63ad25-a085-4904-a735-cdded502be30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254583363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3254583363
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2201582894
Short name T578
Test name
Test status
Simulation time 4867327882 ps
CPU time 7.29 seconds
Started Jul 17 05:53:43 PM PDT 24
Finished Jul 17 05:53:52 PM PDT 24
Peak memory 195988 kb
Host smart-6ca9a8f5-8cec-473e-b0b4-049788c605b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201582894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2201582894
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.4087451054
Short name T395
Test name
Test status
Simulation time 535672761 ps
CPU time 1.75 seconds
Started Jul 17 05:53:42 PM PDT 24
Finished Jul 17 05:53:44 PM PDT 24
Peak memory 199780 kb
Host smart-01b8d2de-25a8-423c-9e4b-0b82d6a8c3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087451054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4087451054
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1253417185
Short name T694
Test name
Test status
Simulation time 205899941823 ps
CPU time 177.1 seconds
Started Jul 17 05:53:44 PM PDT 24
Finished Jul 17 05:56:42 PM PDT 24
Peak memory 199956 kb
Host smart-5214af26-06ef-442a-983c-3dd574b42dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253417185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1253417185
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1793404861
Short name T1068
Test name
Test status
Simulation time 1080798999 ps
CPU time 3.37 seconds
Started Jul 17 05:53:42 PM PDT 24
Finished Jul 17 05:53:46 PM PDT 24
Peak memory 199368 kb
Host smart-06743dde-3901-41dd-b662-641d6f3a9ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793404861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1793404861
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.581090963
Short name T1011
Test name
Test status
Simulation time 83329645090 ps
CPU time 53.35 seconds
Started Jul 17 05:53:48 PM PDT 24
Finished Jul 17 05:54:42 PM PDT 24
Peak memory 199976 kb
Host smart-1325cee7-9812-4dd8-a061-096cf551ebe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581090963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.581090963
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3696786055
Short name T1149
Test name
Test status
Simulation time 14249727 ps
CPU time 0.55 seconds
Started Jul 17 05:54:05 PM PDT 24
Finished Jul 17 05:54:06 PM PDT 24
Peak memory 195304 kb
Host smart-ab992b18-0486-437d-abfe-e79e51d31fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696786055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3696786055
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1325767269
Short name T1087
Test name
Test status
Simulation time 87669637767 ps
CPU time 135.35 seconds
Started Jul 17 05:53:44 PM PDT 24
Finished Jul 17 05:56:01 PM PDT 24
Peak memory 200000 kb
Host smart-7f66956c-306d-4e34-90a2-71a9a3d89008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325767269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1325767269
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.793200347
Short name T324
Test name
Test status
Simulation time 136441001717 ps
CPU time 179.73 seconds
Started Jul 17 05:53:56 PM PDT 24
Finished Jul 17 05:56:57 PM PDT 24
Peak memory 199992 kb
Host smart-b9d42a84-77ba-4051-98d1-22766e5379e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793200347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.793200347
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1679464433
Short name T899
Test name
Test status
Simulation time 28872379237 ps
CPU time 18.6 seconds
Started Jul 17 05:53:56 PM PDT 24
Finished Jul 17 05:54:15 PM PDT 24
Peak memory 199936 kb
Host smart-9fb232e9-2137-4ae8-8d3e-787ab70935e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679464433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1679464433
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.4194683105
Short name T253
Test name
Test status
Simulation time 8260076689 ps
CPU time 10.88 seconds
Started Jul 17 05:54:09 PM PDT 24
Finished Jul 17 05:54:20 PM PDT 24
Peak memory 198644 kb
Host smart-6247f26d-fe3f-408f-a5ef-0d7a62aa7e31
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194683105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.4194683105
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2669692038
Short name T1096
Test name
Test status
Simulation time 297539809433 ps
CPU time 298.99 seconds
Started Jul 17 05:53:57 PM PDT 24
Finished Jul 17 05:58:57 PM PDT 24
Peak memory 199904 kb
Host smart-13e3e37f-1eae-4902-adea-fa48b45e7f55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669692038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2669692038
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2131838364
Short name T69
Test name
Test status
Simulation time 2298131257 ps
CPU time 4.26 seconds
Started Jul 17 05:54:02 PM PDT 24
Finished Jul 17 05:54:07 PM PDT 24
Peak memory 198412 kb
Host smart-7ec37c1e-cc85-43c6-92a1-c4f0e6ff061c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131838364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2131838364
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.821841341
Short name T1168
Test name
Test status
Simulation time 364942800282 ps
CPU time 75.14 seconds
Started Jul 17 05:54:03 PM PDT 24
Finished Jul 17 05:55:19 PM PDT 24
Peak memory 208000 kb
Host smart-534210f2-203d-4839-bb85-5d4f138aa71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821841341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.821841341
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1468229461
Short name T1178
Test name
Test status
Simulation time 20136135825 ps
CPU time 1236.37 seconds
Started Jul 17 05:54:05 PM PDT 24
Finished Jul 17 06:14:42 PM PDT 24
Peak memory 199880 kb
Host smart-7a3c5b93-3ab8-4819-bc5e-fb473aba0a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468229461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1468229461
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1852683027
Short name T465
Test name
Test status
Simulation time 2012023812 ps
CPU time 4.77 seconds
Started Jul 17 05:54:00 PM PDT 24
Finished Jul 17 05:54:06 PM PDT 24
Peak memory 198104 kb
Host smart-b4a240ef-c9f5-48cf-8dbf-885ecc999359
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1852683027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1852683027
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1897147925
Short name T495
Test name
Test status
Simulation time 33719186280 ps
CPU time 13.72 seconds
Started Jul 17 05:54:02 PM PDT 24
Finished Jul 17 05:54:16 PM PDT 24
Peak memory 199896 kb
Host smart-ac3c0125-5af1-463f-a716-0e984d6b4ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897147925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1897147925
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2338588072
Short name T768
Test name
Test status
Simulation time 6621279576 ps
CPU time 1.26 seconds
Started Jul 17 05:54:01 PM PDT 24
Finished Jul 17 05:54:03 PM PDT 24
Peak memory 196168 kb
Host smart-7750dff6-8a89-4b08-a015-0dad14903a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338588072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2338588072
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3935659392
Short name T38
Test name
Test status
Simulation time 782822485 ps
CPU time 1.16 seconds
Started Jul 17 05:53:42 PM PDT 24
Finished Jul 17 05:53:45 PM PDT 24
Peak memory 198360 kb
Host smart-9ff21a34-2561-419d-ada7-4bc4dc573e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935659392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3935659392
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1873280128
Short name T1159
Test name
Test status
Simulation time 64894137611 ps
CPU time 102.65 seconds
Started Jul 17 05:53:59 PM PDT 24
Finished Jul 17 05:55:43 PM PDT 24
Peak memory 199948 kb
Host smart-ba223540-0729-4988-ad78-ad4964813150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873280128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1873280128
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3355755763
Short name T338
Test name
Test status
Simulation time 2837716323 ps
CPU time 76.05 seconds
Started Jul 17 05:53:56 PM PDT 24
Finished Jul 17 05:55:13 PM PDT 24
Peak memory 208500 kb
Host smart-f9e1005b-c96f-4ec6-affa-54cab4560561
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355755763 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3355755763
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3028782399
Short name T299
Test name
Test status
Simulation time 991158679 ps
CPU time 1.49 seconds
Started Jul 17 05:53:54 PM PDT 24
Finished Jul 17 05:53:56 PM PDT 24
Peak memory 197780 kb
Host smart-d354039b-c6ef-423e-8889-f90664f1b6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028782399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3028782399
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2998246854
Short name T1030
Test name
Test status
Simulation time 122413966549 ps
CPU time 133.19 seconds
Started Jul 17 05:53:45 PM PDT 24
Finished Jul 17 05:56:00 PM PDT 24
Peak memory 199992 kb
Host smart-57cadd24-d79c-4138-a214-2e835da19405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998246854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2998246854
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1633069694
Short name T372
Test name
Test status
Simulation time 23367084 ps
CPU time 0.58 seconds
Started Jul 17 05:53:56 PM PDT 24
Finished Jul 17 05:53:58 PM PDT 24
Peak memory 195264 kb
Host smart-82b42032-b3f1-4abe-b5c5-8db3639b3234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633069694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1633069694
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1823174121
Short name T255
Test name
Test status
Simulation time 144608551034 ps
CPU time 200.49 seconds
Started Jul 17 05:54:09 PM PDT 24
Finished Jul 17 05:57:30 PM PDT 24
Peak memory 199844 kb
Host smart-1951972f-475f-44cd-80c8-3b89f0fe7aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823174121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1823174121
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1300777047
Short name T681
Test name
Test status
Simulation time 153479445729 ps
CPU time 53.6 seconds
Started Jul 17 05:53:57 PM PDT 24
Finished Jul 17 05:54:52 PM PDT 24
Peak memory 199980 kb
Host smart-803d32a9-8d4c-4798-b322-ad55a42ca7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300777047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1300777047
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3500710212
Short name T498
Test name
Test status
Simulation time 8350914765 ps
CPU time 9.62 seconds
Started Jul 17 05:53:58 PM PDT 24
Finished Jul 17 05:54:08 PM PDT 24
Peak memory 199944 kb
Host smart-d7b05d92-d41d-4f5e-96e0-8948292ed5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500710212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3500710212
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1012799246
Short name T630
Test name
Test status
Simulation time 29420732077 ps
CPU time 20.59 seconds
Started Jul 17 05:53:55 PM PDT 24
Finished Jul 17 05:54:16 PM PDT 24
Peak memory 199872 kb
Host smart-eb62d4cb-3a12-455a-b143-cd59cee81f82
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012799246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1012799246
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2772791191
Short name T928
Test name
Test status
Simulation time 62402860667 ps
CPU time 223.41 seconds
Started Jul 17 05:54:02 PM PDT 24
Finished Jul 17 05:57:46 PM PDT 24
Peak memory 199968 kb
Host smart-930b214a-4cac-4083-9042-7397ccb8a494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772791191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2772791191
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3322242121
Short name T357
Test name
Test status
Simulation time 1655924692 ps
CPU time 1.76 seconds
Started Jul 17 05:53:55 PM PDT 24
Finished Jul 17 05:53:58 PM PDT 24
Peak memory 198416 kb
Host smart-96abcdf5-d9ba-4708-ac62-012ec0e5885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322242121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3322242121
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2994685490
Short name T731
Test name
Test status
Simulation time 61253363073 ps
CPU time 24.93 seconds
Started Jul 17 05:54:04 PM PDT 24
Finished Jul 17 05:54:30 PM PDT 24
Peak memory 197740 kb
Host smart-afedfb4d-cc83-40dd-82fa-d9899de29da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994685490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2994685490
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.4004708205
Short name T710
Test name
Test status
Simulation time 14619388595 ps
CPU time 81.89 seconds
Started Jul 17 05:53:56 PM PDT 24
Finished Jul 17 05:55:19 PM PDT 24
Peak memory 199976 kb
Host smart-36a866f2-7c9b-4355-b374-69d82a15f774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004708205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.4004708205
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.485058049
Short name T1032
Test name
Test status
Simulation time 1481187784 ps
CPU time 5.94 seconds
Started Jul 17 05:53:57 PM PDT 24
Finished Jul 17 05:54:04 PM PDT 24
Peak memory 198120 kb
Host smart-362fd76e-03ea-484f-87cc-abb81af564d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485058049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.485058049
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.811131435
Short name T1109
Test name
Test status
Simulation time 2896788599 ps
CPU time 5.23 seconds
Started Jul 17 05:54:00 PM PDT 24
Finished Jul 17 05:54:06 PM PDT 24
Peak memory 195928 kb
Host smart-0fc82c2f-e7bc-400b-bea3-8e9589a42786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811131435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.811131435
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.713414748
Short name T453
Test name
Test status
Simulation time 963245474 ps
CPU time 1.63 seconds
Started Jul 17 05:53:56 PM PDT 24
Finished Jul 17 05:53:58 PM PDT 24
Peak memory 199760 kb
Host smart-bbaa9442-bd7e-4c70-b275-d91929f55a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713414748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.713414748
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1449401828
Short name T189
Test name
Test status
Simulation time 270662525060 ps
CPU time 715.63 seconds
Started Jul 17 05:54:07 PM PDT 24
Finished Jul 17 06:06:03 PM PDT 24
Peak memory 216416 kb
Host smart-9b8f3ffa-ce4c-491a-afa9-2a6e41e77d35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449401828 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1449401828
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3405333062
Short name T1018
Test name
Test status
Simulation time 7501535642 ps
CPU time 6.08 seconds
Started Jul 17 05:54:09 PM PDT 24
Finished Jul 17 05:54:15 PM PDT 24
Peak memory 199268 kb
Host smart-932d4403-cb77-4704-a8df-7dd095082111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405333062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3405333062
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2701789750
Short name T1028
Test name
Test status
Simulation time 31615406785 ps
CPU time 52.6 seconds
Started Jul 17 05:54:01 PM PDT 24
Finished Jul 17 05:54:55 PM PDT 24
Peak memory 199980 kb
Host smart-111d7584-9173-4c7f-aa63-7b90052a50d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701789750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2701789750
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.271066210
Short name T88
Test name
Test status
Simulation time 12741762 ps
CPU time 0.55 seconds
Started Jul 17 05:54:12 PM PDT 24
Finished Jul 17 05:54:14 PM PDT 24
Peak memory 194292 kb
Host smart-c057c721-a46e-4418-b505-cbed3568d8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271066210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.271066210
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3886164780
Short name T729
Test name
Test status
Simulation time 73983707191 ps
CPU time 35.08 seconds
Started Jul 17 05:54:01 PM PDT 24
Finished Jul 17 05:54:37 PM PDT 24
Peak memory 199916 kb
Host smart-10c3cd36-4190-4b75-8b52-58946c01dd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886164780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3886164780
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.622023406
Short name T285
Test name
Test status
Simulation time 10256437217 ps
CPU time 16.6 seconds
Started Jul 17 05:53:56 PM PDT 24
Finished Jul 17 05:54:14 PM PDT 24
Peak memory 198032 kb
Host smart-7a6f2e39-fbe7-41c4-b603-f239ec414e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622023406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.622023406
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1972788115
Short name T649
Test name
Test status
Simulation time 160640411278 ps
CPU time 67.24 seconds
Started Jul 17 05:54:02 PM PDT 24
Finished Jul 17 05:55:10 PM PDT 24
Peak memory 199904 kb
Host smart-acbfbf0d-d498-4544-b3e6-617d58f0bece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972788115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1972788115
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3187740651
Short name T422
Test name
Test status
Simulation time 4234290142 ps
CPU time 8.56 seconds
Started Jul 17 05:54:01 PM PDT 24
Finished Jul 17 05:54:11 PM PDT 24
Peak memory 199524 kb
Host smart-f823fa72-73d2-4958-a016-745ee7cdf73a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187740651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3187740651
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1342895444
Short name T717
Test name
Test status
Simulation time 187406319749 ps
CPU time 264.33 seconds
Started Jul 17 05:54:10 PM PDT 24
Finished Jul 17 05:58:36 PM PDT 24
Peak memory 199844 kb
Host smart-5e7e2a80-16fb-40a9-9c71-5a164590aa95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342895444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1342895444
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1108587725
Short name T381
Test name
Test status
Simulation time 9404265376 ps
CPU time 10.71 seconds
Started Jul 17 05:53:54 PM PDT 24
Finished Jul 17 05:54:06 PM PDT 24
Peak memory 199932 kb
Host smart-cb4d9ef6-51cb-42af-a3f8-4e7816bf00bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108587725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1108587725
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2713862928
Short name T604
Test name
Test status
Simulation time 36229184304 ps
CPU time 95.93 seconds
Started Jul 17 05:54:00 PM PDT 24
Finished Jul 17 05:55:37 PM PDT 24
Peak memory 208140 kb
Host smart-bdc6cd57-8019-4597-bdbc-89b23549ed93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713862928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2713862928
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.142625601
Short name T283
Test name
Test status
Simulation time 16501038153 ps
CPU time 745.01 seconds
Started Jul 17 05:54:11 PM PDT 24
Finished Jul 17 06:06:38 PM PDT 24
Peak memory 199968 kb
Host smart-dc42c6fb-9f58-46b9-8543-fde00af66c01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=142625601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.142625601
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1829810485
Short name T742
Test name
Test status
Simulation time 4266413422 ps
CPU time 9.37 seconds
Started Jul 17 05:53:57 PM PDT 24
Finished Jul 17 05:54:07 PM PDT 24
Peak memory 198316 kb
Host smart-f4a14813-7fd2-45dd-a9c0-6e25913268d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829810485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1829810485
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1956141432
Short name T380
Test name
Test status
Simulation time 37435759719 ps
CPU time 14 seconds
Started Jul 17 05:54:03 PM PDT 24
Finished Jul 17 05:54:18 PM PDT 24
Peak memory 199848 kb
Host smart-a1ce24d5-a445-4d38-9090-202fbe64f968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956141432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1956141432
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1004436286
Short name T407
Test name
Test status
Simulation time 3817456796 ps
CPU time 2.17 seconds
Started Jul 17 05:54:03 PM PDT 24
Finished Jul 17 05:54:06 PM PDT 24
Peak memory 196400 kb
Host smart-f5f0f12a-7511-4f8c-9fe4-4073f258ff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004436286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1004436286
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2472720010
Short name T606
Test name
Test status
Simulation time 159370949 ps
CPU time 0.88 seconds
Started Jul 17 05:54:03 PM PDT 24
Finished Jul 17 05:54:05 PM PDT 24
Peak memory 197940 kb
Host smart-3c4e3d3f-0f4d-47b7-bddc-3cd59214f341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472720010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2472720010
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3613698914
Short name T326
Test name
Test status
Simulation time 631182162314 ps
CPU time 755.59 seconds
Started Jul 17 05:54:13 PM PDT 24
Finished Jul 17 06:06:50 PM PDT 24
Peak memory 199868 kb
Host smart-f6d424bf-decc-448d-96b7-e81d2b07d12a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613698914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3613698914
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.930256434
Short name T447
Test name
Test status
Simulation time 181390769712 ps
CPU time 141.79 seconds
Started Jul 17 05:54:11 PM PDT 24
Finished Jul 17 05:56:35 PM PDT 24
Peak memory 216416 kb
Host smart-55cfbca4-13cc-4160-a04a-18db1a0255be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930256434 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.930256434
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.580221367
Short name T845
Test name
Test status
Simulation time 1474723344 ps
CPU time 2.01 seconds
Started Jul 17 05:53:57 PM PDT 24
Finished Jul 17 05:54:00 PM PDT 24
Peak memory 198600 kb
Host smart-09169dc3-a73f-4332-858f-0aa06a0f249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580221367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.580221367
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.749123209
Short name T517
Test name
Test status
Simulation time 86652832748 ps
CPU time 84.37 seconds
Started Jul 17 05:53:54 PM PDT 24
Finished Jul 17 05:55:20 PM PDT 24
Peak memory 199812 kb
Host smart-56f49dd4-3456-418a-88b1-363c5ba12b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749123209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.749123209
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2524067026
Short name T698
Test name
Test status
Simulation time 46849500 ps
CPU time 0.57 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:50:49 PM PDT 24
Peak memory 195220 kb
Host smart-c63e1762-f52a-4e3b-9c90-d09cd29d0529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524067026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2524067026
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1177124562
Short name T483
Test name
Test status
Simulation time 224321914777 ps
CPU time 109.97 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:52:38 PM PDT 24
Peak memory 199980 kb
Host smart-670c62cb-4990-4db0-91db-3364c07e2880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177124562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1177124562
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2522193092
Short name T435
Test name
Test status
Simulation time 55749021236 ps
CPU time 23.8 seconds
Started Jul 17 05:50:45 PM PDT 24
Finished Jul 17 05:51:09 PM PDT 24
Peak memory 199276 kb
Host smart-7382ab38-99d2-41bf-aaa1-f2340c58b798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522193092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2522193092
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2664077542
Short name T47
Test name
Test status
Simulation time 137076999008 ps
CPU time 50.56 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:51:41 PM PDT 24
Peak memory 199940 kb
Host smart-0eb74bd5-5449-4a70-bc5a-a122b42eab8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664077542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2664077542
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1086164166
Short name T941
Test name
Test status
Simulation time 44245814330 ps
CPU time 20.92 seconds
Started Jul 17 05:50:45 PM PDT 24
Finished Jul 17 05:51:07 PM PDT 24
Peak memory 199900 kb
Host smart-57cece48-c1fb-4b33-b5fb-6b0847d6d403
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086164166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1086164166
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1432674751
Short name T565
Test name
Test status
Simulation time 33859686750 ps
CPU time 319.55 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:56:10 PM PDT 24
Peak memory 199936 kb
Host smart-65b928d4-1e1d-411d-8ecd-e7886ebd19b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1432674751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1432674751
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3364584434
Short name T579
Test name
Test status
Simulation time 5590908211 ps
CPU time 10.77 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:51:01 PM PDT 24
Peak memory 199924 kb
Host smart-52d36f8f-5f65-4f46-9f6a-07bbe99cece7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364584434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3364584434
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2143553108
Short name T631
Test name
Test status
Simulation time 54437224639 ps
CPU time 80.84 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:52:10 PM PDT 24
Peak memory 199080 kb
Host smart-b6eafc0e-571c-42aa-9749-6392f3de1406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143553108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2143553108
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2145523607
Short name T1088
Test name
Test status
Simulation time 17675053992 ps
CPU time 891.25 seconds
Started Jul 17 05:50:46 PM PDT 24
Finished Jul 17 06:05:39 PM PDT 24
Peak memory 200084 kb
Host smart-02abde94-37ae-46b7-af56-4432e9dd60e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145523607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2145523607
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1260691993
Short name T1161
Test name
Test status
Simulation time 5081457853 ps
CPU time 11.7 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:51:02 PM PDT 24
Peak memory 198104 kb
Host smart-ceca6ea7-3157-48a8-95ab-82120997a18b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260691993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1260691993
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.628889844
Short name T1066
Test name
Test status
Simulation time 111745538037 ps
CPU time 181.56 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:53:52 PM PDT 24
Peak memory 199952 kb
Host smart-e5fe7dd2-cea1-4669-be45-4318f1e451e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628889844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.628889844
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3141808785
Short name T1107
Test name
Test status
Simulation time 67341610949 ps
CPU time 86.77 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:52:17 PM PDT 24
Peak memory 196192 kb
Host smart-37677b70-75bc-4f0c-8b0a-44f8d22779f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141808785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3141808785
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3100727306
Short name T332
Test name
Test status
Simulation time 5972601083 ps
CPU time 16.12 seconds
Started Jul 17 05:50:38 PM PDT 24
Finished Jul 17 05:50:55 PM PDT 24
Peak memory 199652 kb
Host smart-9c9e2317-2000-464a-89c7-5a5e3baf925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100727306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3100727306
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.783896336
Short name T516
Test name
Test status
Simulation time 171789463446 ps
CPU time 1890.96 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 06:22:21 PM PDT 24
Peak memory 199892 kb
Host smart-50591255-28ee-4f66-819d-1fb4855f2d92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783896336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.783896336
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.227553426
Short name T1019
Test name
Test status
Simulation time 336009187556 ps
CPU time 198.51 seconds
Started Jul 17 05:50:49 PM PDT 24
Finished Jul 17 05:54:10 PM PDT 24
Peak memory 215088 kb
Host smart-3027f10d-6000-4d17-95b2-ed933a031f72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227553426 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.227553426
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3617168243
Short name T1090
Test name
Test status
Simulation time 1460917968 ps
CPU time 2.12 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:50:52 PM PDT 24
Peak memory 198804 kb
Host smart-31fa2893-a915-4cb7-9c99-d89dd3ba638f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617168243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3617168243
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.502789872
Short name T522
Test name
Test status
Simulation time 185847884864 ps
CPU time 89.11 seconds
Started Jul 17 05:50:40 PM PDT 24
Finished Jul 17 05:52:10 PM PDT 24
Peak memory 200064 kb
Host smart-2028401f-a211-403f-8f6c-a1998eb11eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502789872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.502789872
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3650629780
Short name T785
Test name
Test status
Simulation time 120270289630 ps
CPU time 54.75 seconds
Started Jul 17 05:54:11 PM PDT 24
Finished Jul 17 05:55:07 PM PDT 24
Peak memory 199920 kb
Host smart-1ad4395f-fb63-4a20-adce-93ded67459c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650629780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3650629780
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1092270590
Short name T314
Test name
Test status
Simulation time 172936518938 ps
CPU time 1143.33 seconds
Started Jul 17 05:54:13 PM PDT 24
Finished Jul 17 06:13:18 PM PDT 24
Peak memory 224884 kb
Host smart-be717184-de4f-4785-9234-76516219d823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092270590 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1092270590
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3321805706
Short name T197
Test name
Test status
Simulation time 23756412566 ps
CPU time 32.11 seconds
Started Jul 17 05:54:22 PM PDT 24
Finished Jul 17 05:54:55 PM PDT 24
Peak memory 199896 kb
Host smart-4844fde6-a111-4239-a6ad-76ec17c7bb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321805706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3321805706
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.290064750
Short name T25
Test name
Test status
Simulation time 44832331179 ps
CPU time 830.93 seconds
Started Jul 17 05:54:18 PM PDT 24
Finished Jul 17 06:08:10 PM PDT 24
Peak memory 212160 kb
Host smart-6f2b6a65-c614-4463-b877-0eaee97e4e00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290064750 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.290064750
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2461754612
Short name T186
Test name
Test status
Simulation time 13160670531 ps
CPU time 23.83 seconds
Started Jul 17 05:54:12 PM PDT 24
Finished Jul 17 05:54:38 PM PDT 24
Peak memory 199976 kb
Host smart-8f1aef51-ee6d-40d6-a6e6-dec788a76f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461754612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2461754612
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3553023046
Short name T147
Test name
Test status
Simulation time 131534346698 ps
CPU time 474.39 seconds
Started Jul 17 05:54:13 PM PDT 24
Finished Jul 17 06:02:09 PM PDT 24
Peak memory 216500 kb
Host smart-929e5b49-b86d-45fd-ab29-c800832d9f96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553023046 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3553023046
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1097958050
Short name T55
Test name
Test status
Simulation time 277272423436 ps
CPU time 749.59 seconds
Started Jul 17 05:54:17 PM PDT 24
Finished Jul 17 06:06:47 PM PDT 24
Peak memory 226724 kb
Host smart-97a3cbd3-7382-4315-8223-8b15acd14b0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097958050 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1097958050
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3364968700
Short name T467
Test name
Test status
Simulation time 170270889808 ps
CPU time 162.18 seconds
Started Jul 17 05:54:10 PM PDT 24
Finished Jul 17 05:56:53 PM PDT 24
Peak memory 208320 kb
Host smart-75582b85-c8f7-44a4-9388-03654cf9b5b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364968700 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3364968700
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1523151316
Short name T181
Test name
Test status
Simulation time 9960008105 ps
CPU time 17.54 seconds
Started Jul 17 05:54:12 PM PDT 24
Finished Jul 17 05:54:31 PM PDT 24
Peak memory 199968 kb
Host smart-9d18f7fb-60ea-4261-b0db-7e55a01b0173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523151316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1523151316
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1503798163
Short name T1021
Test name
Test status
Simulation time 172386013452 ps
CPU time 360.92 seconds
Started Jul 17 05:54:10 PM PDT 24
Finished Jul 17 06:00:12 PM PDT 24
Peak memory 216132 kb
Host smart-a8cc2aa5-7061-499a-8eef-3ad6702a15d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503798163 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1503798163
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1672184702
Short name T937
Test name
Test status
Simulation time 142552203483 ps
CPU time 40.59 seconds
Started Jul 17 05:54:12 PM PDT 24
Finished Jul 17 05:54:55 PM PDT 24
Peak memory 199972 kb
Host smart-8d1b692d-a40f-41bf-a02e-82e0baf4148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672184702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1672184702
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1408464640
Short name T478
Test name
Test status
Simulation time 222153247788 ps
CPU time 711.37 seconds
Started Jul 17 05:54:10 PM PDT 24
Finished Jul 17 06:06:03 PM PDT 24
Peak memory 224892 kb
Host smart-2e403106-53f2-458c-9fe6-7a382e019d79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408464640 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1408464640
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2636737788
Short name T1102
Test name
Test status
Simulation time 8529465159 ps
CPU time 29.88 seconds
Started Jul 17 05:54:11 PM PDT 24
Finished Jul 17 05:54:43 PM PDT 24
Peak memory 199976 kb
Host smart-76cc98e1-e344-42e6-97de-d1ba9c606f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636737788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2636737788
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1060541077
Short name T1073
Test name
Test status
Simulation time 90576716979 ps
CPU time 148.78 seconds
Started Jul 17 05:54:12 PM PDT 24
Finished Jul 17 05:56:42 PM PDT 24
Peak memory 199920 kb
Host smart-dc7f95c7-e332-4f88-899e-4b174e7438d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060541077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1060541077
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2425809123
Short name T737
Test name
Test status
Simulation time 77592090745 ps
CPU time 1048.7 seconds
Started Jul 17 05:54:12 PM PDT 24
Finished Jul 17 06:11:43 PM PDT 24
Peak memory 216488 kb
Host smart-2a640e6e-f225-40f9-99d0-30cab74d6ec2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425809123 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2425809123
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.4200899746
Short name T856
Test name
Test status
Simulation time 59063556332 ps
CPU time 148.61 seconds
Started Jul 17 05:54:12 PM PDT 24
Finished Jul 17 05:56:42 PM PDT 24
Peak memory 199936 kb
Host smart-571c02e7-1186-4c13-88ac-d424187fdef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200899746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.4200899746
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.999919943
Short name T888
Test name
Test status
Simulation time 126646663163 ps
CPU time 707.57 seconds
Started Jul 17 05:54:18 PM PDT 24
Finished Jul 17 06:06:07 PM PDT 24
Peak memory 216396 kb
Host smart-1cd4870a-731f-4d45-8525-fca6b13f24d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999919943 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.999919943
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3214458506
Short name T1007
Test name
Test status
Simulation time 32860874 ps
CPU time 0.6 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:50:51 PM PDT 24
Peak memory 195512 kb
Host smart-7a42939a-cf52-4f13-ad61-4dcf2cc357fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214458506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3214458506
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3375626612
Short name T276
Test name
Test status
Simulation time 164752615234 ps
CPU time 309.54 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:55:58 PM PDT 24
Peak memory 199856 kb
Host smart-63b12b3c-eee8-404f-87f2-fe97078cb513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375626612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3375626612
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2364007294
Short name T313
Test name
Test status
Simulation time 190666261622 ps
CPU time 291.95 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:55:40 PM PDT 24
Peak memory 199916 kb
Host smart-c40ab07e-ac97-4d23-953d-8c75b47b83de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364007294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2364007294
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.343243703
Short name T536
Test name
Test status
Simulation time 37821073325 ps
CPU time 19.29 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:51:09 PM PDT 24
Peak memory 199888 kb
Host smart-b9aef4e5-5577-4901-94ab-546ed555d68f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343243703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.343243703
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.4013658967
Short name T788
Test name
Test status
Simulation time 104692057350 ps
CPU time 755.47 seconds
Started Jul 17 05:50:52 PM PDT 24
Finished Jul 17 06:03:28 PM PDT 24
Peak memory 199964 kb
Host smart-fc05c8cf-c9b8-4851-bbe3-01896e35f8c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013658967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.4013658967
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3315011336
Short name T504
Test name
Test status
Simulation time 10183101888 ps
CPU time 32.64 seconds
Started Jul 17 05:50:51 PM PDT 24
Finished Jul 17 05:51:25 PM PDT 24
Peak memory 199928 kb
Host smart-e55a0ef1-93d1-4dfd-b3dc-41ca676f745e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315011336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3315011336
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3513492547
Short name T456
Test name
Test status
Simulation time 63234334478 ps
CPU time 91.99 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:52:23 PM PDT 24
Peak memory 198712 kb
Host smart-dfa4d6da-a188-40b6-81d6-5d433a4dd1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513492547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3513492547
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1871117589
Short name T532
Test name
Test status
Simulation time 24023844650 ps
CPU time 63.11 seconds
Started Jul 17 05:50:49 PM PDT 24
Finished Jul 17 05:51:54 PM PDT 24
Peak memory 199836 kb
Host smart-dce9bf61-89c9-4da1-9d8d-e1dfa5f739cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1871117589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1871117589
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1062690024
Short name T355
Test name
Test status
Simulation time 6134370913 ps
CPU time 58.53 seconds
Started Jul 17 05:50:50 PM PDT 24
Finished Jul 17 05:51:50 PM PDT 24
Peak memory 198332 kb
Host smart-cf1dd970-77a5-4e44-b11b-1454613df874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062690024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1062690024
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2629598121
Short name T538
Test name
Test status
Simulation time 72358611873 ps
CPU time 29.42 seconds
Started Jul 17 05:50:49 PM PDT 24
Finished Jul 17 05:51:21 PM PDT 24
Peak memory 199972 kb
Host smart-dd4da4e5-d5d1-4443-8e1a-f76ead0f5471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629598121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2629598121
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1855178665
Short name T706
Test name
Test status
Simulation time 591070946 ps
CPU time 1.72 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:50:51 PM PDT 24
Peak memory 195400 kb
Host smart-7f07ad71-2285-4276-bb58-5873f1481d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855178665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1855178665
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.401140965
Short name T1118
Test name
Test status
Simulation time 5591766886 ps
CPU time 4.79 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:50:53 PM PDT 24
Peak memory 199956 kb
Host smart-e4ab7e51-e87a-422f-b79e-ec1b8ce87217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401140965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.401140965
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2942754892
Short name T1010
Test name
Test status
Simulation time 214356988902 ps
CPU time 576.45 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 06:00:26 PM PDT 24
Peak memory 216484 kb
Host smart-4e0217d3-7584-4142-80c5-7adbbfde9d97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942754892 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2942754892
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3888358299
Short name T603
Test name
Test status
Simulation time 1929154217 ps
CPU time 2.22 seconds
Started Jul 17 05:50:46 PM PDT 24
Finished Jul 17 05:50:50 PM PDT 24
Peak memory 199096 kb
Host smart-a59d2045-6413-4fcf-9dac-25b28e96feb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888358299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3888358299
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.4067992520
Short name T823
Test name
Test status
Simulation time 141575758098 ps
CPU time 76.23 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:52:04 PM PDT 24
Peak memory 199980 kb
Host smart-b5435071-e0ca-400e-bd71-cb13bd76e507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067992520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.4067992520
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.4254690850
Short name T626
Test name
Test status
Simulation time 82792278854 ps
CPU time 130.32 seconds
Started Jul 17 05:54:11 PM PDT 24
Finished Jul 17 05:56:23 PM PDT 24
Peak memory 199920 kb
Host smart-18d69bc2-ac24-46d8-8a4d-290309b9175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254690850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4254690850
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3827747667
Short name T1005
Test name
Test status
Simulation time 123824707668 ps
CPU time 747.32 seconds
Started Jul 17 05:54:15 PM PDT 24
Finished Jul 17 06:06:43 PM PDT 24
Peak memory 216136 kb
Host smart-fa7a2880-51f0-4043-9ef0-6fc9f763dbcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827747667 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3827747667
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.4283500763
Short name T271
Test name
Test status
Simulation time 11404733344 ps
CPU time 21.81 seconds
Started Jul 17 05:54:12 PM PDT 24
Finished Jul 17 05:54:35 PM PDT 24
Peak memory 199988 kb
Host smart-40fedc76-a552-4baa-9b45-0f8edb185f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283500763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4283500763
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1820007187
Short name T339
Test name
Test status
Simulation time 85616243785 ps
CPU time 253.73 seconds
Started Jul 17 05:54:18 PM PDT 24
Finished Jul 17 05:58:33 PM PDT 24
Peak memory 216424 kb
Host smart-84571ad2-f351-4328-abef-fcba867b53ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820007187 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1820007187
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.295191657
Short name T214
Test name
Test status
Simulation time 20557200498 ps
CPU time 29.97 seconds
Started Jul 17 05:54:09 PM PDT 24
Finished Jul 17 05:54:39 PM PDT 24
Peak memory 199924 kb
Host smart-b2f4347e-52b5-42af-aaf5-6005593e999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295191657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.295191657
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.810711101
Short name T424
Test name
Test status
Simulation time 25407131639 ps
CPU time 20.39 seconds
Started Jul 17 05:54:11 PM PDT 24
Finished Jul 17 05:54:32 PM PDT 24
Peak memory 199588 kb
Host smart-62c579a2-0707-4590-90a8-eee884250cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810711101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.810711101
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.77406204
Short name T150
Test name
Test status
Simulation time 18754319161 ps
CPU time 177.56 seconds
Started Jul 17 05:54:12 PM PDT 24
Finished Jul 17 05:57:11 PM PDT 24
Peak memory 216500 kb
Host smart-c478788f-6749-4894-905f-eeff7b44fde3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77406204 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.77406204
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1209097981
Short name T254
Test name
Test status
Simulation time 73452946776 ps
CPU time 25.36 seconds
Started Jul 17 05:54:10 PM PDT 24
Finished Jul 17 05:54:36 PM PDT 24
Peak memory 199864 kb
Host smart-488f5a67-e06c-41a9-b468-f52dfc790309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209097981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1209097981
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.640942083
Short name T736
Test name
Test status
Simulation time 32918336679 ps
CPU time 309.35 seconds
Started Jul 17 05:54:11 PM PDT 24
Finished Jul 17 05:59:23 PM PDT 24
Peak memory 216420 kb
Host smart-c5db5844-8149-4e22-9b42-a0e7741aa0f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640942083 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.640942083
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.494767874
Short name T106
Test name
Test status
Simulation time 26772923599 ps
CPU time 10.79 seconds
Started Jul 17 05:54:14 PM PDT 24
Finished Jul 17 05:54:26 PM PDT 24
Peak memory 199708 kb
Host smart-cfd9cbfa-9883-4cc8-8771-a5b5e10ca467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494767874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.494767874
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2601446220
Short name T221
Test name
Test status
Simulation time 82270263601 ps
CPU time 497.41 seconds
Started Jul 17 05:54:11 PM PDT 24
Finished Jul 17 06:02:31 PM PDT 24
Peak memory 216696 kb
Host smart-cefd506c-b17b-46dd-9ea5-9b03b55db028
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601446220 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2601446220
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2668391919
Short name T190
Test name
Test status
Simulation time 121367374379 ps
CPU time 179.27 seconds
Started Jul 17 05:54:15 PM PDT 24
Finished Jul 17 05:57:15 PM PDT 24
Peak memory 199944 kb
Host smart-b5491987-d1b5-4584-bb23-31bf3969bf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668391919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2668391919
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1970920655
Short name T1101
Test name
Test status
Simulation time 38442672573 ps
CPU time 659.87 seconds
Started Jul 17 05:54:14 PM PDT 24
Finished Jul 17 06:05:15 PM PDT 24
Peak memory 216720 kb
Host smart-5ebb9230-cdae-4374-8b1e-7e421058a969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970920655 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1970920655
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.372797850
Short name T923
Test name
Test status
Simulation time 23207576085 ps
CPU time 174.64 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 05:57:23 PM PDT 24
Peak memory 216352 kb
Host smart-2c3f8760-4370-4d20-8e19-e05d1dfb5c44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372797850 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.372797850
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2866130213
Short name T714
Test name
Test status
Simulation time 18740457328 ps
CPU time 7.66 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 05:54:36 PM PDT 24
Peak memory 199968 kb
Host smart-c11dc42c-d4ae-4787-8e18-bbedd64d446e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866130213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2866130213
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3444548683
Short name T73
Test name
Test status
Simulation time 17325170580 ps
CPU time 228.98 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 05:58:17 PM PDT 24
Peak memory 215832 kb
Host smart-b8a89a12-6a51-41b0-8ada-f38bc5762475
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444548683 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3444548683
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1910801600
Short name T1016
Test name
Test status
Simulation time 54533576023 ps
CPU time 20 seconds
Started Jul 17 05:54:23 PM PDT 24
Finished Jul 17 05:54:44 PM PDT 24
Peak memory 199264 kb
Host smart-d4785400-d002-4c11-b76b-36f198197c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910801600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1910801600
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2595488892
Short name T52
Test name
Test status
Simulation time 83207713173 ps
CPU time 1772.62 seconds
Started Jul 17 05:54:23 PM PDT 24
Finished Jul 17 06:23:57 PM PDT 24
Peak memory 216492 kb
Host smart-94c72f45-de34-4739-9cb4-7a43fc956b93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595488892 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2595488892
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3940595258
Short name T528
Test name
Test status
Simulation time 60456179 ps
CPU time 0.56 seconds
Started Jul 17 05:51:02 PM PDT 24
Finished Jul 17 05:51:04 PM PDT 24
Peak memory 194480 kb
Host smart-c30907e9-58a6-42e4-9bb2-7052fb342a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940595258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3940595258
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.887451879
Short name T722
Test name
Test status
Simulation time 206931270873 ps
CPU time 75.55 seconds
Started Jul 17 05:50:52 PM PDT 24
Finished Jul 17 05:52:08 PM PDT 24
Peak memory 199952 kb
Host smart-30433199-af56-48e2-93a4-7ca6f9b4107d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887451879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.887451879
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.859218252
Short name T747
Test name
Test status
Simulation time 17627218039 ps
CPU time 16.69 seconds
Started Jul 17 05:50:49 PM PDT 24
Finished Jul 17 05:51:08 PM PDT 24
Peak memory 199628 kb
Host smart-141d48e5-e78f-458d-8a01-21d569974e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859218252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.859218252
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.348933128
Short name T627
Test name
Test status
Simulation time 31894584656 ps
CPU time 25.31 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:51:14 PM PDT 24
Peak memory 199980 kb
Host smart-d73d9ce3-208f-4805-ad3e-fba2492a23bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348933128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.348933128
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2117351895
Short name T834
Test name
Test status
Simulation time 234277665945 ps
CPU time 223.67 seconds
Started Jul 17 05:50:45 PM PDT 24
Finished Jul 17 05:54:30 PM PDT 24
Peak memory 199932 kb
Host smart-28f45cbc-98fa-4e32-8916-fd360eb872b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117351895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2117351895
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.734058294
Short name T829
Test name
Test status
Simulation time 135258532848 ps
CPU time 800.13 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 06:04:25 PM PDT 24
Peak memory 199876 kb
Host smart-3e63328c-0b15-4e99-8800-2dd325d65206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734058294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.734058294
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3820385115
Short name T463
Test name
Test status
Simulation time 7507247680 ps
CPU time 17.6 seconds
Started Jul 17 05:50:50 PM PDT 24
Finished Jul 17 05:51:09 PM PDT 24
Peak memory 199592 kb
Host smart-e8d6ebe4-3b74-425d-840f-d2ab84173301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820385115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3820385115
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1665475925
Short name T400
Test name
Test status
Simulation time 26629178221 ps
CPU time 12.2 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:51:01 PM PDT 24
Peak memory 198120 kb
Host smart-9c2be896-0fee-447f-bf7e-efb0cf50e04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665475925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1665475925
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1382528227
Short name T595
Test name
Test status
Simulation time 3647687694 ps
CPU time 162.54 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:53:32 PM PDT 24
Peak memory 199980 kb
Host smart-66e7a1d5-6e65-4fba-bca4-df8d8a44741f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1382528227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1382528227
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2040237104
Short name T700
Test name
Test status
Simulation time 3046750929 ps
CPU time 15.15 seconds
Started Jul 17 05:50:49 PM PDT 24
Finished Jul 17 05:51:06 PM PDT 24
Peak memory 197964 kb
Host smart-d25bf3df-205b-4a71-93ac-19814e9b1f34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040237104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2040237104
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.4127303388
Short name T1092
Test name
Test status
Simulation time 29542534712 ps
CPU time 26.93 seconds
Started Jul 17 05:50:47 PM PDT 24
Finished Jul 17 05:51:16 PM PDT 24
Peak memory 199976 kb
Host smart-a2d12045-174e-45d5-9bd1-08841a0bf379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127303388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.4127303388
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2428006589
Short name T607
Test name
Test status
Simulation time 5658526769 ps
CPU time 5.01 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:50:55 PM PDT 24
Peak memory 196016 kb
Host smart-b532bb20-12e3-4551-a89d-c8827fd8cee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428006589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2428006589
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.79707727
Short name T1002
Test name
Test status
Simulation time 5289126332 ps
CPU time 11.63 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:51:01 PM PDT 24
Peak memory 199956 kb
Host smart-20758709-b3f8-443e-9c97-433836794460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79707727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.79707727
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3662347387
Short name T1135
Test name
Test status
Simulation time 327602274427 ps
CPU time 360.15 seconds
Started Jul 17 05:51:01 PM PDT 24
Finished Jul 17 05:57:03 PM PDT 24
Peak memory 199896 kb
Host smart-5ca4bf20-4e7e-48c7-9c5e-a6a91eab08a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662347387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3662347387
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2845472268
Short name T56
Test name
Test status
Simulation time 509434506120 ps
CPU time 1024.01 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 06:08:10 PM PDT 24
Peak memory 229968 kb
Host smart-84aee3ab-f3cb-4d38-a837-f6071203bf9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845472268 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2845472268
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.228385211
Short name T812
Test name
Test status
Simulation time 655643139 ps
CPU time 1.61 seconds
Started Jul 17 05:50:48 PM PDT 24
Finished Jul 17 05:50:52 PM PDT 24
Peak memory 199736 kb
Host smart-483242ea-996c-4118-bbf3-99d0eded6e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228385211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.228385211
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1361621171
Short name T317
Test name
Test status
Simulation time 59613243949 ps
CPU time 63.55 seconds
Started Jul 17 05:50:45 PM PDT 24
Finished Jul 17 05:51:49 PM PDT 24
Peak memory 199972 kb
Host smart-1406f419-5ca3-45d2-9e68-fbd8eb008544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361621171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1361621171
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2771477075
Short name T1144
Test name
Test status
Simulation time 76051039175 ps
CPU time 95.11 seconds
Started Jul 17 05:54:24 PM PDT 24
Finished Jul 17 05:56:00 PM PDT 24
Peak memory 199936 kb
Host smart-e8222d97-c9b8-443e-8b32-575d0f9d4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771477075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2771477075
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3343563075
Short name T1125
Test name
Test status
Simulation time 41184781258 ps
CPU time 629.48 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 06:04:58 PM PDT 24
Peak memory 216360 kb
Host smart-657bb63a-24af-4397-b421-427ebf7662eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343563075 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3343563075
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1132220222
Short name T279
Test name
Test status
Simulation time 49132892709 ps
CPU time 22.48 seconds
Started Jul 17 05:54:25 PM PDT 24
Finished Jul 17 05:54:49 PM PDT 24
Peak memory 199908 kb
Host smart-1e43a97c-f762-493c-a4f8-6168196ef086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132220222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1132220222
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2861966826
Short name T108
Test name
Test status
Simulation time 14703528447 ps
CPU time 172.05 seconds
Started Jul 17 05:54:25 PM PDT 24
Finished Jul 17 05:57:20 PM PDT 24
Peak memory 215592 kb
Host smart-3bcc661f-352c-49f1-9442-682ff2604541
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861966826 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2861966826
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3122728747
Short name T727
Test name
Test status
Simulation time 76059269635 ps
CPU time 19.4 seconds
Started Jul 17 05:54:24 PM PDT 24
Finished Jul 17 05:54:45 PM PDT 24
Peak memory 199912 kb
Host smart-e78ea8a7-7ef7-45c2-b977-30af5c57d3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122728747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3122728747
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.862906465
Short name T544
Test name
Test status
Simulation time 87730495016 ps
CPU time 846.69 seconds
Started Jul 17 05:54:24 PM PDT 24
Finished Jul 17 06:08:31 PM PDT 24
Peak memory 227928 kb
Host smart-21fab52b-c7c3-4877-b945-f09ff2d294fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862906465 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.862906465
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2844334926
Short name T933
Test name
Test status
Simulation time 48623401922 ps
CPU time 45.67 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 05:55:15 PM PDT 24
Peak memory 199980 kb
Host smart-3e03e3e7-b8ea-4ec8-bf1c-cc691206714d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844334926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2844334926
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3118335262
Short name T542
Test name
Test status
Simulation time 20586212306 ps
CPU time 283.41 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 05:59:12 PM PDT 24
Peak memory 215604 kb
Host smart-b53e58fc-82a5-457b-b3cb-18e4ea2dfd52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118335262 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3118335262
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2490305178
Short name T884
Test name
Test status
Simulation time 50988991722 ps
CPU time 83.52 seconds
Started Jul 17 05:54:20 PM PDT 24
Finished Jul 17 05:55:45 PM PDT 24
Peak memory 199944 kb
Host smart-3f611885-8a82-4246-941f-a826e63932fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490305178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2490305178
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.4128174864
Short name T1017
Test name
Test status
Simulation time 309659990303 ps
CPU time 1062.15 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 06:12:11 PM PDT 24
Peak memory 225192 kb
Host smart-054aeafd-b792-4aa5-808c-20a2ca9c08e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128174864 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.4128174864
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2036455063
Short name T193
Test name
Test status
Simulation time 68640445445 ps
CPU time 149.01 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 05:56:57 PM PDT 24
Peak memory 199928 kb
Host smart-d67532ea-272c-4cfc-8d9d-963a0183a55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036455063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2036455063
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2151216412
Short name T857
Test name
Test status
Simulation time 75980238577 ps
CPU time 648.95 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 06:05:17 PM PDT 24
Peak memory 224840 kb
Host smart-57ba19c7-1cca-47fc-83e9-7cb5045c6a57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151216412 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2151216412
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.898504480
Short name T297
Test name
Test status
Simulation time 225909029313 ps
CPU time 221.32 seconds
Started Jul 17 05:54:27 PM PDT 24
Finished Jul 17 05:58:10 PM PDT 24
Peak memory 216460 kb
Host smart-9e2be7b3-673b-4674-8573-4f206817ddaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898504480 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.898504480
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3738157076
Short name T352
Test name
Test status
Simulation time 63197350079 ps
CPU time 19.12 seconds
Started Jul 17 05:54:29 PM PDT 24
Finished Jul 17 05:54:50 PM PDT 24
Peak memory 199932 kb
Host smart-3b4a20a4-0ba0-48e5-baec-d23c0bd449c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738157076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3738157076
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3716333974
Short name T477
Test name
Test status
Simulation time 366657319739 ps
CPU time 1809.11 seconds
Started Jul 17 05:54:25 PM PDT 24
Finished Jul 17 06:24:36 PM PDT 24
Peak memory 227684 kb
Host smart-e7cb7388-ff80-4ca8-b3b5-19cf5e013294
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716333974 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3716333974
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1452165941
Short name T746
Test name
Test status
Simulation time 42483302165 ps
CPU time 21.62 seconds
Started Jul 17 05:54:24 PM PDT 24
Finished Jul 17 05:54:47 PM PDT 24
Peak memory 199920 kb
Host smart-a707060d-6080-45a6-8767-5c471c02aa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452165941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1452165941
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.132792503
Short name T612
Test name
Test status
Simulation time 76398040082 ps
CPU time 705.98 seconds
Started Jul 17 05:54:25 PM PDT 24
Finished Jul 17 06:06:14 PM PDT 24
Peak memory 216680 kb
Host smart-0f80646f-da98-4b3f-ae54-22c3924a785e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132792503 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.132792503
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1068629541
Short name T520
Test name
Test status
Simulation time 121317534271 ps
CPU time 50.73 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 05:55:19 PM PDT 24
Peak memory 199820 kb
Host smart-a8664d74-f481-41c3-bfa3-943e22af5cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068629541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1068629541
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2629359957
Short name T348
Test name
Test status
Simulation time 195121342082 ps
CPU time 434.55 seconds
Started Jul 17 05:54:28 PM PDT 24
Finished Jul 17 06:01:44 PM PDT 24
Peak memory 216436 kb
Host smart-66f87ed0-131a-41ce-9d0c-fc1b96e327cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629359957 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2629359957
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3912106845
Short name T587
Test name
Test status
Simulation time 16226894 ps
CPU time 0.6 seconds
Started Jul 17 05:51:04 PM PDT 24
Finished Jul 17 05:51:08 PM PDT 24
Peak memory 195292 kb
Host smart-2cb45dfc-aa6b-4fa3-bacf-674d2b035a6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912106845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3912106845
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3916393641
Short name T614
Test name
Test status
Simulation time 145222084025 ps
CPU time 282.93 seconds
Started Jul 17 05:51:04 PM PDT 24
Finished Jul 17 05:55:49 PM PDT 24
Peak memory 199964 kb
Host smart-3e441bc2-e59d-474c-8af8-093bf0b54fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916393641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3916393641
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.546532574
Short name T639
Test name
Test status
Simulation time 34477910839 ps
CPU time 30.5 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 05:51:35 PM PDT 24
Peak memory 199872 kb
Host smart-1616a296-e8d7-44a0-8733-aad3f1323c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546532574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.546532574
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3806929204
Short name T761
Test name
Test status
Simulation time 35663789153 ps
CPU time 52.75 seconds
Started Jul 17 05:51:02 PM PDT 24
Finished Jul 17 05:51:57 PM PDT 24
Peak memory 199976 kb
Host smart-dcb9247c-e302-49a3-be93-37a187d89e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806929204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3806929204
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3284268673
Short name T1129
Test name
Test status
Simulation time 590621475664 ps
CPU time 217.94 seconds
Started Jul 17 05:51:04 PM PDT 24
Finished Jul 17 05:54:44 PM PDT 24
Peak memory 199884 kb
Host smart-9eceaa42-cbcd-406f-8d79-a285def91ff6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284268673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3284268673
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.132803504
Short name T1031
Test name
Test status
Simulation time 78191930404 ps
CPU time 505.31 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 05:59:32 PM PDT 24
Peak memory 199912 kb
Host smart-c70e7650-1d72-45ed-a651-b70b7dec2573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=132803504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.132803504
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2715920258
Short name T956
Test name
Test status
Simulation time 11597845591 ps
CPU time 10.58 seconds
Started Jul 17 05:51:04 PM PDT 24
Finished Jul 17 05:51:17 PM PDT 24
Peak memory 199368 kb
Host smart-a689d69d-8188-49da-a403-1cafb03d41a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715920258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2715920258
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3848045296
Short name T305
Test name
Test status
Simulation time 32293281958 ps
CPU time 49.31 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 05:51:55 PM PDT 24
Peak memory 198320 kb
Host smart-c77fb53b-17f6-4968-8e5b-68c8e48f26b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848045296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3848045296
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2406948901
Short name T509
Test name
Test status
Simulation time 13931785620 ps
CPU time 160.3 seconds
Started Jul 17 05:51:02 PM PDT 24
Finished Jul 17 05:53:44 PM PDT 24
Peak memory 199668 kb
Host smart-df9773de-fe15-41ee-8ecf-5ee1ae0d6e56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2406948901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2406948901
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1893120869
Short name T383
Test name
Test status
Simulation time 1583683194 ps
CPU time 6.13 seconds
Started Jul 17 05:51:02 PM PDT 24
Finished Jul 17 05:51:10 PM PDT 24
Peak memory 197752 kb
Host smart-43f19fc4-239a-40b5-81b1-f3a44001e76d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893120869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1893120869
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1526336389
Short name T164
Test name
Test status
Simulation time 33887878012 ps
CPU time 19.43 seconds
Started Jul 17 05:51:06 PM PDT 24
Finished Jul 17 05:51:28 PM PDT 24
Peak memory 199972 kb
Host smart-cd5661af-c6d9-4507-bf62-eba84fe35616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526336389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1526336389
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2354027358
Short name T1111
Test name
Test status
Simulation time 2011463073 ps
CPU time 1.32 seconds
Started Jul 17 05:51:04 PM PDT 24
Finished Jul 17 05:51:08 PM PDT 24
Peak memory 195328 kb
Host smart-eef11217-6b4a-4ce9-a0e8-72dbebde093c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354027358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2354027358
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.905545705
Short name T671
Test name
Test status
Simulation time 5554782353 ps
CPU time 28.91 seconds
Started Jul 17 05:51:04 PM PDT 24
Finished Jul 17 05:51:35 PM PDT 24
Peak memory 199684 kb
Host smart-43519cfb-41e5-44c9-ab0f-2ea053c5f9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905545705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.905545705
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1978157376
Short name T753
Test name
Test status
Simulation time 269409281903 ps
CPU time 1301.12 seconds
Started Jul 17 05:51:06 PM PDT 24
Finished Jul 17 06:12:50 PM PDT 24
Peak memory 199860 kb
Host smart-c763482d-167e-4fe9-b7fa-1cc6471c0115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978157376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1978157376
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1007321866
Short name T995
Test name
Test status
Simulation time 1200269256 ps
CPU time 6.44 seconds
Started Jul 17 05:51:07 PM PDT 24
Finished Jul 17 05:51:15 PM PDT 24
Peak memory 216300 kb
Host smart-6ed70869-5a2f-432b-9c9c-37a087b11988
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007321866 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1007321866
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.4063865046
Short name T535
Test name
Test status
Simulation time 6897546313 ps
CPU time 18.53 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 05:51:23 PM PDT 24
Peak memory 199784 kb
Host smart-2b586a92-2e97-4d53-bc07-567ca9cbef39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063865046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.4063865046
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3578458728
Short name T552
Test name
Test status
Simulation time 110685051197 ps
CPU time 214.45 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 05:54:40 PM PDT 24
Peak memory 199908 kb
Host smart-8f95fb4e-0a44-4ccd-8beb-501f7490e5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578458728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3578458728
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.264341193
Short name T938
Test name
Test status
Simulation time 178656019683 ps
CPU time 46.43 seconds
Started Jul 17 05:54:21 PM PDT 24
Finished Jul 17 05:55:08 PM PDT 24
Peak memory 200196 kb
Host smart-920a3770-c3aa-45d2-9187-30451c5f0c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264341193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.264341193
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2960064448
Short name T726
Test name
Test status
Simulation time 23773231079 ps
CPU time 282.44 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 05:59:11 PM PDT 24
Peak memory 215972 kb
Host smart-7a89f45d-a63a-4b21-95aa-b680fe33b1e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960064448 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2960064448
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2352106759
Short name T1106
Test name
Test status
Simulation time 28868429495 ps
CPU time 23.48 seconds
Started Jul 17 05:54:23 PM PDT 24
Finished Jul 17 05:54:48 PM PDT 24
Peak memory 199988 kb
Host smart-d38a613c-8c69-4d1c-aedf-658a06bc8b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352106759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2352106759
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1039410473
Short name T201
Test name
Test status
Simulation time 20758928174 ps
CPU time 29.47 seconds
Started Jul 17 05:54:23 PM PDT 24
Finished Jul 17 05:54:53 PM PDT 24
Peak memory 199664 kb
Host smart-0f6fe970-fd9a-43ec-82e2-309307bea7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039410473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1039410473
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3497369769
Short name T891
Test name
Test status
Simulation time 30843183764 ps
CPU time 799.54 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 06:07:48 PM PDT 24
Peak memory 216624 kb
Host smart-3d2eb02f-5e51-4be1-840f-322931a710a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497369769 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3497369769
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1993545146
Short name T115
Test name
Test status
Simulation time 5680870337 ps
CPU time 36.84 seconds
Started Jul 17 05:54:24 PM PDT 24
Finished Jul 17 05:55:02 PM PDT 24
Peak memory 208516 kb
Host smart-42bfd48c-cb3f-4bf3-955b-3897e33f3d5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993545146 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1993545146
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3531198190
Short name T767
Test name
Test status
Simulation time 10820208173 ps
CPU time 10.73 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 05:54:40 PM PDT 24
Peak memory 199988 kb
Host smart-8b9738d1-5b94-49ed-97c5-8c8d7c0ca7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531198190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3531198190
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1025713040
Short name T519
Test name
Test status
Simulation time 117022854485 ps
CPU time 386.69 seconds
Started Jul 17 05:54:25 PM PDT 24
Finished Jul 17 06:00:53 PM PDT 24
Peak memory 216592 kb
Host smart-90e8534a-ed8f-4958-b428-01379d89ba96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025713040 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1025713040
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.586075477
Short name T199
Test name
Test status
Simulation time 7168827659 ps
CPU time 18.77 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 05:54:47 PM PDT 24
Peak memory 199756 kb
Host smart-56bc3e42-a36e-4a74-85ba-792be1d6922c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586075477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.586075477
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3387281858
Short name T869
Test name
Test status
Simulation time 125165350428 ps
CPU time 260.55 seconds
Started Jul 17 05:54:25 PM PDT 24
Finished Jul 17 05:58:48 PM PDT 24
Peak memory 214940 kb
Host smart-cf9dc6d9-2ffc-4a03-a3f9-9f6d67c31892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387281858 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3387281858
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.769028414
Short name T952
Test name
Test status
Simulation time 182857996338 ps
CPU time 850.47 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 06:08:38 PM PDT 24
Peak memory 216428 kb
Host smart-752987f4-ec19-44f1-94ac-fd0c85bd49f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769028414 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.769028414
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1162011866
Short name T151
Test name
Test status
Simulation time 34957932715 ps
CPU time 16.81 seconds
Started Jul 17 05:54:20 PM PDT 24
Finished Jul 17 05:54:37 PM PDT 24
Peak memory 199976 kb
Host smart-3bd1cabe-7b1b-44eb-87ae-291a849f081b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162011866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1162011866
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1105027256
Short name T54
Test name
Test status
Simulation time 150077653806 ps
CPU time 582.34 seconds
Started Jul 17 05:54:23 PM PDT 24
Finished Jul 17 06:04:07 PM PDT 24
Peak memory 224892 kb
Host smart-6ab756c8-e871-4674-bc99-202a3e1633c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105027256 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1105027256
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3560179546
Short name T127
Test name
Test status
Simulation time 11651057691 ps
CPU time 31.7 seconds
Started Jul 17 05:54:26 PM PDT 24
Finished Jul 17 05:55:00 PM PDT 24
Peak memory 199908 kb
Host smart-a7cf713f-bb6e-4226-a3df-8f497d7da91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560179546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3560179546
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.341684941
Short name T161
Test name
Test status
Simulation time 141044131360 ps
CPU time 570.58 seconds
Started Jul 17 05:54:28 PM PDT 24
Finished Jul 17 06:04:00 PM PDT 24
Peak memory 216588 kb
Host smart-efda36ae-6081-43b8-98d5-2954433155df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341684941 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.341684941
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.713782774
Short name T241
Test name
Test status
Simulation time 113578201176 ps
CPU time 42.68 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:55:24 PM PDT 24
Peak memory 199844 kb
Host smart-854a8638-fa19-4da8-9dd0-e72c0f37ade6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713782774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.713782774
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1515741770
Short name T105
Test name
Test status
Simulation time 291004604702 ps
CPU time 1148.92 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 06:13:51 PM PDT 24
Peak memory 216324 kb
Host smart-19e1ba92-1ae7-4907-932e-24aa0a9c7235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515741770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1515741770
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.501891314
Short name T653
Test name
Test status
Simulation time 39002035 ps
CPU time 0.56 seconds
Started Jul 17 05:51:06 PM PDT 24
Finished Jul 17 05:51:09 PM PDT 24
Peak memory 194564 kb
Host smart-824965d1-9101-44db-bc2e-6d9dae34dad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501891314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.501891314
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1271068457
Short name T560
Test name
Test status
Simulation time 127119255897 ps
CPU time 196.33 seconds
Started Jul 17 05:51:02 PM PDT 24
Finished Jul 17 05:54:21 PM PDT 24
Peak memory 199964 kb
Host smart-76f4312f-8b67-4b2e-944a-62cb266ed614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271068457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1271068457
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3831384691
Short name T1064
Test name
Test status
Simulation time 34885141112 ps
CPU time 24.77 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 05:51:30 PM PDT 24
Peak memory 199640 kb
Host smart-81831e9d-00d3-4d08-94c4-88b84cbc8ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831384691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3831384691
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3612002464
Short name T155
Test name
Test status
Simulation time 174215495202 ps
CPU time 258.89 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 05:55:24 PM PDT 24
Peak memory 199916 kb
Host smart-5e66ed0c-0367-4a9a-acc0-47407e73b500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612002464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3612002464
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.4211144774
Short name T451
Test name
Test status
Simulation time 19236393205 ps
CPU time 9 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 05:51:14 PM PDT 24
Peak memory 197752 kb
Host smart-af2b94dd-b925-4509-bd84-d906cde9ca4d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211144774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4211144774
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2859651139
Short name T1121
Test name
Test status
Simulation time 33302277660 ps
CPU time 54.17 seconds
Started Jul 17 05:51:04 PM PDT 24
Finished Jul 17 05:52:01 PM PDT 24
Peak memory 199792 kb
Host smart-1dcbac34-12bc-40c4-8910-afc498c32bc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2859651139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2859651139
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.4231917286
Short name T1
Test name
Test status
Simulation time 9137082014 ps
CPU time 8.6 seconds
Started Jul 17 05:51:02 PM PDT 24
Finished Jul 17 05:51:11 PM PDT 24
Peak memory 199704 kb
Host smart-358df64e-5424-4e0c-9066-f2e7c29ff7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231917286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4231917286
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1910915652
Short name T684
Test name
Test status
Simulation time 12312492915 ps
CPU time 22.92 seconds
Started Jul 17 05:51:04 PM PDT 24
Finished Jul 17 05:51:30 PM PDT 24
Peak memory 198580 kb
Host smart-3538760b-6c81-43cd-a1ca-faf23fd193cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910915652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1910915652
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2726584666
Short name T633
Test name
Test status
Simulation time 10646513798 ps
CPU time 514.77 seconds
Started Jul 17 05:51:03 PM PDT 24
Finished Jul 17 05:59:40 PM PDT 24
Peak memory 199904 kb
Host smart-48ed8087-27e9-47d2-a31b-700a9f922266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726584666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2726584666
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.129328638
Short name T771
Test name
Test status
Simulation time 5513914726 ps
CPU time 3.51 seconds
Started Jul 17 05:51:02 PM PDT 24
Finished Jul 17 05:51:08 PM PDT 24
Peak memory 198760 kb
Host smart-122a9242-6646-47a3-a4e5-7c5afb28b0b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=129328638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.129328638
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.93003991
Short name T1072
Test name
Test status
Simulation time 13979006784 ps
CPU time 19.75 seconds
Started Jul 17 05:51:02 PM PDT 24
Finished Jul 17 05:51:23 PM PDT 24
Peak memory 199928 kb
Host smart-eff78e2f-3d03-4aa5-a1cb-214fdd364027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93003991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.93003991
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1965431586
Short name T510
Test name
Test status
Simulation time 42517845463 ps
CPU time 18.02 seconds
Started Jul 17 05:51:08 PM PDT 24
Finished Jul 17 05:51:28 PM PDT 24
Peak memory 196716 kb
Host smart-1ce7ac06-c6bc-4c93-aeb2-54d11c0c2309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965431586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1965431586
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1330829279
Short name T705
Test name
Test status
Simulation time 5689667709 ps
CPU time 7.04 seconds
Started Jul 17 05:51:04 PM PDT 24
Finished Jul 17 05:51:14 PM PDT 24
Peak memory 199780 kb
Host smart-bf92f052-586b-462a-820c-3d00d9c9b234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330829279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1330829279
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.747623668
Short name T975
Test name
Test status
Simulation time 101523016366 ps
CPU time 861.59 seconds
Started Jul 17 05:51:08 PM PDT 24
Finished Jul 17 06:05:32 PM PDT 24
Peak memory 199956 kb
Host smart-d6fa8a5c-f961-4546-bd1c-e0ec92da45c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747623668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.747623668
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2188671051
Short name T99
Test name
Test status
Simulation time 1450692099 ps
CPU time 1.98 seconds
Started Jul 17 05:51:06 PM PDT 24
Finished Jul 17 05:51:10 PM PDT 24
Peak memory 198520 kb
Host smart-f31d38eb-837d-4f91-8df1-c31fbf3f1b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188671051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2188671051
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2653338807
Short name T808
Test name
Test status
Simulation time 37644734482 ps
CPU time 20.76 seconds
Started Jul 17 05:51:05 PM PDT 24
Finished Jul 17 05:51:29 PM PDT 24
Peak memory 199840 kb
Host smart-25a870d5-8f20-4b83-80a9-65f849616714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653338807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2653338807
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3781687018
Short name T764
Test name
Test status
Simulation time 9309559114 ps
CPU time 17.04 seconds
Started Jul 17 05:54:38 PM PDT 24
Finished Jul 17 05:54:57 PM PDT 24
Peak memory 199924 kb
Host smart-834945e2-4c7c-4260-bc01-8dba789b5c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781687018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3781687018
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2632687775
Short name T676
Test name
Test status
Simulation time 31277591293 ps
CPU time 189.71 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 05:57:53 PM PDT 24
Peak memory 215504 kb
Host smart-993ea2e3-2e4e-47ac-b741-6998893f0a90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632687775 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2632687775
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3609517498
Short name T518
Test name
Test status
Simulation time 40408533750 ps
CPU time 91.02 seconds
Started Jul 17 05:54:41 PM PDT 24
Finished Jul 17 05:56:15 PM PDT 24
Peak memory 199836 kb
Host smart-f036d77a-21c8-40a4-97ba-10ed04780edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609517498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3609517498
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3406335436
Short name T1147
Test name
Test status
Simulation time 99655068519 ps
CPU time 473.73 seconds
Started Jul 17 05:54:43 PM PDT 24
Finished Jul 17 06:02:39 PM PDT 24
Peak memory 216628 kb
Host smart-916d7169-8423-4817-9318-4dacd0800adc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406335436 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3406335436
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2382497946
Short name T838
Test name
Test status
Simulation time 70220167217 ps
CPU time 48.63 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:55:31 PM PDT 24
Peak memory 199784 kb
Host smart-52fd2f14-339d-4e55-ad5f-4692a6d9af69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382497946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2382497946
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.114868077
Short name T690
Test name
Test status
Simulation time 88470786824 ps
CPU time 643.08 seconds
Started Jul 17 05:54:43 PM PDT 24
Finished Jul 17 06:05:28 PM PDT 24
Peak memory 224904 kb
Host smart-4cdd8cb1-8a57-401b-a3c4-b01ed0d007cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114868077 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.114868077
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3569648405
Short name T336
Test name
Test status
Simulation time 85481943382 ps
CPU time 65.73 seconds
Started Jul 17 05:54:38 PM PDT 24
Finished Jul 17 05:55:44 PM PDT 24
Peak memory 199856 kb
Host smart-145df472-7362-4b98-9f77-630730ee41bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569648405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3569648405
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1624109344
Short name T1067
Test name
Test status
Simulation time 96711438964 ps
CPU time 2508.78 seconds
Started Jul 17 05:54:36 PM PDT 24
Finished Jul 17 06:36:25 PM PDT 24
Peak memory 214812 kb
Host smart-8b83c073-6475-44a5-9914-e78b9f33065b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624109344 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1624109344
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2302769999
Short name T187
Test name
Test status
Simulation time 41714367273 ps
CPU time 57.71 seconds
Started Jul 17 05:54:41 PM PDT 24
Finished Jul 17 05:55:42 PM PDT 24
Peak memory 199892 kb
Host smart-413165bf-de11-4919-b6b0-a2f161257782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302769999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2302769999
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2408892709
Short name T446
Test name
Test status
Simulation time 70320175658 ps
CPU time 256.7 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:58:59 PM PDT 24
Peak memory 208336 kb
Host smart-ef1be806-a295-4912-8e02-0e8cec448bd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408892709 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2408892709
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2032161812
Short name T235
Test name
Test status
Simulation time 30833671625 ps
CPU time 13.21 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 05:54:57 PM PDT 24
Peak memory 199776 kb
Host smart-a73be39d-9620-4d2b-b3ec-14774feddc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032161812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2032161812
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.174357580
Short name T958
Test name
Test status
Simulation time 337126719041 ps
CPU time 962.82 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 06:10:44 PM PDT 24
Peak memory 216404 kb
Host smart-1c563059-39fa-4ecb-8c12-71e75ac7adb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174357580 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.174357580
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1660324502
Short name T1158
Test name
Test status
Simulation time 82149703659 ps
CPU time 23.42 seconds
Started Jul 17 05:54:40 PM PDT 24
Finished Jul 17 05:55:06 PM PDT 24
Peak memory 199928 kb
Host smart-37469b83-75d4-46f0-aeeb-183a5513b475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660324502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1660324502
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3529856017
Short name T30
Test name
Test status
Simulation time 57676945116 ps
CPU time 353.93 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 06:00:34 PM PDT 24
Peak memory 208584 kb
Host smart-77527cde-c4a0-4524-b29e-6e8df37877b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529856017 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3529856017
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.4228150278
Short name T213
Test name
Test status
Simulation time 57836164842 ps
CPU time 42.64 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:55:25 PM PDT 24
Peak memory 199924 kb
Host smart-75e30ac3-b230-442e-9074-65bb45d551ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228150278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.4228150278
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2184651263
Short name T211
Test name
Test status
Simulation time 26235951068 ps
CPU time 43.21 seconds
Started Jul 17 05:54:38 PM PDT 24
Finished Jul 17 05:55:23 PM PDT 24
Peak memory 199980 kb
Host smart-caee870e-56e3-4551-b663-6654a48d0810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184651263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2184651263
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.832801497
Short name T57
Test name
Test status
Simulation time 77884852087 ps
CPU time 184.08 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:57:46 PM PDT 24
Peak memory 216560 kb
Host smart-93d38047-b437-4731-b037-33ffe5ca5bfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832801497 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.832801497
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3008719143
Short name T924
Test name
Test status
Simulation time 134016272230 ps
CPU time 86.93 seconds
Started Jul 17 05:54:39 PM PDT 24
Finished Jul 17 05:56:09 PM PDT 24
Peak memory 199892 kb
Host smart-a5b9f1b6-0fcd-4b98-b7c4-b5f844875e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008719143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3008719143
Directory /workspace/99.uart_fifo_reset/latest
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