Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	124001	1			T1	12		T2	31		T3	8
all_values[1]	124001	1			T1	12		T2	31		T3	8
all_values[2]	124001	1			T1	12		T2	31		T3	8
all_values[3]	124001	1			T1	12		T2	31		T3	8
all_values[4]	124001	1			T1	12		T2	31		T3	8
all_values[5]	124001	1			T1	12		T2	31		T3	8
all_values[6]	124001	1			T1	12		T2	31		T3	8
all_values[7]	124001	1			T1	12		T2	31		T3	8
all_values[8]	124001	1			T1	12		T2	31		T3	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

564530

1

T1

70

T2

115

T3

36

auto[1]

551479

1

T1

38

T2

164

T3

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1014249

1

T1

86

T2

262

T3

56

auto[1]

101760

1

T1

22

T2

17

T3

16

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	35564	1			T2	17		T4	1078		T7	56
all_values[0]	auto[0]	auto[1]	27040	1			T3	3		T4	368		T5	7
all_values[0]	auto[1]	auto[0]	37569	1			T1	1		T2	10		T3	2
all_values[0]	auto[1]	auto[1]	23828	1			T1	11		T2	4		T3	3
all_values[1]	auto[0]	auto[0]	59542	1			T1	12		T2	8		T3	5
all_values[1]	auto[0]	auto[1]	1606	1			T5	5		T6	1		T11	1
all_values[1]	auto[1]	auto[0]	60975	1			T2	23		T3	3		T4	420
all_values[1]	auto[1]	auto[1]	1878	1			T15	13		T124	2		T246	1
all_values[2]	auto[0]	auto[0]	60914	1			T1	2		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	2900	1			T1	3		T2	6		T3	2
all_values[2]	auto[1]	auto[0]	57642	1			T1	6		T2	20		T3	3
all_values[2]	auto[1]	auto[1]	2545	1			T1	1		T2	3		T4	11
all_values[3]	auto[0]	auto[0]	62046	1			T1	12		T2	6		T3	8
all_values[3]	auto[0]	auto[1]	288	1			T11	2		T15	1		T16	1
all_values[3]	auto[1]	auto[0]	61282	1			T2	25		T4	358		T5	11
all_values[3]	auto[1]	auto[1]	385	1			T15	4		T13	1		T16	3
all_values[4]	auto[0]	auto[0]	63779	1			T1	5		T2	14		T3	3
all_values[4]	auto[0]	auto[1]	495	1			T15	4		T16	4		T17	1
all_values[4]	auto[1]	auto[0]	59309	1			T1	7		T2	17		T3	5
all_values[4]	auto[1]	auto[1]	418	1			T15	5		T14	1		T17	3
all_values[5]	auto[0]	auto[0]	62107	1			T1	12		T2	23		T4	1195
all_values[5]	auto[0]	auto[1]	186	1			T15	2		T16	5		T17	4
all_values[5]	auto[1]	auto[0]	61517	1			T2	8		T3	8		T4	527
all_values[5]	auto[1]	auto[1]	191	1			T15	3		T16	2		T17	6
all_values[6]	auto[0]	auto[0]	65364	1			T1	5		T2	14		T3	2
all_values[6]	auto[0]	auto[1]	178	1			T15	5		T16	2		T17	6
all_values[6]	auto[1]	auto[0]	58244	1			T1	7		T2	17		T3	6
all_values[6]	auto[1]	auto[1]	215	1			T15	5		T16	2		T17	5
all_values[7]	auto[0]	auto[0]	59072	1			T1	12		T2	17		T3	5
all_values[7]	auto[0]	auto[1]	367	1			T3	3		T15	3		T16	5
all_values[7]	auto[1]	auto[0]	64156	1			T2	14		T4	1321		T5	8
all_values[7]	auto[1]	auto[1]	406	1			T15	4		T16	1		T17	2
all_values[8]	auto[0]	auto[0]	41235	1			T2	4		T3	2		T4	1129
all_values[8]	auto[0]	auto[1]	21847	1			T1	7		T2	4		T4	267
all_values[8]	auto[1]	auto[0]	43932	1			T1	5		T2	23		T3	1
all_values[8]	auto[1]	auto[1]	16987	1			T3	5		T5	2		T6	3