Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2374	1			T5	3		T7	5		T8	1
auto[BaudRate115200]	2154	1			T3	1		T4	1		T5	1
auto[BaudRate230400]	2076	1			T1	1		T4	1		T6	1
auto[BaudRate128Kbps]	2147	1			T1	3		T4	1		T5	1
auto[BaudRate256Kbps]	2322	1			T1	1		T2	2		T3	1
auto[BaudRate1Mbps]	1925	1			T2	1		T3	3		T4	2
auto[BaudRate1p5Mbps]	1333	1			T1	2		T2	5		T4	3

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1272	1			T126	10		T13	8		T132	6
freqs[25]	1768	1			T11	8		T45	8		T296	2
freqs[48]	605	1			T2	8		T6	5		T43	5
freqs[50]	588	1			T284	2		T133	7		T250	9
freqs[100]	1205	1			T7	10		T12	9		T15	16

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	175	1			T126	2		T13	2		T53	1
auto[BaudRate9600]	freqs[25]	296	1			T11	1		T296	1		T36	8
auto[BaudRate9600]	freqs[48]	108	1			T43	1		T289	3		T185	4
auto[BaudRate9600]	freqs[50]	64	1			T250	1		T262	4		T251	1
auto[BaudRate9600]	freqs[100]	211	1			T7	5		T12	3		T26	5
auto[BaudRate115200]	freqs[24]	184	1			T126	1		T13	1		T53	1
auto[BaudRate115200]	freqs[25]	271	1			T45	3		T296	1		T23	1
auto[BaudRate115200]	freqs[48]	80	1			T43	3		T19	1		T185	2
auto[BaudRate115200]	freqs[50]	91	1			T284	1		T133	1		T250	1
auto[BaudRate115200]	freqs[100]	142	1			T12	1		T15	6		T46	1
auto[BaudRate230400]	freqs[24]	180	1			T13	2		T132	1		T263	1
auto[BaudRate230400]	freqs[25]	255	1			T45	1		T36	7		T135	23
auto[BaudRate230400]	freqs[48]	76	1			T6	1		T312	6		T185	1
auto[BaudRate230400]	freqs[50]	96	1			T284	1		T250	1		T262	11
auto[BaudRate230400]	freqs[100]	153	1			T7	2		T12	1		T15	3
auto[BaudRate128Kbps]	freqs[24]	191	1			T126	2		T13	1		T132	2
auto[BaudRate128Kbps]	freqs[25]	280	1			T45	2		T36	20		T298	1
auto[BaudRate128Kbps]	freqs[48]	67	1			T6	2		T119	2		T312	9
auto[BaudRate128Kbps]	freqs[50]	86	1			T133	2		T250	1		T262	11
auto[BaudRate128Kbps]	freqs[100]	178	1			T7	3		T15	1		T26	8
auto[BaudRate256Kbps]	freqs[24]	200	1			T126	2		T132	2		T53	1
auto[BaudRate256Kbps]	freqs[25]	276	1			T11	6		T48	5		T36	7
auto[BaudRate256Kbps]	freqs[48]	100	1			T2	2		T6	2		T43	1
auto[BaudRate256Kbps]	freqs[50]	92	1			T133	1		T250	2		T262	14
auto[BaudRate256Kbps]	freqs[100]	179	1			T12	2		T15	3		T46	1
auto[BaudRate1Mbps]	freqs[24]	221	1			T126	3		T13	1		T132	1
auto[BaudRate1Mbps]	freqs[25]	243	1			T11	1		T45	1		T48	1
auto[BaudRate1Mbps]	freqs[48]	87	1			T2	1		T267	3		T312	3
auto[BaudRate1Mbps]	freqs[50]	83	1			T133	3		T250	1		T262	9
auto[BaudRate1Mbps]	freqs[100]	193	1			T46	3		T26	20		T266	1
auto[BaudRate1p5Mbps]	freqs[25]	147	1			T45	1		T48	2		T36	1
auto[BaudRate1p5Mbps]	freqs[48]	87	1			T2	5		T267	2		T312	12
auto[BaudRate1p5Mbps]	freqs[50]	76	1			T250	2		T262	2		T251	2
auto[BaudRate1p5Mbps]	freqs[100]	149	1			T12	2		T15	3		T46	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded