Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	34990410	1			T1	27		T2	82482		T3	61
all_levels[1]	207461	1			T2	4107		T4	272		T5	2
all_levels[2]	2655	1			T2	1		T5	3		T6	4
all_levels[3]	1071	1			T7	2		T8	1		T12	1
all_levels[4]	700	1			T5	1		T6	1		T8	2
all_levels[5]	485	1			T5	3		T6	1		T12	1
all_levels[6]	442	1			T15	2		T43	1		T45	1
all_levels[7]	304	1			T1	2		T5	2		T6	1
all_levels[8]	291	1			T45	1		T124	1		T20	1
all_levels[9]	241	1			T5	2		T15	1		T124	2
all_levels[10]	195	1			T46	1		T26	1		T125	3
all_levels[11]	175	1			T1	1		T126	1		T15	1
all_levels[12]	174	1			T1	1		T45	2		T46	2
all_levels[13]	154	1			T1	1		T3	1		T5	1
all_levels[14]	149	1			T12	2		T20	1		T22	3
all_levels[15]	131	1			T5	1		T12	1		T126	1
all_levels[16]	134	1			T5	1		T45	2		T125	1
all_levels[17]	88	1			T125	1		T127	1		T49	1
all_levels[18]	88	1			T6	1		T126	1		T124	1
all_levels[19]	89	1			T5	1		T36	1		T128	1
all_levels[20]	74	1			T5	1		T12	1		T20	1
all_levels[21]	65	1			T6	1		T45	1		T118	1
all_levels[22]	88	1			T6	1		T45	1		T17	1
all_levels[23]	55	1			T5	1		T7	1		T129	1
all_levels[24]	66	1			T75	1		T130	1		T131	2
all_levels[25]	54	1			T3	1		T11	1		T20	1
all_levels[26]	50	1			T126	1		T13	1		T132	3
all_levels[27]	44	1			T5	1		T12	1		T133	2
all_levels[28]	55	1			T12	2		T129	2		T108	1
all_levels[29]	27	1			T114	1		T111	1		T134	1
all_levels[30]	40	1			T6	1		T17	3		T135	2
all_levels[31]	28	1			T136	1		T137	1		T135	2
all_levels[32]	25	1			T133	1		T36	1		T137	3
all_levels[33]	26	1			T114	1		T135	1		T138	1
all_levels[34]	40	1			T45	1		T139	1		T140	1
all_levels[35]	16	1			T129	1		T141	2		T142	1
all_levels[36]	22	1			T45	2		T143	1		T144	4
all_levels[37]	23	1			T57	1		T145	3		T146	2
all_levels[38]	26	1			T34	1		T129	1		T143	1
all_levels[39]	29	1			T54	1		T75	1		T56	2
all_levels[40]	16	1			T17	1		T133	1		T147	2
all_levels[41]	19	1			T17	2		T148	1		T142	1
all_levels[42]	25	1			T149	1		T113	1		T150	1
all_levels[43]	17	1			T143	1		T151	1		T149	1
all_levels[44]	12	1			T129	1		T135	1		T152	1
all_levels[45]	14	1			T5	1		T118	1		T54	1
all_levels[46]	12	1			T153	1		T141	1		T154	1
all_levels[47]	16	1			T124	1		T111	1		T148	1
all_levels[48]	17	1			T3	1		T135	1		T56	1
all_levels[49]	11	1			T17	1		T151	1		T155	1
all_levels[50]	14	1			T125	3		T156	1		T157	2
all_levels[51]	8	1			T158	1		T159	1		T153	1
all_levels[52]	13	1			T3	1		T124	1		T20	1
all_levels[53]	9	1			T34	1		T160	1		T161	2
all_levels[54]	13	1			T36	1		T162	1		T163	1
all_levels[55]	6	1			T146	1		T164	1		T165	1
all_levels[56]	8	1			T166	2		T167	3		T168	1
all_levels[57]	9	1			T3	1		T169	1		T170	2
all_levels[58]	3	1			T111	1		T171	1		T145	1
all_levels[59]	4	1			T124	1		T172	2		T173	1
all_levels[60]	8	1			T135	1		T167	1		T174	1
all_levels[61]	7	1			T175	1		T176	2		T177	1
all_levels[62]	5	1			T116	1		T136	1		T141	1
all_levels[63]	7	1			T178	4		T179	1		T180	1
all_levels[64]	123	1			T11	3		T14	3		T17	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35201714

1

T1

26

T2

86590

T3

66

auto[1]

4972

1

T1

6

T5

3

T6

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[31]]	[auto[1]]	0	1	1
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[40]]	[auto[1]]	0	1	1
[all_levels[43] , all_levels[44] , all_levels[45]]	[auto[1]]	--	--	3
[all_levels[49]]	[auto[1]]	0	1	1
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[60]]	[auto[1]]	0	1	1
[all_levels[62]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	34985879	1			T1	22		T2	82482		T3	61
all_levels[0]	auto[1]	4531	1			T1	5		T5	3		T6	2
all_levels[1]	auto[0]	207376	1			T2	4107		T4	272		T5	2
all_levels[1]	auto[1]	85	1			T124	1		T181	3		T13	1
all_levels[2]	auto[0]	2623	1			T2	1		T5	3		T6	1
all_levels[2]	auto[1]	32	1			T6	3		T182	1		T151	2
all_levels[3]	auto[0]	1039	1			T7	2		T8	1		T12	1
all_levels[3]	auto[1]	32	1			T38	2		T183	3		T144	1
all_levels[4]	auto[0]	690	1			T5	1		T6	1		T8	2
all_levels[4]	auto[1]	10	1			T184	1		T185	2		T186	1
all_levels[5]	auto[0]	472	1			T5	3		T6	1		T12	1
all_levels[5]	auto[1]	13	1			T125	1		T128	2		T144	1
all_levels[6]	auto[0]	429	1			T15	2		T43	1		T45	1
all_levels[6]	auto[1]	13	1			T34	2		T143	1		T187	1
all_levels[7]	auto[0]	295	1			T1	1		T5	2		T6	1
all_levels[7]	auto[1]	9	1			T1	1		T188	1		T189	1
all_levels[8]	auto[0]	285	1			T45	1		T124	1		T20	1
all_levels[8]	auto[1]	6	1			T190	1		T191	2		T192	1
all_levels[9]	auto[0]	225	1			T5	2		T15	1		T124	1
all_levels[9]	auto[1]	16	1			T124	1		T144	1		T193	1
all_levels[10]	auto[0]	186	1			T46	1		T26	1		T125	3
all_levels[10]	auto[1]	9	1			T152	2		T194	1		T195	1
all_levels[11]	auto[0]	169	1			T1	1		T126	1		T15	1
all_levels[11]	auto[1]	6	1			T43	1		T196	1		T197	1
all_levels[12]	auto[0]	170	1			T1	1		T45	2		T46	2
all_levels[12]	auto[1]	4	1			T198	1		T199	1		T200	1
all_levels[13]	auto[0]	142	1			T1	1		T3	1		T5	1
all_levels[13]	auto[1]	12	1			T125	1		T36	1		T190	1
all_levels[14]	auto[0]	140	1			T12	2		T20	1		T22	3
all_levels[14]	auto[1]	9	1			T197	2		T201	2		T202	1
all_levels[15]	auto[0]	122	1			T5	1		T12	1		T126	1
all_levels[15]	auto[1]	9	1			T117	1		T203	1		T204	1
all_levels[16]	auto[0]	127	1			T5	1		T45	2		T125	1
all_levels[16]	auto[1]	7	1			T205	1		T206	1		T176	1
all_levels[17]	auto[0]	84	1			T125	1		T127	1		T49	1
all_levels[17]	auto[1]	4	1			T207	1		T208	1		T209	1
all_levels[18]	auto[0]	81	1			T6	1		T126	1		T124	1
all_levels[18]	auto[1]	7	1			T210	1		T152	3		T211	3
all_levels[19]	auto[0]	77	1			T5	1		T36	1		T128	1
all_levels[19]	auto[1]	12	1			T212	2		T164	1		T213	3
all_levels[20]	auto[0]	66	1			T5	1		T12	1		T20	1
all_levels[20]	auto[1]	8	1			T151	1		T205	1		T207	1
all_levels[21]	auto[0]	57	1			T6	1		T45	1		T118	1
all_levels[21]	auto[1]	8	1			T211	1		T214	2		T215	1
all_levels[22]	auto[0]	80	1			T6	1		T45	1		T17	1
all_levels[22]	auto[1]	8	1			T205	2		T216	3		T173	1
all_levels[23]	auto[0]	54	1			T5	1		T7	1		T129	1
all_levels[23]	auto[1]	1	1			T154	1		-	-		-	-
all_levels[24]	auto[0]	60	1			T75	1		T130	1		T131	2
all_levels[24]	auto[1]	6	1			T111	1		T217	1		T218	1
all_levels[25]	auto[0]	52	1			T3	1		T11	1		T20	1
all_levels[25]	auto[1]	2	1			T219	2		-	-		-	-
all_levels[26]	auto[0]	46	1			T126	1		T13	1		T132	2
all_levels[26]	auto[1]	4	1			T132	1		T151	1		T220	1
all_levels[27]	auto[0]	36	1			T5	1		T12	1		T133	2
all_levels[27]	auto[1]	8	1			T221	1		T222	2		T223	3
all_levels[28]	auto[0]	49	1			T12	1		T129	1		T108	1
all_levels[28]	auto[1]	6	1			T12	1		T129	1		T185	2
all_levels[29]	auto[0]	23	1			T114	1		T111	1		T134	1
all_levels[29]	auto[1]	4	1			T189	1		T215	1		T224	1
all_levels[30]	auto[0]	37	1			T6	1		T17	1		T135	2
all_levels[30]	auto[1]	3	1			T17	2		T225	1		-	-
all_levels[31]	auto[0]	28	1			T136	1		T137	1		T135	2
all_levels[32]	auto[0]	24	1			T133	1		T36	1		T137	2
all_levels[32]	auto[1]	1	1			T137	1		-	-		-	-
all_levels[33]	auto[0]	23	1			T114	1		T135	1		T138	1
all_levels[33]	auto[1]	3	1			T154	1		T208	2		-	-
all_levels[34]	auto[0]	31	1			T45	1		T139	1		T140	1
all_levels[34]	auto[1]	9	1			T226	1		T171	1		T227	2
all_levels[35]	auto[0]	16	1			T129	1		T141	2		T142	1
all_levels[36]	auto[0]	18	1			T45	2		T143	1		T144	3
all_levels[36]	auto[1]	4	1			T144	1		T74	1		T228	2
all_levels[37]	auto[0]	15	1			T57	1		T145	1		T146	2
all_levels[37]	auto[1]	8	1			T145	2		T229	3		T230	1
all_levels[38]	auto[0]	24	1			T34	1		T129	1		T143	1
all_levels[38]	auto[1]	2	1			T118	1		T220	1		-	-
all_levels[39]	auto[0]	27	1			T54	1		T75	1		T56	2
all_levels[39]	auto[1]	2	1			T231	1		T232	1		-	-
all_levels[40]	auto[0]	16	1			T17	1		T133	1		T147	2
all_levels[41]	auto[0]	13	1			T17	1		T148	1		T142	1
all_levels[41]	auto[1]	6	1			T17	1		T211	1		T214	2
all_levels[42]	auto[0]	22	1			T149	1		T113	1		T150	1
all_levels[42]	auto[1]	3	1			T195	1		T233	1		T234	1
all_levels[43]	auto[0]	17	1			T143	1		T151	1		T149	1
all_levels[44]	auto[0]	12	1			T129	1		T135	1		T152	1
all_levels[45]	auto[0]	14	1			T5	1		T118	1		T54	1
all_levels[46]	auto[0]	11	1			T153	1		T141	1		T154	1
all_levels[46]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[47]	auto[0]	10	1			T124	1		T111	1		T148	1
all_levels[47]	auto[1]	6	1			T236	1		T237	5		-	-
all_levels[48]	auto[0]	12	1			T3	1		T135	1		T56	1
all_levels[48]	auto[1]	5	1			T238	1		T239	3		T240	1
all_levels[49]	auto[0]	11	1			T17	1		T151	1		T155	1
all_levels[50]	auto[0]	10	1			T125	1		T156	1		T157	1
all_levels[50]	auto[1]	4	1			T125	2		T157	1		T241	1
all_levels[51]	auto[0]	8	1			T158	1		T159	1		T153	1
all_levels[52]	auto[0]	12	1			T3	1		T124	1		T20	1
all_levels[52]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[53]	auto[0]	8	1			T34	1		T160	1		T161	1
all_levels[53]	auto[1]	1	1			T161	1		-	-		-	-
all_levels[54]	auto[0]	11	1			T36	1		T162	1		T163	1
all_levels[54]	auto[1]	2	1			T243	2		-	-		-	-
all_levels[55]	auto[0]	5	1			T146	1		T164	1		T165	1
all_levels[55]	auto[1]	1	1			T244	1		-	-		-	-
all_levels[56]	auto[0]	7	1			T166	1		T167	3		T168	1
all_levels[56]	auto[1]	1	1			T166	1		-	-		-	-
all_levels[57]	auto[0]	7	1			T3	1		T169	1		T170	1
all_levels[57]	auto[1]	2	1			T170	1		T245	1		-	-
all_levels[58]	auto[0]	3	1			T111	1		T171	1		T145	1
all_levels[59]	auto[0]	3	1			T124	1		T172	1		T173	1
all_levels[59]	auto[1]	1	1			T172	1		-	-		-	-
all_levels[60]	auto[0]	8	1			T135	1		T167	1		T174	1
all_levels[61]	auto[0]	5	1			T175	1		T176	1		T177	1
all_levels[61]	auto[1]	2	1			T176	1		T216	1		-	-
all_levels[62]	auto[0]	5	1			T116	1		T136	1		T141	1
all_levels[63]	auto[0]	4	1			T178	1		T179	1		T180	1
all_levels[63]	auto[1]	3	1			T178	3		-	-		-	-
all_levels[64]	auto[0]	103	1			T11	1		T14	3		T17	1
all_levels[64]	auto[1]	20	1			T11	2		T20	1		T118	1