Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	124001	1			T1	12		T2	31		T3	8
all_pins[1]	124001	1			T1	12		T2	31		T3	8
all_pins[2]	124001	1			T1	12		T2	31		T3	8
all_pins[3]	124001	1			T1	12		T2	31		T3	8
all_pins[4]	124001	1			T1	12		T2	31		T3	8
all_pins[5]	124001	1			T1	12		T2	31		T3	8
all_pins[6]	124001	1			T1	12		T2	31		T3	8
all_pins[7]	124001	1			T1	12		T2	31		T3	8
all_pins[8]	124001	1			T1	12		T2	31		T3	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1068203	1			T1	95		T2	272		T3	64
values[0x1]	47806	1			T1	13		T2	7		T3	8
transitions[0x0=>0x1]	38579	1			T1	13		T2	7		T3	7
transitions[0x1=>0x0]	38360	1			T1	12		T2	6		T3	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100087	1			T1	1		T2	27		T3	5
all_pins[0]	values[0x1]	23914	1			T1	11		T2	4		T3	3
all_pins[0]	transitions[0x0=>0x1]	23239	1			T1	11		T2	4		T3	3
all_pins[0]	transitions[0x1=>0x0]	1203	1			T15	5		T246	1		T14	10
all_pins[1]	values[0x0]	122123	1			T1	12		T2	31		T3	8
all_pins[1]	values[0x1]	1878	1			T15	13		T124	2		T246	1
all_pins[1]	transitions[0x0=>0x1]	1769	1			T15	13		T14	10		T17	2
all_pins[1]	transitions[0x1=>0x0]	2505	1			T1	1		T2	3		T4	11
all_pins[2]	values[0x0]	121387	1			T1	11		T2	28		T3	8
all_pins[2]	values[0x1]	2614	1			T1	1		T2	3		T4	11
all_pins[2]	transitions[0x0=>0x1]	2528	1			T1	1		T2	3		T4	11
all_pins[2]	transitions[0x1=>0x0]	299	1			T15	4		T16	1		T14	1
all_pins[3]	values[0x0]	123616	1			T1	12		T2	31		T3	8
all_pins[3]	values[0x1]	385	1			T15	4		T13	1		T16	3
all_pins[3]	transitions[0x0=>0x1]	339	1			T15	4		T13	1		T16	3
all_pins[3]	transitions[0x1=>0x0]	372	1			T15	5		T14	1		T17	3
all_pins[4]	values[0x0]	123583	1			T1	12		T2	31		T3	8
all_pins[4]	values[0x1]	418	1			T15	5		T14	1		T17	3
all_pins[4]	transitions[0x0=>0x1]	357	1			T15	5		T14	1		T17	2
all_pins[4]	transitions[0x1=>0x0]	187	1			T15	3		T16	2		T17	5
all_pins[5]	values[0x0]	123753	1			T1	12		T2	31		T3	8
all_pins[5]	values[0x1]	248	1			T15	3		T16	2		T17	6
all_pins[5]	transitions[0x0=>0x1]	199	1			T15	3		T16	2		T17	3
all_pins[5]	transitions[0x1=>0x0]	826	1			T1	1		T7	2		T8	1
all_pins[6]	values[0x0]	123126	1			T1	11		T2	31		T3	8
all_pins[6]	values[0x1]	875	1			T1	1		T7	2		T8	1
all_pins[6]	transitions[0x0=>0x1]	803	1			T1	1		T7	2		T8	1
all_pins[6]	transitions[0x1=>0x0]	334	1			T15	3		T16	1		T17	2
all_pins[7]	values[0x0]	123595	1			T1	12		T2	31		T3	8
all_pins[7]	values[0x1]	406	1			T15	4		T16	1		T17	2
all_pins[7]	transitions[0x0=>0x1]	266	1			T15	3		T16	1		T17	1
all_pins[7]	transitions[0x1=>0x0]	16928	1			T3	5		T5	2		T6	3
all_pins[8]	values[0x0]	106933	1			T1	12		T2	31		T3	3
all_pins[8]	values[0x1]	17068	1			T3	5		T5	2		T6	3
all_pins[8]	transitions[0x0=>0x1]	9079	1			T3	4		T6	3		T7	3
all_pins[8]	transitions[0x1=>0x0]	15706	1			T1	10		T2	3		T3	1