Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	9359049	1			T1	8		T2	25943		T3	37
all_levels[1]	1734856	1			T2	109		T3	1		T4	146723
all_levels[2]	465775	1			T2	95		T3	2		T4	6077
all_levels[3]	470150	1			T2	94		T4	6104		T7	8
all_levels[4]	391352	1			T2	99		T3	1		T4	6091
all_levels[5]	228887	1			T2	104		T4	6104		T7	317
all_levels[6]	331348	1			T2	100		T4	6055		T8	4
all_levels[7]	533332	1			T1	1		T2	93		T4	5634
all_levels[8]	354948	1			T2	99		T3	1		T4	5628
all_levels[9]	279410	1			T2	98		T4	5632		T12	8
all_levels[10]	254664	1			T2	90		T4	5624		T8	2
all_levels[11]	298969	1			T2	83		T3	3		T4	5607
all_levels[12]	301313	1			T2	89		T3	1		T4	33859
all_levels[13]	241907	1			T2	105		T4	5630		T5	3
all_levels[14]	399271	1			T2	103		T4	5424		T7	3
all_levels[15]	235938	1			T2	98		T3	2		T4	3277
all_levels[16]	246978	1			T1	4		T2	82		T4	3271
all_levels[17]	373660	1			T2	99		T3	1		T4	3251
all_levels[18]	242287	1			T2	92		T3	1		T4	3262
all_levels[19]	418407	1			T1	3		T2	100		T3	3
all_levels[20]	292258	1			T2	109		T4	3267		T7	2
all_levels[21]	242922	1			T1	2		T2	102		T3	1
all_levels[22]	472136	1			T2	107		T4	3275		T7	2
all_levels[23]	211588	1			T1	14		T2	96		T4	3275
all_levels[24]	414471	1			T2	107		T3	2		T4	27517
all_levels[25]	187213	1			T2	105		T3	7		T4	3262
all_levels[26]	432775	1			T2	111		T3	1		T4	3272
all_levels[27]	291885	1			T2	94		T3	2		T4	3256
all_levels[28]	279488	1			T2	87		T4	3253		T7	3
all_levels[29]	219067	1			T2	86		T4	3242		T10	2
all_levels[30]	491410	1			T2	98		T3	1		T4	3271
all_levels[31]	625908	1			T2	3464		T4	19844		T7	8
all_levels[32]	13882573	1			T2	54249		T4	154234		T6	16

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35201714

1

T1

26

T2

86590

T3

66

auto[1]

4481

1

T1

6

T3

1

T4

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	9356405	1			T1	6		T2	25943		T3	37
all_levels[0]	auto[1]	2644	1			T1	2		T5	1		T6	1
all_levels[1]	auto[0]	1734553	1			T2	109		T3	1		T4	146723
all_levels[1]	auto[1]	303	1			T5	3		T7	3		T12	1
all_levels[2]	auto[0]	465740	1			T2	95		T3	2		T4	6077
all_levels[2]	auto[1]	35	1			T47	2		T294	1		T117	1
all_levels[3]	auto[0]	469974	1			T2	94		T4	6104		T7	6
all_levels[3]	auto[1]	176	1			T7	2		T305	1		T183	3
all_levels[4]	auto[0]	391320	1			T2	99		T3	1		T4	6091
all_levels[4]	auto[1]	32	1			T282	1		T205	1		T313	1
all_levels[5]	auto[0]	228869	1			T2	104		T4	6104		T7	317
all_levels[5]	auto[1]	18	1			T117	3		T144	1		T314	1
all_levels[6]	auto[0]	331324	1			T2	100		T4	6055		T8	4
all_levels[6]	auto[1]	24	1			T10	1		T11	1		T315	3
all_levels[7]	auto[0]	533211	1			T1	1		T2	93		T4	5634
all_levels[7]	auto[1]	121	1			T43	1		T123	26		T38	9
all_levels[8]	auto[0]	354930	1			T2	99		T3	1		T4	5628
all_levels[8]	auto[1]	18	1			T264	1		T289	1		T191	1
all_levels[9]	auto[0]	279380	1			T2	98		T4	5632		T12	5
all_levels[9]	auto[1]	30	1			T12	3		T279	2		T282	2
all_levels[10]	auto[0]	254633	1			T2	90		T4	5624		T8	2
all_levels[10]	auto[1]	31	1			T13	1		T17	2		T182	2
all_levels[11]	auto[0]	298948	1			T2	83		T3	3		T4	5607
all_levels[11]	auto[1]	21	1			T11	1		T106	1		T75	1
all_levels[12]	auto[0]	301290	1			T2	89		T3	1		T4	33859
all_levels[12]	auto[1]	23	1			T247	1		T274	2		T202	3
all_levels[13]	auto[0]	241886	1			T2	105		T4	5630		T5	2
all_levels[13]	auto[1]	21	1			T5	1		T7	1		T266	1
all_levels[14]	auto[0]	399251	1			T2	103		T4	5424		T7	3
all_levels[14]	auto[1]	20	1			T17	1		T276	1		T316	3
all_levels[15]	auto[0]	235829	1			T2	98		T3	2		T4	3277
all_levels[15]	auto[1]	109	1			T41	1		T253	14		T159	1
all_levels[16]	auto[0]	246962	1			T1	4		T2	82		T4	3271
all_levels[16]	auto[1]	16	1			T130	1		T274	2		T317	1
all_levels[17]	auto[0]	373645	1			T2	99		T3	1		T4	3251
all_levels[17]	auto[1]	15	1			T271	1		T203	1		T55	1
all_levels[18]	auto[0]	242264	1			T2	92		T3	1		T4	3262
all_levels[18]	auto[1]	23	1			T133	2		T104	1		T268	1
all_levels[19]	auto[0]	418391	1			T1	3		T2	100		T3	3
all_levels[19]	auto[1]	16	1			T137	1		T318	1		T211	2
all_levels[20]	auto[0]	292238	1			T2	109		T4	3267		T7	2
all_levels[20]	auto[1]	20	1			T128	2		T143	1		T118	2
all_levels[21]	auto[0]	242896	1			T1	2		T2	102		T3	1
all_levels[21]	auto[1]	26	1			T132	2		T136	2		T319	1
all_levels[22]	auto[0]	472115	1			T2	107		T4	3275		T7	2
all_levels[22]	auto[1]	21	1			T249	1		T320	1		T321	1
all_levels[23]	auto[0]	211551	1			T1	10		T2	96		T4	3275
all_levels[23]	auto[1]	37	1			T1	4		T135	1		T322	1
all_levels[24]	auto[0]	414458	1			T2	107		T3	2		T4	27517
all_levels[24]	auto[1]	13	1			T300	1		T139	1		T323	1
all_levels[25]	auto[0]	187197	1			T2	105		T3	6		T4	3262
all_levels[25]	auto[1]	16	1			T3	1		T247	3		T324	4
all_levels[26]	auto[0]	432756	1			T2	111		T3	1		T4	3272
all_levels[26]	auto[1]	19	1			T47	1		T320	2		T325	3
all_levels[27]	auto[0]	291864	1			T2	94		T3	2		T4	3256
all_levels[27]	auto[1]	21	1			T143	1		T203	1		T326	1
all_levels[28]	auto[0]	279471	1			T2	87		T4	3253		T7	3
all_levels[28]	auto[1]	17	1			T56	1		T207	1		T212	1
all_levels[29]	auto[0]	219048	1			T2	86		T4	3242		T10	2
all_levels[29]	auto[1]	19	1			T187	2		T327	1		T328	2
all_levels[30]	auto[0]	491393	1			T2	98		T3	1		T4	3271
all_levels[30]	auto[1]	17	1			T329	1		T178	2		T220	1
all_levels[31]	auto[0]	625891	1			T2	3464		T4	19844		T7	8
all_levels[31]	auto[1]	17	1			T315	2		T78	3		T212	1
all_levels[32]	auto[0]	13882031	1			T2	54249		T4	154233		T6	13
all_levels[32]	auto[1]	542	1			T4	1		T6	3		T10	2