Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	841	1			T15	15		T16	11		T17	23
all_values[1]	841	1			T15	15		T16	11		T17	23
all_values[2]	841	1			T15	15		T16	11		T17	23
all_values[3]	841	1			T15	15		T16	11		T17	23
all_values[4]	841	1			T15	15		T16	11		T17	23
all_values[5]	841	1			T15	15		T16	11		T17	23
all_values[6]	841	1			T15	15		T16	11		T17	23
all_values[7]	841	1			T15	15		T16	11		T17	23
all_values[8]	841	1			T15	15		T16	11		T17	23

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3988

1

T15

70

T16

48

T17

107

auto[1]

3581

1

T15

65

T16

51

T17

100

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2511

1

T15

49

T16

40

T17

81

auto[1]

5058

1

T15

86

T16

59

T17

126

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4462

1

T15

78

T16

62

T17

137

auto[1]

3107

1

T15

57

T16

37

T17

70

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	272	1			T15	3		T16	4		T17	10
all_values[0]	auto[0]	auto[1]	auto[1]	233	1			T15	3		T16	4		T17	9
all_values[0]	auto[1]	auto[0]	auto[1]	179	1			T15	3		T16	1		T17	2
all_values[0]	auto[1]	auto[1]	auto[1]	157	1			T15	6		T16	2		T17	2
all_values[1]	auto[0]	auto[0]	auto[0]	244	1			T15	5		T17	8		T35	2
all_values[1]	auto[0]	auto[1]	auto[0]	241	1			T15	5		T16	10		T17	8
all_values[1]	auto[1]	auto[0]	auto[1]	201	1			T15	4		T16	1		T17	3
all_values[1]	auto[1]	auto[1]	auto[1]	155	1			T15	1		T17	4		T35	1
all_values[2]	auto[0]	auto[0]	auto[0]	171	1			T15	3		T16	6		T17	3
all_values[2]	auto[0]	auto[0]	auto[1]	84	1			T15	1		T17	2		T35	1
all_values[2]	auto[0]	auto[1]	auto[0]	150	1			T15	3		T16	2		T17	3
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T15	1		T16	1		T17	5
all_values[2]	auto[1]	auto[0]	auto[1]	188	1			T15	5		T17	3		T35	2
all_values[2]	auto[1]	auto[1]	auto[1]	157	1			T15	2		T16	2		T17	7
all_values[3]	auto[0]	auto[0]	auto[0]	187	1			T15	2		T16	3		T17	9
all_values[3]	auto[0]	auto[0]	auto[1]	72	1			T17	1		T37	2		T122	2
all_values[3]	auto[0]	auto[1]	auto[0]	155	1			T15	4		T16	3		T17	6
all_values[3]	auto[0]	auto[1]	auto[1]	93	1			T15	2		T16	1		T17	1
all_values[3]	auto[1]	auto[0]	auto[1]	162	1			T15	3		T16	2		T17	4
all_values[3]	auto[1]	auto[1]	auto[1]	172	1			T15	4		T16	2		T17	2
all_values[4]	auto[0]	auto[0]	auto[0]	196	1			T15	3		T17	8		T35	2
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T15	1		T16	2		T17	2
all_values[4]	auto[0]	auto[1]	auto[0]	185	1			T15	6		T16	5		T17	8
all_values[4]	auto[0]	auto[1]	auto[1]	77	1			T104	1		T123	4		T37	4
all_values[4]	auto[1]	auto[0]	auto[1]	177	1			T15	5		T16	4		T17	2
all_values[4]	auto[1]	auto[1]	auto[1]	140	1			T17	3		T35	2		T104	3
all_values[5]	auto[0]	auto[0]	auto[0]	177	1			T15	3		T16	1		T17	3
all_values[5]	auto[0]	auto[0]	auto[1]	72	1			T15	1		T16	3		T17	1
all_values[5]	auto[0]	auto[1]	auto[0]	158	1			T15	5		T16	2		T17	5
all_values[5]	auto[0]	auto[1]	auto[1]	80	1			T15	1		T17	3		T35	1
all_values[5]	auto[1]	auto[0]	auto[1]	186	1			T15	4		T16	3		T17	3
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T15	1		T16	2		T17	8
all_values[6]	auto[0]	auto[0]	auto[0]	185	1			T15	1		T16	2		T17	6
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T15	2		T17	3		T123	2
all_values[6]	auto[0]	auto[1]	auto[0]	143	1			T15	3		T16	3		T17	3
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T15	1		T16	1		T17	2
all_values[6]	auto[1]	auto[0]	auto[1]	180	1			T15	5		T16	2		T17	4
all_values[6]	auto[1]	auto[1]	auto[1]	174	1			T15	3		T16	3		T17	5
all_values[7]	auto[0]	auto[0]	auto[0]	160	1			T15	4		T17	6		T35	1
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T15	1		T16	3		T17	2
all_values[7]	auto[0]	auto[1]	auto[0]	159	1			T15	2		T16	3		T17	5
all_values[7]	auto[0]	auto[1]	auto[1]	80	1			T15	1		T104	1		T123	1
all_values[7]	auto[1]	auto[0]	auto[1]	209	1			T15	3		T16	4		T17	7
all_values[7]	auto[1]	auto[1]	auto[1]	148	1			T15	4		T16	1		T17	3
all_values[8]	auto[0]	auto[0]	auto[1]	270	1			T15	7		T16	2		T17	9
all_values[8]	auto[0]	auto[1]	auto[1]	217	1			T15	4		T16	1		T17	6
all_values[8]	auto[1]	auto[0]	auto[1]	191	1			T15	1		T16	5		T17	6
all_values[8]	auto[1]	auto[1]	auto[1]	163	1			T15	3		T16	3		T17	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal