Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1317
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T1251 /workspace/coverage/cover_reg_top/6.uart_tl_errors.511621948 Jul 18 06:39:25 PM PDT 24 Jul 18 06:39:27 PM PDT 24 1421543013 ps
T1252 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3736968965 Jul 18 06:38:41 PM PDT 24 Jul 18 06:38:43 PM PDT 24 179692389 ps
T1253 /workspace/coverage/cover_reg_top/27.uart_intr_test.3187392397 Jul 18 06:40:19 PM PDT 24 Jul 18 06:40:22 PM PDT 24 12410141 ps
T1254 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.746423226 Jul 18 06:39:39 PM PDT 24 Jul 18 06:39:43 PM PDT 24 131394228 ps
T1255 /workspace/coverage/cover_reg_top/47.uart_intr_test.2622462784 Jul 18 06:40:14 PM PDT 24 Jul 18 06:40:17 PM PDT 24 14056705 ps
T1256 /workspace/coverage/cover_reg_top/41.uart_intr_test.1714946531 Jul 18 06:40:15 PM PDT 24 Jul 18 06:40:17 PM PDT 24 48340943 ps
T1257 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2662927798 Jul 18 06:39:58 PM PDT 24 Jul 18 06:40:03 PM PDT 24 16489286 ps
T1258 /workspace/coverage/cover_reg_top/12.uart_tl_errors.134138771 Jul 18 06:39:39 PM PDT 24 Jul 18 06:39:41 PM PDT 24 56252541 ps
T1259 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3078855764 Jul 18 06:39:28 PM PDT 24 Jul 18 06:39:31 PM PDT 24 359409948 ps
T1260 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1858677617 Jul 18 06:39:59 PM PDT 24 Jul 18 06:40:05 PM PDT 24 282566742 ps
T1261 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2153625445 Jul 18 06:39:55 PM PDT 24 Jul 18 06:39:57 PM PDT 24 67067827 ps
T1262 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1410443450 Jul 18 06:39:56 PM PDT 24 Jul 18 06:40:01 PM PDT 24 32087589 ps
T1263 /workspace/coverage/cover_reg_top/12.uart_intr_test.1195883133 Jul 18 06:39:40 PM PDT 24 Jul 18 06:39:43 PM PDT 24 51057192 ps
T1264 /workspace/coverage/cover_reg_top/21.uart_intr_test.4016816279 Jul 18 06:40:14 PM PDT 24 Jul 18 06:40:16 PM PDT 24 12864923 ps
T1265 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2130259819 Jul 18 06:39:13 PM PDT 24 Jul 18 06:39:17 PM PDT 24 36865387 ps
T1266 /workspace/coverage/cover_reg_top/30.uart_intr_test.704640975 Jul 18 06:40:16 PM PDT 24 Jul 18 06:40:21 PM PDT 24 12696672 ps
T1267 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3458437890 Jul 18 06:39:40 PM PDT 24 Jul 18 06:39:44 PM PDT 24 186698065 ps
T1268 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.677559052 Jul 18 06:39:43 PM PDT 24 Jul 18 06:39:46 PM PDT 24 190461473 ps
T1269 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1825847625 Jul 18 06:39:29 PM PDT 24 Jul 18 06:39:31 PM PDT 24 15495397 ps
T1270 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2058444421 Jul 18 06:40:17 PM PDT 24 Jul 18 06:40:21 PM PDT 24 20110438 ps
T1271 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2287501335 Jul 18 06:40:15 PM PDT 24 Jul 18 06:40:17 PM PDT 24 24857275 ps
T1272 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1994062603 Jul 18 06:39:15 PM PDT 24 Jul 18 06:39:18 PM PDT 24 34631213 ps
T1273 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3938457571 Jul 18 06:39:41 PM PDT 24 Jul 18 06:39:45 PM PDT 24 78774482 ps
T1274 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.164317212 Jul 18 06:39:27 PM PDT 24 Jul 18 06:39:30 PM PDT 24 22379551 ps
T1275 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2395166616 Jul 18 06:39:59 PM PDT 24 Jul 18 06:40:04 PM PDT 24 46853233 ps
T1276 /workspace/coverage/cover_reg_top/33.uart_intr_test.3028734111 Jul 18 06:40:16 PM PDT 24 Jul 18 06:40:20 PM PDT 24 16222519 ps
T1277 /workspace/coverage/cover_reg_top/13.uart_intr_test.2800872926 Jul 18 06:39:57 PM PDT 24 Jul 18 06:40:01 PM PDT 24 20013612 ps
T1278 /workspace/coverage/cover_reg_top/19.uart_tl_errors.369204612 Jul 18 06:40:14 PM PDT 24 Jul 18 06:40:18 PM PDT 24 37122810 ps
T1279 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.626293955 Jul 18 06:40:16 PM PDT 24 Jul 18 06:40:21 PM PDT 24 47376606 ps
T1280 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3453223811 Jul 18 06:39:29 PM PDT 24 Jul 18 06:39:31 PM PDT 24 23641501 ps
T1281 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.4116890870 Jul 18 06:39:00 PM PDT 24 Jul 18 06:39:03 PM PDT 24 47719347 ps
T1282 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2130649979 Jul 18 06:39:55 PM PDT 24 Jul 18 06:39:57 PM PDT 24 89880805 ps
T1283 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3635442096 Jul 18 06:39:57 PM PDT 24 Jul 18 06:40:01 PM PDT 24 14686448 ps
T1284 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4042240074 Jul 18 06:39:56 PM PDT 24 Jul 18 06:40:01 PM PDT 24 152793150 ps
T1285 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3751602702 Jul 18 06:38:59 PM PDT 24 Jul 18 06:39:03 PM PDT 24 36528777 ps
T1286 /workspace/coverage/cover_reg_top/19.uart_intr_test.3131237100 Jul 18 06:40:13 PM PDT 24 Jul 18 06:40:15 PM PDT 24 89401948 ps
T1287 /workspace/coverage/cover_reg_top/22.uart_intr_test.2892850890 Jul 18 06:40:14 PM PDT 24 Jul 18 06:40:16 PM PDT 24 30135488 ps
T1288 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3310435835 Jul 18 06:40:15 PM PDT 24 Jul 18 06:40:20 PM PDT 24 140046599 ps
T1289 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.322655569 Jul 18 06:39:29 PM PDT 24 Jul 18 06:39:32 PM PDT 24 31163418 ps
T1290 /workspace/coverage/cover_reg_top/2.uart_intr_test.2412040529 Jul 18 06:38:58 PM PDT 24 Jul 18 06:39:00 PM PDT 24 13491358 ps
T1291 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3158651384 Jul 18 06:39:15 PM PDT 24 Jul 18 06:39:20 PM PDT 24 163708323 ps
T1292 /workspace/coverage/cover_reg_top/9.uart_intr_test.3234879768 Jul 18 06:39:27 PM PDT 24 Jul 18 06:39:30 PM PDT 24 41099722 ps
T1293 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3737001883 Jul 18 06:39:27 PM PDT 24 Jul 18 06:39:29 PM PDT 24 53799150 ps
T1294 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2423980654 Jul 18 06:39:25 PM PDT 24 Jul 18 06:39:28 PM PDT 24 154538013 ps
T1295 /workspace/coverage/cover_reg_top/10.uart_intr_test.613439498 Jul 18 06:39:40 PM PDT 24 Jul 18 06:39:43 PM PDT 24 27918840 ps
T1296 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1758045634 Jul 18 06:38:59 PM PDT 24 Jul 18 06:39:02 PM PDT 24 94775296 ps
T1297 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.836274462 Jul 18 06:39:42 PM PDT 24 Jul 18 06:39:46 PM PDT 24 56973324 ps
T1298 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3070072607 Jul 18 06:39:58 PM PDT 24 Jul 18 06:40:02 PM PDT 24 15832952 ps
T1299 /workspace/coverage/cover_reg_top/8.uart_intr_test.192449990 Jul 18 06:39:29 PM PDT 24 Jul 18 06:39:32 PM PDT 24 30528290 ps
T1300 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.4278628653 Jul 18 06:39:40 PM PDT 24 Jul 18 06:39:43 PM PDT 24 13752698 ps
T1301 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1882902221 Jul 18 06:39:56 PM PDT 24 Jul 18 06:40:00 PM PDT 24 102610356 ps
T1302 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.563713656 Jul 18 06:39:13 PM PDT 24 Jul 18 06:39:16 PM PDT 24 21683769 ps
T1303 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2008999877 Jul 18 06:39:57 PM PDT 24 Jul 18 06:40:02 PM PDT 24 60835805 ps
T1304 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.491838628 Jul 18 06:39:13 PM PDT 24 Jul 18 06:39:17 PM PDT 24 146732527 ps
T1305 /workspace/coverage/cover_reg_top/4.uart_intr_test.4063611202 Jul 18 06:39:12 PM PDT 24 Jul 18 06:39:13 PM PDT 24 33397953 ps
T1306 /workspace/coverage/cover_reg_top/43.uart_intr_test.1492508595 Jul 18 06:40:16 PM PDT 24 Jul 18 06:40:21 PM PDT 24 17444250 ps
T1307 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3887188596 Jul 18 06:39:21 PM PDT 24 Jul 18 06:39:24 PM PDT 24 15527171 ps
T1308 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.625010525 Jul 18 06:39:29 PM PDT 24 Jul 18 06:39:32 PM PDT 24 32748838 ps
T1309 /workspace/coverage/cover_reg_top/16.uart_intr_test.3380401749 Jul 18 06:39:56 PM PDT 24 Jul 18 06:39:59 PM PDT 24 28472761 ps
T1310 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1011812922 Jul 18 06:39:01 PM PDT 24 Jul 18 06:39:03 PM PDT 24 66350857 ps
T1311 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2983503599 Jul 18 06:39:57 PM PDT 24 Jul 18 06:40:01 PM PDT 24 43870033 ps
T1312 /workspace/coverage/cover_reg_top/25.uart_intr_test.759262160 Jul 18 06:40:17 PM PDT 24 Jul 18 06:40:21 PM PDT 24 45240208 ps
T1313 /workspace/coverage/cover_reg_top/1.uart_intr_test.2618456507 Jul 18 06:39:00 PM PDT 24 Jul 18 06:39:02 PM PDT 24 18190422 ps
T1314 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1717679311 Jul 18 06:39:15 PM PDT 24 Jul 18 06:39:18 PM PDT 24 107144439 ps
T1315 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.613441483 Jul 18 06:39:00 PM PDT 24 Jul 18 06:39:03 PM PDT 24 247494699 ps
T1316 /workspace/coverage/cover_reg_top/29.uart_intr_test.478076360 Jul 18 06:40:15 PM PDT 24 Jul 18 06:40:19 PM PDT 24 44353613 ps
T1317 /workspace/coverage/cover_reg_top/31.uart_intr_test.2146765858 Jul 18 06:40:14 PM PDT 24 Jul 18 06:40:17 PM PDT 24 11607427 ps

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.197839543
Short name T2
Test name
Test status
Simulation time 106687345763 ps
CPU time 555.22 seconds
Started Jul 18 06:48:53 PM PDT 24
Finished Jul 18 06:58:11 PM PDT 24
Peak memory 200116 kb
Host smart-98b65449-c6de-47c0-993f-8612d13832db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=197839543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.197839543
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2755027416
Short name T22
Test name
Test status
Simulation time 685344363583 ps
CPU time 838.21 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 07:02:07 PM PDT 24
Peak memory 233108 kb
Host smart-2fbed0d8-8a03-4407-842c-6430fee490d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755027416 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2755027416
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3677250394
Short name T35
Test name
Test status
Simulation time 141541155453 ps
CPU time 657.72 seconds
Started Jul 18 06:51:35 PM PDT 24
Finished Jul 18 07:02:37 PM PDT 24
Peak memory 216828 kb
Host smart-428e3ae9-b3cd-4691-a19d-2d5dad642ed7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677250394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3677250394
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3323232889
Short name T16
Test name
Test status
Simulation time 89812363646 ps
CPU time 967.49 seconds
Started Jul 18 06:51:34 PM PDT 24
Finished Jul 18 07:07:46 PM PDT 24
Peak memory 216124 kb
Host smart-31766b02-3a68-490e-94ca-1df43b0df390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323232889 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3323232889
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all.2631572075
Short name T14
Test name
Test status
Simulation time 359288044554 ps
CPU time 1223.51 seconds
Started Jul 18 06:50:21 PM PDT 24
Finished Jul 18 07:10:47 PM PDT 24
Peak memory 210152 kb
Host smart-f9af099d-deb6-4e43-bff9-2e871e5452cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631572075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2631572075
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2459417657
Short name T7
Test name
Test status
Simulation time 327160909892 ps
CPU time 776.98 seconds
Started Jul 18 06:48:04 PM PDT 24
Finished Jul 18 07:01:04 PM PDT 24
Peak memory 200212 kb
Host smart-359053c4-0d94-49d2-bbb1-fb74613fea91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459417657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2459417657
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.178500659
Short name T135
Test name
Test status
Simulation time 244404088703 ps
CPU time 858.77 seconds
Started Jul 18 06:51:58 PM PDT 24
Finished Jul 18 07:06:19 PM PDT 24
Peak memory 226024 kb
Host smart-170ed60e-1969-4994-b2d4-25656b3709be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178500659 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.178500659
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.126370456
Short name T20
Test name
Test status
Simulation time 647130957351 ps
CPU time 143.41 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:50:53 PM PDT 24
Peak memory 200116 kb
Host smart-b320d0dd-8914-4140-a22c-c7b67cc6af86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126370456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.126370456
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3974446710
Short name T31
Test name
Test status
Simulation time 112243425 ps
CPU time 0.78 seconds
Started Jul 18 06:47:51 PM PDT 24
Finished Jul 18 06:47:58 PM PDT 24
Peak memory 218336 kb
Host smart-c6822019-313d-410e-b980-6a7f0974bc46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974446710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3974446710
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3072428672
Short name T246
Test name
Test status
Simulation time 150345716691 ps
CPU time 1752.94 seconds
Started Jul 18 06:48:38 PM PDT 24
Finished Jul 18 07:17:55 PM PDT 24
Peak memory 200124 kb
Host smart-4ac2960d-fc10-4919-ac36-73551fb997b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072428672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3072428672
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_stress_all.1374408715
Short name T262
Test name
Test status
Simulation time 300853902399 ps
CPU time 495.29 seconds
Started Jul 18 06:48:27 PM PDT 24
Finished Jul 18 06:56:48 PM PDT 24
Peak memory 208528 kb
Host smart-b6b71476-0be3-47b8-a60b-5a780a229b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374408715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1374408715
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3018372167
Short name T54
Test name
Test status
Simulation time 284698800790 ps
CPU time 698.34 seconds
Started Jul 18 06:51:37 PM PDT 24
Finished Jul 18 07:03:18 PM PDT 24
Peak memory 216916 kb
Host smart-c7433ae6-4139-4c91-af4f-c1c3c3a1eba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018372167 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3018372167
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1343415376
Short name T126
Test name
Test status
Simulation time 182571415062 ps
CPU time 102.51 seconds
Started Jul 18 06:51:01 PM PDT 24
Finished Jul 18 06:52:47 PM PDT 24
Peak memory 200264 kb
Host smart-ee2d612f-3268-4ffe-8608-7da7edd75e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343415376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1343415376
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_stress_all.3707936591
Short name T211
Test name
Test status
Simulation time 141868188203 ps
CPU time 1285.4 seconds
Started Jul 18 06:50:43 PM PDT 24
Finished Jul 18 07:12:10 PM PDT 24
Peak memory 200120 kb
Host smart-f7d14c61-f4db-49fa-beb5-e6b9e2fa8d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707936591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3707936591
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3824125800
Short name T111
Test name
Test status
Simulation time 83120387783 ps
CPU time 487.07 seconds
Started Jul 18 06:48:37 PM PDT 24
Finished Jul 18 06:56:48 PM PDT 24
Peak memory 225280 kb
Host smart-c816186d-df74-4e5e-9c68-6c6cc36ee6cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824125800 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3824125800
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.441141801
Short name T137
Test name
Test status
Simulation time 312851886978 ps
CPU time 155.74 seconds
Started Jul 18 06:53:51 PM PDT 24
Finished Jul 18 06:56:29 PM PDT 24
Peak memory 200152 kb
Host smart-f8392b62-e14c-4a64-83d2-7640a1813a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441141801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.441141801
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2996494092
Short name T97
Test name
Test status
Simulation time 96197146 ps
CPU time 1.29 seconds
Started Jul 18 06:38:59 PM PDT 24
Finished Jul 18 06:39:02 PM PDT 24
Peak memory 200364 kb
Host smart-286b99b8-5429-4de5-939d-f19d285aad93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996494092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2996494092
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.4278433314
Short name T36
Test name
Test status
Simulation time 103970478718 ps
CPU time 281.44 seconds
Started Jul 18 06:51:33 PM PDT 24
Finished Jul 18 06:56:19 PM PDT 24
Peak memory 215480 kb
Host smart-f412a70a-ce76-4a05-9507-fce31237b1e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278433314 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.4278433314
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2124473076
Short name T9
Test name
Test status
Simulation time 42638743 ps
CPU time 0.54 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 06:48:47 PM PDT 24
Peak memory 195588 kb
Host smart-255ace14-1b89-4a7e-9054-e2a0792e8899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124473076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2124473076
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.725718254
Short name T67
Test name
Test status
Simulation time 12073995 ps
CPU time 0.59 seconds
Started Jul 18 06:38:39 PM PDT 24
Finished Jul 18 06:38:41 PM PDT 24
Peak memory 196356 kb
Host smart-67ddec56-1707-456a-b144-2e536ab89649
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725718254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.725718254
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/default/24.uart_stress_all.1253201670
Short name T104
Test name
Test status
Simulation time 208619425542 ps
CPU time 670.62 seconds
Started Jul 18 06:49:07 PM PDT 24
Finished Jul 18 07:00:20 PM PDT 24
Peak memory 216496 kb
Host smart-c7891059-9afe-4fde-a1ad-377d47dbaf5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253201670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1253201670
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2711157666
Short name T17
Test name
Test status
Simulation time 233205790330 ps
CPU time 630.91 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 06:59:17 PM PDT 24
Peak memory 216640 kb
Host smart-cd509abf-5111-4070-8a8d-506fe9f8deca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711157666 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2711157666
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2607921748
Short name T141
Test name
Test status
Simulation time 225585930780 ps
CPU time 424.71 seconds
Started Jul 18 06:51:18 PM PDT 24
Finished Jul 18 06:58:26 PM PDT 24
Peak memory 225036 kb
Host smart-5bd1ecdc-7a68-487b-a08a-42bde3950deb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607921748 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2607921748
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1816307753
Short name T185
Test name
Test status
Simulation time 94563049821 ps
CPU time 85.97 seconds
Started Jul 18 06:52:12 PM PDT 24
Finished Jul 18 06:53:41 PM PDT 24
Peak memory 200084 kb
Host smart-8bc80ab2-2a9e-43f2-8cea-71fcf1657d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816307753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1816307753
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1382306817
Short name T93
Test name
Test status
Simulation time 312768247 ps
CPU time 1.26 seconds
Started Jul 18 06:39:13 PM PDT 24
Finished Jul 18 06:39:16 PM PDT 24
Peak memory 200036 kb
Host smart-9652719f-7989-4f44-9708-21681f69c11f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382306817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1382306817
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.811053880
Short name T176
Test name
Test status
Simulation time 94055223564 ps
CPU time 59.31 seconds
Started Jul 18 06:52:15 PM PDT 24
Finished Jul 18 06:53:18 PM PDT 24
Peak memory 200220 kb
Host smart-ce9ab3f0-5108-48b6-8bbf-ad4f1259b8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811053880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.811053880
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_stress_all.1210279934
Short name T26
Test name
Test status
Simulation time 141802965356 ps
CPU time 412.47 seconds
Started Jul 18 06:50:20 PM PDT 24
Finished Jul 18 06:57:13 PM PDT 24
Peak memory 208524 kb
Host smart-f1a2dfef-882e-427d-9ab3-e31b4f0ac50f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210279934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1210279934
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2184232466
Short name T113
Test name
Test status
Simulation time 163029498599 ps
CPU time 1832.77 seconds
Started Jul 18 06:51:35 PM PDT 24
Finished Jul 18 07:22:12 PM PDT 24
Peak memory 225884 kb
Host smart-a211dfb0-56b1-4a8f-ad18-c9cbb37b6275
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184232466 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2184232466
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all.3375370435
Short name T274
Test name
Test status
Simulation time 503845523795 ps
CPU time 1194.78 seconds
Started Jul 18 06:49:23 PM PDT 24
Finished Jul 18 07:09:19 PM PDT 24
Peak memory 200124 kb
Host smart-d4af3018-fe07-4c56-99e2-afae266513e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375370435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3375370435
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.388923630
Short name T124
Test name
Test status
Simulation time 44531897479 ps
CPU time 31.69 seconds
Started Jul 18 06:51:34 PM PDT 24
Finished Jul 18 06:52:10 PM PDT 24
Peak memory 200188 kb
Host smart-6ad0bef4-86d3-4ede-83a4-8f63d7163abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388923630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.388923630
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2057289879
Short name T170
Test name
Test status
Simulation time 283698289613 ps
CPU time 231.03 seconds
Started Jul 18 06:52:10 PM PDT 24
Finished Jul 18 06:56:04 PM PDT 24
Peak memory 200132 kb
Host smart-d9de0d8e-f091-4a71-8f77-17a6c5b737c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057289879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2057289879
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.673586292
Short name T55
Test name
Test status
Simulation time 2176913540240 ps
CPU time 988.96 seconds
Started Jul 18 06:48:56 PM PDT 24
Finished Jul 18 07:05:29 PM PDT 24
Peak memory 225336 kb
Host smart-0a234c7f-32a7-409e-96f9-c6936bf3454b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673586292 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.673586292
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.41583998
Short name T161
Test name
Test status
Simulation time 58070572438 ps
CPU time 31.72 seconds
Started Jul 18 06:53:56 PM PDT 24
Finished Jul 18 06:54:31 PM PDT 24
Peak memory 200184 kb
Host smart-fc7075f4-99a3-4b79-96fa-349c03527c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41583998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.41583998
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2811816359
Short name T151
Test name
Test status
Simulation time 155266698293 ps
CPU time 34.12 seconds
Started Jul 18 06:53:36 PM PDT 24
Finished Jul 18 06:54:11 PM PDT 24
Peak memory 199876 kb
Host smart-f2defdde-57aa-4e68-9269-1252c7feaf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811816359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2811816359
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3246792060
Short name T180
Test name
Test status
Simulation time 59143684765 ps
CPU time 25.67 seconds
Started Jul 18 06:54:10 PM PDT 24
Finished Jul 18 06:54:44 PM PDT 24
Peak memory 200188 kb
Host smart-68b87417-2e03-46f1-8571-5d42d4291af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246792060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3246792060
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3272747967
Short name T144
Test name
Test status
Simulation time 62420037505 ps
CPU time 91.31 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 06:53:30 PM PDT 24
Peak memory 200120 kb
Host smart-c18948f7-eba7-4e91-9e2e-64564e288c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272747967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3272747967
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3236059810
Short name T939
Test name
Test status
Simulation time 128220493053 ps
CPU time 495.55 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:56:43 PM PDT 24
Peak memory 216856 kb
Host smart-d3704e7d-e94d-410e-afac-23fcd924f0f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236059810 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3236059810
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_full.792869056
Short name T146
Test name
Test status
Simulation time 26398284477 ps
CPU time 13.32 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:48:57 PM PDT 24
Peak memory 200172 kb
Host smart-aeb34eb8-2cca-4b9c-9280-7111a86115cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792869056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.792869056
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2610738146
Short name T329
Test name
Test status
Simulation time 206097708869 ps
CPU time 263.23 seconds
Started Jul 18 06:54:13 PM PDT 24
Finished Jul 18 06:58:45 PM PDT 24
Peak memory 200204 kb
Host smart-31deac02-3ae3-4edd-b7e5-c96b66a2b0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610738146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2610738146
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3113996780
Short name T241
Test name
Test status
Simulation time 60392816766 ps
CPU time 25.45 seconds
Started Jul 18 06:52:13 PM PDT 24
Finished Jul 18 06:52:41 PM PDT 24
Peak memory 200104 kb
Host smart-c4fdbe1f-b4d5-4256-b751-ed210ad35dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113996780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3113996780
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.557512020
Short name T74
Test name
Test status
Simulation time 23428523982 ps
CPU time 9.59 seconds
Started Jul 18 06:54:03 PM PDT 24
Finished Jul 18 06:54:20 PM PDT 24
Peak memory 200148 kb
Host smart-db5d0754-4692-4425-b4b4-020d8a2e42fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557512020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.557512020
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2556994384
Short name T195
Test name
Test status
Simulation time 23369926915 ps
CPU time 34.83 seconds
Started Jul 18 06:50:59 PM PDT 24
Finished Jul 18 06:51:35 PM PDT 24
Peak memory 200168 kb
Host smart-41266a46-05c0-4dbd-83f6-a71f831f226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556994384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2556994384
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3220035120
Short name T98
Test name
Test status
Simulation time 501419210 ps
CPU time 1.31 seconds
Started Jul 18 06:40:16 PM PDT 24
Finished Jul 18 06:40:21 PM PDT 24
Peak memory 199576 kb
Host smart-5d7a68c0-2ba2-4e20-90dd-8a87fc283ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220035120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3220035120
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.760181746
Short name T213
Test name
Test status
Simulation time 43219046960 ps
CPU time 20.92 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 06:52:20 PM PDT 24
Peak memory 200188 kb
Host smart-2b2c44cb-7e9c-407c-8842-c1fdb64d7b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760181746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.760181746
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1527517417
Short name T200
Test name
Test status
Simulation time 22696697808 ps
CPU time 43.77 seconds
Started Jul 18 06:52:11 PM PDT 24
Finished Jul 18 06:52:57 PM PDT 24
Peak memory 200204 kb
Host smart-1bc21f69-0df3-469e-8baf-c07c970a4d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527517417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1527517417
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.2479396642
Short name T123
Test name
Test status
Simulation time 295073575393 ps
CPU time 130.6 seconds
Started Jul 18 06:48:55 PM PDT 24
Finished Jul 18 06:51:09 PM PDT 24
Peak memory 216376 kb
Host smart-ccd1e164-9663-458b-bfde-093db83584a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479396642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2479396642
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1219737950
Short name T208
Test name
Test status
Simulation time 208035346993 ps
CPU time 93.99 seconds
Started Jul 18 06:54:03 PM PDT 24
Finished Jul 18 06:55:45 PM PDT 24
Peak memory 200372 kb
Host smart-c1beab20-05dd-4e04-8b6e-c27b10f56da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219737950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1219737950
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3943791406
Short name T168
Test name
Test status
Simulation time 341956106562 ps
CPU time 1009.49 seconds
Started Jul 18 06:48:53 PM PDT 24
Finished Jul 18 07:05:46 PM PDT 24
Peak memory 225016 kb
Host smart-5a197b58-60ca-4db3-aaba-b4495153b3cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943791406 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3943791406
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3561656272
Short name T221
Test name
Test status
Simulation time 15797672466 ps
CPU time 44.96 seconds
Started Jul 18 06:53:55 PM PDT 24
Finished Jul 18 06:54:42 PM PDT 24
Peak memory 200192 kb
Host smart-de572823-4d6e-4ac2-a1bd-fbffa0fe2f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561656272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3561656272
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.506263245
Short name T189
Test name
Test status
Simulation time 69387179066 ps
CPU time 17 seconds
Started Jul 18 06:53:59 PM PDT 24
Finished Jul 18 06:54:21 PM PDT 24
Peak memory 200140 kb
Host smart-676f5683-61af-46ed-86ba-2f2e4a29d9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506263245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.506263245
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3692420059
Short name T166
Test name
Test status
Simulation time 111422913835 ps
CPU time 88.29 seconds
Started Jul 18 06:53:57 PM PDT 24
Finished Jul 18 06:55:29 PM PDT 24
Peak memory 200100 kb
Host smart-877b1e1b-2845-4b6e-bba6-db567731d3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692420059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3692420059
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.3947739482
Short name T197
Test name
Test status
Simulation time 98607968552 ps
CPU time 133.19 seconds
Started Jul 18 06:47:52 PM PDT 24
Finished Jul 18 06:50:11 PM PDT 24
Peak memory 200172 kb
Host smart-47d81e42-527d-4650-a9a7-23f08125d63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947739482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3947739482
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.131280177
Short name T437
Test name
Test status
Simulation time 140028828478 ps
CPU time 519.27 seconds
Started Jul 18 06:50:47 PM PDT 24
Finished Jul 18 06:59:30 PM PDT 24
Peak memory 224464 kb
Host smart-eb48ff85-1438-410d-bf11-a23fd0c8d4fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131280177 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.131280177
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1919073253
Short name T120
Test name
Test status
Simulation time 37157188707 ps
CPU time 31.9 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:48:28 PM PDT 24
Peak memory 200140 kb
Host smart-a62a5e96-fc21-46bf-8fb0-fd3e744ad9be
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919073253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1919073253
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_stress_all.126483889
Short name T177
Test name
Test status
Simulation time 303227085976 ps
CPU time 193.45 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:51:08 PM PDT 24
Peak memory 200208 kb
Host smart-2e114628-50c9-42f7-acab-1326262729ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126483889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.126483889
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.397326154
Short name T235
Test name
Test status
Simulation time 34769703613 ps
CPU time 19.71 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:48:11 PM PDT 24
Peak memory 200204 kb
Host smart-756170e0-18a8-4b4d-8255-04bc3a1af6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397326154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.397326154
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1015162980
Short name T890
Test name
Test status
Simulation time 39289194361 ps
CPU time 98.05 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:50:09 PM PDT 24
Peak memory 208512 kb
Host smart-3bea7d20-6418-48e8-8360-9aab90d16cf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015162980 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1015162980
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3590729308
Short name T755
Test name
Test status
Simulation time 11474378714 ps
CPU time 15.49 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 06:52:14 PM PDT 24
Peak memory 200152 kb
Host smart-3e14f06e-a4d6-44e7-8463-cba4348e224b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590729308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3590729308
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3411939377
Short name T244
Test name
Test status
Simulation time 53603137965 ps
CPU time 78 seconds
Started Jul 18 06:52:11 PM PDT 24
Finished Jul 18 06:53:32 PM PDT 24
Peak memory 200204 kb
Host smart-d6f3e565-3f61-4126-b71f-dd640d9899c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411939377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3411939377
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3008578017
Short name T1139
Test name
Test status
Simulation time 71459501055 ps
CPU time 52.67 seconds
Started Jul 18 06:52:05 PM PDT 24
Finished Jul 18 06:52:59 PM PDT 24
Peak memory 200196 kb
Host smart-c9f43f32-2ce2-403f-a1c2-9b9498136113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008578017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3008578017
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3526881462
Short name T132
Test name
Test status
Simulation time 13672231336 ps
CPU time 6.43 seconds
Started Jul 18 06:52:07 PM PDT 24
Finished Jul 18 06:52:15 PM PDT 24
Peak memory 200164 kb
Host smart-2886b0a7-7ffd-4ba2-9444-e06ccb525438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526881462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3526881462
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2365853549
Short name T236
Test name
Test status
Simulation time 65451000288 ps
CPU time 25.94 seconds
Started Jul 18 06:53:33 PM PDT 24
Finished Jul 18 06:54:00 PM PDT 24
Peak memory 200160 kb
Host smart-0bfb75d9-db9a-4732-9767-05a602717274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365853549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2365853549
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.211352580
Short name T232
Test name
Test status
Simulation time 41784496521 ps
CPU time 51.94 seconds
Started Jul 18 06:53:59 PM PDT 24
Finished Jul 18 06:54:56 PM PDT 24
Peak memory 200100 kb
Host smart-c3436424-e691-45a7-9538-a1f5a40e6b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211352580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.211352580
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.918476477
Short name T178
Test name
Test status
Simulation time 126729353402 ps
CPU time 33.84 seconds
Started Jul 18 06:54:01 PM PDT 24
Finished Jul 18 06:54:43 PM PDT 24
Peak memory 200112 kb
Host smart-56b20181-b439-461e-b328-14ca7eaa4699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918476477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.918476477
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1950308707
Short name T242
Test name
Test status
Simulation time 11534921507 ps
CPU time 54.37 seconds
Started Jul 18 06:54:01 PM PDT 24
Finished Jul 18 06:55:02 PM PDT 24
Peak memory 200200 kb
Host smart-6d4cb0f2-7b09-4cc2-b3b0-545a1822682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950308707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1950308707
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.963629561
Short name T240
Test name
Test status
Simulation time 56482523515 ps
CPU time 20.15 seconds
Started Jul 18 06:53:55 PM PDT 24
Finished Jul 18 06:54:17 PM PDT 24
Peak memory 200144 kb
Host smart-a7a1fa11-2487-41ac-8d47-c808bc14920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963629561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.963629561
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2130608331
Short name T220
Test name
Test status
Simulation time 131577140900 ps
CPU time 46.27 seconds
Started Jul 18 06:48:53 PM PDT 24
Finished Jul 18 06:49:41 PM PDT 24
Peak memory 200352 kb
Host smart-a3082a75-1a21-4d3b-b099-4315d25c0857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130608331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2130608331
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2998673541
Short name T219
Test name
Test status
Simulation time 94544543511 ps
CPU time 33.1 seconds
Started Jul 18 06:54:15 PM PDT 24
Finished Jul 18 06:54:58 PM PDT 24
Peak memory 199816 kb
Host smart-ab1cf819-16af-4e81-b7a9-076ecce6cf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998673541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2998673541
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2767611476
Short name T172
Test name
Test status
Simulation time 9894693862 ps
CPU time 15.88 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 06:51:52 PM PDT 24
Peak memory 200208 kb
Host smart-fa7d6090-dd0c-43e1-b4eb-fad3f9dc2760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767611476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2767611476
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2626696205
Short name T154
Test name
Test status
Simulation time 180219615691 ps
CPU time 37.63 seconds
Started Jul 18 06:51:31 PM PDT 24
Finished Jul 18 06:52:12 PM PDT 24
Peak memory 200132 kb
Host smart-7b376afa-cdcb-4361-82b7-51e603bcf813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626696205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2626696205
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.826961829
Short name T243
Test name
Test status
Simulation time 49218658134 ps
CPU time 33.38 seconds
Started Jul 18 06:51:31 PM PDT 24
Finished Jul 18 06:52:08 PM PDT 24
Peak memory 200132 kb
Host smart-0c10c1bc-f04d-4b1c-b470-bb4935d0dce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826961829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.826961829
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1226595375
Short name T80
Test name
Test status
Simulation time 21639278 ps
CPU time 0.65 seconds
Started Jul 18 06:38:58 PM PDT 24
Finished Jul 18 06:39:00 PM PDT 24
Peak memory 196472 kb
Host smart-5de5ae8d-2454-47fe-a4b3-21a3f6fa4a60
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226595375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1226595375
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.613441483
Short name T1315
Test name
Test status
Simulation time 247494699 ps
CPU time 1.41 seconds
Started Jul 18 06:39:00 PM PDT 24
Finished Jul 18 06:39:03 PM PDT 24
Peak memory 198732 kb
Host smart-1c2a1c2b-7a69-4b93-b519-ac10d90b1cf6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613441483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.613441483
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3476141940
Short name T1191
Test name
Test status
Simulation time 63645886 ps
CPU time 0.55 seconds
Started Jul 18 06:38:42 PM PDT 24
Finished Jul 18 06:38:44 PM PDT 24
Peak memory 196340 kb
Host smart-c174c1b6-a32b-4d61-931b-63dba54b7131
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476141940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3476141940
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3504878619
Short name T1242
Test name
Test status
Simulation time 32946749 ps
CPU time 1.43 seconds
Started Jul 18 06:38:59 PM PDT 24
Finished Jul 18 06:39:02 PM PDT 24
Peak memory 200900 kb
Host smart-1a7e7d37-3aac-427b-aa27-3c8494c3f8dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504878619 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3504878619
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.692035755
Short name T1211
Test name
Test status
Simulation time 41074543 ps
CPU time 0.57 seconds
Started Jul 18 06:38:40 PM PDT 24
Finished Jul 18 06:38:42 PM PDT 24
Peak memory 195328 kb
Host smart-935623e0-2dd5-4d72-841e-05e0914a2250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692035755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.692035755
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1011812922
Short name T1310
Test name
Test status
Simulation time 66350857 ps
CPU time 0.66 seconds
Started Jul 18 06:39:01 PM PDT 24
Finished Jul 18 06:39:03 PM PDT 24
Peak memory 196404 kb
Host smart-56595c3b-91e1-47fb-85c2-320884b53f68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011812922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1011812922
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.4174152817
Short name T1196
Test name
Test status
Simulation time 100769664 ps
CPU time 1.13 seconds
Started Jul 18 06:38:39 PM PDT 24
Finished Jul 18 06:38:41 PM PDT 24
Peak memory 200956 kb
Host smart-faf50988-c42f-4172-ba8d-c1f9c52ef78f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174152817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.4174152817
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3736968965
Short name T1252
Test name
Test status
Simulation time 179692389 ps
CPU time 0.94 seconds
Started Jul 18 06:38:41 PM PDT 24
Finished Jul 18 06:38:43 PM PDT 24
Peak memory 199996 kb
Host smart-272fc217-393d-4f09-9f6a-8684e17fb440
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736968965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3736968965
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.599668459
Short name T63
Test name
Test status
Simulation time 43368880 ps
CPU time 0.62 seconds
Started Jul 18 06:38:58 PM PDT 24
Finished Jul 18 06:38:59 PM PDT 24
Peak memory 196340 kb
Host smart-8b5a61f9-703e-4025-a9b4-9a34f6f9ae37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599668459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.599668459
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3751602702
Short name T1285
Test name
Test status
Simulation time 36528777 ps
CPU time 1.39 seconds
Started Jul 18 06:38:59 PM PDT 24
Finished Jul 18 06:39:03 PM PDT 24
Peak memory 198708 kb
Host smart-95c88153-0ce7-4710-bc3b-10dfaea7face
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751602702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3751602702
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3399596326
Short name T1225
Test name
Test status
Simulation time 108022009 ps
CPU time 0.6 seconds
Started Jul 18 06:39:01 PM PDT 24
Finished Jul 18 06:39:03 PM PDT 24
Peak memory 196316 kb
Host smart-8c1ccedb-ebed-46a8-816c-c9c7afa7648e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399596326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3399596326
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1758045634
Short name T1296
Test name
Test status
Simulation time 94775296 ps
CPU time 0.75 seconds
Started Jul 18 06:38:59 PM PDT 24
Finished Jul 18 06:39:02 PM PDT 24
Peak memory 200096 kb
Host smart-911c0be9-0440-4993-b846-5f72708693e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758045634 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1758045634
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3063654923
Short name T84
Test name
Test status
Simulation time 19187409 ps
CPU time 0.69 seconds
Started Jul 18 06:39:01 PM PDT 24
Finished Jul 18 06:39:03 PM PDT 24
Peak memory 196524 kb
Host smart-39c8455b-e92c-42dd-8cfa-93cd6f596010
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063654923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3063654923
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2618456507
Short name T1313
Test name
Test status
Simulation time 18190422 ps
CPU time 0.59 seconds
Started Jul 18 06:39:00 PM PDT 24
Finished Jul 18 06:39:02 PM PDT 24
Peak memory 195304 kb
Host smart-cb9922ce-d01f-439f-a1a2-9acf9009a7c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618456507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2618456507
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3194797470
Short name T88
Test name
Test status
Simulation time 23037089 ps
CPU time 0.65 seconds
Started Jul 18 06:38:59 PM PDT 24
Finished Jul 18 06:39:01 PM PDT 24
Peak memory 196552 kb
Host smart-2fee787e-6131-4031-90ae-0a20acbef5fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194797470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3194797470
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3615423311
Short name T1219
Test name
Test status
Simulation time 434208709 ps
CPU time 2.02 seconds
Started Jul 18 06:39:00 PM PDT 24
Finished Jul 18 06:39:04 PM PDT 24
Peak memory 200928 kb
Host smart-3b3858f2-3b4e-48d8-9e87-a98f452e0484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615423311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3615423311
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1453013231
Short name T1248
Test name
Test status
Simulation time 92298213 ps
CPU time 0.81 seconds
Started Jul 18 06:39:40 PM PDT 24
Finished Jul 18 06:39:43 PM PDT 24
Peak memory 200596 kb
Host smart-e6b435a5-2c63-417f-8f93-723b845f1230
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453013231 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1453013231
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.241450004
Short name T87
Test name
Test status
Simulation time 15277074 ps
CPU time 0.61 seconds
Started Jul 18 06:39:40 PM PDT 24
Finished Jul 18 06:39:43 PM PDT 24
Peak memory 196532 kb
Host smart-48e8ef2d-b1cd-4451-9825-3020c76eff37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241450004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.241450004
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.613439498
Short name T1295
Test name
Test status
Simulation time 27918840 ps
CPU time 0.62 seconds
Started Jul 18 06:39:40 PM PDT 24
Finished Jul 18 06:39:43 PM PDT 24
Peak memory 195288 kb
Host smart-2d9882d2-fd03-4a1b-8d5c-c206a8b8b1ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613439498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.613439498
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.4278628653
Short name T1300
Test name
Test status
Simulation time 13752698 ps
CPU time 0.6 seconds
Started Jul 18 06:39:40 PM PDT 24
Finished Jul 18 06:39:43 PM PDT 24
Peak memory 195644 kb
Host smart-12f393e2-9b4b-4be5-8721-6a5c43cdaa90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278628653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.4278628653
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3938457571
Short name T1273
Test name
Test status
Simulation time 78774482 ps
CPU time 1.6 seconds
Started Jul 18 06:39:41 PM PDT 24
Finished Jul 18 06:39:45 PM PDT 24
Peak memory 201008 kb
Host smart-7460b1f9-2749-4dd7-8062-fed671656ad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938457571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3938457571
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.746423226
Short name T1254
Test name
Test status
Simulation time 131394228 ps
CPU time 1.31 seconds
Started Jul 18 06:39:39 PM PDT 24
Finished Jul 18 06:39:43 PM PDT 24
Peak memory 199912 kb
Host smart-cffd8e97-da81-4f35-b1e4-3fa06f771732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746423226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.746423226
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1133231108
Short name T1236
Test name
Test status
Simulation time 97966645 ps
CPU time 1.16 seconds
Started Jul 18 06:39:42 PM PDT 24
Finished Jul 18 06:39:46 PM PDT 24
Peak memory 200984 kb
Host smart-92f8876c-37c1-4b0a-86f1-ed01893621ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133231108 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1133231108
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.763905625
Short name T65
Test name
Test status
Simulation time 17071649 ps
CPU time 0.62 seconds
Started Jul 18 06:39:44 PM PDT 24
Finished Jul 18 06:39:46 PM PDT 24
Peak memory 196416 kb
Host smart-a05e37fa-8b27-4a1a-bd09-2337f5ce83bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763905625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.763905625
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.4103535401
Short name T1238
Test name
Test status
Simulation time 15152034 ps
CPU time 0.57 seconds
Started Jul 18 06:39:41 PM PDT 24
Finished Jul 18 06:39:44 PM PDT 24
Peak memory 195320 kb
Host smart-83a21042-c762-476c-8b69-b091acc6ad8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103535401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4103535401
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2580448598
Short name T85
Test name
Test status
Simulation time 18048140 ps
CPU time 0.62 seconds
Started Jul 18 06:39:38 PM PDT 24
Finished Jul 18 06:39:40 PM PDT 24
Peak memory 196472 kb
Host smart-216a8c6a-8d3b-4dfe-b229-8b13c94c1857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580448598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2580448598
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.403217286
Short name T1207
Test name
Test status
Simulation time 85366137 ps
CPU time 1.88 seconds
Started Jul 18 06:39:40 PM PDT 24
Finished Jul 18 06:39:44 PM PDT 24
Peak memory 200968 kb
Host smart-859dabf8-20ab-43a5-ac90-32ed79f5114c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403217286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.403217286
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3458437890
Short name T1267
Test name
Test status
Simulation time 186698065 ps
CPU time 0.92 seconds
Started Jul 18 06:39:40 PM PDT 24
Finished Jul 18 06:39:44 PM PDT 24
Peak memory 199696 kb
Host smart-98241514-e931-413c-a888-c93004ccc893
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458437890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3458437890
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2426468938
Short name T1205
Test name
Test status
Simulation time 214365190 ps
CPU time 0.67 seconds
Started Jul 18 06:39:56 PM PDT 24
Finished Jul 18 06:39:59 PM PDT 24
Peak memory 199116 kb
Host smart-a671b892-b293-489f-a370-df77b89a6b64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426468938 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2426468938
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2494899067
Short name T83
Test name
Test status
Simulation time 11028435 ps
CPU time 0.56 seconds
Started Jul 18 06:39:54 PM PDT 24
Finished Jul 18 06:39:56 PM PDT 24
Peak memory 196272 kb
Host smart-ad3c7ad5-986a-4f63-8fa2-f2ad7e42425e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494899067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2494899067
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1195883133
Short name T1263
Test name
Test status
Simulation time 51057192 ps
CPU time 0.57 seconds
Started Jul 18 06:39:40 PM PDT 24
Finished Jul 18 06:39:43 PM PDT 24
Peak memory 195312 kb
Host smart-40590fbc-6718-4746-82b6-68d38b6c522b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195883133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1195883133
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3211172990
Short name T1212
Test name
Test status
Simulation time 25530833 ps
CPU time 0.66 seconds
Started Jul 18 06:39:55 PM PDT 24
Finished Jul 18 06:39:58 PM PDT 24
Peak memory 195796 kb
Host smart-0eafa864-3f07-4a8c-a9a5-0de0caea4d3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211172990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3211172990
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.134138771
Short name T1258
Test name
Test status
Simulation time 56252541 ps
CPU time 1.22 seconds
Started Jul 18 06:39:39 PM PDT 24
Finished Jul 18 06:39:41 PM PDT 24
Peak memory 200992 kb
Host smart-d0dc077d-9df6-493f-bd0c-4e0752297366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134138771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.134138771
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.677559052
Short name T1268
Test name
Test status
Simulation time 190461473 ps
CPU time 1.02 seconds
Started Jul 18 06:39:43 PM PDT 24
Finished Jul 18 06:39:46 PM PDT 24
Peak memory 200004 kb
Host smart-227cc502-04d7-479d-9ba7-6903a23f6917
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677559052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.677559052
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2567339253
Short name T1210
Test name
Test status
Simulation time 115625958 ps
CPU time 0.68 seconds
Started Jul 18 06:39:59 PM PDT 24
Finished Jul 18 06:40:04 PM PDT 24
Peak memory 198876 kb
Host smart-a8048a42-a2d8-4523-ae31-b6b1ed63b80d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567339253 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2567339253
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1644441574
Short name T66
Test name
Test status
Simulation time 43956376 ps
CPU time 0.61 seconds
Started Jul 18 06:39:56 PM PDT 24
Finished Jul 18 06:39:59 PM PDT 24
Peak memory 196528 kb
Host smart-0ed01cff-540e-4846-89d3-2005e63de6ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644441574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1644441574
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2800872926
Short name T1277
Test name
Test status
Simulation time 20013612 ps
CPU time 0.54 seconds
Started Jul 18 06:39:57 PM PDT 24
Finished Jul 18 06:40:01 PM PDT 24
Peak memory 195300 kb
Host smart-540e1c4d-c858-42df-9a1a-0ec811866b2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800872926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2800872926
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4075780476
Short name T1230
Test name
Test status
Simulation time 30195997 ps
CPU time 0.75 seconds
Started Jul 18 06:39:59 PM PDT 24
Finished Jul 18 06:40:04 PM PDT 24
Peak memory 197820 kb
Host smart-d08f4d7f-f002-4951-b713-d3409edc1bba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075780476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.4075780476
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.4272406058
Short name T1209
Test name
Test status
Simulation time 200928787 ps
CPU time 2.16 seconds
Started Jul 18 06:39:56 PM PDT 24
Finished Jul 18 06:40:02 PM PDT 24
Peak memory 200984 kb
Host smart-cc12cda1-c24f-4dc4-b9c5-2cde4713a268
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272406058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.4272406058
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2718325958
Short name T96
Test name
Test status
Simulation time 260127444 ps
CPU time 1.33 seconds
Started Jul 18 06:39:58 PM PDT 24
Finished Jul 18 06:40:04 PM PDT 24
Peak memory 200200 kb
Host smart-47fd4953-efc3-44e8-8799-b262bbde6220
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718325958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2718325958
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3490324339
Short name T1195
Test name
Test status
Simulation time 43034913 ps
CPU time 0.86 seconds
Started Jul 18 06:39:55 PM PDT 24
Finished Jul 18 06:39:58 PM PDT 24
Peak memory 200752 kb
Host smart-5bd90753-6fc3-41c0-87e6-1b5a4738f007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490324339 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3490324339
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2983503599
Short name T1311
Test name
Test status
Simulation time 43870033 ps
CPU time 0.63 seconds
Started Jul 18 06:39:57 PM PDT 24
Finished Jul 18 06:40:01 PM PDT 24
Peak memory 196556 kb
Host smart-7b961c73-6aa9-482f-935a-2fd5e64821cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983503599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2983503599
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3659686386
Short name T1221
Test name
Test status
Simulation time 55266429 ps
CPU time 0.6 seconds
Started Jul 18 06:39:57 PM PDT 24
Finished Jul 18 06:40:01 PM PDT 24
Peak memory 195304 kb
Host smart-14d69a7f-fa0c-4e39-9ad0-ed116c746ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659686386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3659686386
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1266202433
Short name T1227
Test name
Test status
Simulation time 23900918 ps
CPU time 0.61 seconds
Started Jul 18 06:39:56 PM PDT 24
Finished Jul 18 06:39:59 PM PDT 24
Peak memory 195608 kb
Host smart-c8ec9201-28a6-4e54-ae59-bf2b19e2abde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266202433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1266202433
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1882902221
Short name T1301
Test name
Test status
Simulation time 102610356 ps
CPU time 1.97 seconds
Started Jul 18 06:39:56 PM PDT 24
Finished Jul 18 06:40:00 PM PDT 24
Peak memory 200892 kb
Host smart-93bcce55-2012-4461-9711-7729a6fa0477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882902221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1882902221
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3415761474
Short name T100
Test name
Test status
Simulation time 57267720 ps
CPU time 1 seconds
Started Jul 18 06:39:58 PM PDT 24
Finished Jul 18 06:40:03 PM PDT 24
Peak memory 200036 kb
Host smart-7ce7f90d-83d5-4532-b8bf-085cc69e16ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415761474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3415761474
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1316991845
Short name T1239
Test name
Test status
Simulation time 31046465 ps
CPU time 0.88 seconds
Started Jul 18 06:39:57 PM PDT 24
Finished Jul 18 06:40:02 PM PDT 24
Peak memory 200736 kb
Host smart-3e9fc739-fbb7-46da-a6f4-f475bdae8d18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316991845 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1316991845
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3070072607
Short name T1298
Test name
Test status
Simulation time 15832952 ps
CPU time 0.6 seconds
Started Jul 18 06:39:58 PM PDT 24
Finished Jul 18 06:40:02 PM PDT 24
Peak memory 196348 kb
Host smart-9a48e8a4-3e2a-4596-a5a7-ce25930defa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070072607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3070072607
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2928498265
Short name T1189
Test name
Test status
Simulation time 21877369 ps
CPU time 0.56 seconds
Started Jul 18 06:39:56 PM PDT 24
Finished Jul 18 06:40:00 PM PDT 24
Peak memory 195352 kb
Host smart-95df3b76-b0fd-4c3f-84f9-56ed3e2f3cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928498265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2928498265
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3321847979
Short name T1223
Test name
Test status
Simulation time 28801670 ps
CPU time 0.84 seconds
Started Jul 18 06:39:58 PM PDT 24
Finished Jul 18 06:40:03 PM PDT 24
Peak memory 197788 kb
Host smart-83654eba-bea8-4dee-ac39-aa642834d8c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321847979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3321847979
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1410443450
Short name T1262
Test name
Test status
Simulation time 32087589 ps
CPU time 1.24 seconds
Started Jul 18 06:39:56 PM PDT 24
Finished Jul 18 06:40:01 PM PDT 24
Peak memory 200996 kb
Host smart-d0a50ba5-dd6f-4f62-a279-df0cbb448f32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410443450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1410443450
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4042240074
Short name T1284
Test name
Test status
Simulation time 152793150 ps
CPU time 1.27 seconds
Started Jul 18 06:39:56 PM PDT 24
Finished Jul 18 06:40:01 PM PDT 24
Peak memory 200200 kb
Host smart-c358cdee-bb36-48f1-94bd-cb76c9d599f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042240074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.4042240074
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2008999877
Short name T1303
Test name
Test status
Simulation time 60835805 ps
CPU time 0.67 seconds
Started Jul 18 06:39:57 PM PDT 24
Finished Jul 18 06:40:02 PM PDT 24
Peak memory 198608 kb
Host smart-b4822b4a-ce56-40e4-a276-e217e1b8b56a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008999877 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2008999877
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3635442096
Short name T1283
Test name
Test status
Simulation time 14686448 ps
CPU time 0.64 seconds
Started Jul 18 06:39:57 PM PDT 24
Finished Jul 18 06:40:01 PM PDT 24
Peak memory 196616 kb
Host smart-12c3a72d-9dd3-4522-b940-05200d30d601
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635442096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3635442096
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3380401749
Short name T1309
Test name
Test status
Simulation time 28472761 ps
CPU time 0.55 seconds
Started Jul 18 06:39:56 PM PDT 24
Finished Jul 18 06:39:59 PM PDT 24
Peak memory 195248 kb
Host smart-7959bc9c-18f1-454a-b84e-1afa7b735874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380401749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3380401749
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2153625445
Short name T1261
Test name
Test status
Simulation time 67067827 ps
CPU time 0.67 seconds
Started Jul 18 06:39:55 PM PDT 24
Finished Jul 18 06:39:57 PM PDT 24
Peak memory 195772 kb
Host smart-206ba042-7289-4337-8a13-f5bf7f2ca0d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153625445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2153625445
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1858677617
Short name T1260
Test name
Test status
Simulation time 282566742 ps
CPU time 1.83 seconds
Started Jul 18 06:39:59 PM PDT 24
Finished Jul 18 06:40:05 PM PDT 24
Peak memory 200940 kb
Host smart-6239d9fb-3d5e-4ed7-abb5-34aa0079c396
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858677617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1858677617
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1500862722
Short name T91
Test name
Test status
Simulation time 145025036 ps
CPU time 0.93 seconds
Started Jul 18 06:39:57 PM PDT 24
Finished Jul 18 06:40:02 PM PDT 24
Peak memory 199664 kb
Host smart-c28c2820-728e-4140-a446-51415d5a6d08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500862722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1500862722
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2130649979
Short name T1282
Test name
Test status
Simulation time 89880805 ps
CPU time 0.8 seconds
Started Jul 18 06:39:55 PM PDT 24
Finished Jul 18 06:39:57 PM PDT 24
Peak memory 198604 kb
Host smart-2a1cbc49-c135-4685-b29b-9d117711ec41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130649979 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2130649979
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2662927798
Short name T1257
Test name
Test status
Simulation time 16489286 ps
CPU time 0.62 seconds
Started Jul 18 06:39:58 PM PDT 24
Finished Jul 18 06:40:03 PM PDT 24
Peak memory 196368 kb
Host smart-a92f09aa-3450-4160-8cbb-0fcf6e033b2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662927798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2662927798
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3130821789
Short name T1200
Test name
Test status
Simulation time 45367827 ps
CPU time 0.59 seconds
Started Jul 18 06:39:58 PM PDT 24
Finished Jul 18 06:40:03 PM PDT 24
Peak memory 195332 kb
Host smart-63c67d60-44de-4b10-a9ff-0a281e9cf042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130821789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3130821789
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1447333486
Short name T1215
Test name
Test status
Simulation time 29429838 ps
CPU time 0.72 seconds
Started Jul 18 06:39:56 PM PDT 24
Finished Jul 18 06:39:59 PM PDT 24
Peak memory 197888 kb
Host smart-09ded502-cc66-4927-9902-8c21ebc0cbd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447333486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1447333486
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.4269745437
Short name T1247
Test name
Test status
Simulation time 580715393 ps
CPU time 2.39 seconds
Started Jul 18 06:39:55 PM PDT 24
Finished Jul 18 06:39:58 PM PDT 24
Peak memory 200984 kb
Host smart-7e586e9b-b1ec-4eda-9299-73ecf3ecdcb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269745437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.4269745437
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1441035742
Short name T1250
Test name
Test status
Simulation time 807207819 ps
CPU time 1.3 seconds
Started Jul 18 06:39:56 PM PDT 24
Finished Jul 18 06:40:00 PM PDT 24
Peak memory 200180 kb
Host smart-daa036bd-5e67-4e4b-8c0b-a261b51fb27a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441035742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1441035742
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.626293955
Short name T1279
Test name
Test status
Simulation time 47376606 ps
CPU time 1.17 seconds
Started Jul 18 06:40:16 PM PDT 24
Finished Jul 18 06:40:21 PM PDT 24
Peak memory 201016 kb
Host smart-e6697534-665f-4120-826d-7d911b75bc15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626293955 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.626293955
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3310435835
Short name T1288
Test name
Test status
Simulation time 140046599 ps
CPU time 0.62 seconds
Started Jul 18 06:40:15 PM PDT 24
Finished Jul 18 06:40:20 PM PDT 24
Peak memory 196336 kb
Host smart-13e5e699-b35a-4a06-892a-2e45e6de558d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310435835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3310435835
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.193473211
Short name T1245
Test name
Test status
Simulation time 14985280 ps
CPU time 0.6 seconds
Started Jul 18 06:39:56 PM PDT 24
Finished Jul 18 06:40:00 PM PDT 24
Peak memory 195292 kb
Host smart-e044af36-a2e9-4bb4-9d17-a382c2318f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193473211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.193473211
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2287501335
Short name T1271
Test name
Test status
Simulation time 24857275 ps
CPU time 0.68 seconds
Started Jul 18 06:40:15 PM PDT 24
Finished Jul 18 06:40:17 PM PDT 24
Peak memory 195392 kb
Host smart-b449e2db-5320-4237-a00d-83c7b615aafb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287501335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2287501335
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2395166616
Short name T1275
Test name
Test status
Simulation time 46853233 ps
CPU time 1.18 seconds
Started Jul 18 06:39:59 PM PDT 24
Finished Jul 18 06:40:04 PM PDT 24
Peak memory 201004 kb
Host smart-2555b900-d6c3-4ee1-af82-201518a6fceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395166616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2395166616
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.72018317
Short name T92
Test name
Test status
Simulation time 118888388 ps
CPU time 1.35 seconds
Started Jul 18 06:39:57 PM PDT 24
Finished Jul 18 06:40:01 PM PDT 24
Peak memory 200184 kb
Host smart-ad9f7b04-e9b7-4680-ae35-99df1f898543
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72018317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.72018317
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3757107864
Short name T1243
Test name
Test status
Simulation time 22491730 ps
CPU time 1.06 seconds
Started Jul 18 06:40:14 PM PDT 24
Finished Jul 18 06:40:16 PM PDT 24
Peak memory 201000 kb
Host smart-fe66938c-6a8c-4807-915d-ddd16e6576f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757107864 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3757107864
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2058444421
Short name T1270
Test name
Test status
Simulation time 20110438 ps
CPU time 0.58 seconds
Started Jul 18 06:40:17 PM PDT 24
Finished Jul 18 06:40:21 PM PDT 24
Peak memory 196336 kb
Host smart-defcdc21-9ad1-48db-b391-763d38d5cdaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058444421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2058444421
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3131237100
Short name T1286
Test name
Test status
Simulation time 89401948 ps
CPU time 0.58 seconds
Started Jul 18 06:40:13 PM PDT 24
Finished Jul 18 06:40:15 PM PDT 24
Peak memory 195412 kb
Host smart-234459c5-f971-4f57-a2ac-10f209f1b70a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131237100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3131237100
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1993777747
Short name T86
Test name
Test status
Simulation time 118632509 ps
CPU time 0.76 seconds
Started Jul 18 06:40:15 PM PDT 24
Finished Jul 18 06:40:18 PM PDT 24
Peak memory 197912 kb
Host smart-41fbfcf9-4d6b-4228-8002-15896e1db721
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993777747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1993777747
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.369204612
Short name T1278
Test name
Test status
Simulation time 37122810 ps
CPU time 1.47 seconds
Started Jul 18 06:40:14 PM PDT 24
Finished Jul 18 06:40:18 PM PDT 24
Peak memory 201156 kb
Host smart-5819b6ff-4f49-45e8-aa15-ba777dd9d572
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369204612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.369204612
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2342474877
Short name T81
Test name
Test status
Simulation time 13935595 ps
CPU time 0.67 seconds
Started Jul 18 06:39:13 PM PDT 24
Finished Jul 18 06:39:15 PM PDT 24
Peak memory 196348 kb
Host smart-b85ac3e1-0fe1-4e6a-8920-8d964839a20b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342474877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2342474877
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.469434012
Short name T1233
Test name
Test status
Simulation time 981200160 ps
CPU time 2.49 seconds
Started Jul 18 06:39:12 PM PDT 24
Finished Jul 18 06:39:15 PM PDT 24
Peak memory 199012 kb
Host smart-132f26bc-1044-41f6-9a78-38bc5884cd31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469434012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.469434012
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2463599905
Short name T82
Test name
Test status
Simulation time 61031286 ps
CPU time 0.62 seconds
Started Jul 18 06:38:59 PM PDT 24
Finished Jul 18 06:39:02 PM PDT 24
Peak memory 196340 kb
Host smart-eb22ff52-3ef8-4871-81cf-51cb859d4b9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463599905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2463599905
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1994062603
Short name T1272
Test name
Test status
Simulation time 34631213 ps
CPU time 0.88 seconds
Started Jul 18 06:39:15 PM PDT 24
Finished Jul 18 06:39:18 PM PDT 24
Peak memory 200824 kb
Host smart-f377d5be-61d8-4f61-9456-1deacd894beb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994062603 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1994062603
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3633418226
Short name T1224
Test name
Test status
Simulation time 58307861 ps
CPU time 0.62 seconds
Started Jul 18 06:38:59 PM PDT 24
Finished Jul 18 06:39:02 PM PDT 24
Peak memory 196420 kb
Host smart-c7f32a31-6e17-4cd1-929d-03b97240c3fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633418226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3633418226
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2412040529
Short name T1290
Test name
Test status
Simulation time 13491358 ps
CPU time 0.57 seconds
Started Jul 18 06:38:58 PM PDT 24
Finished Jul 18 06:39:00 PM PDT 24
Peak memory 195284 kb
Host smart-964883db-ad08-4087-b321-553c79387909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412040529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2412040529
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1354343955
Short name T89
Test name
Test status
Simulation time 82257820 ps
CPU time 0.74 seconds
Started Jul 18 06:39:11 PM PDT 24
Finished Jul 18 06:39:13 PM PDT 24
Peak memory 196804 kb
Host smart-6db55308-8e40-4b00-9b70-39869f7d47d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354343955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1354343955
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2739935236
Short name T1214
Test name
Test status
Simulation time 121662022 ps
CPU time 2.33 seconds
Started Jul 18 06:39:00 PM PDT 24
Finished Jul 18 06:39:04 PM PDT 24
Peak memory 200924 kb
Host smart-4b653584-12cb-44df-9c33-d3d21a283719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739935236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2739935236
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.4116890870
Short name T1281
Test name
Test status
Simulation time 47719347 ps
CPU time 0.96 seconds
Started Jul 18 06:39:00 PM PDT 24
Finished Jul 18 06:39:03 PM PDT 24
Peak memory 199564 kb
Host smart-9d0159d6-5570-4818-a433-ffc263b6cd80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116890870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.4116890870
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.4018094437
Short name T1182
Test name
Test status
Simulation time 15459409 ps
CPU time 0.54 seconds
Started Jul 18 06:40:13 PM PDT 24
Finished Jul 18 06:40:15 PM PDT 24
Peak memory 195260 kb
Host smart-c8a48746-cc23-4b57-86d6-f5173f31e36c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018094437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.4018094437
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.4016816279
Short name T1264
Test name
Test status
Simulation time 12864923 ps
CPU time 0.57 seconds
Started Jul 18 06:40:14 PM PDT 24
Finished Jul 18 06:40:16 PM PDT 24
Peak memory 195300 kb
Host smart-c0588c7d-020b-4af1-a265-7477a2a6367f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016816279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.4016816279
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2892850890
Short name T1287
Test name
Test status
Simulation time 30135488 ps
CPU time 0.55 seconds
Started Jul 18 06:40:14 PM PDT 24
Finished Jul 18 06:40:16 PM PDT 24
Peak memory 195400 kb
Host smart-84c85a04-f486-4286-8a24-1dbef272eebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892850890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2892850890
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3561821190
Short name T1197
Test name
Test status
Simulation time 23973396 ps
CPU time 0.54 seconds
Started Jul 18 06:40:15 PM PDT 24
Finished Jul 18 06:40:18 PM PDT 24
Peak memory 195280 kb
Host smart-010e2a84-3e2a-451a-9453-179d66d41ca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561821190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3561821190
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3005086557
Short name T1199
Test name
Test status
Simulation time 73794938 ps
CPU time 0.56 seconds
Started Jul 18 06:40:14 PM PDT 24
Finished Jul 18 06:40:17 PM PDT 24
Peak memory 195312 kb
Host smart-93b985c3-e6c8-4d4c-aa95-c13f42de9360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005086557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3005086557
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.759262160
Short name T1312
Test name
Test status
Simulation time 45240208 ps
CPU time 0.55 seconds
Started Jul 18 06:40:17 PM PDT 24
Finished Jul 18 06:40:21 PM PDT 24
Peak memory 195236 kb
Host smart-583bddec-6d73-4132-91d7-f9ae7c43ddc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759262160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.759262160
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3098614250
Short name T1185
Test name
Test status
Simulation time 21207168 ps
CPU time 0.57 seconds
Started Jul 18 06:40:16 PM PDT 24
Finished Jul 18 06:40:21 PM PDT 24
Peak memory 194508 kb
Host smart-5d0b116c-f1e6-4c16-8003-475aa663f265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098614250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3098614250
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3187392397
Short name T1253
Test name
Test status
Simulation time 12410141 ps
CPU time 0.54 seconds
Started Jul 18 06:40:19 PM PDT 24
Finished Jul 18 06:40:22 PM PDT 24
Peak memory 195316 kb
Host smart-9212dcea-95bf-4b6c-8b1e-518ac0e30538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187392397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3187392397
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2488340124
Short name T1240
Test name
Test status
Simulation time 180383504 ps
CPU time 0.62 seconds
Started Jul 18 06:40:17 PM PDT 24
Finished Jul 18 06:40:21 PM PDT 24
Peak memory 195328 kb
Host smart-80ebc056-b0f2-471e-aeda-0c4d307f66d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488340124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2488340124
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.478076360
Short name T1316
Test name
Test status
Simulation time 44353613 ps
CPU time 0.55 seconds
Started Jul 18 06:40:15 PM PDT 24
Finished Jul 18 06:40:19 PM PDT 24
Peak memory 195248 kb
Host smart-9e3082ab-49b5-42b3-8046-d138597a5bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478076360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.478076360
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1161038527
Short name T68
Test name
Test status
Simulation time 88101237 ps
CPU time 0.79 seconds
Started Jul 18 06:39:14 PM PDT 24
Finished Jul 18 06:39:17 PM PDT 24
Peak memory 197760 kb
Host smart-e77a4500-155f-4ae3-a7c2-5b5c9f4aa118
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161038527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1161038527
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3548449963
Short name T1246
Test name
Test status
Simulation time 107001564 ps
CPU time 1.32 seconds
Started Jul 18 06:39:12 PM PDT 24
Finished Jul 18 06:39:15 PM PDT 24
Peak memory 198848 kb
Host smart-9c08717a-01d5-4e40-8fcf-73bb106c547a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548449963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3548449963
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1983316506
Short name T1203
Test name
Test status
Simulation time 37584389 ps
CPU time 0.56 seconds
Started Jul 18 06:39:15 PM PDT 24
Finished Jul 18 06:39:18 PM PDT 24
Peak memory 196412 kb
Host smart-4c914031-042a-4b06-a778-d5068425985c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983316506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1983316506
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.553932876
Short name T1194
Test name
Test status
Simulation time 48108670 ps
CPU time 0.77 seconds
Started Jul 18 06:39:15 PM PDT 24
Finished Jul 18 06:39:18 PM PDT 24
Peak memory 200588 kb
Host smart-5c24a139-a2ef-4a6e-8b83-6aed164f7cb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553932876 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.553932876
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1326190407
Short name T79
Test name
Test status
Simulation time 43341936 ps
CPU time 0.6 seconds
Started Jul 18 06:39:14 PM PDT 24
Finished Jul 18 06:39:17 PM PDT 24
Peak memory 196448 kb
Host smart-71d17618-3309-4f4d-9990-f19f881e438a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326190407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1326190407
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2464371784
Short name T1237
Test name
Test status
Simulation time 22711243 ps
CPU time 0.61 seconds
Started Jul 18 06:39:15 PM PDT 24
Finished Jul 18 06:39:18 PM PDT 24
Peak memory 195320 kb
Host smart-7f9f335a-f028-4566-85da-33341af07e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464371784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2464371784
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.563713656
Short name T1302
Test name
Test status
Simulation time 21683769 ps
CPU time 0.66 seconds
Started Jul 18 06:39:13 PM PDT 24
Finished Jul 18 06:39:16 PM PDT 24
Peak memory 196620 kb
Host smart-17ebdc45-8e16-4bac-9f9c-6d6fd1bf0692
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563713656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.563713656
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3158651384
Short name T1291
Test name
Test status
Simulation time 163708323 ps
CPU time 2.17 seconds
Started Jul 18 06:39:15 PM PDT 24
Finished Jul 18 06:39:20 PM PDT 24
Peak memory 200972 kb
Host smart-5e22c1c5-94a0-4f52-99ee-0abb1c3b3647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158651384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3158651384
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2567559315
Short name T95
Test name
Test status
Simulation time 39850875 ps
CPU time 0.94 seconds
Started Jul 18 06:39:14 PM PDT 24
Finished Jul 18 06:39:17 PM PDT 24
Peak memory 199636 kb
Host smart-fec25c45-bb60-4373-976d-3f6de0ccdfb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567559315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2567559315
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.704640975
Short name T1266
Test name
Test status
Simulation time 12696672 ps
CPU time 0.57 seconds
Started Jul 18 06:40:16 PM PDT 24
Finished Jul 18 06:40:21 PM PDT 24
Peak memory 195344 kb
Host smart-8811fd61-157d-4bb0-9760-2d948554970e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704640975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.704640975
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2146765858
Short name T1317
Test name
Test status
Simulation time 11607427 ps
CPU time 0.58 seconds
Started Jul 18 06:40:14 PM PDT 24
Finished Jul 18 06:40:17 PM PDT 24
Peak memory 195320 kb
Host smart-1d9e1195-5d57-4ede-9f8c-ccc3defdb1c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146765858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2146765858
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3382940551
Short name T1216
Test name
Test status
Simulation time 16278485 ps
CPU time 0.58 seconds
Started Jul 18 06:40:17 PM PDT 24
Finished Jul 18 06:40:22 PM PDT 24
Peak memory 195336 kb
Host smart-b71d238d-d1e9-4020-b9b1-f8f27e1db080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382940551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3382940551
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3028734111
Short name T1276
Test name
Test status
Simulation time 16222519 ps
CPU time 0.56 seconds
Started Jul 18 06:40:16 PM PDT 24
Finished Jul 18 06:40:20 PM PDT 24
Peak memory 195280 kb
Host smart-49452d74-c0d5-4f91-b188-c56fdce6764d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028734111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3028734111
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2770223428
Short name T1231
Test name
Test status
Simulation time 13063075 ps
CPU time 0.55 seconds
Started Jul 18 06:40:19 PM PDT 24
Finished Jul 18 06:40:22 PM PDT 24
Peak memory 195248 kb
Host smart-2a84d996-ddd6-439f-b806-998e897d202f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770223428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2770223428
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.34874634
Short name T1217
Test name
Test status
Simulation time 17436999 ps
CPU time 0.6 seconds
Started Jul 18 06:40:14 PM PDT 24
Finished Jul 18 06:40:17 PM PDT 24
Peak memory 195344 kb
Host smart-3330839b-159e-4c56-92af-11768da94cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34874634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.34874634
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1849350968
Short name T1188
Test name
Test status
Simulation time 43741950 ps
CPU time 0.6 seconds
Started Jul 18 06:40:18 PM PDT 24
Finished Jul 18 06:40:22 PM PDT 24
Peak memory 195320 kb
Host smart-d665b1b2-f833-45b7-b10f-904562fde86a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849350968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1849350968
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1807038092
Short name T1201
Test name
Test status
Simulation time 41330357 ps
CPU time 0.58 seconds
Started Jul 18 06:40:19 PM PDT 24
Finished Jul 18 06:40:22 PM PDT 24
Peak memory 195240 kb
Host smart-f3ff6908-7914-4512-b0b2-4ed568aecbbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807038092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1807038092
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.766455516
Short name T1198
Test name
Test status
Simulation time 34481897 ps
CPU time 0.52 seconds
Started Jul 18 06:40:19 PM PDT 24
Finished Jul 18 06:40:22 PM PDT 24
Peak memory 195248 kb
Host smart-f119ccfd-b4d6-419a-9ea0-b60553d2daed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766455516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.766455516
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.161526180
Short name T1186
Test name
Test status
Simulation time 13546299 ps
CPU time 0.58 seconds
Started Jul 18 06:40:18 PM PDT 24
Finished Jul 18 06:40:22 PM PDT 24
Peak memory 195292 kb
Host smart-bdc4f675-0791-4cb9-82dc-07baa8faa4d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161526180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.161526180
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3031658849
Short name T1204
Test name
Test status
Simulation time 19290857 ps
CPU time 0.67 seconds
Started Jul 18 06:39:12 PM PDT 24
Finished Jul 18 06:39:14 PM PDT 24
Peak memory 196328 kb
Host smart-72f739b6-5e36-4dd4-83b0-c55952e35854
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031658849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3031658849
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.491838628
Short name T1304
Test name
Test status
Simulation time 146732527 ps
CPU time 1.52 seconds
Started Jul 18 06:39:13 PM PDT 24
Finished Jul 18 06:39:17 PM PDT 24
Peak memory 198636 kb
Host smart-f6ce3aa6-ce2c-45c5-a561-f6b9a20aa62f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491838628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.491838628
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3887188596
Short name T1307
Test name
Test status
Simulation time 15527171 ps
CPU time 0.6 seconds
Started Jul 18 06:39:21 PM PDT 24
Finished Jul 18 06:39:24 PM PDT 24
Peak memory 196324 kb
Host smart-44a735a1-1bc7-4e37-9bc3-26312d91a762
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887188596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3887188596
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2130259819
Short name T1265
Test name
Test status
Simulation time 36865387 ps
CPU time 1.1 seconds
Started Jul 18 06:39:13 PM PDT 24
Finished Jul 18 06:39:17 PM PDT 24
Peak memory 200992 kb
Host smart-bfbdb45e-0595-4471-9067-98f5b80ab29a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130259819 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2130259819
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3277978975
Short name T1220
Test name
Test status
Simulation time 15132520 ps
CPU time 0.59 seconds
Started Jul 18 06:39:13 PM PDT 24
Finished Jul 18 06:39:15 PM PDT 24
Peak memory 196300 kb
Host smart-f8502655-423a-487f-a25c-8d275a3546c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277978975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3277978975
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.4063611202
Short name T1305
Test name
Test status
Simulation time 33397953 ps
CPU time 0.56 seconds
Started Jul 18 06:39:12 PM PDT 24
Finished Jul 18 06:39:13 PM PDT 24
Peak memory 195276 kb
Host smart-62b6bc91-248a-47bd-b73a-e0f99358ef3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063611202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4063611202
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1717679311
Short name T1314
Test name
Test status
Simulation time 107144439 ps
CPU time 0.63 seconds
Started Jul 18 06:39:15 PM PDT 24
Finished Jul 18 06:39:18 PM PDT 24
Peak memory 196672 kb
Host smart-c4b3b151-6baa-495d-9ae6-fb0db765e668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717679311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1717679311
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3065555664
Short name T1184
Test name
Test status
Simulation time 68256111 ps
CPU time 1.85 seconds
Started Jul 18 06:39:13 PM PDT 24
Finished Jul 18 06:39:17 PM PDT 24
Peak memory 200976 kb
Host smart-23753b46-3dce-4779-8946-f4206db180c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065555664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3065555664
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3021254741
Short name T94
Test name
Test status
Simulation time 87618180 ps
CPU time 1.32 seconds
Started Jul 18 06:39:12 PM PDT 24
Finished Jul 18 06:39:14 PM PDT 24
Peak memory 200188 kb
Host smart-20dd408b-e2ec-4be6-8704-d1731a94f484
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021254741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3021254741
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3993315146
Short name T1228
Test name
Test status
Simulation time 37929147 ps
CPU time 0.57 seconds
Started Jul 18 06:40:15 PM PDT 24
Finished Jul 18 06:40:19 PM PDT 24
Peak memory 195328 kb
Host smart-8b685f24-6058-4ed4-ac1e-5152837ee374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993315146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3993315146
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1714946531
Short name T1256
Test name
Test status
Simulation time 48340943 ps
CPU time 0.58 seconds
Started Jul 18 06:40:15 PM PDT 24
Finished Jul 18 06:40:17 PM PDT 24
Peak memory 195328 kb
Host smart-b241ba76-abee-4a2a-9b48-6df52919841a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714946531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1714946531
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1123270951
Short name T1192
Test name
Test status
Simulation time 10853751 ps
CPU time 0.57 seconds
Started Jul 18 06:40:17 PM PDT 24
Finished Jul 18 06:40:22 PM PDT 24
Peak memory 195312 kb
Host smart-0f0baef4-bd68-4f8a-9c52-7d00500aea5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123270951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1123270951
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1492508595
Short name T1306
Test name
Test status
Simulation time 17444250 ps
CPU time 0.54 seconds
Started Jul 18 06:40:16 PM PDT 24
Finished Jul 18 06:40:21 PM PDT 24
Peak memory 195296 kb
Host smart-5d7bd68d-da85-4d2c-9088-41a7f4f21da8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492508595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1492508595
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2083437229
Short name T1235
Test name
Test status
Simulation time 15322691 ps
CPU time 0.57 seconds
Started Jul 18 06:40:15 PM PDT 24
Finished Jul 18 06:40:19 PM PDT 24
Peak memory 195336 kb
Host smart-4eefb185-d623-4ef8-ac84-71357f03ddd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083437229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2083437229
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2324031930
Short name T1213
Test name
Test status
Simulation time 18392221 ps
CPU time 0.61 seconds
Started Jul 18 06:40:15 PM PDT 24
Finished Jul 18 06:40:18 PM PDT 24
Peak memory 195440 kb
Host smart-e1e5e97f-ff1b-4bd0-9116-23eb5b1c1552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324031930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2324031930
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2882436024
Short name T1218
Test name
Test status
Simulation time 15185752 ps
CPU time 0.59 seconds
Started Jul 18 06:40:16 PM PDT 24
Finished Jul 18 06:40:20 PM PDT 24
Peak memory 195304 kb
Host smart-fd29e6d6-5185-4481-a831-f4c62bae11ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882436024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2882436024
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2622462784
Short name T1255
Test name
Test status
Simulation time 14056705 ps
CPU time 0.58 seconds
Started Jul 18 06:40:14 PM PDT 24
Finished Jul 18 06:40:17 PM PDT 24
Peak memory 195260 kb
Host smart-e58330ae-47a2-4e0d-99f4-6ab9f3b54353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622462784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2622462784
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.235529823
Short name T1190
Test name
Test status
Simulation time 23062561 ps
CPU time 0.56 seconds
Started Jul 18 06:40:13 PM PDT 24
Finished Jul 18 06:40:15 PM PDT 24
Peak memory 195284 kb
Host smart-cbbae21e-0109-4f4c-9008-e7aa398594b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235529823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.235529823
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.478964568
Short name T1244
Test name
Test status
Simulation time 15871155 ps
CPU time 0.56 seconds
Started Jul 18 06:40:18 PM PDT 24
Finished Jul 18 06:40:22 PM PDT 24
Peak memory 195328 kb
Host smart-46df9352-c96b-481c-9869-75e804c5fba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478964568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.478964568
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.179212176
Short name T1187
Test name
Test status
Simulation time 91348388 ps
CPU time 0.96 seconds
Started Jul 18 06:39:25 PM PDT 24
Finished Jul 18 06:39:27 PM PDT 24
Peak memory 200824 kb
Host smart-e922bad0-587c-4ad2-8727-1f62fecb50dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179212176 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.179212176
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3453223811
Short name T1280
Test name
Test status
Simulation time 23641501 ps
CPU time 0.59 seconds
Started Jul 18 06:39:29 PM PDT 24
Finished Jul 18 06:39:31 PM PDT 24
Peak memory 196360 kb
Host smart-d6ac6d73-1269-4d03-823e-98ae1c203155
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453223811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3453223811
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.510617718
Short name T1222
Test name
Test status
Simulation time 14628644 ps
CPU time 0.57 seconds
Started Jul 18 06:39:27 PM PDT 24
Finished Jul 18 06:39:29 PM PDT 24
Peak memory 195500 kb
Host smart-d928deb5-30da-4984-a80b-029b317df577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510617718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.510617718
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4011269475
Short name T1232
Test name
Test status
Simulation time 156841584 ps
CPU time 0.63 seconds
Started Jul 18 06:39:26 PM PDT 24
Finished Jul 18 06:39:29 PM PDT 24
Peak memory 195448 kb
Host smart-60f8f2ca-3304-4a66-8c91-44f64f00f4c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011269475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.4011269475
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2019019701
Short name T1193
Test name
Test status
Simulation time 94422583 ps
CPU time 1.31 seconds
Started Jul 18 06:39:13 PM PDT 24
Finished Jul 18 06:39:16 PM PDT 24
Peak memory 200968 kb
Host smart-d6bee4a3-f324-4f04-9b11-fe6b395715e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019019701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2019019701
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.625010525
Short name T1308
Test name
Test status
Simulation time 32748838 ps
CPU time 0.9 seconds
Started Jul 18 06:39:29 PM PDT 24
Finished Jul 18 06:39:32 PM PDT 24
Peak memory 200764 kb
Host smart-4b68d0b9-bff7-4251-bc4e-e42da98e6311
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625010525 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.625010525
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3618687145
Short name T69
Test name
Test status
Simulation time 46840607 ps
CPU time 0.62 seconds
Started Jul 18 06:39:28 PM PDT 24
Finished Jul 18 06:39:31 PM PDT 24
Peak memory 196352 kb
Host smart-4feb7d83-9822-4faa-80b7-2003917f0ddc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618687145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3618687145
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1729495174
Short name T1208
Test name
Test status
Simulation time 29795202 ps
CPU time 0.57 seconds
Started Jul 18 06:39:27 PM PDT 24
Finished Jul 18 06:39:29 PM PDT 24
Peak memory 195252 kb
Host smart-d7633a6c-e038-46a0-932d-91bd37b4d11d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729495174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1729495174
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.164317212
Short name T1274
Test name
Test status
Simulation time 22379551 ps
CPU time 0.68 seconds
Started Jul 18 06:39:27 PM PDT 24
Finished Jul 18 06:39:30 PM PDT 24
Peak memory 196564 kb
Host smart-0ea95469-23d7-43a6-867d-8d4491f53d22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164317212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.164317212
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.511621948
Short name T1251
Test name
Test status
Simulation time 1421543013 ps
CPU time 1.52 seconds
Started Jul 18 06:39:25 PM PDT 24
Finished Jul 18 06:39:27 PM PDT 24
Peak memory 200952 kb
Host smart-55d38102-ae01-4cc4-a400-a29208436815
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511621948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.511621948
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3078855764
Short name T1259
Test name
Test status
Simulation time 359409948 ps
CPU time 0.95 seconds
Started Jul 18 06:39:28 PM PDT 24
Finished Jul 18 06:39:31 PM PDT 24
Peak memory 199828 kb
Host smart-a8d77d34-c8b3-4384-acf2-0886e925df9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078855764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3078855764
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3181144951
Short name T1241
Test name
Test status
Simulation time 28096335 ps
CPU time 0.78 seconds
Started Jul 18 06:39:26 PM PDT 24
Finished Jul 18 06:39:29 PM PDT 24
Peak memory 199208 kb
Host smart-534d90d1-d0fb-47ef-9d98-abd16e969d4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181144951 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3181144951
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3737001883
Short name T1293
Test name
Test status
Simulation time 53799150 ps
CPU time 0.61 seconds
Started Jul 18 06:39:27 PM PDT 24
Finished Jul 18 06:39:29 PM PDT 24
Peak memory 196412 kb
Host smart-75b5e912-5fc6-4166-8180-acf970bee40b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737001883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3737001883
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.556249895
Short name T1206
Test name
Test status
Simulation time 11115127 ps
CPU time 0.57 seconds
Started Jul 18 06:39:30 PM PDT 24
Finished Jul 18 06:39:32 PM PDT 24
Peak memory 195332 kb
Host smart-6c9ccece-0e15-469d-a3db-3c9eeaef5b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556249895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.556249895
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.322655569
Short name T1289
Test name
Test status
Simulation time 31163418 ps
CPU time 0.76 seconds
Started Jul 18 06:39:29 PM PDT 24
Finished Jul 18 06:39:32 PM PDT 24
Peak memory 197996 kb
Host smart-d0abc9c2-93d7-4d04-a312-a107c3b74c6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322655569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.322655569
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1077175043
Short name T1234
Test name
Test status
Simulation time 33257742 ps
CPU time 1.62 seconds
Started Jul 18 06:39:27 PM PDT 24
Finished Jul 18 06:39:30 PM PDT 24
Peak memory 200996 kb
Host smart-12be91e0-8265-4d4d-bb58-ebfcc9db2310
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077175043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1077175043
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3728468211
Short name T90
Test name
Test status
Simulation time 51634980 ps
CPU time 0.96 seconds
Started Jul 18 06:39:27 PM PDT 24
Finished Jul 18 06:39:30 PM PDT 24
Peak memory 199892 kb
Host smart-b76759e9-b457-4d8d-8b2a-201d7db715e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728468211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3728468211
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.329016860
Short name T1202
Test name
Test status
Simulation time 97710690 ps
CPU time 0.89 seconds
Started Jul 18 06:39:28 PM PDT 24
Finished Jul 18 06:39:31 PM PDT 24
Peak memory 200708 kb
Host smart-bf395e25-7190-4b8a-a393-673881be1573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329016860 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.329016860
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1825847625
Short name T1269
Test name
Test status
Simulation time 15495397 ps
CPU time 0.59 seconds
Started Jul 18 06:39:29 PM PDT 24
Finished Jul 18 06:39:31 PM PDT 24
Peak memory 196420 kb
Host smart-15ea31a6-236e-4964-bb12-a0c79e6c1eb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825847625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1825847625
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.192449990
Short name T1299
Test name
Test status
Simulation time 30528290 ps
CPU time 0.58 seconds
Started Jul 18 06:39:29 PM PDT 24
Finished Jul 18 06:39:32 PM PDT 24
Peak memory 195340 kb
Host smart-d503f47e-e39e-4816-a8dd-7479aea8008f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192449990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.192449990
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2306797149
Short name T1249
Test name
Test status
Simulation time 27190032 ps
CPU time 0.72 seconds
Started Jul 18 06:39:30 PM PDT 24
Finished Jul 18 06:39:32 PM PDT 24
Peak memory 197808 kb
Host smart-9cbb93f0-b6d2-4da9-be93-026050bfd9c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306797149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2306797149
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3232230784
Short name T1229
Test name
Test status
Simulation time 158302046 ps
CPU time 2.11 seconds
Started Jul 18 06:39:28 PM PDT 24
Finished Jul 18 06:39:32 PM PDT 24
Peak memory 200944 kb
Host smart-8839fb97-9b18-4251-b76a-8cb542aade27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232230784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3232230784
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2423980654
Short name T1294
Test name
Test status
Simulation time 154538013 ps
CPU time 1.26 seconds
Started Jul 18 06:39:25 PM PDT 24
Finished Jul 18 06:39:28 PM PDT 24
Peak memory 200348 kb
Host smart-71496b78-1146-4563-9af5-296a076ae77b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423980654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2423980654
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.877674501
Short name T1226
Test name
Test status
Simulation time 113142510 ps
CPU time 0.8 seconds
Started Jul 18 06:39:40 PM PDT 24
Finished Jul 18 06:39:43 PM PDT 24
Peak memory 200652 kb
Host smart-f2d0b6dc-921f-4fdc-a55d-d1532f9f5ed7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877674501 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.877674501
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2524193446
Short name T64
Test name
Test status
Simulation time 18058704 ps
CPU time 0.6 seconds
Started Jul 18 06:39:27 PM PDT 24
Finished Jul 18 06:39:29 PM PDT 24
Peak memory 196412 kb
Host smart-cd67c847-3e55-437e-bd23-d17011338702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524193446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2524193446
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3234879768
Short name T1292
Test name
Test status
Simulation time 41099722 ps
CPU time 0.56 seconds
Started Jul 18 06:39:27 PM PDT 24
Finished Jul 18 06:39:30 PM PDT 24
Peak memory 195320 kb
Host smart-0794e141-0379-40cc-892d-493d5173d2ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234879768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3234879768
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.836274462
Short name T1297
Test name
Test status
Simulation time 56973324 ps
CPU time 0.75 seconds
Started Jul 18 06:39:42 PM PDT 24
Finished Jul 18 06:39:46 PM PDT 24
Peak memory 198052 kb
Host smart-a239e98b-a1df-4b4c-bc52-91bab1d1a622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836274462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.836274462
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.4260657063
Short name T1183
Test name
Test status
Simulation time 400237835 ps
CPU time 2.25 seconds
Started Jul 18 06:39:27 PM PDT 24
Finished Jul 18 06:39:31 PM PDT 24
Peak memory 201152 kb
Host smart-fab22a86-c8b8-4f0b-8a60-ff4bf2168bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260657063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.4260657063
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2791307779
Short name T99
Test name
Test status
Simulation time 142479753 ps
CPU time 1.22 seconds
Started Jul 18 06:39:28 PM PDT 24
Finished Jul 18 06:39:31 PM PDT 24
Peak memory 200072 kb
Host smart-19cd1701-42eb-48e5-8c3e-d018afd79f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791307779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2791307779
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.926131961
Short name T355
Test name
Test status
Simulation time 48335765 ps
CPU time 0.55 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:47:55 PM PDT 24
Peak memory 195868 kb
Host smart-f8745cb6-25f9-4625-ade7-d01c15b362b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926131961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.926131961
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.31316714
Short name T412
Test name
Test status
Simulation time 31307554601 ps
CPU time 57.74 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:48:52 PM PDT 24
Peak memory 200128 kb
Host smart-878e09d3-9d51-4baa-873e-2ac472a0af9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31316714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.31316714
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.4094901262
Short name T836
Test name
Test status
Simulation time 135946594141 ps
CPU time 206.97 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:51:21 PM PDT 24
Peak memory 200100 kb
Host smart-69ee3c59-9072-4df6-95e1-c607360d98db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094901262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.4094901262
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3992905388
Short name T1179
Test name
Test status
Simulation time 19152383843 ps
CPU time 32.88 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:48:21 PM PDT 24
Peak memory 200192 kb
Host smart-8bae745c-3ee1-4a53-8d38-b78bcd916b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992905388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3992905388
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2832863956
Short name T784
Test name
Test status
Simulation time 137236461523 ps
CPU time 1241.63 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 07:08:35 PM PDT 24
Peak memory 200116 kb
Host smart-ee127a4e-b829-4aef-9782-3e6ea962362a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2832863956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2832863956
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2290898314
Short name T624
Test name
Test status
Simulation time 2317276810 ps
CPU time 1.88 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:47:53 PM PDT 24
Peak memory 197848 kb
Host smart-ab64aa22-d7cb-47c0-a528-e6a6b8728eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290898314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2290898314
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.207978213
Short name T1046
Test name
Test status
Simulation time 185099239512 ps
CPU time 71.32 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:49:07 PM PDT 24
Peak memory 200312 kb
Host smart-67ba3798-5673-4d0f-9811-c0cc784f080a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207978213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.207978213
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.403023829
Short name T658
Test name
Test status
Simulation time 11559766197 ps
CPU time 666.86 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:58:56 PM PDT 24
Peak memory 200200 kb
Host smart-bff2a1b2-0964-4284-bb48-df4ba303e003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403023829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.403023829
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2723265694
Short name T805
Test name
Test status
Simulation time 3618671942 ps
CPU time 7.83 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:48:00 PM PDT 24
Peak memory 198208 kb
Host smart-e20c9447-b4a0-4d83-9fa8-8340016426c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2723265694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2723265694
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.853793911
Short name T914
Test name
Test status
Simulation time 229819551192 ps
CPU time 172.83 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:50:43 PM PDT 24
Peak memory 199960 kb
Host smart-e9f1ffca-4046-4773-8ff7-df5921f8c419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853793911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.853793911
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2288340722
Short name T330
Test name
Test status
Simulation time 47459544728 ps
CPU time 77.2 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:49:09 PM PDT 24
Peak memory 196016 kb
Host smart-0adc8e77-f7c5-497a-9e24-3da2eda130ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288340722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2288340722
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2648035332
Short name T33
Test name
Test status
Simulation time 62636182 ps
CPU time 0.88 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:47:54 PM PDT 24
Peak memory 218588 kb
Host smart-52a58aa9-682c-442e-8875-6e2c0e5ef782
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648035332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2648035332
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2730133712
Short name T748
Test name
Test status
Simulation time 293585622 ps
CPU time 0.93 seconds
Started Jul 18 06:47:42 PM PDT 24
Finished Jul 18 06:47:46 PM PDT 24
Peak memory 198716 kb
Host smart-b4b31bde-1786-405b-ae94-56f3a85ad1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730133712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2730133712
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.523785146
Short name T57
Test name
Test status
Simulation time 169019128652 ps
CPU time 719.14 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:59:53 PM PDT 24
Peak memory 216800 kb
Host smart-b136f6f3-606e-482f-a1dd-957900934bbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523785146 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.523785146
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1336330632
Short name T510
Test name
Test status
Simulation time 591305863 ps
CPU time 2.21 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:47:54 PM PDT 24
Peak memory 198504 kb
Host smart-813fb857-aa30-4e75-a3a7-96b9e5af0f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336330632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1336330632
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.221071927
Short name T321
Test name
Test status
Simulation time 8020951720 ps
CPU time 4.1 seconds
Started Jul 18 06:47:42 PM PDT 24
Finished Jul 18 06:47:50 PM PDT 24
Peak memory 198796 kb
Host smart-6b0b1996-8b18-4aae-a8ed-ed4f9193aa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221071927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.221071927
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2056176567
Short name T907
Test name
Test status
Simulation time 13754899 ps
CPU time 0.55 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:47:56 PM PDT 24
Peak memory 195040 kb
Host smart-8caaaafa-5156-43a0-9d99-25960338894d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056176567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2056176567
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1127158272
Short name T175
Test name
Test status
Simulation time 100499833445 ps
CPU time 25.98 seconds
Started Jul 18 06:47:41 PM PDT 24
Finished Jul 18 06:48:09 PM PDT 24
Peak memory 200212 kb
Host smart-c4e7c7c7-b8cc-469b-8709-447c1eca144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127158272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1127158272
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2296244275
Short name T1141
Test name
Test status
Simulation time 141486527193 ps
CPU time 109.69 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:49:43 PM PDT 24
Peak memory 200372 kb
Host smart-ac377f83-1a8f-4adc-8255-b3666b62d974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296244275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2296244275
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.3667359450
Short name T480
Test name
Test status
Simulation time 24832528143 ps
CPU time 51.39 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:48:45 PM PDT 24
Peak memory 200360 kb
Host smart-39f1b829-c0c3-4e16-bb1a-c41e0da6131c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667359450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3667359450
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.4127046972
Short name T468
Test name
Test status
Simulation time 83466258723 ps
CPU time 162.83 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:50:32 PM PDT 24
Peak memory 200104 kb
Host smart-e68e6d15-0a84-4222-92fd-28b898ade4ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4127046972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.4127046972
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3076875572
Short name T1078
Test name
Test status
Simulation time 450259174 ps
CPU time 1.32 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:47:55 PM PDT 24
Peak memory 196208 kb
Host smart-25c18a91-8b0b-47fc-b8b9-a128c4fa3ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076875572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3076875572
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3924738721
Short name T686
Test name
Test status
Simulation time 8681466846 ps
CPU time 13.99 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:48:10 PM PDT 24
Peak memory 200108 kb
Host smart-130d291c-1d02-4ff7-ac9f-d5fe65add6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924738721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3924738721
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1901377082
Short name T377
Test name
Test status
Simulation time 7634577261 ps
CPU time 424.63 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:54:59 PM PDT 24
Peak memory 200208 kb
Host smart-e3fa5ac2-4a75-44f6-91c1-65973ab92b45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901377082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1901377082
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.261670073
Short name T382
Test name
Test status
Simulation time 4216628331 ps
CPU time 17.54 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:48:13 PM PDT 24
Peak memory 198416 kb
Host smart-338a54a6-ae31-428f-8cf6-87f8e31b8c97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261670073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.261670073
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3024028039
Short name T1022
Test name
Test status
Simulation time 219012961987 ps
CPU time 253.1 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:52:08 PM PDT 24
Peak memory 200200 kb
Host smart-1a889c64-76b2-496a-9404-f04b0f2a9660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024028039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3024028039
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.4144442874
Short name T28
Test name
Test status
Simulation time 3528132667 ps
CPU time 6.5 seconds
Started Jul 18 06:47:40 PM PDT 24
Finished Jul 18 06:47:48 PM PDT 24
Peak memory 196300 kb
Host smart-717ff530-0321-4231-ac98-aecfadcbac7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144442874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4144442874
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1003342526
Short name T101
Test name
Test status
Simulation time 100571195 ps
CPU time 0.9 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:47:51 PM PDT 24
Peak memory 218408 kb
Host smart-b9106d8d-2e2f-4099-b450-95128344df16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003342526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1003342526
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1683323487
Short name T278
Test name
Test status
Simulation time 649624533 ps
CPU time 2.57 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:47:57 PM PDT 24
Peak memory 199548 kb
Host smart-664556a2-f700-45de-9396-738e3d80ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683323487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1683323487
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3502962249
Short name T822
Test name
Test status
Simulation time 137502898477 ps
CPU time 610.57 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:58:05 PM PDT 24
Peak memory 200184 kb
Host smart-40be44e1-b887-4137-ac27-a7a583a91b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502962249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3502962249
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2060854231
Short name T311
Test name
Test status
Simulation time 120311389374 ps
CPU time 200.94 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:51:10 PM PDT 24
Peak memory 216812 kb
Host smart-56a6d2e0-dba2-4456-8c73-b838fa7f01a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060854231 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2060854231
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3841129946
Short name T1021
Test name
Test status
Simulation time 6619740853 ps
CPU time 19.14 seconds
Started Jul 18 06:47:43 PM PDT 24
Finished Jul 18 06:48:07 PM PDT 24
Peak memory 199944 kb
Host smart-e29a4337-68c4-41ff-b291-2b39ea1a7504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841129946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3841129946
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3147812350
Short name T800
Test name
Test status
Simulation time 69157814401 ps
CPU time 52.24 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:48:44 PM PDT 24
Peak memory 200316 kb
Host smart-14b2f6b4-04d7-4b4a-b3e4-f01a72792fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147812350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3147812350
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2134813104
Short name T776
Test name
Test status
Simulation time 24350934 ps
CPU time 0.59 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:30 PM PDT 24
Peak memory 195576 kb
Host smart-79ce5ab8-b718-4ea1-8fee-0b7c8d435db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134813104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2134813104
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.403742109
Short name T600
Test name
Test status
Simulation time 35390968150 ps
CPU time 15 seconds
Started Jul 18 06:48:07 PM PDT 24
Finished Jul 18 06:48:26 PM PDT 24
Peak memory 199944 kb
Host smart-5984288d-e8fa-49a3-b5ed-14a0001aedc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403742109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.403742109
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2808991338
Short name T1001
Test name
Test status
Simulation time 11485703173 ps
CPU time 20.38 seconds
Started Jul 18 06:48:10 PM PDT 24
Finished Jul 18 06:48:34 PM PDT 24
Peak memory 200180 kb
Host smart-2e2fd38a-7f76-47a7-9c4c-0dfc690ab7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808991338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2808991338
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3009101480
Short name T247
Test name
Test status
Simulation time 15022151199 ps
CPU time 20.2 seconds
Started Jul 18 06:48:07 PM PDT 24
Finished Jul 18 06:48:31 PM PDT 24
Peak memory 200192 kb
Host smart-ea405e4e-e206-46cf-973c-2e815c756705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009101480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3009101480
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.201807216
Short name T572
Test name
Test status
Simulation time 8911437459 ps
CPU time 5.59 seconds
Started Jul 18 06:48:07 PM PDT 24
Finished Jul 18 06:48:16 PM PDT 24
Peak memory 200184 kb
Host smart-c0e90fc6-abc3-49c6-912f-2dca3ede3dec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201807216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.201807216
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2148142720
Short name T630
Test name
Test status
Simulation time 74270851981 ps
CPU time 399.38 seconds
Started Jul 18 06:48:27 PM PDT 24
Finished Jul 18 06:55:12 PM PDT 24
Peak memory 200168 kb
Host smart-3ca4c239-1c04-4ca4-9dd4-c9eb5d000e4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148142720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2148142720
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.761550556
Short name T863
Test name
Test status
Simulation time 4305812555 ps
CPU time 1.46 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:31 PM PDT 24
Peak memory 198724 kb
Host smart-20214587-91cd-4c7b-932c-686944169ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761550556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.761550556
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2379423635
Short name T807
Test name
Test status
Simulation time 55496261610 ps
CPU time 103.71 seconds
Started Jul 18 06:48:22 PM PDT 24
Finished Jul 18 06:50:07 PM PDT 24
Peak memory 200400 kb
Host smart-78413c35-f230-4258-8fd4-2ab2daa8c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379423635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2379423635
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.4270025777
Short name T589
Test name
Test status
Simulation time 20239556987 ps
CPU time 253.25 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:52:42 PM PDT 24
Peak memory 200208 kb
Host smart-b94ff4a5-b510-4754-97d5-b74a92ac2418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270025777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4270025777
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.437049551
Short name T364
Test name
Test status
Simulation time 5665922075 ps
CPU time 13.06 seconds
Started Jul 18 06:48:08 PM PDT 24
Finished Jul 18 06:48:25 PM PDT 24
Peak memory 198652 kb
Host smart-95a37af6-7a3e-4d57-aa7a-4e8985cc4d1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=437049551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.437049551
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3806313422
Short name T895
Test name
Test status
Simulation time 17100838725 ps
CPU time 23.74 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:53 PM PDT 24
Peak memory 198664 kb
Host smart-1a835b6e-6521-41e5-8cdf-2fb8664d7024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806313422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3806313422
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2499093196
Short name T639
Test name
Test status
Simulation time 41445724548 ps
CPU time 3.42 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:48:34 PM PDT 24
Peak memory 196040 kb
Host smart-40bd0514-ef9c-4780-8727-95a93c9b36d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499093196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2499093196
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2175820444
Short name T408
Test name
Test status
Simulation time 5974700791 ps
CPU time 24.03 seconds
Started Jul 18 06:48:06 PM PDT 24
Finished Jul 18 06:48:33 PM PDT 24
Peak memory 200184 kb
Host smart-ddc4f8e8-caf9-4d9e-9270-6ec8d5feb385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175820444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2175820444
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.4278391856
Short name T812
Test name
Test status
Simulation time 354576895437 ps
CPU time 203.8 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:51:52 PM PDT 24
Peak memory 216692 kb
Host smart-de210337-2a2e-49d7-a275-b14f88806880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278391856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4278391856
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2678711535
Short name T342
Test name
Test status
Simulation time 539964724 ps
CPU time 2.01 seconds
Started Jul 18 06:48:22 PM PDT 24
Finished Jul 18 06:48:25 PM PDT 24
Peak memory 198656 kb
Host smart-02b74539-c6ae-4252-aa87-fe341edf4651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678711535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2678711535
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3618765353
Short name T773
Test name
Test status
Simulation time 83076239647 ps
CPU time 86.2 seconds
Started Jul 18 06:48:08 PM PDT 24
Finished Jul 18 06:49:38 PM PDT 24
Peak memory 200136 kb
Host smart-aaf15b72-6ce3-41dc-8394-e49fa0e66b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618765353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3618765353
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1129785605
Short name T824
Test name
Test status
Simulation time 59025155874 ps
CPU time 22.88 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 06:52:22 PM PDT 24
Peak memory 200044 kb
Host smart-7fc2e308-cef7-4811-934a-dd16a4978948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129785605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1129785605
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1635967437
Short name T1073
Test name
Test status
Simulation time 15169877219 ps
CPU time 14.02 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 06:52:13 PM PDT 24
Peak memory 200192 kb
Host smart-49c558c6-861c-4263-abea-a585bdea7d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635967437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1635967437
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3795625639
Short name T257
Test name
Test status
Simulation time 148692090944 ps
CPU time 137.76 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 06:54:16 PM PDT 24
Peak memory 200136 kb
Host smart-ccd273f3-6245-4325-85dd-d3c63c7774b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795625639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3795625639
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.355480106
Short name T876
Test name
Test status
Simulation time 47315789991 ps
CPU time 21.17 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 06:52:18 PM PDT 24
Peak memory 200128 kb
Host smart-def07acd-f7b3-41a0-b210-b48bbf5e0204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355480106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.355480106
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1444676567
Short name T414
Test name
Test status
Simulation time 35342948722 ps
CPU time 14.3 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 06:52:14 PM PDT 24
Peak memory 199688 kb
Host smart-230aded9-a5e2-4cd3-a3ef-52b0a870c110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444676567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1444676567
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.2955677292
Short name T772
Test name
Test status
Simulation time 148282812663 ps
CPU time 123.71 seconds
Started Jul 18 06:51:53 PM PDT 24
Finished Jul 18 06:53:58 PM PDT 24
Peak memory 200164 kb
Host smart-7d293cfa-1438-4df6-95b8-077b5ddfa572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955677292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2955677292
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3793178495
Short name T188
Test name
Test status
Simulation time 66469629753 ps
CPU time 97.61 seconds
Started Jul 18 06:51:58 PM PDT 24
Finished Jul 18 06:53:38 PM PDT 24
Peak memory 200136 kb
Host smart-f21679f5-24da-4d60-91c0-1806f11ef3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793178495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3793178495
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.614700032
Short name T129
Test name
Test status
Simulation time 18792571506 ps
CPU time 27.41 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 06:52:27 PM PDT 24
Peak memory 199968 kb
Host smart-1ef0fbe3-7812-4f42-81bb-25007ac6b2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614700032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.614700032
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.336737339
Short name T635
Test name
Test status
Simulation time 40988656891 ps
CPU time 13.46 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 06:52:12 PM PDT 24
Peak memory 199916 kb
Host smart-8f4fe43d-a262-49c5-ab06-64b6677f6812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336737339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.336737339
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.197395324
Short name T603
Test name
Test status
Simulation time 23184186736 ps
CPU time 38.14 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 06:52:35 PM PDT 24
Peak memory 200268 kb
Host smart-3c03f3d5-39f4-4296-a0f9-d2412a357705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197395324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.197395324
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2895137678
Short name T752
Test name
Test status
Simulation time 114130326 ps
CPU time 0.58 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:48:32 PM PDT 24
Peak memory 194920 kb
Host smart-6d182f25-efd7-43e7-8188-8f7dc6f1087b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895137678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2895137678
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.4196529581
Short name T806
Test name
Test status
Simulation time 4221903528 ps
CPU time 7.03 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:35 PM PDT 24
Peak memory 200128 kb
Host smart-1fe9fef3-a235-4309-9b00-bf75bb8e350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196529581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.4196529581
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1530741559
Short name T1088
Test name
Test status
Simulation time 32854524955 ps
CPU time 51.64 seconds
Started Jul 18 06:48:27 PM PDT 24
Finished Jul 18 06:49:24 PM PDT 24
Peak memory 200200 kb
Host smart-0e89f9d3-d4fc-4931-a518-684bdaacca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530741559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1530741559
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.643418402
Short name T848
Test name
Test status
Simulation time 85399002793 ps
CPU time 76.21 seconds
Started Jul 18 06:48:28 PM PDT 24
Finished Jul 18 06:49:49 PM PDT 24
Peak memory 200176 kb
Host smart-87f6578c-8f2d-4c7c-aa88-58408a7c8034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643418402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.643418402
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1344576610
Short name T397
Test name
Test status
Simulation time 17844704398 ps
CPU time 20.75 seconds
Started Jul 18 06:48:20 PM PDT 24
Finished Jul 18 06:48:41 PM PDT 24
Peak memory 200140 kb
Host smart-cc304148-91bc-49ad-ac52-1a4e92764275
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344576610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1344576610
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2128051192
Short name T497
Test name
Test status
Simulation time 119721044613 ps
CPU time 833.68 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 07:02:24 PM PDT 24
Peak memory 200080 kb
Host smart-28654f83-b26d-4014-b716-207a86d3aa59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128051192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2128051192
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1305868929
Short name T920
Test name
Test status
Simulation time 9451152613 ps
CPU time 5.3 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:48:30 PM PDT 24
Peak memory 198908 kb
Host smart-a78b33d8-6da4-4517-a64a-0a157a70e8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305868929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1305868929
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1672980940
Short name T280
Test name
Test status
Simulation time 239351047025 ps
CPU time 28.93 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:48:55 PM PDT 24
Peak memory 208176 kb
Host smart-5306b899-4eea-4045-ada0-9908f814ba4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672980940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1672980940
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1093009261
Short name T1093
Test name
Test status
Simulation time 23228946559 ps
CPU time 1126.08 seconds
Started Jul 18 06:48:27 PM PDT 24
Finished Jul 18 07:07:18 PM PDT 24
Peak memory 200200 kb
Host smart-3e1ca0fd-4da0-4539-8d29-8fdd4d3b56ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093009261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1093009261
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2081699837
Short name T1041
Test name
Test status
Simulation time 6666888480 ps
CPU time 13.73 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:43 PM PDT 24
Peak memory 198296 kb
Host smart-a29a84e2-ea1f-4480-b08c-f78224dbb3d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081699837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2081699837
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2792757837
Short name T815
Test name
Test status
Simulation time 86287767738 ps
CPU time 63.97 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:49:34 PM PDT 24
Peak memory 200132 kb
Host smart-a8e6f1f3-5717-4e2e-82ba-ab85a5d3bbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792757837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2792757837
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.942427053
Short name T307
Test name
Test status
Simulation time 4284513721 ps
CPU time 6.33 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:48:32 PM PDT 24
Peak memory 196488 kb
Host smart-5a10a7de-f79c-40c1-a9d1-f4753a3aa7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942427053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.942427053
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.809755989
Short name T621
Test name
Test status
Simulation time 429512227 ps
CPU time 1.83 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:30 PM PDT 24
Peak memory 198604 kb
Host smart-f9c1e801-d63e-4019-849b-5bd768a57ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809755989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.809755989
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1460430434
Short name T121
Test name
Test status
Simulation time 155987968416 ps
CPU time 289.83 seconds
Started Jul 18 06:48:27 PM PDT 24
Finished Jul 18 06:53:23 PM PDT 24
Peak memory 200184 kb
Host smart-790f5fab-bef0-4648-9250-9dfd4801421b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460430434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1460430434
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1521863173
Short name T58
Test name
Test status
Simulation time 37121554014 ps
CPU time 830.1 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 07:02:19 PM PDT 24
Peak memory 216924 kb
Host smart-bd023126-0638-4d51-a92d-4d4a79a06633
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521863173 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1521863173
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.267797816
Short name T794
Test name
Test status
Simulation time 1293455850 ps
CPU time 2.13 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:32 PM PDT 24
Peak memory 199072 kb
Host smart-27454207-f3d1-4b27-8df8-047c28cb9ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267797816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.267797816
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.4115349117
Short name T481
Test name
Test status
Simulation time 34273627115 ps
CPU time 13.86 seconds
Started Jul 18 06:48:20 PM PDT 24
Finished Jul 18 06:48:34 PM PDT 24
Peak memory 199988 kb
Host smart-cd3ac725-f468-4fd4-8ba4-f17a548f499a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115349117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4115349117
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3774403453
Short name T586
Test name
Test status
Simulation time 32607837241 ps
CPU time 53.88 seconds
Started Jul 18 06:51:58 PM PDT 24
Finished Jul 18 06:52:54 PM PDT 24
Peak memory 200156 kb
Host smart-97c27ec2-933f-4f72-8b30-3752dd5e67b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774403453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3774403453
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1351066
Short name T697
Test name
Test status
Simulation time 134834243022 ps
CPU time 21.31 seconds
Started Jul 18 06:52:08 PM PDT 24
Finished Jul 18 06:52:30 PM PDT 24
Peak memory 200200 kb
Host smart-276202c6-c663-4931-a4e8-fdad8b99006f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1351066
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.914783272
Short name T309
Test name
Test status
Simulation time 10519750891 ps
CPU time 15.01 seconds
Started Jul 18 06:52:13 PM PDT 24
Finished Jul 18 06:52:31 PM PDT 24
Peak memory 200192 kb
Host smart-09c1faa3-5ba4-40cb-b017-b5093b7539ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914783272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.914783272
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2588930905
Short name T484
Test name
Test status
Simulation time 69078753128 ps
CPU time 87.92 seconds
Started Jul 18 06:52:10 PM PDT 24
Finished Jul 18 06:53:40 PM PDT 24
Peak memory 200196 kb
Host smart-6f65f490-8584-4af8-a89a-a7c3a012920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588930905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2588930905
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.305686449
Short name T289
Test name
Test status
Simulation time 173351506811 ps
CPU time 142.65 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:54:34 PM PDT 24
Peak memory 200112 kb
Host smart-4d4b992d-7792-4985-88cf-0c6cb84219b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305686449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.305686449
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3662270213
Short name T76
Test name
Test status
Simulation time 43584275840 ps
CPU time 114.24 seconds
Started Jul 18 06:52:07 PM PDT 24
Finished Jul 18 06:54:03 PM PDT 24
Peak memory 200160 kb
Host smart-ea0145e4-6555-4867-a927-f6208f78fb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662270213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3662270213
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2117038744
Short name T10
Test name
Test status
Simulation time 18954882011 ps
CPU time 42.21 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:52:54 PM PDT 24
Peak memory 200168 kb
Host smart-fa183aef-2739-4ff9-af52-76c835101111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117038744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2117038744
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.4058249758
Short name T645
Test name
Test status
Simulation time 24721454 ps
CPU time 0.57 seconds
Started Jul 18 06:48:22 PM PDT 24
Finished Jul 18 06:48:25 PM PDT 24
Peak memory 195568 kb
Host smart-8246c74b-b24a-4326-8bd2-5a92f095c6c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058249758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4058249758
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2378534680
Short name T1091
Test name
Test status
Simulation time 13682490780 ps
CPU time 22.94 seconds
Started Jul 18 06:48:20 PM PDT 24
Finished Jul 18 06:48:44 PM PDT 24
Peak memory 200216 kb
Host smart-21e63be6-9473-43a3-a50d-4d8835b5fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378534680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2378534680
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.4087744591
Short name T1118
Test name
Test status
Simulation time 132705541471 ps
CPU time 49.43 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:49:17 PM PDT 24
Peak memory 200200 kb
Host smart-8da94508-f81c-438d-914a-604ef53b47ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087744591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.4087744591
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2951964714
Short name T999
Test name
Test status
Simulation time 62927036783 ps
CPU time 47.94 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:49:15 PM PDT 24
Peak memory 200196 kb
Host smart-5e494359-15b0-485f-95e2-de797bb8f37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951964714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2951964714
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.479772347
Short name T713
Test name
Test status
Simulation time 49354447874 ps
CPU time 22.02 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:48:53 PM PDT 24
Peak memory 199932 kb
Host smart-a0420f40-b21e-452c-af6b-bcb2d18963a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479772347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.479772347
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.608970856
Short name T248
Test name
Test status
Simulation time 114121712791 ps
CPU time 469.66 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:56:19 PM PDT 24
Peak memory 200108 kb
Host smart-ff13d539-f28e-4138-9df2-1931182176e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=608970856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.608970856
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1663035507
Short name T360
Test name
Test status
Simulation time 3968495413 ps
CPU time 8.25 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:37 PM PDT 24
Peak memory 199924 kb
Host smart-97b3e775-8def-4126-93d2-4a5351756486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663035507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1663035507
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.820935305
Short name T41
Test name
Test status
Simulation time 14364704579 ps
CPU time 25.11 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:48:51 PM PDT 24
Peak memory 198648 kb
Host smart-202bcc9e-1b48-469b-bb2a-ee436593aaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820935305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.820935305
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2550872681
Short name T1043
Test name
Test status
Simulation time 23621898251 ps
CPU time 1207.75 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 07:08:37 PM PDT 24
Peak memory 200212 kb
Host smart-19860764-eeff-45fa-a8d9-ad200e4dd710
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2550872681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2550872681
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1469551897
Short name T1005
Test name
Test status
Simulation time 5586496857 ps
CPU time 43.44 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:49:11 PM PDT 24
Peak memory 199016 kb
Host smart-e83ca984-3c7a-4785-b982-974cd38b9034
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469551897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1469551897
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.122784925
Short name T433
Test name
Test status
Simulation time 70072868375 ps
CPU time 73.71 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:49:43 PM PDT 24
Peak memory 200136 kb
Host smart-0d5f756f-2e6f-4ee8-8793-7c830b4d2716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122784925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.122784925
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3044254266
Short name T498
Test name
Test status
Simulation time 4524943030 ps
CPU time 1.4 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:31 PM PDT 24
Peak memory 196304 kb
Host smart-742106c6-411e-47d4-b70d-21cc21d79430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044254266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3044254266
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1409366898
Short name T409
Test name
Test status
Simulation time 669773095 ps
CPU time 1.61 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:31 PM PDT 24
Peak memory 198964 kb
Host smart-fb1cdbad-4dc6-4fbb-bef6-e3f833c4db7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409366898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1409366898
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.448291356
Short name T775
Test name
Test status
Simulation time 6731568952 ps
CPU time 12.88 seconds
Started Jul 18 06:48:22 PM PDT 24
Finished Jul 18 06:48:36 PM PDT 24
Peak memory 199992 kb
Host smart-e4573b80-232d-4a08-aee6-b9837f9b53c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448291356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.448291356
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2585118429
Short name T287
Test name
Test status
Simulation time 102525207840 ps
CPU time 27.28 seconds
Started Jul 18 06:48:22 PM PDT 24
Finished Jul 18 06:48:51 PM PDT 24
Peak memory 200204 kb
Host smart-ce61f8fe-027f-4ee2-945d-ec948f309918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585118429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2585118429
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1288410877
Short name T1010
Test name
Test status
Simulation time 45902423133 ps
CPU time 62.04 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:53:13 PM PDT 24
Peak memory 200156 kb
Host smart-630d8c79-f806-47ce-af1b-368efa5b413d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288410877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1288410877
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.4127951684
Short name T525
Test name
Test status
Simulation time 70963211464 ps
CPU time 46.88 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:52:59 PM PDT 24
Peak memory 200192 kb
Host smart-93f90d0f-c173-430e-8f98-3af46c1094fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127951684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.4127951684
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1382952256
Short name T592
Test name
Test status
Simulation time 54944090237 ps
CPU time 56.62 seconds
Started Jul 18 06:52:08 PM PDT 24
Finished Jul 18 06:53:06 PM PDT 24
Peak memory 200200 kb
Host smart-b3b171b6-7815-4e27-8229-f9b5d8e10d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382952256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1382952256
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3009987812
Short name T796
Test name
Test status
Simulation time 48376113279 ps
CPU time 32.02 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:52:43 PM PDT 24
Peak memory 200192 kb
Host smart-2d971794-7b61-499c-97bc-f915c7d60bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009987812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3009987812
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.975153540
Short name T1101
Test name
Test status
Simulation time 44305614822 ps
CPU time 63.78 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:53:15 PM PDT 24
Peak memory 200120 kb
Host smart-53aa9bb8-2459-4337-8e6b-a8bd2fc2d20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975153540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.975153540
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.4101981385
Short name T585
Test name
Test status
Simulation time 167370028431 ps
CPU time 23.64 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:52:36 PM PDT 24
Peak memory 200208 kb
Host smart-23ab4451-b951-4b96-ba0c-6b026dc13525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101981385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.4101981385
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2277428691
Short name T492
Test name
Test status
Simulation time 168305894024 ps
CPU time 143.51 seconds
Started Jul 18 06:52:13 PM PDT 24
Finished Jul 18 06:54:40 PM PDT 24
Peak memory 200200 kb
Host smart-32dbc2da-7bc0-4875-a249-ca9cfd25a70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277428691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2277428691
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2013608442
Short name T71
Test name
Test status
Simulation time 62651504695 ps
CPU time 16.39 seconds
Started Jul 18 06:52:14 PM PDT 24
Finished Jul 18 06:52:34 PM PDT 24
Peak memory 200280 kb
Host smart-e586f474-533e-4cc8-9f0e-6d0e6d7aa3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013608442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2013608442
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2540758307
Short name T778
Test name
Test status
Simulation time 28852444374 ps
CPU time 36.92 seconds
Started Jul 18 06:52:12 PM PDT 24
Finished Jul 18 06:52:51 PM PDT 24
Peak memory 200140 kb
Host smart-f6595679-a1a7-4be3-8aef-6dee188abfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540758307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2540758307
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.178639048
Short name T529
Test name
Test status
Simulation time 22248308 ps
CPU time 0.57 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:48:32 PM PDT 24
Peak memory 194560 kb
Host smart-8c7790d7-40bb-44b9-8127-cef9b2b01171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178639048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.178639048
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.426997882
Short name T103
Test name
Test status
Simulation time 27882385924 ps
CPU time 48.21 seconds
Started Jul 18 06:48:22 PM PDT 24
Finished Jul 18 06:49:11 PM PDT 24
Peak memory 200196 kb
Host smart-61ea680a-e305-41de-8a98-759857b9ad96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426997882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.426997882
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.389876314
Short name T604
Test name
Test status
Simulation time 120192934101 ps
CPU time 86.47 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:49:52 PM PDT 24
Peak memory 200144 kb
Host smart-4f98c8b9-4db9-4e1a-b89c-761b764bd4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389876314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.389876314
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.428982189
Short name T898
Test name
Test status
Simulation time 47518465977 ps
CPU time 128.75 seconds
Started Jul 18 06:48:27 PM PDT 24
Finished Jul 18 06:50:41 PM PDT 24
Peak memory 200184 kb
Host smart-afe7fcbe-db21-4f30-b647-acc6d8bec2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428982189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.428982189
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2911003723
Short name T795
Test name
Test status
Simulation time 25931222830 ps
CPU time 15.49 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:43 PM PDT 24
Peak memory 200188 kb
Host smart-a3c4f793-58f0-4564-9b2f-e9cb4e98459a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911003723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2911003723
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1966161341
Short name T516
Test name
Test status
Simulation time 138041223335 ps
CPU time 536.06 seconds
Started Jul 18 06:48:28 PM PDT 24
Finished Jul 18 06:57:29 PM PDT 24
Peak memory 200172 kb
Host smart-12a51f8a-2b70-4a44-9e89-17017ab72477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1966161341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1966161341
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1506026421
Short name T861
Test name
Test status
Simulation time 542915339 ps
CPU time 0.99 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:48:31 PM PDT 24
Peak memory 198448 kb
Host smart-b7c6b69d-3bfb-42ab-8be8-069d612d0110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506026421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1506026421
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3753475221
Short name T526
Test name
Test status
Simulation time 24005522687 ps
CPU time 10.42 seconds
Started Jul 18 06:48:27 PM PDT 24
Finished Jul 18 06:48:43 PM PDT 24
Peak memory 198908 kb
Host smart-1a501c6f-e797-4f52-815b-488fd212a326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753475221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3753475221
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.377836968
Short name T400
Test name
Test status
Simulation time 16692933109 ps
CPU time 60.98 seconds
Started Jul 18 06:48:27 PM PDT 24
Finished Jul 18 06:49:34 PM PDT 24
Peak memory 200200 kb
Host smart-f93b48ad-f755-4565-b7b3-1cbb71a4952d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377836968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.377836968
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2272211470
Short name T482
Test name
Test status
Simulation time 4508666941 ps
CPU time 9.11 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:38 PM PDT 24
Peak memory 198268 kb
Host smart-7105d795-eb9e-4826-b8c3-9a3d69cfe6fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272211470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2272211470
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1862617938
Short name T680
Test name
Test status
Simulation time 49531353008 ps
CPU time 94.35 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:50:01 PM PDT 24
Peak memory 200272 kb
Host smart-d84046ce-43b1-4517-a00e-20303f15c851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862617938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1862617938
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1719736755
Short name T292
Test name
Test status
Simulation time 7114671938 ps
CPU time 5.7 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:48:31 PM PDT 24
Peak memory 196688 kb
Host smart-294a9399-a3ae-4362-bf16-0a7dcbbfadc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719736755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1719736755
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3036087561
Short name T1086
Test name
Test status
Simulation time 109699357 ps
CPU time 0.93 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:48:26 PM PDT 24
Peak memory 197484 kb
Host smart-c98f71b6-8327-4a17-bb38-86a492154859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036087561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3036087561
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1898814492
Short name T496
Test name
Test status
Simulation time 374226994376 ps
CPU time 974.65 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 07:04:45 PM PDT 24
Peak memory 216204 kb
Host smart-f872c373-4afc-4856-ab7a-532c77fb7d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898814492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1898814492
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.661503702
Short name T108
Test name
Test status
Simulation time 135360342886 ps
CPU time 224.77 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:52:15 PM PDT 24
Peak memory 216672 kb
Host smart-fe261824-9e05-476b-b6ec-c1ec824372a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661503702 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.661503702
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.653659286
Short name T308
Test name
Test status
Simulation time 1909119038 ps
CPU time 2.74 seconds
Started Jul 18 06:48:26 PM PDT 24
Finished Jul 18 06:48:35 PM PDT 24
Peak memory 198644 kb
Host smart-c8ab49b1-e352-46d2-af76-f62c385505f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653659286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.653659286
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2229673820
Short name T828
Test name
Test status
Simulation time 23628400847 ps
CPU time 10.26 seconds
Started Jul 18 06:48:26 PM PDT 24
Finished Jul 18 06:48:42 PM PDT 24
Peak memory 200140 kb
Host smart-e4659fe4-6035-49f8-bf8a-3e9b5ddf8521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229673820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2229673820
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.950187039
Short name T1092
Test name
Test status
Simulation time 56664723347 ps
CPU time 45.39 seconds
Started Jul 18 06:52:13 PM PDT 24
Finished Jul 18 06:53:02 PM PDT 24
Peak memory 199856 kb
Host smart-a9bde455-9e52-43cf-8e51-d11ba89fd970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950187039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.950187039
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2580137520
Short name T966
Test name
Test status
Simulation time 29486183207 ps
CPU time 6.71 seconds
Started Jul 18 06:52:14 PM PDT 24
Finished Jul 18 06:52:25 PM PDT 24
Peak memory 199548 kb
Host smart-eda318d5-0105-4e13-ab51-2eeae50cbdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580137520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2580137520
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2508435046
Short name T712
Test name
Test status
Simulation time 27074198582 ps
CPU time 40.64 seconds
Started Jul 18 06:52:13 PM PDT 24
Finished Jul 18 06:52:57 PM PDT 24
Peak memory 200168 kb
Host smart-d5cd665d-e364-487d-ad2f-09afe4a47d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508435046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2508435046
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3991408017
Short name T615
Test name
Test status
Simulation time 42932509213 ps
CPU time 135.27 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:54:26 PM PDT 24
Peak memory 200176 kb
Host smart-c36a2ef7-c5c1-40bf-9df2-a6f1413f80f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991408017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3991408017
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2038371324
Short name T294
Test name
Test status
Simulation time 100058444074 ps
CPU time 313.13 seconds
Started Jul 18 06:52:10 PM PDT 24
Finished Jul 18 06:57:26 PM PDT 24
Peak memory 200188 kb
Host smart-890f69df-cd7b-4aa1-8ec3-3928b377e5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038371324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2038371324
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3400347714
Short name T683
Test name
Test status
Simulation time 192862734685 ps
CPU time 69.06 seconds
Started Jul 18 06:52:14 PM PDT 24
Finished Jul 18 06:53:27 PM PDT 24
Peak memory 200140 kb
Host smart-c7e13c12-d506-42ca-86ba-d0a56e6be4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400347714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3400347714
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.4007937338
Short name T580
Test name
Test status
Simulation time 72179808255 ps
CPU time 56.33 seconds
Started Jul 18 06:52:10 PM PDT 24
Finished Jul 18 06:53:09 PM PDT 24
Peak memory 200212 kb
Host smart-f2384f3f-1482-4f75-b1fc-74d4d1e84f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007937338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4007937338
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.323031425
Short name T1176
Test name
Test status
Simulation time 20116420 ps
CPU time 0.57 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:48:31 PM PDT 24
Peak memory 195588 kb
Host smart-72bae7e8-241b-4fd8-bb96-218864c982c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323031425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.323031425
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.4134672369
Short name T793
Test name
Test status
Simulation time 73796519968 ps
CPU time 58.18 seconds
Started Jul 18 06:48:24 PM PDT 24
Finished Jul 18 06:49:28 PM PDT 24
Peak memory 200196 kb
Host smart-98f2a73f-ae6d-4a89-99b3-41413988ce0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134672369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.4134672369
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1274220136
Short name T843
Test name
Test status
Simulation time 249829505977 ps
CPU time 76.38 seconds
Started Jul 18 06:48:22 PM PDT 24
Finished Jul 18 06:49:40 PM PDT 24
Peak memory 200144 kb
Host smart-736bb1b1-1ef7-4ec4-a76e-00d2106eca94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274220136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1274220136
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.4180448783
Short name T204
Test name
Test status
Simulation time 23312056521 ps
CPU time 55.72 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:49:20 PM PDT 24
Peak memory 200132 kb
Host smart-c9057fb0-12f4-467e-9c10-71d454c69edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180448783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.4180448783
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1022263306
Short name T417
Test name
Test status
Simulation time 273416721662 ps
CPU time 97.21 seconds
Started Jul 18 06:48:27 PM PDT 24
Finished Jul 18 06:50:10 PM PDT 24
Peak memory 197972 kb
Host smart-1fcf6b8c-18ac-4cb2-9572-fdc5550475dc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022263306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1022263306
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2005953968
Short name T887
Test name
Test status
Simulation time 57514561752 ps
CPU time 314.79 seconds
Started Jul 18 06:48:26 PM PDT 24
Finished Jul 18 06:53:46 PM PDT 24
Peak memory 200096 kb
Host smart-4e5e9890-be15-418c-a3c4-809d5d043f8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005953968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2005953968
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.459800518
Short name T729
Test name
Test status
Simulation time 9147505059 ps
CPU time 14.1 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:48:39 PM PDT 24
Peak memory 200140 kb
Host smart-aeeeb1f8-fe9f-4d86-92d9-b64479727fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459800518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.459800518
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3064041429
Short name T874
Test name
Test status
Simulation time 26407033829 ps
CPU time 11.59 seconds
Started Jul 18 06:48:26 PM PDT 24
Finished Jul 18 06:48:43 PM PDT 24
Peak memory 198452 kb
Host smart-b971ab31-b22a-4d9a-80db-9cb5ebdd4d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064041429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3064041429
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1460748052
Short name T322
Test name
Test status
Simulation time 17909357081 ps
CPU time 157.85 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:51:09 PM PDT 24
Peak memory 200112 kb
Host smart-d1b3c82e-d073-48c5-acff-5aff7a3e5e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1460748052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1460748052
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2080638815
Short name T931
Test name
Test status
Simulation time 6342919261 ps
CPU time 9.99 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:48:37 PM PDT 24
Peak memory 198280 kb
Host smart-f7ddc6f5-4370-4bb7-bd8e-9b7f98ce1eff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080638815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2080638815
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.324410838
Short name T571
Test name
Test status
Simulation time 189137514187 ps
CPU time 65.09 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:49:36 PM PDT 24
Peak memory 200192 kb
Host smart-3b88a6e6-395b-4246-adc1-108fd8ae74b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324410838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.324410838
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.608092413
Short name T283
Test name
Test status
Simulation time 42086956114 ps
CPU time 28.48 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:48:59 PM PDT 24
Peak memory 196036 kb
Host smart-cd0cb2b2-534f-46b7-a297-6e2cbfed7065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608092413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.608092413
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3250270832
Short name T461
Test name
Test status
Simulation time 417410387 ps
CPU time 1.37 seconds
Started Jul 18 06:48:23 PM PDT 24
Finished Jul 18 06:48:26 PM PDT 24
Peak memory 199864 kb
Host smart-79177764-39ce-4cf0-8d6d-6ea23aea9240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250270832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3250270832
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1526444759
Short name T972
Test name
Test status
Simulation time 213671045480 ps
CPU time 206.12 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:51:57 PM PDT 24
Peak memory 215960 kb
Host smart-8455e8d9-a4d2-483d-832a-82ed24d4fcc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526444759 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1526444759
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1096465027
Short name T291
Test name
Test status
Simulation time 834913292 ps
CPU time 3.23 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:48:34 PM PDT 24
Peak memory 199928 kb
Host smart-99c8c053-e3e8-4001-b044-cbc85de304be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096465027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1096465027
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1076938544
Short name T418
Test name
Test status
Simulation time 52303907338 ps
CPU time 14.6 seconds
Started Jul 18 06:48:22 PM PDT 24
Finished Jul 18 06:48:37 PM PDT 24
Peak memory 199972 kb
Host smart-f4fab637-4be8-44a0-9c64-42f7cdd7456a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076938544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1076938544
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1573519508
Short name T969
Test name
Test status
Simulation time 34551034262 ps
CPU time 29.5 seconds
Started Jul 18 06:52:10 PM PDT 24
Finished Jul 18 06:52:42 PM PDT 24
Peak memory 200100 kb
Host smart-1e7494b7-c396-4289-bdaa-6269d4750e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573519508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1573519508
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2305457245
Short name T1181
Test name
Test status
Simulation time 18856862880 ps
CPU time 14.64 seconds
Started Jul 18 06:52:13 PM PDT 24
Finished Jul 18 06:52:31 PM PDT 24
Peak memory 200200 kb
Host smart-43253ca3-166d-46b9-a096-4277b4d803f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305457245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2305457245
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.4235215480
Short name T323
Test name
Test status
Simulation time 16123467914 ps
CPU time 26.3 seconds
Started Jul 18 06:52:12 PM PDT 24
Finished Jul 18 06:52:42 PM PDT 24
Peak memory 200204 kb
Host smart-07479c34-5001-44e1-a7a1-f6075809d6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235215480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.4235215480
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2235659634
Short name T217
Test name
Test status
Simulation time 71930681404 ps
CPU time 111.13 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:54:03 PM PDT 24
Peak memory 200184 kb
Host smart-6affff97-17b8-4b33-9212-932586b8a24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235659634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2235659634
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2964649715
Short name T620
Test name
Test status
Simulation time 59541310505 ps
CPU time 110.85 seconds
Started Jul 18 06:52:15 PM PDT 24
Finished Jul 18 06:54:09 PM PDT 24
Peak memory 200276 kb
Host smart-e07bc428-d3d8-4dda-9315-97726b18e08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964649715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2964649715
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.841429452
Short name T385
Test name
Test status
Simulation time 21087543667 ps
CPU time 32.03 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:52:43 PM PDT 24
Peak memory 200084 kb
Host smart-98f6b527-e495-4b3a-8051-76dc49c89bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841429452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.841429452
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3724914713
Short name T853
Test name
Test status
Simulation time 65200474612 ps
CPU time 110.58 seconds
Started Jul 18 06:52:08 PM PDT 24
Finished Jul 18 06:54:00 PM PDT 24
Peak memory 200192 kb
Host smart-232a6468-61e4-48a7-81e6-79377c16b122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724914713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3724914713
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.311170461
Short name T1172
Test name
Test status
Simulation time 182344559587 ps
CPU time 335.19 seconds
Started Jul 18 06:52:12 PM PDT 24
Finished Jul 18 06:57:51 PM PDT 24
Peak memory 200132 kb
Host smart-2c23eb65-cec7-47b3-8a39-974d41e5aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311170461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.311170461
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3187241345
Short name T1030
Test name
Test status
Simulation time 47230031918 ps
CPU time 10.16 seconds
Started Jul 18 06:52:12 PM PDT 24
Finished Jul 18 06:52:26 PM PDT 24
Peak memory 200204 kb
Host smart-996e9743-b976-4f9f-98f2-21a0a4cb6293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187241345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3187241345
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3498118564
Short name T477
Test name
Test status
Simulation time 12649748 ps
CPU time 0.55 seconds
Started Jul 18 06:48:42 PM PDT 24
Finished Jul 18 06:48:47 PM PDT 24
Peak memory 195564 kb
Host smart-f11686c8-1b79-4d9e-bc62-bdc36dfccb56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498118564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3498118564
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1174870221
Short name T1126
Test name
Test status
Simulation time 113325672214 ps
CPU time 43.23 seconds
Started Jul 18 06:48:30 PM PDT 24
Finished Jul 18 06:49:17 PM PDT 24
Peak memory 200152 kb
Host smart-5811b51a-a0ea-40ef-abd2-f0651b570790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174870221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1174870221
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3486401146
Short name T254
Test name
Test status
Simulation time 40661636255 ps
CPU time 64.23 seconds
Started Jul 18 06:48:28 PM PDT 24
Finished Jul 18 06:49:37 PM PDT 24
Peak memory 200188 kb
Host smart-74c35577-b454-4fc3-bfcf-7e1fd5f314e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486401146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3486401146
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1168461913
Short name T136
Test name
Test status
Simulation time 18429616331 ps
CPU time 11.29 seconds
Started Jul 18 06:48:29 PM PDT 24
Finished Jul 18 06:48:45 PM PDT 24
Peak memory 200136 kb
Host smart-28e08926-12eb-4ea9-8fee-65e66eaa0374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168461913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1168461913
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1579248968
Short name T23
Test name
Test status
Simulation time 9202932457 ps
CPU time 9.13 seconds
Started Jul 18 06:48:30 PM PDT 24
Finished Jul 18 06:48:43 PM PDT 24
Peak memory 200160 kb
Host smart-bc28a5c2-e93b-492e-8990-d7887d7a10da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579248968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1579248968
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3314441083
Short name T1035
Test name
Test status
Simulation time 71667725999 ps
CPU time 134.1 seconds
Started Jul 18 06:48:37 PM PDT 24
Finished Jul 18 06:50:53 PM PDT 24
Peak memory 200180 kb
Host smart-ff9fc0c4-c3b4-432c-9fe3-d2bbdab2cb5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314441083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3314441083
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.306733984
Short name T395
Test name
Test status
Simulation time 10689357887 ps
CPU time 6.37 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:48:37 PM PDT 24
Peak memory 199828 kb
Host smart-b0bdabbe-1e7b-4f54-9640-6b39807d98c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306733984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.306733984
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3375052352
Short name T1076
Test name
Test status
Simulation time 44154413526 ps
CPU time 60.72 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 06:49:31 PM PDT 24
Peak memory 198592 kb
Host smart-57ec720b-1ce1-47fa-9ff0-d35ca18bd0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375052352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3375052352
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.72899759
Short name T647
Test name
Test status
Simulation time 22154524120 ps
CPU time 911.74 seconds
Started Jul 18 06:48:25 PM PDT 24
Finished Jul 18 07:03:42 PM PDT 24
Peak memory 200176 kb
Host smart-c125f71d-dd6e-41af-b71c-32efa25ac4a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72899759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.72899759
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3255904398
Short name T642
Test name
Test status
Simulation time 5037351485 ps
CPU time 21.4 seconds
Started Jul 18 06:48:29 PM PDT 24
Finished Jul 18 06:48:55 PM PDT 24
Peak memory 198560 kb
Host smart-66bc9943-6855-4e89-b4f3-f1d7c975603c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255904398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3255904398
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3023706464
Short name T727
Test name
Test status
Simulation time 203312646483 ps
CPU time 399.06 seconds
Started Jul 18 06:48:29 PM PDT 24
Finished Jul 18 06:55:13 PM PDT 24
Peak memory 200184 kb
Host smart-df679009-efce-4c7a-8554-5f6d29a3eebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023706464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3023706464
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.631150413
Short name T517
Test name
Test status
Simulation time 35938245439 ps
CPU time 10.42 seconds
Started Jul 18 06:48:29 PM PDT 24
Finished Jul 18 06:48:44 PM PDT 24
Peak memory 196212 kb
Host smart-29e208b5-fb05-4329-ac4d-149d1cbed3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631150413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.631150413
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1456904651
Short name T719
Test name
Test status
Simulation time 11069973009 ps
CPU time 14.65 seconds
Started Jul 18 06:48:30 PM PDT 24
Finished Jul 18 06:48:49 PM PDT 24
Peak memory 199744 kb
Host smart-ba252341-0ca3-4f3e-839d-f46d60840053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456904651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1456904651
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.599736646
Short name T990
Test name
Test status
Simulation time 400184167405 ps
CPU time 111.69 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:50:35 PM PDT 24
Peak memory 200184 kb
Host smart-5ede6023-5a93-49f0-a1ce-f1bfa052ca46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599736646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.599736646
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3724189329
Short name T376
Test name
Test status
Simulation time 732568873 ps
CPU time 2.22 seconds
Started Jul 18 06:48:27 PM PDT 24
Finished Jul 18 06:48:35 PM PDT 24
Peak memory 198564 kb
Host smart-395fa810-a2ee-4ee0-a6f0-7d2a35fb9213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724189329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3724189329
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2724809676
Short name T271
Test name
Test status
Simulation time 98063045391 ps
CPU time 23.85 seconds
Started Jul 18 06:48:30 PM PDT 24
Finished Jul 18 06:48:58 PM PDT 24
Peak memory 200156 kb
Host smart-6c288657-2331-46af-b20b-b6105e2c58ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724809676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2724809676
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1153289008
Short name T741
Test name
Test status
Simulation time 43363450515 ps
CPU time 17.2 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:52:29 PM PDT 24
Peak memory 200204 kb
Host smart-5e96fa02-0c58-4910-8eba-64c53dbac641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153289008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1153289008
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2393961292
Short name T865
Test name
Test status
Simulation time 38001325927 ps
CPU time 49.67 seconds
Started Jul 18 06:52:13 PM PDT 24
Finished Jul 18 06:53:07 PM PDT 24
Peak memory 200216 kb
Host smart-c3b05918-28cf-4a93-ba94-b892f09d592b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393961292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2393961292
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2189208035
Short name T886
Test name
Test status
Simulation time 32395780256 ps
CPU time 16.68 seconds
Started Jul 18 06:52:14 PM PDT 24
Finished Jul 18 06:52:35 PM PDT 24
Peak memory 200180 kb
Host smart-99f608f9-4bd5-4553-87fa-88c06d405676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189208035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2189208035
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1435118149
Short name T305
Test name
Test status
Simulation time 141528538578 ps
CPU time 18.29 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:52:31 PM PDT 24
Peak memory 200100 kb
Host smart-2ba35c87-f29b-4d31-a4d3-ec6765599b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435118149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1435118149
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3444586718
Short name T128
Test name
Test status
Simulation time 64483481410 ps
CPU time 111.15 seconds
Started Jul 18 06:52:10 PM PDT 24
Finished Jul 18 06:54:04 PM PDT 24
Peak memory 199988 kb
Host smart-7e9c7288-1eaa-43f4-ad67-d4df3bf91fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444586718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3444586718
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.965152680
Short name T932
Test name
Test status
Simulation time 128459733651 ps
CPU time 49.51 seconds
Started Jul 18 06:52:09 PM PDT 24
Finished Jul 18 06:53:01 PM PDT 24
Peak memory 200168 kb
Host smart-2ae3e817-472e-4b09-aac9-d12efc46be04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965152680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.965152680
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2680931446
Short name T1114
Test name
Test status
Simulation time 132871603198 ps
CPU time 147.11 seconds
Started Jul 18 06:52:10 PM PDT 24
Finished Jul 18 06:54:40 PM PDT 24
Peak memory 200188 kb
Host smart-2c282536-0d74-4225-8c7b-3a8debfbd2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680931446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2680931446
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2909879688
Short name T51
Test name
Test status
Simulation time 45886088455 ps
CPU time 99.08 seconds
Started Jul 18 06:52:12 PM PDT 24
Finished Jul 18 06:53:54 PM PDT 24
Peak memory 200188 kb
Host smart-3720f74d-e718-484d-a982-c4102449cc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909879688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2909879688
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2547113977
Short name T1167
Test name
Test status
Simulation time 32301423724 ps
CPU time 8.77 seconds
Started Jul 18 06:52:13 PM PDT 24
Finished Jul 18 06:52:25 PM PDT 24
Peak memory 200072 kb
Host smart-3658874c-5f67-4f9e-896d-478929fbad3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547113977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2547113977
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3750558836
Short name T923
Test name
Test status
Simulation time 11463038 ps
CPU time 0.54 seconds
Started Jul 18 06:48:38 PM PDT 24
Finished Jul 18 06:48:41 PM PDT 24
Peak memory 195648 kb
Host smart-337b3186-f06f-45b6-9d00-3694ba967e06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750558836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3750558836
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1978464220
Short name T1084
Test name
Test status
Simulation time 63415781349 ps
CPU time 26.5 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:49:10 PM PDT 24
Peak memory 200128 kb
Host smart-98b7637e-1703-4394-8826-ba6cea214630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978464220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1978464220
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.153657625
Short name T536
Test name
Test status
Simulation time 54999070594 ps
CPU time 78.38 seconds
Started Jul 18 06:48:36 PM PDT 24
Finished Jul 18 06:49:57 PM PDT 24
Peak memory 200028 kb
Host smart-3173ffd8-6563-461e-9be1-2abf302f0679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153657625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.153657625
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2127291182
Short name T127
Test name
Test status
Simulation time 16989825974 ps
CPU time 6.97 seconds
Started Jul 18 06:48:37 PM PDT 24
Finished Jul 18 06:48:48 PM PDT 24
Peak memory 200192 kb
Host smart-8a698cd7-321a-419d-8d3f-c86d1cdd95c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127291182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2127291182
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1634499092
Short name T674
Test name
Test status
Simulation time 63534967599 ps
CPU time 56.37 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:49:40 PM PDT 24
Peak memory 200128 kb
Host smart-cf05acd4-b5b6-4073-9b13-fd7a2ab114c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634499092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1634499092
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2696554011
Short name T367
Test name
Test status
Simulation time 74772350958 ps
CPU time 672.72 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:59:56 PM PDT 24
Peak memory 200176 kb
Host smart-f7e37652-cbfe-4bc7-b9e2-e3c53b01f4ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2696554011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2696554011
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3420294691
Short name T522
Test name
Test status
Simulation time 6533891596 ps
CPU time 5.26 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 06:48:51 PM PDT 24
Peak memory 199828 kb
Host smart-1b94e77e-ee89-41d5-a480-006b7fffbc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420294691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3420294691
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.104388567
Short name T952
Test name
Test status
Simulation time 15295622918 ps
CPU time 22.3 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:49:07 PM PDT 24
Peak memory 196952 kb
Host smart-b71c68de-50e7-4bee-b739-27315a58f12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104388567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.104388567
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1261675257
Short name T1063
Test name
Test status
Simulation time 18457500837 ps
CPU time 1005.58 seconds
Started Jul 18 06:48:38 PM PDT 24
Finished Jul 18 07:05:27 PM PDT 24
Peak memory 200208 kb
Host smart-935808ba-c4be-4e6e-bce8-a829693c8a08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1261675257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1261675257
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2678306999
Short name T1122
Test name
Test status
Simulation time 6808322722 ps
CPU time 15.5 seconds
Started Jul 18 06:48:37 PM PDT 24
Finished Jul 18 06:48:55 PM PDT 24
Peak memory 198052 kb
Host smart-10728e83-4ef2-4333-a5aa-fc7d06827298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2678306999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2678306999
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2931267412
Short name T667
Test name
Test status
Simulation time 60827444739 ps
CPU time 29.97 seconds
Started Jul 18 06:48:40 PM PDT 24
Finished Jul 18 06:49:15 PM PDT 24
Peak memory 200192 kb
Host smart-09955d3d-1e8e-4deb-a6c8-ab46d51ce6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931267412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2931267412
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2760214032
Short name T455
Test name
Test status
Simulation time 3771275780 ps
CPU time 3.46 seconds
Started Jul 18 06:48:37 PM PDT 24
Finished Jul 18 06:48:43 PM PDT 24
Peak memory 196680 kb
Host smart-e4fb0e97-bbb7-4346-b5e2-c9eb8739abb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760214032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2760214032
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2047936575
Short name T584
Test name
Test status
Simulation time 508383272 ps
CPU time 1.51 seconds
Started Jul 18 06:48:40 PM PDT 24
Finished Jul 18 06:48:46 PM PDT 24
Peak memory 199880 kb
Host smart-4156966f-ff17-4abd-8225-3b1f0b57b8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047936575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2047936575
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.957925569
Short name T446
Test name
Test status
Simulation time 43795863169 ps
CPU time 72.38 seconds
Started Jul 18 06:48:37 PM PDT 24
Finished Jul 18 06:49:52 PM PDT 24
Peak memory 200112 kb
Host smart-b8bbdffa-8b8a-4ee4-86dd-9c69f3cb6658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957925569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.957925569
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2512477319
Short name T879
Test name
Test status
Simulation time 239075688245 ps
CPU time 999.93 seconds
Started Jul 18 06:48:37 PM PDT 24
Finished Jul 18 07:05:19 PM PDT 24
Peak memory 225044 kb
Host smart-8dbf3b27-a1ac-4c96-9912-6dd996881ec4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512477319 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2512477319
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1230870223
Short name T524
Test name
Test status
Simulation time 1915974740 ps
CPU time 1.72 seconds
Started Jul 18 06:48:38 PM PDT 24
Finished Jul 18 06:48:43 PM PDT 24
Peak memory 198716 kb
Host smart-627d957f-1d37-4198-98b5-fdae742ee09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230870223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1230870223
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.4154263859
Short name T610
Test name
Test status
Simulation time 22909731394 ps
CPU time 34.18 seconds
Started Jul 18 06:48:36 PM PDT 24
Finished Jul 18 06:49:13 PM PDT 24
Peak memory 200220 kb
Host smart-1d4b66d7-0f45-4c5e-99df-1395e11f29ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154263859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.4154263859
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.780842104
Short name T226
Test name
Test status
Simulation time 39777074286 ps
CPU time 15.65 seconds
Started Jul 18 06:52:13 PM PDT 24
Finished Jul 18 06:52:32 PM PDT 24
Peak memory 200200 kb
Host smart-b88ca9e7-09c9-4898-99a8-e239362bd727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780842104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.780842104
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2544649746
Short name T546
Test name
Test status
Simulation time 16423541299 ps
CPU time 17.05 seconds
Started Jul 18 06:52:08 PM PDT 24
Finished Jul 18 06:52:26 PM PDT 24
Peak memory 199820 kb
Host smart-776d577c-8c8c-49bf-9d21-21f4cf7412b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544649746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2544649746
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1930094932
Short name T205
Test name
Test status
Simulation time 23533530347 ps
CPU time 46.45 seconds
Started Jul 18 06:52:12 PM PDT 24
Finished Jul 18 06:53:02 PM PDT 24
Peak memory 200120 kb
Host smart-deee8f8a-47b2-4267-ba37-1582eda62701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930094932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1930094932
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2978068403
Short name T717
Test name
Test status
Simulation time 18156808977 ps
CPU time 27.53 seconds
Started Jul 18 06:52:13 PM PDT 24
Finished Jul 18 06:52:44 PM PDT 24
Peak memory 200200 kb
Host smart-95c012da-fe66-4f3d-ad45-42d001c49ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978068403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2978068403
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.761144001
Short name T191
Test name
Test status
Simulation time 28454342117 ps
CPU time 10.79 seconds
Started Jul 18 06:52:12 PM PDT 24
Finished Jul 18 06:52:26 PM PDT 24
Peak memory 200188 kb
Host smart-7181bdf0-0207-4671-ada8-91d34d4f7d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761144001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.761144001
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3921641451
Short name T53
Test name
Test status
Simulation time 62984184779 ps
CPU time 25.08 seconds
Started Jul 18 06:52:14 PM PDT 24
Finished Jul 18 06:52:43 PM PDT 24
Peak memory 199720 kb
Host smart-b3c4efcc-0153-4c93-8d7f-83732bca07aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921641451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3921641451
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2546708852
Short name T138
Test name
Test status
Simulation time 16468038915 ps
CPU time 23.66 seconds
Started Jul 18 06:52:12 PM PDT 24
Finished Jul 18 06:52:39 PM PDT 24
Peak memory 200132 kb
Host smart-bea5836c-3a6a-48ed-a362-8f0564f14953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546708852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2546708852
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1157445990
Short name T196
Test name
Test status
Simulation time 30760035135 ps
CPU time 47.82 seconds
Started Jul 18 06:52:12 PM PDT 24
Finished Jul 18 06:53:03 PM PDT 24
Peak memory 200180 kb
Host smart-da793a66-2b95-4456-b9b8-202a91e3ef90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157445990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1157445990
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1899370082
Short name T681
Test name
Test status
Simulation time 75660902375 ps
CPU time 225.99 seconds
Started Jul 18 06:52:14 PM PDT 24
Finished Jul 18 06:56:04 PM PDT 24
Peak memory 200216 kb
Host smart-24f2d5b4-3128-449b-bbbc-9a0832fdd9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899370082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1899370082
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2419929825
Short name T512
Test name
Test status
Simulation time 107392568870 ps
CPU time 91.39 seconds
Started Jul 18 06:48:35 PM PDT 24
Finished Jul 18 06:50:09 PM PDT 24
Peak memory 200308 kb
Host smart-ea19d83c-1c71-4061-b826-41fa2853884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419929825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2419929825
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3109293551
Short name T275
Test name
Test status
Simulation time 18125795970 ps
CPU time 11.2 seconds
Started Jul 18 06:48:42 PM PDT 24
Finished Jul 18 06:48:58 PM PDT 24
Peak memory 199992 kb
Host smart-b1bac1c2-0aba-4240-99df-2fd1e7dec89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109293551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3109293551
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3663162528
Short name T726
Test name
Test status
Simulation time 117110816752 ps
CPU time 247.8 seconds
Started Jul 18 06:48:40 PM PDT 24
Finished Jul 18 06:52:53 PM PDT 24
Peak memory 200200 kb
Host smart-13886c51-69a3-41f1-baad-486499c23259
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663162528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3663162528
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_loopback.2321507452
Short name T1016
Test name
Test status
Simulation time 3022146544 ps
CPU time 5.47 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:48:49 PM PDT 24
Peak memory 198884 kb
Host smart-088bfa32-2e3b-447b-8b6d-4adfb8af7ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321507452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2321507452
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2430162276
Short name T903
Test name
Test status
Simulation time 26090820380 ps
CPU time 40.59 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 06:49:27 PM PDT 24
Peak memory 200296 kb
Host smart-03eeb995-37f6-4313-8286-e06f53249f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430162276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2430162276
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1213921025
Short name T1018
Test name
Test status
Simulation time 11532020085 ps
CPU time 454.82 seconds
Started Jul 18 06:48:42 PM PDT 24
Finished Jul 18 06:56:22 PM PDT 24
Peak memory 200212 kb
Host smart-308a535b-7e66-4683-be71-2fbc352f314b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1213921025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1213921025
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1225329734
Short name T789
Test name
Test status
Simulation time 1167904696 ps
CPU time 2.52 seconds
Started Jul 18 06:48:42 PM PDT 24
Finished Jul 18 06:48:50 PM PDT 24
Peak memory 197876 kb
Host smart-1546b3fa-03ed-4b3e-83b7-02a77aa9a2f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225329734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1225329734
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.4129182128
Short name T534
Test name
Test status
Simulation time 31403728110 ps
CPU time 50.64 seconds
Started Jul 18 06:48:40 PM PDT 24
Finished Jul 18 06:49:36 PM PDT 24
Peak memory 200132 kb
Host smart-c859afb3-9614-4925-bc00-97eb9c3e6c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129182128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4129182128
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4046324001
Short name T998
Test name
Test status
Simulation time 4488362922 ps
CPU time 3.95 seconds
Started Jul 18 06:48:38 PM PDT 24
Finished Jul 18 06:48:46 PM PDT 24
Peak memory 196684 kb
Host smart-3f18a474-dfed-4e02-ba10-0d6fc520564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046324001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4046324001
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.4189359941
Short name T456
Test name
Test status
Simulation time 5450589543 ps
CPU time 15.95 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 06:49:02 PM PDT 24
Peak memory 199528 kb
Host smart-06e0be1f-adf4-418d-b6d3-163f28a2cfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189359941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.4189359941
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1509722023
Short name T754
Test name
Test status
Simulation time 698411742071 ps
CPU time 2417.36 seconds
Started Jul 18 06:48:37 PM PDT 24
Finished Jul 18 07:28:57 PM PDT 24
Peak memory 200072 kb
Host smart-ae5b7cec-970a-4308-be5c-1abe2c3d3f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509722023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1509722023
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.543359899
Short name T110
Test name
Test status
Simulation time 32026894726 ps
CPU time 262.69 seconds
Started Jul 18 06:48:38 PM PDT 24
Finished Jul 18 06:53:04 PM PDT 24
Peak memory 215748 kb
Host smart-4eac609c-cf5f-4529-bd53-a4162cbbff24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543359899 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.543359899
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1383547235
Short name T1166
Test name
Test status
Simulation time 2060231457 ps
CPU time 2.28 seconds
Started Jul 18 06:48:40 PM PDT 24
Finished Jul 18 06:48:47 PM PDT 24
Peak memory 198596 kb
Host smart-ace175c1-b03f-4edb-8b2d-c2fe6a188374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383547235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1383547235
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1481410064
Short name T703
Test name
Test status
Simulation time 27204461528 ps
CPU time 33.15 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:49:17 PM PDT 24
Peak memory 200176 kb
Host smart-5bdcff6c-8f2c-42ba-a295-543a7906093a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481410064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1481410064
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2643371207
Short name T181
Test name
Test status
Simulation time 126765794710 ps
CPU time 104.96 seconds
Started Jul 18 06:52:12 PM PDT 24
Finished Jul 18 06:53:59 PM PDT 24
Peak memory 200132 kb
Host smart-82c56715-062a-478b-84a0-c2379b39418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643371207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2643371207
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3519318106
Short name T573
Test name
Test status
Simulation time 181767171892 ps
CPU time 98.36 seconds
Started Jul 18 06:52:12 PM PDT 24
Finished Jul 18 06:53:53 PM PDT 24
Peak memory 200184 kb
Host smart-7c5934c9-d437-4268-b54e-31ea423d0d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519318106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3519318106
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2867595583
Short name T1134
Test name
Test status
Simulation time 52817694719 ps
CPU time 101.89 seconds
Started Jul 18 06:52:14 PM PDT 24
Finished Jul 18 06:53:59 PM PDT 24
Peak memory 200200 kb
Host smart-29263d30-11cc-4eb1-905e-d4ab8d02bf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867595583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2867595583
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2027096125
Short name T1048
Test name
Test status
Simulation time 213846672650 ps
CPU time 24.51 seconds
Started Jul 18 06:52:13 PM PDT 24
Finished Jul 18 06:52:41 PM PDT 24
Peak memory 200180 kb
Host smart-8b1ef27f-c4e7-4419-a6ea-19b06431094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027096125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2027096125
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.68311374
Short name T1044
Test name
Test status
Simulation time 51467338939 ps
CPU time 77.38 seconds
Started Jul 18 06:52:27 PM PDT 24
Finished Jul 18 06:53:47 PM PDT 24
Peak memory 200196 kb
Host smart-4f01509f-02f9-4bf3-8575-96c196a1cc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68311374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.68311374
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1770644945
Short name T1142
Test name
Test status
Simulation time 128737958106 ps
CPU time 111.54 seconds
Started Jul 18 06:52:29 PM PDT 24
Finished Jul 18 06:54:23 PM PDT 24
Peak memory 200184 kb
Host smart-742b54a1-e3cc-4fa2-833d-a8e5a0cd6342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770644945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1770644945
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1936298408
Short name T905
Test name
Test status
Simulation time 26955117411 ps
CPU time 46.44 seconds
Started Jul 18 06:52:30 PM PDT 24
Finished Jul 18 06:53:18 PM PDT 24
Peak memory 200196 kb
Host smart-93cee5e0-0bf4-4484-97d9-d700f65a1e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936298408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1936298408
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3472445065
Short name T320
Test name
Test status
Simulation time 79990858476 ps
CPU time 104.18 seconds
Started Jul 18 06:53:34 PM PDT 24
Finished Jul 18 06:55:19 PM PDT 24
Peak memory 200168 kb
Host smart-e740f62a-c125-47ea-af79-1da6f088d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472445065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3472445065
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.22434728
Short name T878
Test name
Test status
Simulation time 48677383951 ps
CPU time 35.34 seconds
Started Jul 18 06:53:33 PM PDT 24
Finished Jul 18 06:54:10 PM PDT 24
Peak memory 200268 kb
Host smart-612bb15a-f0e4-4a54-9774-8dfdf806d48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22434728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.22434728
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.4170861303
Short name T73
Test name
Test status
Simulation time 13443009 ps
CPU time 0.56 seconds
Started Jul 18 06:48:42 PM PDT 24
Finished Jul 18 06:48:48 PM PDT 24
Peak memory 194564 kb
Host smart-6d9fe645-183c-4ad0-b18e-5d0b4934ce5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170861303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.4170861303
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1642640925
Short name T142
Test name
Test status
Simulation time 28487774218 ps
CPU time 23.28 seconds
Started Jul 18 06:48:40 PM PDT 24
Finished Jul 18 06:49:08 PM PDT 24
Peak memory 200184 kb
Host smart-9905bb33-39d0-4458-97fa-85a883630627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642640925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1642640925
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3933015061
Short name T374
Test name
Test status
Simulation time 140794256833 ps
CPU time 43.51 seconds
Started Jul 18 06:48:38 PM PDT 24
Finished Jul 18 06:49:27 PM PDT 24
Peak memory 200104 kb
Host smart-e9a70923-3c63-4cc3-a97b-07699a7baa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933015061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3933015061
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1945748278
Short name T237
Test name
Test status
Simulation time 37588230475 ps
CPU time 16.36 seconds
Started Jul 18 06:48:42 PM PDT 24
Finished Jul 18 06:49:03 PM PDT 24
Peak memory 199024 kb
Host smart-60a16121-864f-4bc8-b78e-e13f6b83e090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945748278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1945748278
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2945751003
Short name T295
Test name
Test status
Simulation time 49994813842 ps
CPU time 6.19 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 06:48:52 PM PDT 24
Peak memory 199964 kb
Host smart-6cb06969-2e11-48de-b354-32cfda3d3266
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945751003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2945751003
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.278152127
Short name T617
Test name
Test status
Simulation time 60566721780 ps
CPU time 426.01 seconds
Started Jul 18 06:48:42 PM PDT 24
Finished Jul 18 06:55:53 PM PDT 24
Peak memory 200128 kb
Host smart-6f5abe67-15c5-4101-88f5-6651fb123dd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278152127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.278152127
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3101310053
Short name T335
Test name
Test status
Simulation time 193381556 ps
CPU time 0.82 seconds
Started Jul 18 06:48:40 PM PDT 24
Finished Jul 18 06:48:46 PM PDT 24
Peak memory 196144 kb
Host smart-175d82bb-f6f4-4a32-a1a1-fd1e2b1d38e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101310053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3101310053
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1880963038
Short name T977
Test name
Test status
Simulation time 301983833396 ps
CPU time 256.19 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:53:01 PM PDT 24
Peak memory 208504 kb
Host smart-c54739f5-ae85-4772-8438-323ad1bac999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880963038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1880963038
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1324764104
Short name T368
Test name
Test status
Simulation time 9752995753 ps
CPU time 267.51 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:53:11 PM PDT 24
Peak memory 200148 kb
Host smart-9cba30c0-3559-4dce-9be2-acfa3c9eb6aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324764104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1324764104
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.575388366
Short name T366
Test name
Test status
Simulation time 7271135143 ps
CPU time 69.17 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 06:49:55 PM PDT 24
Peak memory 200076 kb
Host smart-856e1514-07fe-423b-80e1-c0cd6a5206c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=575388366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.575388366
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1541263524
Short name T901
Test name
Test status
Simulation time 47547472290 ps
CPU time 21.88 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:49:05 PM PDT 24
Peak memory 199804 kb
Host smart-4bd2955f-99c7-448b-854e-09baebe445f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541263524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1541263524
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1226630486
Short name T485
Test name
Test status
Simulation time 2838549992 ps
CPU time 1.76 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 06:48:48 PM PDT 24
Peak memory 195996 kb
Host smart-e8639005-f7f1-476b-a128-d5ffd689f6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226630486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1226630486
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3029740995
Short name T891
Test name
Test status
Simulation time 650619025 ps
CPU time 2.68 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:48:46 PM PDT 24
Peak memory 199792 kb
Host smart-c5cc7838-d4ab-49c0-a1b1-a7b60cae1b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029740995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3029740995
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.715081817
Short name T803
Test name
Test status
Simulation time 49228061740 ps
CPU time 86.47 seconds
Started Jul 18 06:48:39 PM PDT 24
Finished Jul 18 06:50:11 PM PDT 24
Peak memory 200188 kb
Host smart-023412ae-79f6-437f-8740-9d28612d6ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715081817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.715081817
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2872164732
Short name T532
Test name
Test status
Simulation time 9107071229 ps
CPU time 6.93 seconds
Started Jul 18 06:48:37 PM PDT 24
Finished Jul 18 06:48:46 PM PDT 24
Peak memory 200160 kb
Host smart-2a15fe63-3ea4-41b5-a4e7-f64135076dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872164732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2872164732
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.153291600
Short name T1140
Test name
Test status
Simulation time 91069601098 ps
CPU time 102.69 seconds
Started Jul 18 06:48:38 PM PDT 24
Finished Jul 18 06:50:25 PM PDT 24
Peak memory 200128 kb
Host smart-93cefd45-06d8-48f4-92f5-3ca35a62e165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153291600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.153291600
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3504744811
Short name T11
Test name
Test status
Simulation time 135737346290 ps
CPU time 63.05 seconds
Started Jul 18 06:53:37 PM PDT 24
Finished Jul 18 06:54:42 PM PDT 24
Peak memory 200132 kb
Host smart-05821383-1e55-4027-9cc9-cc3caeff54c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504744811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3504744811
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2764432962
Short name T207
Test name
Test status
Simulation time 75845799441 ps
CPU time 61.78 seconds
Started Jul 18 06:53:36 PM PDT 24
Finished Jul 18 06:54:39 PM PDT 24
Peak memory 200200 kb
Host smart-faffd11c-5eff-486e-92be-0b5d6cc4b68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764432962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2764432962
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1737227760
Short name T78
Test name
Test status
Simulation time 4790627207 ps
CPU time 8.26 seconds
Started Jul 18 06:53:34 PM PDT 24
Finished Jul 18 06:53:44 PM PDT 24
Peak memory 200048 kb
Host smart-6dc7ef70-7311-4b11-9efe-4b9c213244b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737227760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1737227760
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3530739290
Short name T1
Test name
Test status
Simulation time 27471122555 ps
CPU time 28.19 seconds
Started Jul 18 06:53:34 PM PDT 24
Finished Jul 18 06:54:04 PM PDT 24
Peak memory 200132 kb
Host smart-1e0159fc-47a7-43c2-9280-5073461bdecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530739290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3530739290
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2166676689
Short name T721
Test name
Test status
Simulation time 7083095294 ps
CPU time 7.55 seconds
Started Jul 18 06:53:33 PM PDT 24
Finished Jul 18 06:53:42 PM PDT 24
Peak memory 200116 kb
Host smart-d62c1abe-3ed9-443c-9f66-bfc9e746de0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166676689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2166676689
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.4154007827
Short name T225
Test name
Test status
Simulation time 147175016447 ps
CPU time 119.63 seconds
Started Jul 18 06:53:36 PM PDT 24
Finished Jul 18 06:55:37 PM PDT 24
Peak memory 200200 kb
Host smart-492a232e-5a87-4f45-822a-907179fa36dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154007827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.4154007827
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1188680582
Short name T768
Test name
Test status
Simulation time 14285544640 ps
CPU time 22.98 seconds
Started Jul 18 06:53:36 PM PDT 24
Finished Jul 18 06:54:00 PM PDT 24
Peak memory 200168 kb
Host smart-ce850a45-af11-4045-8b63-974531c05574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188680582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1188680582
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3458671319
Short name T340
Test name
Test status
Simulation time 19707001920 ps
CPU time 30.53 seconds
Started Jul 18 06:53:37 PM PDT 24
Finished Jul 18 06:54:09 PM PDT 24
Peak memory 199988 kb
Host smart-e5e43df8-9a7b-4897-9c64-0d7a018c5a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458671319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3458671319
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3167190249
Short name T1117
Test name
Test status
Simulation time 23753993408 ps
CPU time 36.15 seconds
Started Jul 18 06:53:35 PM PDT 24
Finished Jul 18 06:54:13 PM PDT 24
Peak memory 199852 kb
Host smart-60d28bb5-1c7a-4d19-a9b4-22348abf1a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167190249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3167190249
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2700754549
Short name T763
Test name
Test status
Simulation time 54252922 ps
CPU time 0.57 seconds
Started Jul 18 06:48:37 PM PDT 24
Finished Jul 18 06:48:40 PM PDT 24
Peak memory 195556 kb
Host smart-af69a5e0-52cb-46af-b425-0361baec6340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700754549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2700754549
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.826159453
Short name T938
Test name
Test status
Simulation time 152887259776 ps
CPU time 119.59 seconds
Started Jul 18 06:48:43 PM PDT 24
Finished Jul 18 06:50:48 PM PDT 24
Peak memory 200100 kb
Host smart-517c5832-e8d8-4d34-b336-48514a8e6bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826159453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.826159453
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.144300602
Short name T327
Test name
Test status
Simulation time 20255987089 ps
CPU time 17.32 seconds
Started Jul 18 06:48:43 PM PDT 24
Finished Jul 18 06:49:05 PM PDT 24
Peak memory 197484 kb
Host smart-d2cbcd2c-b1f4-421f-88a5-5c50c9355040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144300602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.144300602
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.564902756
Short name T1008
Test name
Test status
Simulation time 102011039160 ps
CPU time 148.04 seconds
Started Jul 18 06:48:42 PM PDT 24
Finished Jul 18 06:51:15 PM PDT 24
Peak memory 200188 kb
Host smart-35652710-ce04-4335-a271-f85c07c78552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564902756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.564902756
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3977633096
Short name T633
Test name
Test status
Simulation time 58961378348 ps
CPU time 28.63 seconds
Started Jul 18 06:48:42 PM PDT 24
Finished Jul 18 06:49:16 PM PDT 24
Peak memory 200204 kb
Host smart-b5c1c8c4-94cc-440b-a034-fd12b39e6313
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977633096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3977633096
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.230858932
Short name T640
Test name
Test status
Simulation time 85857685441 ps
CPU time 525.5 seconds
Started Jul 18 06:48:43 PM PDT 24
Finished Jul 18 06:57:34 PM PDT 24
Peak memory 199920 kb
Host smart-7f9bc196-5e9c-4566-b8a5-02cd7f707530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230858932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.230858932
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.328967892
Short name T790
Test name
Test status
Simulation time 8865309455 ps
CPU time 11.41 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 06:48:58 PM PDT 24
Peak memory 199992 kb
Host smart-6d8124a7-0cc1-4b39-9ef7-8bdfd93fcf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328967892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.328967892
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2485689441
Short name T1085
Test name
Test status
Simulation time 66550737557 ps
CPU time 176.46 seconds
Started Jul 18 06:48:37 PM PDT 24
Finished Jul 18 06:51:36 PM PDT 24
Peak memory 200220 kb
Host smart-3a87fb01-47a7-4513-b30e-d6c83fd5b1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485689441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2485689441
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3591013272
Short name T555
Test name
Test status
Simulation time 21628022528 ps
CPU time 599.84 seconds
Started Jul 18 06:48:42 PM PDT 24
Finished Jul 18 06:58:47 PM PDT 24
Peak memory 200108 kb
Host smart-8facde47-e5c8-4a57-bb7b-69e537d0452c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591013272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3591013272
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.353567500
Short name T451
Test name
Test status
Simulation time 2347321020 ps
CPU time 19.35 seconds
Started Jul 18 06:48:43 PM PDT 24
Finished Jul 18 06:49:07 PM PDT 24
Peak memory 198252 kb
Host smart-f78fed76-8111-45cf-b88d-2899c2ec8d4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353567500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.353567500
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1900915569
Short name T379
Test name
Test status
Simulation time 45127321682 ps
CPU time 36.12 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 06:49:23 PM PDT 24
Peak memory 200160 kb
Host smart-58a16862-ac85-45c2-8f3e-500150e5bb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900915569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1900915569
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.4137344765
Short name T299
Test name
Test status
Simulation time 2820117292 ps
CPU time 5.13 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 06:48:51 PM PDT 24
Peak memory 196008 kb
Host smart-b90aed5b-34a9-4c13-941c-caef37c0daaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137344765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.4137344765
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3737433507
Short name T293
Test name
Test status
Simulation time 453770231 ps
CPU time 1.92 seconds
Started Jul 18 06:48:40 PM PDT 24
Finished Jul 18 06:48:47 PM PDT 24
Peak memory 198516 kb
Host smart-8b537563-6cd0-482a-a10d-c3a4e2dd1ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737433507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3737433507
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3287307387
Short name T192
Test name
Test status
Simulation time 403837736963 ps
CPU time 803.12 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 07:02:09 PM PDT 24
Peak memory 199844 kb
Host smart-cacca7a5-8669-47f8-874b-6b0a339cd5fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287307387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3287307387
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3947959402
Short name T814
Test name
Test status
Simulation time 221570107901 ps
CPU time 453.28 seconds
Started Jul 18 06:48:41 PM PDT 24
Finished Jul 18 06:56:19 PM PDT 24
Peak memory 216584 kb
Host smart-06d35687-dd98-422d-9eb2-2e3ba4794d50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947959402 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3947959402
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2725371952
Short name T1146
Test name
Test status
Simulation time 1998005968 ps
CPU time 1.66 seconds
Started Jul 18 06:48:42 PM PDT 24
Finished Jul 18 06:48:49 PM PDT 24
Peak memory 198572 kb
Host smart-52fd09b1-c108-4aca-9722-d52c3abe7d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725371952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2725371952
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.217366402
Short name T1032
Test name
Test status
Simulation time 119548562441 ps
CPU time 52.85 seconds
Started Jul 18 06:48:42 PM PDT 24
Finished Jul 18 06:49:40 PM PDT 24
Peak memory 200132 kb
Host smart-01dcc5a2-7a8e-4dce-ad93-eb9f3ea021d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217366402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.217366402
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2213722742
Short name T487
Test name
Test status
Simulation time 13310825521 ps
CPU time 23.01 seconds
Started Jul 18 06:53:34 PM PDT 24
Finished Jul 18 06:53:59 PM PDT 24
Peak memory 199884 kb
Host smart-00187923-f8b6-45fa-94b7-181487a1ffb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213722742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2213722742
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3887296958
Short name T710
Test name
Test status
Simulation time 37485991653 ps
CPU time 15.94 seconds
Started Jul 18 06:53:34 PM PDT 24
Finished Jul 18 06:53:52 PM PDT 24
Peak memory 200200 kb
Host smart-78622267-06e6-4034-8323-dc445e5bf87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887296958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3887296958
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3500088124
Short name T273
Test name
Test status
Simulation time 219614570814 ps
CPU time 218.36 seconds
Started Jul 18 06:53:35 PM PDT 24
Finished Jul 18 06:57:15 PM PDT 24
Peak memory 200212 kb
Host smart-d59d45bc-d91f-4c7a-82d0-71c64dbd6080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500088124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3500088124
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.367032864
Short name T644
Test name
Test status
Simulation time 75979146967 ps
CPU time 14.22 seconds
Started Jul 18 06:53:36 PM PDT 24
Finished Jul 18 06:53:52 PM PDT 24
Peak memory 200276 kb
Host smart-ba80614f-bba8-4f75-9916-91c6979f7495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367032864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.367032864
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3096836797
Short name T530
Test name
Test status
Simulation time 28422519967 ps
CPU time 20.96 seconds
Started Jul 18 06:53:35 PM PDT 24
Finished Jul 18 06:53:58 PM PDT 24
Peak memory 200216 kb
Host smart-08a6db2a-113b-4877-b693-6bcdd3421441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096836797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3096836797
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2925536455
Short name T826
Test name
Test status
Simulation time 36356816125 ps
CPU time 16.22 seconds
Started Jul 18 06:53:35 PM PDT 24
Finished Jul 18 06:53:53 PM PDT 24
Peak memory 200264 kb
Host smart-52e35280-9ab1-4061-bbac-363b2c8f9c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925536455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2925536455
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3163874501
Short name T671
Test name
Test status
Simulation time 43871382283 ps
CPU time 63.26 seconds
Started Jul 18 06:54:00 PM PDT 24
Finished Jul 18 06:55:09 PM PDT 24
Peak memory 200192 kb
Host smart-736f58dc-ab33-49a4-8508-e1bfb42945c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163874501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3163874501
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3232380720
Short name T837
Test name
Test status
Simulation time 53200366654 ps
CPU time 19.18 seconds
Started Jul 18 06:53:53 PM PDT 24
Finished Jul 18 06:54:14 PM PDT 24
Peak memory 200188 kb
Host smart-1c5fca0c-e65e-4054-a7a2-7a90f2e5083f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232380720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3232380720
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2893022607
Short name T457
Test name
Test status
Simulation time 42011814 ps
CPU time 0.54 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:47:51 PM PDT 24
Peak memory 195576 kb
Host smart-282c425f-ec6b-46aa-9d7b-9dc3fad82ef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893022607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2893022607
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.4261626147
Short name T961
Test name
Test status
Simulation time 130277731024 ps
CPU time 204.33 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:51:18 PM PDT 24
Peak memory 200192 kb
Host smart-ed9455a0-2bdf-4bce-8ef0-ab868c1deb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261626147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.4261626147
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1708844464
Short name T864
Test name
Test status
Simulation time 129309947804 ps
CPU time 52.67 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:48:42 PM PDT 24
Peak memory 200192 kb
Host smart-ec15d9af-dca7-4e89-9953-4b504796c618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708844464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1708844464
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2841023336
Short name T988
Test name
Test status
Simulation time 173884133889 ps
CPU time 236.26 seconds
Started Jul 18 06:47:49 PM PDT 24
Finished Jul 18 06:51:53 PM PDT 24
Peak memory 200188 kb
Host smart-1aeacd60-019d-4370-b995-40d5ac293bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841023336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2841023336
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2157129145
Short name T877
Test name
Test status
Simulation time 38363097881 ps
CPU time 72.08 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:49:05 PM PDT 24
Peak memory 200140 kb
Host smart-8466394f-22e4-4136-9a9f-e63652ac51b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157129145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2157129145
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2419077363
Short name T657
Test name
Test status
Simulation time 300531910511 ps
CPU time 471.28 seconds
Started Jul 18 06:47:43 PM PDT 24
Finished Jul 18 06:55:37 PM PDT 24
Peak memory 200184 kb
Host smart-baf510f7-a283-4c7f-a37e-b9ec5d36265c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419077363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2419077363
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3868873463
Short name T24
Test name
Test status
Simulation time 552692494 ps
CPU time 1.5 seconds
Started Jul 18 06:47:43 PM PDT 24
Finished Jul 18 06:47:49 PM PDT 24
Peak memory 196252 kb
Host smart-8b4eece1-08a2-41c0-b61a-804f1665ad88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868873463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3868873463
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2149890557
Short name T474
Test name
Test status
Simulation time 53544841083 ps
CPU time 87.51 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:49:19 PM PDT 24
Peak memory 208488 kb
Host smart-f9651a24-7dfb-4c9f-b531-103635dba798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149890557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2149890557
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.268427887
Short name T953
Test name
Test status
Simulation time 7735813858 ps
CPU time 471.95 seconds
Started Jul 18 06:47:43 PM PDT 24
Finished Jul 18 06:55:38 PM PDT 24
Peak memory 200096 kb
Host smart-4b3f0b24-f251-4507-84c8-422f4f56d009
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=268427887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.268427887
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.4160470031
Short name T835
Test name
Test status
Simulation time 6284440701 ps
CPU time 13.01 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:48:05 PM PDT 24
Peak memory 198392 kb
Host smart-347473e2-f220-4c74-b499-e91a9756b46b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4160470031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.4160470031
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.4079748140
Short name T464
Test name
Test status
Simulation time 115634850349 ps
CPU time 162.66 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:50:32 PM PDT 24
Peak memory 199568 kb
Host smart-6cbad727-293d-4c8c-a936-8b32eb8ea9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079748140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.4079748140
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2663627890
Short name T1069
Test name
Test status
Simulation time 6795700577 ps
CPU time 3.17 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:47:57 PM PDT 24
Peak memory 196600 kb
Host smart-79feb6ac-fd7b-4b31-b367-146b3f767a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663627890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2663627890
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.882055207
Short name T102
Test name
Test status
Simulation time 142657248 ps
CPU time 0.75 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:47:51 PM PDT 24
Peak memory 218424 kb
Host smart-e5614f73-7bfc-41bc-be5a-9efe53600bb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882055207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.882055207
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2310177201
Short name T1150
Test name
Test status
Simulation time 504462832 ps
CPU time 1.2 seconds
Started Jul 18 06:47:43 PM PDT 24
Finished Jul 18 06:47:48 PM PDT 24
Peak memory 200080 kb
Host smart-e8a0886e-8737-4f9b-b15f-cefe94e321f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310177201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2310177201
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.177626273
Short name T816
Test name
Test status
Simulation time 34622260885 ps
CPU time 32.15 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:48:24 PM PDT 24
Peak memory 200380 kb
Host smart-e4f6cc1b-d255-4c2e-8550-8edc85db8fc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177626273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.177626273
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.61183424
Short name T112
Test name
Test status
Simulation time 45907059701 ps
CPU time 574.14 seconds
Started Jul 18 06:47:42 PM PDT 24
Finished Jul 18 06:57:20 PM PDT 24
Peak memory 216920 kb
Host smart-90179866-dc58-45fd-ab24-e9271fb4fc75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61183424 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.61183424
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1177970650
Short name T664
Test name
Test status
Simulation time 6337583559 ps
CPU time 13.57 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:48:04 PM PDT 24
Peak memory 200176 kb
Host smart-60dc43e1-5428-406a-8bd8-3006f7c2aabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177970650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1177970650
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3681645333
Short name T693
Test name
Test status
Simulation time 79630032823 ps
CPU time 33.44 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:48:28 PM PDT 24
Peak memory 200192 kb
Host smart-09e783d1-484e-49d9-864b-90573346535d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681645333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3681645333
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3258463684
Short name T1177
Test name
Test status
Simulation time 34299333 ps
CPU time 0.55 seconds
Started Jul 18 06:48:54 PM PDT 24
Finished Jul 18 06:48:58 PM PDT 24
Peak memory 195588 kb
Host smart-dadb1aeb-79ad-448c-a0b2-586249061f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258463684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3258463684
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1035665330
Short name T582
Test name
Test status
Simulation time 34031787436 ps
CPU time 55.25 seconds
Started Jul 18 06:48:52 PM PDT 24
Finished Jul 18 06:49:49 PM PDT 24
Peak memory 200156 kb
Host smart-65f1c8a3-3898-49bd-87c8-cfb0d83c60b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035665330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1035665330
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.126531963
Short name T1094
Test name
Test status
Simulation time 67625938770 ps
CPU time 47.95 seconds
Started Jul 18 06:48:55 PM PDT 24
Finished Jul 18 06:49:46 PM PDT 24
Peak memory 200092 kb
Host smart-4d4c52fa-7b77-40f6-ab72-dd473251af33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126531963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.126531963
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.200534048
Short name T153
Test name
Test status
Simulation time 65731723728 ps
CPU time 24 seconds
Started Jul 18 06:48:52 PM PDT 24
Finished Jul 18 06:49:18 PM PDT 24
Peak memory 200128 kb
Host smart-28497950-2be0-4008-8999-0fd59d022104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200534048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.200534048
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.304846902
Short name T714
Test name
Test status
Simulation time 67871811724 ps
CPU time 33.52 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:34 PM PDT 24
Peak memory 198952 kb
Host smart-2ed6eeb1-5b44-422f-8349-03cf79296a02
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304846902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.304846902
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.149996534
Short name T337
Test name
Test status
Simulation time 43866746421 ps
CPU time 170.94 seconds
Started Jul 18 06:48:53 PM PDT 24
Finished Jul 18 06:51:46 PM PDT 24
Peak memory 200120 kb
Host smart-0ff462ed-8f37-406e-8096-c8b0e1ff1522
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=149996534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.149996534
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.184951747
Short name T637
Test name
Test status
Simulation time 2357721289 ps
CPU time 2.59 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:04 PM PDT 24
Peak memory 196412 kb
Host smart-067fe6f3-6189-4a3d-9832-d3a725a7d6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184951747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.184951747
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.433542230
Short name T893
Test name
Test status
Simulation time 45313848948 ps
CPU time 44.92 seconds
Started Jul 18 06:48:54 PM PDT 24
Finished Jul 18 06:49:42 PM PDT 24
Peak memory 198668 kb
Host smart-c2863460-c822-4b4e-809a-0c871b0b0b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433542230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.433542230
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3294235494
Short name T372
Test name
Test status
Simulation time 19367003052 ps
CPU time 242.65 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:53:04 PM PDT 24
Peak memory 200132 kb
Host smart-99b9af6e-be81-4bf4-ae43-8b0b86752ff7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3294235494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3294235494
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1964134961
Short name T950
Test name
Test status
Simulation time 1703868516 ps
CPU time 8.19 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:09 PM PDT 24
Peak memory 198228 kb
Host smart-fc4c7538-9c9d-4d82-82f0-0dd99b4c11b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964134961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1964134961
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1098536843
Short name T605
Test name
Test status
Simulation time 69677427004 ps
CPU time 133.1 seconds
Started Jul 18 06:48:53 PM PDT 24
Finished Jul 18 06:51:09 PM PDT 24
Peak memory 200144 kb
Host smart-1474fb90-c81d-490a-90fc-2fbc8a2b97d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098536843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1098536843
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.860091559
Short name T797
Test name
Test status
Simulation time 48308387700 ps
CPU time 13.58 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:15 PM PDT 24
Peak memory 196888 kb
Host smart-e803e438-07ff-46bd-9618-8e16c70f0f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860091559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.860091559
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3596530698
Short name T724
Test name
Test status
Simulation time 299647153 ps
CPU time 1.36 seconds
Started Jul 18 06:48:54 PM PDT 24
Finished Jul 18 06:48:58 PM PDT 24
Peak memory 198652 kb
Host smart-18261fa0-8cde-4e58-97ca-6597acae342d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596530698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3596530698
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.445946721
Short name T1034
Test name
Test status
Simulation time 6828341391 ps
CPU time 9.35 seconds
Started Jul 18 06:48:53 PM PDT 24
Finished Jul 18 06:49:04 PM PDT 24
Peak memory 200124 kb
Host smart-d54efdc8-dbef-4107-a179-d83669dc4edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445946721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.445946721
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.41114310
Short name T716
Test name
Test status
Simulation time 53653006829 ps
CPU time 74.53 seconds
Started Jul 18 06:48:58 PM PDT 24
Finished Jul 18 06:50:17 PM PDT 24
Peak memory 200116 kb
Host smart-cf02327a-4970-4ab7-ac65-37fb81de2c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41114310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.41114310
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.438498342
Short name T313
Test name
Test status
Simulation time 13119814692 ps
CPU time 20.37 seconds
Started Jul 18 06:54:02 PM PDT 24
Finished Jul 18 06:54:30 PM PDT 24
Peak memory 200204 kb
Host smart-4540d73e-25a9-4d70-ad53-c261686fa07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438498342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.438498342
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2480741983
Short name T538
Test name
Test status
Simulation time 87315176582 ps
CPU time 145.83 seconds
Started Jul 18 06:54:00 PM PDT 24
Finished Jul 18 06:56:33 PM PDT 24
Peak memory 200264 kb
Host smart-7155ad00-a819-4329-9fa1-54c5bec494e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480741983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2480741983
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2363163305
Short name T326
Test name
Test status
Simulation time 154609389484 ps
CPU time 234.24 seconds
Started Jul 18 06:54:01 PM PDT 24
Finished Jul 18 06:58:03 PM PDT 24
Peak memory 200132 kb
Host smart-aced9668-0152-48fa-b41c-12eb9a86eeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363163305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2363163305
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.4173410038
Short name T1103
Test name
Test status
Simulation time 29135251629 ps
CPU time 39.6 seconds
Started Jul 18 06:54:02 PM PDT 24
Finished Jul 18 06:54:49 PM PDT 24
Peak memory 200200 kb
Host smart-605834b2-6eaf-496e-a84d-26f7036f6d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173410038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.4173410038
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2098341086
Short name T1082
Test name
Test status
Simulation time 79306362575 ps
CPU time 20.26 seconds
Started Jul 18 06:53:54 PM PDT 24
Finished Jul 18 06:54:17 PM PDT 24
Peak memory 200128 kb
Host smart-7d03cc76-25ec-45ed-900b-490c4af08465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098341086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2098341086
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.425633429
Short name T317
Test name
Test status
Simulation time 35547062934 ps
CPU time 53.58 seconds
Started Jul 18 06:54:00 PM PDT 24
Finished Jul 18 06:55:00 PM PDT 24
Peak memory 200204 kb
Host smart-48cee278-676e-494f-be8a-63474ac683fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425633429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.425633429
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3522473777
Short name T695
Test name
Test status
Simulation time 37991515258 ps
CPU time 82.93 seconds
Started Jul 18 06:54:00 PM PDT 24
Finished Jul 18 06:55:28 PM PDT 24
Peak memory 200124 kb
Host smart-97cc0c4d-1455-4009-9635-908757bae90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522473777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3522473777
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2300469297
Short name T30
Test name
Test status
Simulation time 37272862 ps
CPU time 0.58 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:01 PM PDT 24
Peak memory 195592 kb
Host smart-93ab9b59-9fff-4096-9171-480de778d9a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300469297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2300469297
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1018473661
Short name T552
Test name
Test status
Simulation time 34842992227 ps
CPU time 29.4 seconds
Started Jul 18 06:48:51 PM PDT 24
Finished Jul 18 06:49:21 PM PDT 24
Peak memory 200180 kb
Host smart-e458a4f7-9b30-4501-a75d-a4cdce719f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018473661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1018473661
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1155715859
Short name T167
Test name
Test status
Simulation time 146743372629 ps
CPU time 59.09 seconds
Started Jul 18 06:48:55 PM PDT 24
Finished Jul 18 06:49:58 PM PDT 24
Peak memory 200200 kb
Host smart-25199cb1-7bf6-4d21-b11d-bf182ff2ff86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155715859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1155715859
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.951266180
Short name T1164
Test name
Test status
Simulation time 147142839371 ps
CPU time 56.5 seconds
Started Jul 18 06:48:53 PM PDT 24
Finished Jul 18 06:49:51 PM PDT 24
Peak memory 200212 kb
Host smart-83ac5c90-4fa4-4435-92e9-f6cc8d60d373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951266180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.951266180
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1567765313
Short name T463
Test name
Test status
Simulation time 9560067972 ps
CPU time 13.15 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:13 PM PDT 24
Peak memory 196988 kb
Host smart-c8dc6e65-c776-4aa2-a0bc-1c0ba2367804
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567765313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1567765313
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1154934712
Short name T569
Test name
Test status
Simulation time 223195213054 ps
CPU time 400.25 seconds
Started Jul 18 06:48:52 PM PDT 24
Finished Jul 18 06:55:34 PM PDT 24
Peak memory 200148 kb
Host smart-8608e057-a265-4e1b-8e46-5bd88da27c99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1154934712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1154934712
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.457314556
Short name T937
Test name
Test status
Simulation time 3447775350 ps
CPU time 6.52 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:08 PM PDT 24
Peak memory 200108 kb
Host smart-b44046b2-7bd5-4677-9e3c-afa48cdccad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457314556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.457314556
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1905752069
Short name T919
Test name
Test status
Simulation time 224683357613 ps
CPU time 86.88 seconds
Started Jul 18 06:48:55 PM PDT 24
Finished Jul 18 06:50:26 PM PDT 24
Peak memory 208420 kb
Host smart-784c6109-11de-4bf1-a96b-6c6f5fb751a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905752069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1905752069
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.816887851
Short name T1006
Test name
Test status
Simulation time 17499055353 ps
CPU time 904.42 seconds
Started Jul 18 06:48:52 PM PDT 24
Finished Jul 18 07:03:59 PM PDT 24
Peak memory 200172 kb
Host smart-45600b5b-eb10-4832-b2ea-f001d4eef41d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=816887851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.816887851
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3336533975
Short name T578
Test name
Test status
Simulation time 1992975554 ps
CPU time 8.69 seconds
Started Jul 18 06:48:52 PM PDT 24
Finished Jul 18 06:49:02 PM PDT 24
Peak memory 198176 kb
Host smart-ffc3ee88-8f93-4827-b6a9-e0abbbed6f80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336533975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3336533975
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2246187507
Short name T1007
Test name
Test status
Simulation time 99296216840 ps
CPU time 165.43 seconds
Started Jul 18 06:48:51 PM PDT 24
Finished Jul 18 06:51:37 PM PDT 24
Peak memory 200192 kb
Host smart-214037ec-1fc2-420a-80ed-3d8c9daa24b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246187507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2246187507
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3650234314
Short name T424
Test name
Test status
Simulation time 40833314297 ps
CPU time 53.56 seconds
Started Jul 18 06:48:56 PM PDT 24
Finished Jul 18 06:49:53 PM PDT 24
Peak memory 196224 kb
Host smart-8661220d-0496-4250-8a31-4347ef45d924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650234314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3650234314
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3306183534
Short name T860
Test name
Test status
Simulation time 930621931 ps
CPU time 4.19 seconds
Started Jul 18 06:48:58 PM PDT 24
Finished Jul 18 06:49:06 PM PDT 24
Peak memory 199612 kb
Host smart-c0aa3909-1040-4e86-ab8f-c05337f43cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306183534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3306183534
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1268914728
Short name T1029
Test name
Test status
Simulation time 78064336419 ps
CPU time 130.62 seconds
Started Jul 18 06:48:58 PM PDT 24
Finished Jul 18 06:51:13 PM PDT 24
Peak memory 200124 kb
Host smart-577fe365-1148-476d-879d-19730f6fb0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268914728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1268914728
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3780715766
Short name T543
Test name
Test status
Simulation time 2729142154 ps
CPU time 1.58 seconds
Started Jul 18 06:48:53 PM PDT 24
Finished Jul 18 06:48:56 PM PDT 24
Peak memory 199152 kb
Host smart-164e5bb8-08c7-4a6f-a219-71c8c4d78c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780715766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3780715766
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.884266679
Short name T845
Test name
Test status
Simulation time 67579840609 ps
CPU time 114.95 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:50:56 PM PDT 24
Peak memory 200096 kb
Host smart-2426f49e-33f0-4e6b-9e23-e96d41db3028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884266679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.884266679
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.503535689
Short name T846
Test name
Test status
Simulation time 54500548681 ps
CPU time 53.45 seconds
Started Jul 18 06:53:56 PM PDT 24
Finished Jul 18 06:54:52 PM PDT 24
Peak memory 200048 kb
Host smart-ab29977a-e3a8-4d74-abe3-8d5e8b8a65fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503535689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.503535689
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.932205214
Short name T1137
Test name
Test status
Simulation time 51868891802 ps
CPU time 76.15 seconds
Started Jul 18 06:54:00 PM PDT 24
Finished Jul 18 06:55:23 PM PDT 24
Peak memory 200192 kb
Host smart-c8b91026-0649-4079-8b0f-6c923a08922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932205214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.932205214
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1995318222
Short name T473
Test name
Test status
Simulation time 31802964131 ps
CPU time 23.26 seconds
Started Jul 18 06:53:52 PM PDT 24
Finished Jul 18 06:54:17 PM PDT 24
Peak memory 200120 kb
Host smart-70601b3c-b4df-4e37-b2cb-c461a9bd2c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995318222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1995318222
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.3953711628
Short name T1178
Test name
Test status
Simulation time 69033026895 ps
CPU time 91.75 seconds
Started Jul 18 06:54:01 PM PDT 24
Finished Jul 18 06:55:41 PM PDT 24
Peak memory 200200 kb
Host smart-fa983c98-cd7d-49b4-ab3d-11cb0d4429a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953711628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3953711628
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.418857841
Short name T190
Test name
Test status
Simulation time 93421119713 ps
CPU time 23.23 seconds
Started Jul 18 06:53:59 PM PDT 24
Finished Jul 18 06:54:27 PM PDT 24
Peak memory 200140 kb
Host smart-98394a61-ead2-4d82-972b-04f0d49779a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418857841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.418857841
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.957264169
Short name T574
Test name
Test status
Simulation time 206083791665 ps
CPU time 72.73 seconds
Started Jul 18 06:53:53 PM PDT 24
Finished Jul 18 06:55:08 PM PDT 24
Peak memory 200196 kb
Host smart-20cfb4c6-6593-4aa5-917c-fb942a9557a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957264169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.957264169
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2948487485
Short name T817
Test name
Test status
Simulation time 209962772161 ps
CPU time 42.71 seconds
Started Jul 18 06:54:02 PM PDT 24
Finished Jul 18 06:54:52 PM PDT 24
Peak memory 200180 kb
Host smart-f0140cab-9b8a-4972-b86c-2aefa5a537d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948487485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2948487485
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1979150896
Short name T282
Test name
Test status
Simulation time 9777581360 ps
CPU time 18.82 seconds
Started Jul 18 06:53:54 PM PDT 24
Finished Jul 18 06:54:15 PM PDT 24
Peak memory 199980 kb
Host smart-04f49634-7cad-479f-9642-db8e653d9e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979150896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1979150896
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.664846984
Short name T936
Test name
Test status
Simulation time 29343795930 ps
CPU time 12.64 seconds
Started Jul 18 06:53:52 PM PDT 24
Finished Jul 18 06:54:07 PM PDT 24
Peak memory 200192 kb
Host smart-13f0911f-2b8f-41b3-ac99-b6b3acd4f85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664846984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.664846984
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3316728518
Short name T350
Test name
Test status
Simulation time 13737042 ps
CPU time 0.54 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:02 PM PDT 24
Peak memory 195848 kb
Host smart-0794a269-24f6-49d7-b421-711bff453f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316728518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3316728518
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3360668469
Short name T45
Test name
Test status
Simulation time 63033261901 ps
CPU time 28.09 seconds
Started Jul 18 06:48:50 PM PDT 24
Finished Jul 18 06:49:19 PM PDT 24
Peak memory 200192 kb
Host smart-352e9c43-d1ed-47eb-b49e-50da9e3f0b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360668469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3360668469
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.539459506
Short name T1080
Test name
Test status
Simulation time 67872308902 ps
CPU time 110.98 seconds
Started Jul 18 06:48:56 PM PDT 24
Finished Jul 18 06:50:51 PM PDT 24
Peak memory 200192 kb
Host smart-adfd66d6-1428-44e4-b2ca-d0577b9edba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539459506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.539459506
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_intr.691527738
Short name T809
Test name
Test status
Simulation time 6529298129 ps
CPU time 2.99 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:03 PM PDT 24
Peak memory 199416 kb
Host smart-0beac118-c832-4486-8b99-84489b1ca1b5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691527738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.691527738
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_loopback.3834946975
Short name T1054
Test name
Test status
Simulation time 9059737169 ps
CPU time 6.53 seconds
Started Jul 18 06:48:55 PM PDT 24
Finished Jul 18 06:49:05 PM PDT 24
Peak memory 199820 kb
Host smart-604b4690-72ed-402d-92b1-c2c76a75614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834946975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3834946975
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.4247327737
Short name T346
Test name
Test status
Simulation time 28952764487 ps
CPU time 50.85 seconds
Started Jul 18 06:48:56 PM PDT 24
Finished Jul 18 06:49:50 PM PDT 24
Peak memory 199060 kb
Host smart-e37c4fc3-392f-4a1e-aed9-14c49bd2e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247327737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.4247327737
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1019806717
Short name T272
Test name
Test status
Simulation time 30221988967 ps
CPU time 832.26 seconds
Started Jul 18 06:48:54 PM PDT 24
Finished Jul 18 07:02:48 PM PDT 24
Peak memory 200116 kb
Host smart-aa94021a-3be9-48f4-be81-0d359205bec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019806717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1019806717
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2447318173
Short name T851
Test name
Test status
Simulation time 2460684579 ps
CPU time 4.64 seconds
Started Jul 18 06:48:56 PM PDT 24
Finished Jul 18 06:49:04 PM PDT 24
Peak memory 198400 kb
Host smart-58db27b7-3ae2-48b1-8ea7-f976f410e1db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2447318173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2447318173
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2563333494
Short name T147
Test name
Test status
Simulation time 34558389943 ps
CPU time 27.58 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:28 PM PDT 24
Peak memory 200132 kb
Host smart-56cade18-689b-4d59-aaa3-85670adaf68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563333494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2563333494
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2999443709
Short name T27
Test name
Test status
Simulation time 2764929168 ps
CPU time 4.38 seconds
Started Jul 18 06:48:54 PM PDT 24
Finished Jul 18 06:49:02 PM PDT 24
Peak memory 196212 kb
Host smart-cfed34a1-f97f-4840-807e-ba052a4e9d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999443709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2999443709
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1570163609
Short name T339
Test name
Test status
Simulation time 870606018 ps
CPU time 1.92 seconds
Started Jul 18 06:48:52 PM PDT 24
Finished Jul 18 06:48:56 PM PDT 24
Peak memory 200188 kb
Host smart-849d6313-ccc7-4e76-bac6-5bca39028a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570163609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1570163609
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1705538138
Short name T145
Test name
Test status
Simulation time 689418606630 ps
CPU time 72.72 seconds
Started Jul 18 06:48:58 PM PDT 24
Finished Jul 18 06:50:15 PM PDT 24
Peak memory 200112 kb
Host smart-b4cc3e79-d65d-4f85-8d46-931f67782269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705538138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1705538138
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1022814120
Short name T1056
Test name
Test status
Simulation time 85565261675 ps
CPU time 1368.28 seconds
Started Jul 18 06:48:54 PM PDT 24
Finished Jul 18 07:11:45 PM PDT 24
Peak memory 224880 kb
Host smart-8858569c-9c87-489c-8f1f-b4ba8f5acc1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022814120 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1022814120
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1394381235
Short name T453
Test name
Test status
Simulation time 1156927297 ps
CPU time 3.87 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:04 PM PDT 24
Peak memory 198600 kb
Host smart-fb007edf-4834-406a-8be1-24e1bb3cc1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394381235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1394381235
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3479700521
Short name T735
Test name
Test status
Simulation time 9556579606 ps
CPU time 14.71 seconds
Started Jul 18 06:48:54 PM PDT 24
Finished Jul 18 06:49:12 PM PDT 24
Peak memory 200160 kb
Host smart-d77ac71d-ba0e-429f-a5e2-eae39848d7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479700521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3479700521
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.679915460
Short name T665
Test name
Test status
Simulation time 52769105421 ps
CPU time 23.99 seconds
Started Jul 18 06:53:52 PM PDT 24
Finished Jul 18 06:54:18 PM PDT 24
Peak memory 200200 kb
Host smart-c824ee24-3fc5-4d49-9b29-3483718d423d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679915460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.679915460
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.569794095
Short name T507
Test name
Test status
Simulation time 111075343027 ps
CPU time 63.74 seconds
Started Jul 18 06:54:03 PM PDT 24
Finished Jul 18 06:55:15 PM PDT 24
Peak memory 200376 kb
Host smart-f43ae333-c645-492a-b689-fe9c846b7062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569794095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.569794095
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2382672900
Short name T415
Test name
Test status
Simulation time 74177528897 ps
CPU time 116.08 seconds
Started Jul 18 06:53:54 PM PDT 24
Finished Jul 18 06:55:53 PM PDT 24
Peak memory 200112 kb
Host smart-52f75568-2fbc-4e82-b854-e2c564686009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382672900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2382672900
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2550810007
Short name T798
Test name
Test status
Simulation time 79756095717 ps
CPU time 107.65 seconds
Started Jul 18 06:53:55 PM PDT 24
Finished Jul 18 06:55:44 PM PDT 24
Peak memory 200196 kb
Host smart-df40e6e6-b445-4238-b3ef-3851d1f05ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550810007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2550810007
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.128466641
Short name T588
Test name
Test status
Simulation time 29569387772 ps
CPU time 11.59 seconds
Started Jul 18 06:54:03 PM PDT 24
Finished Jul 18 06:54:23 PM PDT 24
Peak memory 200264 kb
Host smart-1cfa88a5-c76f-413d-84c8-2b5107bc590b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128466641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.128466641
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2281992182
Short name T324
Test name
Test status
Simulation time 8982417031 ps
CPU time 14.96 seconds
Started Jul 18 06:54:01 PM PDT 24
Finished Jul 18 06:54:24 PM PDT 24
Peak memory 200188 kb
Host smart-df33e139-5f0f-49d0-8749-e5d3546a40d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281992182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2281992182
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2039912772
Short name T1102
Test name
Test status
Simulation time 103988777729 ps
CPU time 71.15 seconds
Started Jul 18 06:54:05 PM PDT 24
Finished Jul 18 06:55:24 PM PDT 24
Peak memory 200156 kb
Host smart-6fff964e-ea9f-486e-b861-22306738c3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039912772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2039912772
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2036503395
Short name T6
Test name
Test status
Simulation time 22679936124 ps
CPU time 17.2 seconds
Started Jul 18 06:53:53 PM PDT 24
Finished Jul 18 06:54:12 PM PDT 24
Peak memory 200048 kb
Host smart-bb3d2c85-a116-4d8c-b78a-92272faf501e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036503395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2036503395
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1591958910
Short name T334
Test name
Test status
Simulation time 18029177 ps
CPU time 0.56 seconds
Started Jul 18 06:49:07 PM PDT 24
Finished Jul 18 06:49:10 PM PDT 24
Peak memory 195572 kb
Host smart-e5923fd7-4a10-4e72-874d-84c202be2753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591958910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1591958910
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1692212776
Short name T404
Test name
Test status
Simulation time 67449934779 ps
CPU time 78.77 seconds
Started Jul 18 06:48:55 PM PDT 24
Finished Jul 18 06:50:16 PM PDT 24
Peak memory 200148 kb
Host smart-9cf67db3-c944-420b-b54b-2e1d060c3add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692212776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1692212776
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2241689855
Short name T707
Test name
Test status
Simulation time 59105010642 ps
CPU time 23.17 seconds
Started Jul 18 06:48:56 PM PDT 24
Finished Jul 18 06:49:23 PM PDT 24
Peak memory 200136 kb
Host smart-eb6924d4-9d6e-4da8-b6ab-4c658a5643c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241689855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2241689855
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2320233547
Short name T1090
Test name
Test status
Simulation time 109552032195 ps
CPU time 162.3 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:51:42 PM PDT 24
Peak memory 200132 kb
Host smart-9e58133e-cad9-410f-b7da-521e00615777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320233547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2320233547
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1821260159
Short name T1160
Test name
Test status
Simulation time 25017973330 ps
CPU time 10.58 seconds
Started Jul 18 06:48:55 PM PDT 24
Finished Jul 18 06:49:08 PM PDT 24
Peak memory 200180 kb
Host smart-3dc0ac29-ebc4-4f78-a9aa-ea0bde593950
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821260159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1821260159
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3565291328
Short name T666
Test name
Test status
Simulation time 156852909910 ps
CPU time 324.47 seconds
Started Jul 18 06:49:11 PM PDT 24
Finished Jul 18 06:54:38 PM PDT 24
Peak memory 200116 kb
Host smart-bf59dac7-e634-4ac5-971a-16f5b3801f53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3565291328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3565291328
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3004409575
Short name T888
Test name
Test status
Simulation time 9213947498 ps
CPU time 14.25 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:15 PM PDT 24
Peak memory 199956 kb
Host smart-50840598-fc42-4be4-8408-68554f3bafe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004409575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3004409575
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1589463545
Short name T276
Test name
Test status
Simulation time 52396978502 ps
CPU time 33.15 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:34 PM PDT 24
Peak memory 200260 kb
Host smart-9fb37ade-4f88-40d2-877b-756c5c50a191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589463545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1589463545
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2840455340
Short name T1026
Test name
Test status
Simulation time 25298253652 ps
CPU time 542 seconds
Started Jul 18 06:48:58 PM PDT 24
Finished Jul 18 06:58:04 PM PDT 24
Peak memory 200168 kb
Host smart-d10de4a3-fa6a-43c2-916d-1804839c3761
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2840455340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2840455340
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1198360241
Short name T1136
Test name
Test status
Simulation time 4828606174 ps
CPU time 10.1 seconds
Started Jul 18 06:48:56 PM PDT 24
Finished Jul 18 06:49:09 PM PDT 24
Peak memory 199420 kb
Host smart-046da770-d675-4135-ae06-443a56931351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198360241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1198360241
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3207683920
Short name T319
Test name
Test status
Simulation time 73822843183 ps
CPU time 23.55 seconds
Started Jul 18 06:48:58 PM PDT 24
Finished Jul 18 06:49:25 PM PDT 24
Peak memory 200128 kb
Host smart-8f96c1d3-9042-4bf5-8747-790f39e16053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207683920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3207683920
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2305613412
Short name T834
Test name
Test status
Simulation time 5290989731 ps
CPU time 2.69 seconds
Started Jul 18 06:48:58 PM PDT 24
Finished Jul 18 06:49:04 PM PDT 24
Peak memory 196312 kb
Host smart-ba8b10de-e786-4b2f-8732-d1e3a9e89a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305613412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2305613412
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1694079291
Short name T915
Test name
Test status
Simulation time 5867788264 ps
CPU time 19.76 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:21 PM PDT 24
Peak memory 199912 kb
Host smart-f0e9c0c1-0ecc-4106-9ec5-723ab8230465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694079291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1694079291
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3311037807
Short name T297
Test name
Test status
Simulation time 529049764216 ps
CPU time 409.58 seconds
Started Jul 18 06:49:11 PM PDT 24
Finished Jul 18 06:56:04 PM PDT 24
Peak memory 208456 kb
Host smart-139f093b-7fd1-4972-82a4-e0608e06d533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311037807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3311037807
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3930865554
Short name T1138
Test name
Test status
Simulation time 390301587028 ps
CPU time 208.26 seconds
Started Jul 18 06:49:07 PM PDT 24
Finished Jul 18 06:52:38 PM PDT 24
Peak memory 216676 kb
Host smart-06f21965-6231-432d-ba34-f8e28a46eeb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930865554 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3930865554
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2596703099
Short name T883
Test name
Test status
Simulation time 2474370693 ps
CPU time 1.9 seconds
Started Jul 18 06:48:57 PM PDT 24
Finished Jul 18 06:49:03 PM PDT 24
Peak memory 199072 kb
Host smart-78bf5008-20b0-4276-ad81-d968dd59acdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596703099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2596703099
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.4125030755
Short name T601
Test name
Test status
Simulation time 46099453612 ps
CPU time 76.33 seconds
Started Jul 18 06:48:54 PM PDT 24
Finished Jul 18 06:50:14 PM PDT 24
Peak memory 200200 kb
Host smart-c8c5bdfe-2fed-4316-bd18-a0ea0a4315d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125030755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.4125030755
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2548776457
Short name T1036
Test name
Test status
Simulation time 17185921796 ps
CPU time 25.04 seconds
Started Jul 18 06:53:57 PM PDT 24
Finished Jul 18 06:54:26 PM PDT 24
Peak memory 200024 kb
Host smart-370dc7c6-92e8-4b2d-996c-11fdd2af93b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548776457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2548776457
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1866498902
Short name T75
Test name
Test status
Simulation time 154519924355 ps
CPU time 30.16 seconds
Started Jul 18 06:54:02 PM PDT 24
Finished Jul 18 06:54:39 PM PDT 24
Peak memory 200200 kb
Host smart-4f5dfafa-0256-4bdb-ae31-92a874b7f78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866498902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1866498902
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2658868266
Short name T959
Test name
Test status
Simulation time 8373758779 ps
CPU time 6.47 seconds
Started Jul 18 06:53:56 PM PDT 24
Finished Jul 18 06:54:05 PM PDT 24
Peak memory 199272 kb
Host smart-279a10b5-9d8b-4231-8405-be7bc7ec2d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658868266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2658868266
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1840704880
Short name T143
Test name
Test status
Simulation time 9141377790 ps
CPU time 23.62 seconds
Started Jul 18 06:54:01 PM PDT 24
Finished Jul 18 06:54:33 PM PDT 24
Peak memory 200140 kb
Host smart-da384bd4-2f95-4540-af39-2cf9de8846db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840704880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1840704880
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2552878760
Short name T1053
Test name
Test status
Simulation time 80755610763 ps
CPU time 32.77 seconds
Started Jul 18 06:54:04 PM PDT 24
Finished Jul 18 06:54:45 PM PDT 24
Peak memory 200008 kb
Host smart-90c084bb-5fb6-4aab-b3f5-e4b6b0852657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552878760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2552878760
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1975478025
Short name T873
Test name
Test status
Simulation time 34802350018 ps
CPU time 50.59 seconds
Started Jul 18 06:53:54 PM PDT 24
Finished Jul 18 06:54:47 PM PDT 24
Peak memory 200204 kb
Host smart-a960ce8e-8db6-4888-82fc-343f27753144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975478025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1975478025
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1337094854
Short name T661
Test name
Test status
Simulation time 94105685429 ps
CPU time 113.69 seconds
Started Jul 18 06:54:00 PM PDT 24
Finished Jul 18 06:56:00 PM PDT 24
Peak memory 200188 kb
Host smart-ced4be1b-5e17-4228-80f2-c0cf922d7574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337094854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1337094854
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.19248104
Short name T212
Test name
Test status
Simulation time 84816062325 ps
CPU time 54.86 seconds
Started Jul 18 06:53:56 PM PDT 24
Finished Jul 18 06:54:53 PM PDT 24
Peak memory 200096 kb
Host smart-4ab28a8a-52b9-4dab-ac21-a1551b696ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19248104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.19248104
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.4226178015
Short name T13
Test name
Test status
Simulation time 82589901870 ps
CPU time 29.48 seconds
Started Jul 18 06:54:00 PM PDT 24
Finished Jul 18 06:54:36 PM PDT 24
Peak memory 200104 kb
Host smart-8b2f00de-ddfb-44ba-9394-284a1932f720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226178015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.4226178015
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2757203594
Short name T130
Test name
Test status
Simulation time 269953592524 ps
CPU time 110.71 seconds
Started Jul 18 06:54:02 PM PDT 24
Finished Jul 18 06:56:01 PM PDT 24
Peak memory 200204 kb
Host smart-79e14fcd-feae-4d43-855b-efdc5ea6a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757203594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2757203594
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.337776100
Short name T917
Test name
Test status
Simulation time 19865604 ps
CPU time 0.55 seconds
Started Jul 18 06:49:05 PM PDT 24
Finished Jul 18 06:49:08 PM PDT 24
Peak memory 195584 kb
Host smart-fb6a2cdd-a1cb-42e8-8b02-1b5bc818c665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337776100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.337776100
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.961480395
Short name T1050
Test name
Test status
Simulation time 110687939924 ps
CPU time 84.09 seconds
Started Jul 18 06:49:09 PM PDT 24
Finished Jul 18 06:50:36 PM PDT 24
Peak memory 200176 kb
Host smart-7f34d560-7d61-4116-8119-ea6811a82e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961480395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.961480395
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.4294826921
Short name T547
Test name
Test status
Simulation time 92248158074 ps
CPU time 37.32 seconds
Started Jul 18 06:49:07 PM PDT 24
Finished Jul 18 06:49:47 PM PDT 24
Peak memory 200188 kb
Host smart-87bd7372-2334-4c72-a550-98ca874e597e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294826921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.4294826921
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1532179637
Short name T567
Test name
Test status
Simulation time 110481589760 ps
CPU time 162.48 seconds
Started Jul 18 06:49:07 PM PDT 24
Finished Jul 18 06:51:52 PM PDT 24
Peak memory 200180 kb
Host smart-5c6c96be-2394-420c-909d-79f6f0885b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532179637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1532179637
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.233104615
Short name T388
Test name
Test status
Simulation time 39724483961 ps
CPU time 59.22 seconds
Started Jul 18 06:49:09 PM PDT 24
Finished Jul 18 06:50:11 PM PDT 24
Peak memory 200172 kb
Host smart-7a9b03b5-06f9-461f-aac8-81616d38a834
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233104615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.233104615
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.504630339
Short name T358
Test name
Test status
Simulation time 192325809963 ps
CPU time 494.55 seconds
Started Jul 18 06:49:09 PM PDT 24
Finished Jul 18 06:57:27 PM PDT 24
Peak memory 200216 kb
Host smart-07710a94-dfeb-4ec5-b54f-5dbc29182e8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=504630339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.504630339
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.4080726402
Short name T25
Test name
Test status
Simulation time 6356402959 ps
CPU time 4.84 seconds
Started Jul 18 06:49:10 PM PDT 24
Finished Jul 18 06:49:18 PM PDT 24
Peak memory 199992 kb
Host smart-ed2e3062-4412-478e-82cf-5b69ded7b688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080726402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.4080726402
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.4027079604
Short name T431
Test name
Test status
Simulation time 65281688283 ps
CPU time 27.45 seconds
Started Jul 18 06:49:09 PM PDT 24
Finished Jul 18 06:49:40 PM PDT 24
Peak memory 207904 kb
Host smart-3950f3f0-8bac-42b6-acb1-efe4ebe9fc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027079604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4027079604
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2454093384
Short name T4
Test name
Test status
Simulation time 19357088190 ps
CPU time 1023.44 seconds
Started Jul 18 06:49:09 PM PDT 24
Finished Jul 18 07:06:16 PM PDT 24
Peak memory 200208 kb
Host smart-dd361f51-1861-44a5-9455-226c63ec0986
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454093384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2454093384
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2729985172
Short name T426
Test name
Test status
Simulation time 7764095437 ps
CPU time 69.82 seconds
Started Jul 18 06:49:10 PM PDT 24
Finished Jul 18 06:50:23 PM PDT 24
Peak memory 199488 kb
Host smart-c7497ef2-17b0-457a-83b8-e0921fc297ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2729985172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2729985172
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3301621052
Short name T155
Test name
Test status
Simulation time 94894576085 ps
CPU time 94.83 seconds
Started Jul 18 06:49:10 PM PDT 24
Finished Jul 18 06:50:48 PM PDT 24
Peak memory 199876 kb
Host smart-3028989d-e065-4e47-b317-16bf710bcdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301621052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3301621052
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.151911965
Short name T447
Test name
Test status
Simulation time 42119752760 ps
CPU time 58.81 seconds
Started Jul 18 06:49:10 PM PDT 24
Finished Jul 18 06:50:12 PM PDT 24
Peak memory 196116 kb
Host smart-c7eb8f3d-a829-4ecc-856e-3bc48077295b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151911965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.151911965
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.4173004448
Short name T1144
Test name
Test status
Simulation time 712698955 ps
CPU time 1.81 seconds
Started Jul 18 06:49:06 PM PDT 24
Finished Jul 18 06:49:10 PM PDT 24
Peak memory 199908 kb
Host smart-a7af0335-8b50-4a89-8f04-e5af1204c164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173004448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.4173004448
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3701541580
Short name T831
Test name
Test status
Simulation time 161331215208 ps
CPU time 723.47 seconds
Started Jul 18 06:49:08 PM PDT 24
Finished Jul 18 07:01:15 PM PDT 24
Peak memory 225012 kb
Host smart-62ba90bc-f635-4cfd-a655-8f5b8516af00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701541580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3701541580
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.210399895
Short name T1077
Test name
Test status
Simulation time 1757171457 ps
CPU time 1.87 seconds
Started Jul 18 06:49:10 PM PDT 24
Finished Jul 18 06:49:15 PM PDT 24
Peak memory 198936 kb
Host smart-daaf2da8-fe1c-42f3-9ee4-2f9838df9d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210399895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.210399895
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1799552355
Short name T429
Test name
Test status
Simulation time 17559004327 ps
CPU time 17.61 seconds
Started Jul 18 06:49:08 PM PDT 24
Finished Jul 18 06:49:29 PM PDT 24
Peak memory 200192 kb
Host smart-be570ee9-8b97-49ef-85df-080e5fc2a4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799552355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1799552355
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.105731769
Short name T5
Test name
Test status
Simulation time 450518563559 ps
CPU time 47.86 seconds
Started Jul 18 06:53:56 PM PDT 24
Finished Jul 18 06:54:47 PM PDT 24
Peak memory 200100 kb
Host smart-b1064970-27b9-4a08-9a09-4ab2a6958b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105731769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.105731769
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3626406984
Short name T224
Test name
Test status
Simulation time 90519529639 ps
CPU time 36.36 seconds
Started Jul 18 06:54:04 PM PDT 24
Finished Jul 18 06:54:48 PM PDT 24
Peak memory 200320 kb
Host smart-12e3630d-bcee-41c7-98c0-dca18a0b616b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626406984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3626406984
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2821976295
Short name T245
Test name
Test status
Simulation time 17911240451 ps
CPU time 29.67 seconds
Started Jul 18 06:54:04 PM PDT 24
Finished Jul 18 06:54:42 PM PDT 24
Peak memory 200376 kb
Host smart-507f0b82-dfd3-45c1-b170-ac5dc6151202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821976295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2821976295
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3486403028
Short name T486
Test name
Test status
Simulation time 72386375045 ps
CPU time 233.64 seconds
Started Jul 18 06:54:03 PM PDT 24
Finished Jul 18 06:58:05 PM PDT 24
Peak memory 200100 kb
Host smart-0d2e94a0-3f5b-4a74-aa4a-6e3237da75ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486403028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3486403028
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3038940835
Short name T935
Test name
Test status
Simulation time 48569771279 ps
CPU time 22.02 seconds
Started Jul 18 06:53:57 PM PDT 24
Finished Jul 18 06:54:23 PM PDT 24
Peak memory 200100 kb
Host smart-ed095d0e-21ef-41e5-933f-2fb40519a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038940835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3038940835
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.4160867247
Short name T646
Test name
Test status
Simulation time 22757265363 ps
CPU time 14.57 seconds
Started Jul 18 06:54:05 PM PDT 24
Finished Jul 18 06:54:27 PM PDT 24
Peak memory 200132 kb
Host smart-cc97448e-c26a-467f-a4e1-e489da812c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160867247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.4160867247
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.576103800
Short name T239
Test name
Test status
Simulation time 116042960297 ps
CPU time 56.78 seconds
Started Jul 18 06:53:57 PM PDT 24
Finished Jul 18 06:54:57 PM PDT 24
Peak memory 200204 kb
Host smart-d62a0f55-1cfb-4a95-87fc-385edebd4dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576103800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.576103800
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.872628360
Short name T450
Test name
Test status
Simulation time 130681199503 ps
CPU time 166.56 seconds
Started Jul 18 06:54:04 PM PDT 24
Finished Jul 18 06:56:59 PM PDT 24
Peak memory 200040 kb
Host smart-2202673a-f635-4281-92c9-4d272d335ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872628360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.872628360
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1613298453
Short name T519
Test name
Test status
Simulation time 56376897948 ps
CPU time 15.36 seconds
Started Jul 18 06:53:57 PM PDT 24
Finished Jul 18 06:54:16 PM PDT 24
Peak memory 199960 kb
Host smart-97d0759f-f2ae-4303-a5d0-c1e62f984db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613298453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1613298453
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3892782826
Short name T638
Test name
Test status
Simulation time 41729881 ps
CPU time 0.6 seconds
Started Jul 18 06:49:11 PM PDT 24
Finished Jul 18 06:49:15 PM PDT 24
Peak memory 195868 kb
Host smart-7b3496fc-cd52-45f3-a37f-8d75c426444c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892782826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3892782826
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1249735373
Short name T387
Test name
Test status
Simulation time 19197412999 ps
CPU time 37.07 seconds
Started Jul 18 06:49:09 PM PDT 24
Finished Jul 18 06:49:49 PM PDT 24
Peak memory 199736 kb
Host smart-c17560d7-284b-469c-a9cd-6d56701ff27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249735373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1249735373
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1253364655
Short name T606
Test name
Test status
Simulation time 130635037800 ps
CPU time 95.09 seconds
Started Jul 18 06:49:11 PM PDT 24
Finished Jul 18 06:50:49 PM PDT 24
Peak memory 200196 kb
Host smart-10799c85-95e4-4ff4-ac14-78bfb3831630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253364655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1253364655
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1138502776
Short name T47
Test name
Test status
Simulation time 30261779437 ps
CPU time 20.46 seconds
Started Jul 18 06:49:09 PM PDT 24
Finished Jul 18 06:49:33 PM PDT 24
Peak memory 200036 kb
Host smart-72931c4b-2b77-48eb-b1fe-db47ab586233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138502776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1138502776
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3446380563
Short name T871
Test name
Test status
Simulation time 30709322558 ps
CPU time 14.91 seconds
Started Jul 18 06:49:09 PM PDT 24
Finished Jul 18 06:49:27 PM PDT 24
Peak memory 200168 kb
Host smart-9ccc3c98-da70-449a-93dd-897316349c5f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446380563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3446380563
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3141300249
Short name T562
Test name
Test status
Simulation time 197094043331 ps
CPU time 592.23 seconds
Started Jul 18 06:49:08 PM PDT 24
Finished Jul 18 06:59:04 PM PDT 24
Peak memory 200184 kb
Host smart-12eafca3-d753-45a2-9cdd-48e893ffda06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141300249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3141300249
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2975180589
Short name T662
Test name
Test status
Simulation time 9904157755 ps
CPU time 3.5 seconds
Started Jul 18 06:49:08 PM PDT 24
Finished Jul 18 06:49:15 PM PDT 24
Peak memory 199892 kb
Host smart-d6ddfc06-1ab7-42de-8036-9e9e77c7877c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975180589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2975180589
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.908904544
Short name T1087
Test name
Test status
Simulation time 88492409377 ps
CPU time 83.2 seconds
Started Jul 18 06:49:08 PM PDT 24
Finished Jul 18 06:50:34 PM PDT 24
Peak memory 208528 kb
Host smart-7e89ef90-b8d3-4852-9d93-54e4f7c19945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908904544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.908904544
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.300615042
Short name T821
Test name
Test status
Simulation time 21284949527 ps
CPU time 151.76 seconds
Started Jul 18 06:49:08 PM PDT 24
Finished Jul 18 06:51:43 PM PDT 24
Peak memory 200192 kb
Host smart-969644d1-4925-4da7-b8d7-27672144e42a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300615042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.300615042
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.4115778076
Short name T478
Test name
Test status
Simulation time 6572017584 ps
CPU time 60.6 seconds
Started Jul 18 06:49:07 PM PDT 24
Finished Jul 18 06:50:09 PM PDT 24
Peak memory 198336 kb
Host smart-5eb98a7d-a6d4-44e9-98a7-0e645f1b29c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115778076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.4115778076
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1270872330
Short name T261
Test name
Test status
Simulation time 300279371285 ps
CPU time 316.53 seconds
Started Jul 18 06:49:09 PM PDT 24
Finished Jul 18 06:54:29 PM PDT 24
Peak memory 200196 kb
Host smart-7cf774cc-42ef-44df-bbd0-2bec65273c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270872330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1270872330
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.4143979533
Short name T281
Test name
Test status
Simulation time 3097625125 ps
CPU time 3.24 seconds
Started Jul 18 06:49:08 PM PDT 24
Finished Jul 18 06:49:15 PM PDT 24
Peak memory 196104 kb
Host smart-9058e7a9-c2a2-4118-82c0-b09090cfbec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143979533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.4143979533
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1275168744
Short name T841
Test name
Test status
Simulation time 270758462 ps
CPU time 1.36 seconds
Started Jul 18 06:49:11 PM PDT 24
Finished Jul 18 06:49:15 PM PDT 24
Peak memory 198452 kb
Host smart-5a211448-d28a-4f68-816f-8a97a453f0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275168744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1275168744
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.4115182886
Short name T813
Test name
Test status
Simulation time 32687810587 ps
CPU time 1291.58 seconds
Started Jul 18 06:49:08 PM PDT 24
Finished Jul 18 07:10:44 PM PDT 24
Peak memory 200168 kb
Host smart-20b7ad27-d98d-4a70-8554-778a9ca156b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115182886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.4115182886
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.4038830754
Short name T140
Test name
Test status
Simulation time 36313373720 ps
CPU time 181.81 seconds
Started Jul 18 06:49:09 PM PDT 24
Finished Jul 18 06:52:15 PM PDT 24
Peak memory 208508 kb
Host smart-ec5a64c9-40ee-40e2-878f-c1c8097f3c31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038830754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.4038830754
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.4130817987
Short name T706
Test name
Test status
Simulation time 1582170813 ps
CPU time 2.34 seconds
Started Jul 18 06:49:10 PM PDT 24
Finished Jul 18 06:49:16 PM PDT 24
Peak memory 198668 kb
Host smart-ba0e70c5-57fb-4cac-84f8-e851866522c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130817987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.4130817987
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2065800010
Short name T688
Test name
Test status
Simulation time 96483008959 ps
CPU time 65.9 seconds
Started Jul 18 06:49:10 PM PDT 24
Finished Jul 18 06:50:19 PM PDT 24
Peak memory 200108 kb
Host smart-fa1a02c4-1613-4676-9a0a-c7881376938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065800010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2065800010
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2607522078
Short name T234
Test name
Test status
Simulation time 83808257715 ps
CPU time 36.28 seconds
Started Jul 18 06:53:58 PM PDT 24
Finished Jul 18 06:54:39 PM PDT 24
Peak memory 200180 kb
Host smart-38c7eccb-96fa-4c22-9576-b87ab6f10538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607522078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2607522078
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1059053159
Short name T206
Test name
Test status
Simulation time 102827032049 ps
CPU time 148.16 seconds
Started Jul 18 06:53:57 PM PDT 24
Finished Jul 18 06:56:29 PM PDT 24
Peak memory 199952 kb
Host smart-2b64a133-0e5d-4135-b93e-a64a6b08a7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059053159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1059053159
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3921389698
Short name T187
Test name
Test status
Simulation time 28570086722 ps
CPU time 11.46 seconds
Started Jul 18 06:54:04 PM PDT 24
Finished Jul 18 06:54:23 PM PDT 24
Peak memory 200084 kb
Host smart-85a5dd35-9b32-4830-95a0-af08c40f78a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921389698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3921389698
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.150419361
Short name T762
Test name
Test status
Simulation time 72843860249 ps
CPU time 95.71 seconds
Started Jul 18 06:54:00 PM PDT 24
Finished Jul 18 06:55:42 PM PDT 24
Peak memory 200096 kb
Host smart-9c10df8b-6eac-406c-9e30-141d6ad80bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150419361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.150419361
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.4183461419
Short name T737
Test name
Test status
Simulation time 288631534806 ps
CPU time 69.6 seconds
Started Jul 18 06:53:59 PM PDT 24
Finished Jul 18 06:55:12 PM PDT 24
Peak memory 200176 kb
Host smart-0513d17d-e787-4263-8254-c1e3f9a60914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183461419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.4183461419
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.4140569333
Short name T974
Test name
Test status
Simulation time 82975622715 ps
CPU time 63.81 seconds
Started Jul 18 06:54:03 PM PDT 24
Finished Jul 18 06:55:15 PM PDT 24
Peak memory 200100 kb
Host smart-9610039a-afc1-4764-bf06-a0e3d3c74487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140569333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.4140569333
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1403463999
Short name T231
Test name
Test status
Simulation time 42050285456 ps
CPU time 66.23 seconds
Started Jul 18 06:53:55 PM PDT 24
Finished Jul 18 06:55:04 PM PDT 24
Peak memory 200172 kb
Host smart-ae16cafe-b355-4987-99db-834e8af50ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403463999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1403463999
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1634208037
Short name T238
Test name
Test status
Simulation time 115539682878 ps
CPU time 50.35 seconds
Started Jul 18 06:53:56 PM PDT 24
Finished Jul 18 06:54:49 PM PDT 24
Peak memory 200112 kb
Host smart-c8a6dfbd-2859-4fc3-a3bc-07f676f50782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634208037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1634208037
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3537864390
Short name T361
Test name
Test status
Simulation time 40522025 ps
CPU time 0.59 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:49:29 PM PDT 24
Peak memory 195572 kb
Host smart-da1fbfd8-96d5-453f-b484-00c8ff0790ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537864390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3537864390
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3146086447
Short name T668
Test name
Test status
Simulation time 86752253142 ps
CPU time 63.3 seconds
Started Jul 18 06:49:23 PM PDT 24
Finished Jul 18 06:50:28 PM PDT 24
Peak memory 200160 kb
Host smart-9efdc5fe-5a29-4f0c-93ff-dc4f7ca67584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146086447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3146086447
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1016492262
Short name T774
Test name
Test status
Simulation time 19462254457 ps
CPU time 18.34 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:49:49 PM PDT 24
Peak memory 200112 kb
Host smart-530c98e8-c5a0-43b3-a1f2-bb38647281e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016492262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1016492262
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.901670199
Short name T174
Test name
Test status
Simulation time 49481131771 ps
CPU time 43.78 seconds
Started Jul 18 06:49:24 PM PDT 24
Finished Jul 18 06:50:11 PM PDT 24
Peak memory 200188 kb
Host smart-4173fc9d-fb8b-4e1a-bf4b-d9cc46c51a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901670199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.901670199
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.798847809
Short name T909
Test name
Test status
Simulation time 13534904389 ps
CPU time 6.76 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:49:36 PM PDT 24
Peak memory 199708 kb
Host smart-083d0fd8-73db-467a-b28c-34bcf3b20658
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798847809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.798847809
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.4162665921
Short name T698
Test name
Test status
Simulation time 153800300571 ps
CPU time 468.76 seconds
Started Jul 18 06:49:23 PM PDT 24
Finished Jul 18 06:57:14 PM PDT 24
Peak memory 200180 kb
Host smart-0051b6d5-6c18-4b10-8f3a-e2c1499e3a03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4162665921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4162665921
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.399403289
Short name T1131
Test name
Test status
Simulation time 2802741252 ps
CPU time 2.54 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:49:33 PM PDT 24
Peak memory 199824 kb
Host smart-1f444b50-9bfc-4ecd-ad82-eabcd743967a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399403289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.399403289
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.798839139
Short name T300
Test name
Test status
Simulation time 25293394128 ps
CPU time 41.03 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:50:09 PM PDT 24
Peak memory 208412 kb
Host smart-fec091ad-4aed-4e28-960c-ef6681f00955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798839139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.798839139
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.336826212
Short name T544
Test name
Test status
Simulation time 26750287976 ps
CPU time 1603.78 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 07:16:13 PM PDT 24
Peak memory 200156 kb
Host smart-45cdd58e-6540-434b-87ac-bbe4655bc7e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=336826212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.336826212
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.670177967
Short name T1072
Test name
Test status
Simulation time 4212861523 ps
CPU time 33.84 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:50:02 PM PDT 24
Peak memory 198168 kb
Host smart-1d7297d3-50ee-49e0-8a6c-4cdb9651a45a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670177967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.670177967
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.309310436
Short name T1061
Test name
Test status
Simulation time 125740095792 ps
CPU time 17.34 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:49:46 PM PDT 24
Peak memory 199928 kb
Host smart-75bc2063-1e16-407e-9326-83fcda944b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309310436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.309310436
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3378010553
Short name T924
Test name
Test status
Simulation time 33015770460 ps
CPU time 44.69 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:50:13 PM PDT 24
Peak memory 196376 kb
Host smart-4c6c6aa8-6e87-4590-b619-0c1058b40fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378010553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3378010553
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2407874265
Short name T626
Test name
Test status
Simulation time 283679037 ps
CPU time 1.82 seconds
Started Jul 18 06:49:09 PM PDT 24
Finished Jul 18 06:49:15 PM PDT 24
Peak memory 200180 kb
Host smart-27a30f9a-22d1-414c-865d-6fce9f77384e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407874265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2407874265
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.368645342
Short name T918
Test name
Test status
Simulation time 157503824410 ps
CPU time 198.57 seconds
Started Jul 18 06:49:27 PM PDT 24
Finished Jul 18 06:52:49 PM PDT 24
Peak memory 200172 kb
Host smart-fff7283d-2404-4357-839d-923a707e55f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368645342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.368645342
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3435717988
Short name T59
Test name
Test status
Simulation time 102721017911 ps
CPU time 502.7 seconds
Started Jul 18 06:49:24 PM PDT 24
Finished Jul 18 06:57:50 PM PDT 24
Peak memory 216728 kb
Host smart-80148304-2498-401e-b308-2022b5d24259
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435717988 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3435717988
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2863516770
Short name T892
Test name
Test status
Simulation time 5185939484 ps
CPU time 1.73 seconds
Started Jul 18 06:49:31 PM PDT 24
Finished Jul 18 06:49:35 PM PDT 24
Peak memory 198908 kb
Host smart-c155d66e-0887-4327-aec6-b2f218ca16cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863516770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2863516770
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1907355164
Short name T1147
Test name
Test status
Simulation time 104702230192 ps
CPU time 72.53 seconds
Started Jul 18 06:49:24 PM PDT 24
Finished Jul 18 06:50:39 PM PDT 24
Peak memory 200212 kb
Host smart-3af3812e-842b-4917-aaf9-c62b9a682044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907355164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1907355164
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1313442606
Short name T904
Test name
Test status
Simulation time 81941755667 ps
CPU time 64.95 seconds
Started Jul 18 06:54:02 PM PDT 24
Finished Jul 18 06:55:15 PM PDT 24
Peak memory 200092 kb
Host smart-34872211-80d0-48bf-b7bf-78a49c9f9c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313442606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1313442606
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1576630525
Short name T975
Test name
Test status
Simulation time 16938288465 ps
CPU time 12.44 seconds
Started Jul 18 06:54:05 PM PDT 24
Finished Jul 18 06:54:25 PM PDT 24
Peak memory 200204 kb
Host smart-38fddbe8-a5b5-4108-ba0d-dba6d8685db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576630525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1576630525
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3495899946
Short name T210
Test name
Test status
Simulation time 77175236483 ps
CPU time 32.66 seconds
Started Jul 18 06:54:04 PM PDT 24
Finished Jul 18 06:54:45 PM PDT 24
Peak memory 200192 kb
Host smart-00cf361a-25ab-4e77-a522-6b61a54dbca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495899946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3495899946
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1249964866
Short name T811
Test name
Test status
Simulation time 61173101604 ps
CPU time 58.03 seconds
Started Jul 18 06:54:04 PM PDT 24
Finished Jul 18 06:55:10 PM PDT 24
Peak memory 200132 kb
Host smart-25d6f193-4d6e-4a70-a3fd-fec858092601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249964866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1249964866
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.4249959386
Short name T228
Test name
Test status
Simulation time 45244018022 ps
CPU time 23.76 seconds
Started Jul 18 06:54:03 PM PDT 24
Finished Jul 18 06:54:34 PM PDT 24
Peak memory 200204 kb
Host smart-59bcf040-a814-47b5-90e4-ce6d9ad0807d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249959386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.4249959386
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.4276695685
Short name T611
Test name
Test status
Simulation time 24351346376 ps
CPU time 36.8 seconds
Started Jul 18 06:54:02 PM PDT 24
Finished Jul 18 06:54:47 PM PDT 24
Peak memory 200084 kb
Host smart-57adab78-7eb4-4d26-b032-ba93a90ba268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276695685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.4276695685
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2295982601
Short name T1171
Test name
Test status
Simulation time 19723883418 ps
CPU time 10.96 seconds
Started Jul 18 06:54:02 PM PDT 24
Finished Jul 18 06:54:20 PM PDT 24
Peak memory 200188 kb
Host smart-3cc7c665-b40a-47d0-9c03-786a34525d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295982601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2295982601
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.602712921
Short name T201
Test name
Test status
Simulation time 154679223376 ps
CPU time 261.87 seconds
Started Jul 18 06:54:05 PM PDT 24
Finished Jul 18 06:58:35 PM PDT 24
Peak memory 200144 kb
Host smart-c443027d-8094-4829-a293-b12369bae4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602712921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.602712921
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.329994856
Short name T164
Test name
Test status
Simulation time 37432935650 ps
CPU time 19.06 seconds
Started Jul 18 06:54:02 PM PDT 24
Finished Jul 18 06:54:29 PM PDT 24
Peak memory 200240 kb
Host smart-6162ae88-f03f-40e5-ab0d-32cf520d80d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329994856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.329994856
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3238168811
Short name T704
Test name
Test status
Simulation time 48709469768 ps
CPU time 76.72 seconds
Started Jul 18 06:54:04 PM PDT 24
Finished Jul 18 06:55:29 PM PDT 24
Peak memory 200180 kb
Host smart-31a8d804-bea8-46c0-9e6e-4a284ddadb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238168811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3238168811
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.614305791
Short name T596
Test name
Test status
Simulation time 13538544 ps
CPU time 0.57 seconds
Started Jul 18 06:49:24 PM PDT 24
Finished Jul 18 06:49:26 PM PDT 24
Peak memory 195564 kb
Host smart-fcdb5669-979b-48a4-8557-e0bbaa35c79b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614305791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.614305791
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.211776782
Short name T825
Test name
Test status
Simulation time 116712438704 ps
CPU time 201.83 seconds
Started Jul 18 06:49:23 PM PDT 24
Finished Jul 18 06:52:46 PM PDT 24
Peak memory 200184 kb
Host smart-9350942c-ddc3-4ab0-86ab-4b99cec9fe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211776782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.211776782
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1448288923
Short name T1079
Test name
Test status
Simulation time 306948492001 ps
CPU time 33.48 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:50:02 PM PDT 24
Peak memory 200196 kb
Host smart-33338bf7-8990-42d1-917b-336f32845400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448288923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1448288923
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3592064792
Short name T202
Test name
Test status
Simulation time 131000012573 ps
CPU time 92.59 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:51:02 PM PDT 24
Peak memory 200172 kb
Host smart-a24aa7d5-b036-444f-8a83-f1838f31ad7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592064792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3592064792
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.209618785
Short name T679
Test name
Test status
Simulation time 9910485905 ps
CPU time 1.72 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:49:31 PM PDT 24
Peak memory 196964 kb
Host smart-4ff07486-9ad3-4a83-8421-e3eb53da59e0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209618785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.209618785
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2617995776
Short name T629
Test name
Test status
Simulation time 181187788389 ps
CPU time 382.56 seconds
Started Jul 18 06:49:24 PM PDT 24
Finished Jul 18 06:55:48 PM PDT 24
Peak memory 200112 kb
Host smart-8de33c91-cef3-4548-993a-f9689a76853c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617995776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2617995776
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3720704830
Short name T696
Test name
Test status
Simulation time 4933097168 ps
CPU time 4.74 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:49:34 PM PDT 24
Peak memory 198844 kb
Host smart-d6ebacac-ae61-4e9e-b959-c3bf25a3edc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720704830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3720704830
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1775455659
Short name T987
Test name
Test status
Simulation time 165898747786 ps
CPU time 36.42 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:50:07 PM PDT 24
Peak memory 200276 kb
Host smart-459567b0-8342-442a-8228-a5a64d9456fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775455659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1775455659
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3370031010
Short name T997
Test name
Test status
Simulation time 9565955248 ps
CPU time 276.1 seconds
Started Jul 18 06:49:24 PM PDT 24
Finished Jul 18 06:54:03 PM PDT 24
Peak memory 200248 kb
Host smart-6c48e205-de96-4b09-95b8-9ce213e06dd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370031010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3370031010
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1844036982
Short name T548
Test name
Test status
Simulation time 4626586855 ps
CPU time 36.87 seconds
Started Jul 18 06:49:28 PM PDT 24
Finished Jul 18 06:50:09 PM PDT 24
Peak memory 199492 kb
Host smart-20e7535f-a95e-49fc-960f-9b7736597e6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844036982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1844036982
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.232736969
Short name T156
Test name
Test status
Simulation time 130534696374 ps
CPU time 66.84 seconds
Started Jul 18 06:49:24 PM PDT 24
Finished Jul 18 06:50:33 PM PDT 24
Peak memory 200204 kb
Host smart-00b6defa-2a45-42f5-b9e2-fc043dc5420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232736969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.232736969
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3478679041
Short name T1148
Test name
Test status
Simulation time 36947885257 ps
CPU time 14.54 seconds
Started Jul 18 06:49:23 PM PDT 24
Finished Jul 18 06:49:39 PM PDT 24
Peak memory 196684 kb
Host smart-3dc14a87-d28b-4e3e-98cf-c668a98e3d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478679041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3478679041
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.46118596
Short name T564
Test name
Test status
Simulation time 5764715610 ps
CPU time 5.3 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:49:36 PM PDT 24
Peak memory 199664 kb
Host smart-2cd42631-32dd-4a28-8f03-38bf534c514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46118596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.46118596
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3817965987
Short name T1070
Test name
Test status
Simulation time 70614189821 ps
CPU time 207.17 seconds
Started Jul 18 06:49:22 PM PDT 24
Finished Jul 18 06:52:50 PM PDT 24
Peak memory 216804 kb
Host smart-bb8b2e15-47ca-467e-a354-e86b457e50e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817965987 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3817965987
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1197197303
Short name T908
Test name
Test status
Simulation time 7388072352 ps
CPU time 9.4 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:49:37 PM PDT 24
Peak memory 200184 kb
Host smart-ff25c759-20f8-49a7-af17-bac8262d9a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197197303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1197197303
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3671237726
Short name T440
Test name
Test status
Simulation time 122704311761 ps
CPU time 16.49 seconds
Started Jul 18 06:49:22 PM PDT 24
Finished Jul 18 06:49:40 PM PDT 24
Peak memory 200140 kb
Host smart-f6c7a932-78b3-4f5c-b1d9-e35ff50167b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671237726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3671237726
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.4164249986
Short name T229
Test name
Test status
Simulation time 66019880690 ps
CPU time 190.68 seconds
Started Jul 18 06:54:05 PM PDT 24
Finished Jul 18 06:57:23 PM PDT 24
Peak memory 200196 kb
Host smart-3806efff-1974-4ded-9611-9cc761ac1151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164249986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.4164249986
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1867862106
Short name T251
Test name
Test status
Simulation time 45789579304 ps
CPU time 36.37 seconds
Started Jul 18 06:54:05 PM PDT 24
Finished Jul 18 06:54:49 PM PDT 24
Peak memory 199788 kb
Host smart-d350f9ec-bec8-46ae-a4ad-9e229e27903d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867862106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1867862106
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1721415039
Short name T597
Test name
Test status
Simulation time 44676247294 ps
CPU time 34.16 seconds
Started Jul 18 06:54:04 PM PDT 24
Finished Jul 18 06:54:46 PM PDT 24
Peak memory 200136 kb
Host smart-b39ccdc0-f52d-4b00-9fb1-02625743ca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721415039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1721415039
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.293309241
Short name T439
Test name
Test status
Simulation time 25985746688 ps
CPU time 22.4 seconds
Started Jul 18 06:54:16 PM PDT 24
Finished Jul 18 06:54:48 PM PDT 24
Peak memory 200192 kb
Host smart-8010b5de-cc7e-449b-9d2f-7389dcd8cd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293309241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.293309241
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2788163195
Short name T384
Test name
Test status
Simulation time 12931228499 ps
CPU time 19.73 seconds
Started Jul 18 06:54:16 PM PDT 24
Finished Jul 18 06:54:46 PM PDT 24
Peak memory 200200 kb
Host smart-771401db-deb8-4320-a80d-07ed6574401b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788163195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2788163195
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3832088958
Short name T558
Test name
Test status
Simulation time 32309007967 ps
CPU time 52.74 seconds
Started Jul 18 06:54:10 PM PDT 24
Finished Jul 18 06:55:11 PM PDT 24
Peak memory 200120 kb
Host smart-6b41b53d-6ed7-4845-a1e9-16106c6a2649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832088958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3832088958
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3458662754
Short name T230
Test name
Test status
Simulation time 38904183558 ps
CPU time 37.39 seconds
Started Jul 18 06:54:16 PM PDT 24
Finished Jul 18 06:55:03 PM PDT 24
Peak memory 200280 kb
Host smart-83ac59e3-4fc0-4544-ad7d-ad7e7d27d08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458662754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3458662754
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.897341837
Short name T215
Test name
Test status
Simulation time 131945844202 ps
CPU time 192.87 seconds
Started Jul 18 06:54:12 PM PDT 24
Finished Jul 18 06:57:33 PM PDT 24
Peak memory 199816 kb
Host smart-5cea0943-62d2-424c-8bdd-ba228cb1820a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897341837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.897341837
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1495628954
Short name T715
Test name
Test status
Simulation time 173522576666 ps
CPU time 53.09 seconds
Started Jul 18 06:54:13 PM PDT 24
Finished Jul 18 06:55:14 PM PDT 24
Peak memory 200176 kb
Host smart-2ba30362-d588-4551-a4f5-848d47fbb948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495628954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1495628954
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3866923951
Short name T1000
Test name
Test status
Simulation time 78449050895 ps
CPU time 100.96 seconds
Started Jul 18 06:54:08 PM PDT 24
Finished Jul 18 06:55:57 PM PDT 24
Peak memory 200188 kb
Host smart-b017cd59-cc9c-4eb2-9590-57cc1a1b046c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866923951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3866923951
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3684879370
Short name T618
Test name
Test status
Simulation time 28486716 ps
CPU time 0.55 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:49:31 PM PDT 24
Peak memory 195584 kb
Host smart-71de960b-0c7d-4902-81a4-c3f9718d64ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684879370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3684879370
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.4261991560
Short name T613
Test name
Test status
Simulation time 52319475837 ps
CPU time 44.12 seconds
Started Jul 18 06:49:27 PM PDT 24
Finished Jul 18 06:50:15 PM PDT 24
Peak memory 200132 kb
Host smart-23c1f88d-ef93-4945-8615-3d1b0e0f1f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261991560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.4261991560
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.4255690079
Short name T403
Test name
Test status
Simulation time 141723571996 ps
CPU time 91.28 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:51:00 PM PDT 24
Peak memory 200180 kb
Host smart-90e33663-e55f-40d5-99e7-5e996139549c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255690079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.4255690079
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2574774035
Short name T967
Test name
Test status
Simulation time 56214710248 ps
CPU time 46.79 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:50:16 PM PDT 24
Peak memory 200076 kb
Host smart-8bdfb480-3cb0-4b59-9629-897df40c7355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574774035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2574774035
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.329896603
Short name T1173
Test name
Test status
Simulation time 273136651972 ps
CPU time 421.56 seconds
Started Jul 18 06:49:23 PM PDT 24
Finished Jul 18 06:56:26 PM PDT 24
Peak memory 200308 kb
Host smart-b39a61de-0541-44f5-a6ce-4168021482b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329896603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.329896603
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1068296516
Short name T1112
Test name
Test status
Simulation time 50086370544 ps
CPU time 374.57 seconds
Started Jul 18 06:49:29 PM PDT 24
Finished Jul 18 06:55:47 PM PDT 24
Peak memory 200180 kb
Host smart-3d0be875-c636-4d61-97ed-9645440473f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068296516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1068296516
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1921531466
Short name T410
Test name
Test status
Simulation time 6669350058 ps
CPU time 15.11 seconds
Started Jul 18 06:49:27 PM PDT 24
Finished Jul 18 06:49:46 PM PDT 24
Peak memory 199456 kb
Host smart-50e6467d-792f-4fbb-8052-0c3ce317893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921531466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1921531466
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.585293285
Short name T850
Test name
Test status
Simulation time 49664419312 ps
CPU time 86.02 seconds
Started Jul 18 06:49:28 PM PDT 24
Finished Jul 18 06:50:58 PM PDT 24
Peak memory 200244 kb
Host smart-0e38aba7-0368-4e0d-a76c-690bdb19181e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585293285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.585293285
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2553556705
Short name T856
Test name
Test status
Simulation time 9795870918 ps
CPU time 321.25 seconds
Started Jul 18 06:49:28 PM PDT 24
Finished Jul 18 06:54:53 PM PDT 24
Peak memory 200148 kb
Host smart-d90996c6-34d1-48b8-ae51-488d0e62a369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2553556705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2553556705
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1737895359
Short name T483
Test name
Test status
Simulation time 6310982361 ps
CPU time 51.25 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:50:21 PM PDT 24
Peak memory 198996 kb
Host smart-a4871449-14b7-4a1e-a215-bd7f67cf7c24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737895359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1737895359
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3624002194
Short name T1104
Test name
Test status
Simulation time 111508852320 ps
CPU time 34.01 seconds
Started Jul 18 06:49:30 PM PDT 24
Finished Jul 18 06:50:06 PM PDT 24
Peak memory 200196 kb
Host smart-271235be-1c0c-4971-8cd8-c16d6dbc4393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624002194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3624002194
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.74715161
Short name T1064
Test name
Test status
Simulation time 69562734122 ps
CPU time 31.93 seconds
Started Jul 18 06:49:29 PM PDT 24
Finished Jul 18 06:50:04 PM PDT 24
Peak memory 196208 kb
Host smart-8f0df343-faf4-492c-b45c-131f990ebd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74715161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.74715161
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.4011517247
Short name T1011
Test name
Test status
Simulation time 571325156 ps
CPU time 1.71 seconds
Started Jul 18 06:49:24 PM PDT 24
Finished Jul 18 06:49:28 PM PDT 24
Peak memory 199016 kb
Host smart-417c269b-3974-46b0-9627-2baa2fa02f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011517247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4011517247
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1429792931
Short name T160
Test name
Test status
Simulation time 133844570802 ps
CPU time 115.13 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:51:26 PM PDT 24
Peak memory 208516 kb
Host smart-432aeb44-cca6-4e4b-bd32-36ce854c5136
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429792931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1429792931
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1829835273
Short name T503
Test name
Test status
Simulation time 16070392880 ps
CPU time 100.57 seconds
Started Jul 18 06:49:29 PM PDT 24
Finished Jul 18 06:51:13 PM PDT 24
Peak memory 209880 kb
Host smart-033285eb-0295-440f-b7c7-9b0ba6474bda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829835273 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1829835273
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2068048157
Short name T651
Test name
Test status
Simulation time 878949039 ps
CPU time 2.48 seconds
Started Jul 18 06:49:28 PM PDT 24
Finished Jul 18 06:49:34 PM PDT 24
Peak memory 198976 kb
Host smart-0dd69cc4-de70-4c78-8758-266335c76eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068048157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2068048157
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3688942454
Short name T884
Test name
Test status
Simulation time 76112934258 ps
CPU time 75.85 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:50:44 PM PDT 24
Peak memory 200172 kb
Host smart-7e268324-87e9-4404-a928-0cc1f9a86c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688942454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3688942454
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2563240137
Short name T194
Test name
Test status
Simulation time 104511143881 ps
CPU time 68.02 seconds
Started Jul 18 06:54:11 PM PDT 24
Finished Jul 18 06:55:27 PM PDT 24
Peak memory 200108 kb
Host smart-84c68f16-654b-4038-9192-2fef9b7ac928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563240137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2563240137
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.4072597291
Short name T216
Test name
Test status
Simulation time 51157512192 ps
CPU time 43.67 seconds
Started Jul 18 06:54:09 PM PDT 24
Finished Jul 18 06:55:00 PM PDT 24
Peak memory 200204 kb
Host smart-8148454a-4200-458c-9507-db99e81fa254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072597291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4072597291
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1590829865
Short name T260
Test name
Test status
Simulation time 91897217336 ps
CPU time 210.4 seconds
Started Jul 18 06:54:10 PM PDT 24
Finished Jul 18 06:57:48 PM PDT 24
Peak memory 200204 kb
Host smart-240d8944-5702-4ac2-ae55-1d08c6de4ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590829865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1590829865
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1790815645
Short name T756
Test name
Test status
Simulation time 69548133399 ps
CPU time 233.77 seconds
Started Jul 18 06:54:17 PM PDT 24
Finished Jul 18 06:58:20 PM PDT 24
Peak memory 200120 kb
Host smart-fb51cb26-c6b4-43a8-b7ff-838d8dc1ba58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790815645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1790815645
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.4039597335
Short name T77
Test name
Test status
Simulation time 153894869101 ps
CPU time 140.76 seconds
Started Jul 18 06:54:16 PM PDT 24
Finished Jul 18 06:56:47 PM PDT 24
Peak memory 200196 kb
Host smart-9911974f-28d8-4a7f-b939-8e9a7229732c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039597335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.4039597335
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.877011744
Short name T781
Test name
Test status
Simulation time 75471218243 ps
CPU time 201.33 seconds
Started Jul 18 06:54:17 PM PDT 24
Finished Jul 18 06:57:48 PM PDT 24
Peak memory 200200 kb
Host smart-bfbae95c-d779-4dcd-8f10-c7877c8d969a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877011744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.877011744
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2000940168
Short name T641
Test name
Test status
Simulation time 36824353820 ps
CPU time 13.58 seconds
Started Jul 18 06:54:10 PM PDT 24
Finished Jul 18 06:54:32 PM PDT 24
Peak memory 200084 kb
Host smart-4330e193-c81b-4d5d-9f18-860736f6c024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000940168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2000940168
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2017380286
Short name T315
Test name
Test status
Simulation time 22714780805 ps
CPU time 33.12 seconds
Started Jul 18 06:54:17 PM PDT 24
Finished Jul 18 06:55:00 PM PDT 24
Peak memory 200200 kb
Host smart-cd9b9533-9e7d-4caf-952a-d6986408d49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017380286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2017380286
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1057313033
Short name T649
Test name
Test status
Simulation time 17493498 ps
CPU time 0.58 seconds
Started Jul 18 06:49:41 PM PDT 24
Finished Jul 18 06:49:43 PM PDT 24
Peak memory 195564 kb
Host smart-d2510dd3-0665-4610-828a-54c0d6c97235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057313033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1057313033
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3341366159
Short name T948
Test name
Test status
Simulation time 36386073690 ps
CPU time 16.33 seconds
Started Jul 18 06:49:25 PM PDT 24
Finished Jul 18 06:49:44 PM PDT 24
Peak memory 200036 kb
Host smart-44538dbc-cea0-4706-a86a-da3b2cd72491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341366159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3341366159
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2619512814
Short name T70
Test name
Test status
Simulation time 45350494750 ps
CPU time 21.37 seconds
Started Jul 18 06:49:27 PM PDT 24
Finished Jul 18 06:49:52 PM PDT 24
Peak memory 200104 kb
Host smart-a53b3a15-f1b2-457d-8b47-405b675309b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619512814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2619512814
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3819048124
Short name T223
Test name
Test status
Simulation time 56599762436 ps
CPU time 100.66 seconds
Started Jul 18 06:49:28 PM PDT 24
Finished Jul 18 06:51:12 PM PDT 24
Peak memory 200216 kb
Host smart-5ff9cd4c-e27c-46f6-a498-173ac91c80f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819048124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3819048124
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.172341778
Short name T119
Test name
Test status
Simulation time 23967133995 ps
CPU time 17.85 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:49:48 PM PDT 24
Peak memory 197952 kb
Host smart-dcba5532-bfd2-4da5-8408-5a0d0bda4848
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172341778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.172341778
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1875454595
Short name T767
Test name
Test status
Simulation time 139889805295 ps
CPU time 761.38 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 07:02:28 PM PDT 24
Peak memory 200120 kb
Host smart-b9a552fe-1f5c-4481-bad9-b5dba78717f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1875454595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1875454595
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.24741019
Short name T995
Test name
Test status
Simulation time 8427099540 ps
CPU time 8.35 seconds
Started Jul 18 06:49:42 PM PDT 24
Finished Jul 18 06:49:53 PM PDT 24
Peak memory 200196 kb
Host smart-ce3c1bc8-6f8b-4f56-bc4c-05690e1de3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24741019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.24741019
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3491467225
Short name T462
Test name
Test status
Simulation time 112342784289 ps
CPU time 38.28 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:50:08 PM PDT 24
Peak memory 200216 kb
Host smart-24e9592f-17da-49a9-9416-c31c4977696b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491467225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3491467225
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.234967751
Short name T568
Test name
Test status
Simulation time 23938326968 ps
CPU time 166.95 seconds
Started Jul 18 06:49:42 PM PDT 24
Finished Jul 18 06:52:32 PM PDT 24
Peak memory 200208 kb
Host smart-7b776fc9-138f-420c-aea7-2d68660378e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=234967751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.234967751
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2154519682
Short name T52
Test name
Test status
Simulation time 5492547309 ps
CPU time 53.21 seconds
Started Jul 18 06:49:27 PM PDT 24
Finished Jul 18 06:50:24 PM PDT 24
Peak memory 199520 kb
Host smart-640681d5-3f60-4b40-9feb-5fcf46e42ae9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2154519682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2154519682
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1511591051
Short name T452
Test name
Test status
Simulation time 24314412861 ps
CPU time 48.09 seconds
Started Jul 18 06:49:40 PM PDT 24
Finished Jul 18 06:50:29 PM PDT 24
Peak memory 200184 kb
Host smart-615b02de-982f-404b-97b9-ceae44cee4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511591051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1511591051
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1452356430
Short name T1168
Test name
Test status
Simulation time 41689992655 ps
CPU time 4.16 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:49:34 PM PDT 24
Peak memory 196500 kb
Host smart-4ef101ae-3634-434f-a36f-1763ac20f7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452356430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1452356430
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.51213491
Short name T469
Test name
Test status
Simulation time 954935879 ps
CPU time 1.78 seconds
Started Jul 18 06:49:28 PM PDT 24
Finished Jul 18 06:49:33 PM PDT 24
Peak memory 198552 kb
Host smart-1b8ee433-7489-4890-abca-5e01d6e47b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51213491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.51213491
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2900898122
Short name T139
Test name
Test status
Simulation time 167033299025 ps
CPU time 46.92 seconds
Started Jul 18 06:49:42 PM PDT 24
Finished Jul 18 06:50:32 PM PDT 24
Peak memory 200128 kb
Host smart-d76446db-5fdf-4627-b9a3-391218841ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900898122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2900898122
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3831299460
Short name T1023
Test name
Test status
Simulation time 132855206872 ps
CPU time 433.08 seconds
Started Jul 18 06:49:53 PM PDT 24
Finished Jul 18 06:57:07 PM PDT 24
Peak memory 216692 kb
Host smart-56eea344-ac81-488a-b820-50949191c043
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831299460 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3831299460
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.4183092878
Short name T1060
Test name
Test status
Simulation time 641759611 ps
CPU time 2.44 seconds
Started Jul 18 06:49:41 PM PDT 24
Finished Jul 18 06:49:46 PM PDT 24
Peak memory 198692 kb
Host smart-26b2ae5f-f5f2-416f-a0ae-847e33db9b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183092878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.4183092878
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3213036883
Short name T896
Test name
Test status
Simulation time 69450206624 ps
CPU time 135.61 seconds
Started Jul 18 06:49:26 PM PDT 24
Finished Jul 18 06:51:45 PM PDT 24
Peak memory 199788 kb
Host smart-7e89f13e-8d05-4ffd-b994-ee1d54bfed25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213036883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3213036883
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.153299384
Short name T576
Test name
Test status
Simulation time 71514946053 ps
CPU time 33.72 seconds
Started Jul 18 06:54:10 PM PDT 24
Finished Jul 18 06:54:50 PM PDT 24
Peak memory 200196 kb
Host smart-597d5895-7478-41bf-8b3f-2cefd6d82ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153299384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.153299384
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.979143920
Short name T325
Test name
Test status
Simulation time 33725373279 ps
CPU time 15.18 seconds
Started Jul 18 06:54:12 PM PDT 24
Finished Jul 18 06:54:35 PM PDT 24
Peak memory 199756 kb
Host smart-7aecf5e8-e2f6-4d75-940e-97027f1752b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979143920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.979143920
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3391194272
Short name T489
Test name
Test status
Simulation time 86978120557 ps
CPU time 97.68 seconds
Started Jul 18 06:54:12 PM PDT 24
Finished Jul 18 06:55:58 PM PDT 24
Peak memory 200140 kb
Host smart-2c694db9-a740-4074-b955-e37f4bf7da60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391194272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3391194272
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3962240653
Short name T1175
Test name
Test status
Simulation time 71909880432 ps
CPU time 17.32 seconds
Started Jul 18 06:54:12 PM PDT 24
Finished Jul 18 06:54:37 PM PDT 24
Peak memory 200200 kb
Host smart-b844dd0d-227c-4566-8cfc-bd5d7fb13f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962240653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3962240653
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2899014091
Short name T203
Test name
Test status
Simulation time 116825996799 ps
CPU time 172.84 seconds
Started Jul 18 06:54:16 PM PDT 24
Finished Jul 18 06:57:18 PM PDT 24
Peak memory 200196 kb
Host smart-c0528b1f-ccbd-4192-b730-b64579695760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899014091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2899014091
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.842549140
Short name T209
Test name
Test status
Simulation time 28645987286 ps
CPU time 64.38 seconds
Started Jul 18 06:54:11 PM PDT 24
Finished Jul 18 06:55:23 PM PDT 24
Peak memory 200200 kb
Host smart-8a92d96f-4fae-4d39-84c3-47f1e5e7cff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842549140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.842549140
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3855235352
Short name T12
Test name
Test status
Simulation time 108020337280 ps
CPU time 143.64 seconds
Started Jul 18 06:54:16 PM PDT 24
Finished Jul 18 06:56:49 PM PDT 24
Peak memory 200272 kb
Host smart-180d3160-e7da-4e49-bdd5-bae6166c8dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855235352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3855235352
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1498445964
Short name T559
Test name
Test status
Simulation time 35896564037 ps
CPU time 13.81 seconds
Started Jul 18 06:54:12 PM PDT 24
Finished Jul 18 06:54:33 PM PDT 24
Peak memory 199936 kb
Host smart-fe621ae5-c757-4ff5-be99-8169b2ffe8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498445964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1498445964
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3124216718
Short name T926
Test name
Test status
Simulation time 170986356803 ps
CPU time 130.05 seconds
Started Jul 18 06:54:12 PM PDT 24
Finished Jul 18 06:56:30 PM PDT 24
Peak memory 199796 kb
Host smart-d527ca6b-c4a4-4418-b61a-ffb0c94df644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124216718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3124216718
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2383145166
Short name T515
Test name
Test status
Simulation time 46528140 ps
CPU time 0.54 seconds
Started Jul 18 06:47:56 PM PDT 24
Finished Jul 18 06:47:59 PM PDT 24
Peak memory 195588 kb
Host smart-726df95b-4ab2-4f68-929a-bf775c879633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383145166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2383145166
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.4185539311
Short name T660
Test name
Test status
Simulation time 121745818077 ps
CPU time 188.74 seconds
Started Jul 18 06:47:40 PM PDT 24
Finished Jul 18 06:50:51 PM PDT 24
Peak memory 200216 kb
Host smart-6a39990a-5783-4025-b445-cf7510eef7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185539311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.4185539311
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3499315037
Short name T1120
Test name
Test status
Simulation time 221867959603 ps
CPU time 89.92 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:49:21 PM PDT 24
Peak memory 200192 kb
Host smart-aee70b9e-f8dc-4fc0-b6ba-7a5fac3f9f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499315037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3499315037
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2101449355
Short name T1040
Test name
Test status
Simulation time 34690371794 ps
CPU time 16.72 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:48:09 PM PDT 24
Peak memory 200196 kb
Host smart-d85b36b7-8e1c-4d35-9379-708172108c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101449355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2101449355
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2415630728
Short name T253
Test name
Test status
Simulation time 58881455660 ps
CPU time 25.7 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:48:17 PM PDT 24
Peak memory 200196 kb
Host smart-a0c237cf-787c-48e9-b546-503765f39bcb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415630728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2415630728
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1936171016
Short name T652
Test name
Test status
Simulation time 70804361804 ps
CPU time 630.83 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:58:25 PM PDT 24
Peak memory 200312 kb
Host smart-4a064ac2-9869-4050-aa5b-f18791b42f40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1936171016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1936171016
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1940156844
Short name T934
Test name
Test status
Simulation time 1490779427 ps
CPU time 1.85 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:47:56 PM PDT 24
Peak memory 197380 kb
Host smart-17399614-189c-488f-93f5-26be2a33529d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940156844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1940156844
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.857918982
Short name T509
Test name
Test status
Simulation time 87019146647 ps
CPU time 38.68 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:48:34 PM PDT 24
Peak memory 208356 kb
Host smart-26f83f82-2ceb-4fed-b523-e664060c9fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857918982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.857918982
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1964130355
Short name T1174
Test name
Test status
Simulation time 12994678577 ps
CPU time 295.32 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:52:50 PM PDT 24
Peak memory 200144 kb
Host smart-a18c4191-afbb-4d62-9e9e-f251f5013450
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964130355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1964130355
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2195432311
Short name T1083
Test name
Test status
Simulation time 5541135730 ps
CPU time 12.82 seconds
Started Jul 18 06:47:39 PM PDT 24
Finished Jul 18 06:47:54 PM PDT 24
Peak memory 199068 kb
Host smart-9300bdc6-4c04-4596-aa65-86818e8912d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195432311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2195432311
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3418356360
Short name T732
Test name
Test status
Simulation time 27343500276 ps
CPU time 50.41 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:48:45 PM PDT 24
Peak memory 200196 kb
Host smart-37a5c184-b2cf-4399-8f92-65fba6d35a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418356360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3418356360
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3571597458
Short name T885
Test name
Test status
Simulation time 2596723788 ps
CPU time 2.75 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:47:55 PM PDT 24
Peak memory 196736 kb
Host smart-61b6dafa-0e22-4d00-8ae0-fdf915b1fa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571597458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3571597458
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_smoke.1484666101
Short name T616
Test name
Test status
Simulation time 10521213303 ps
CPU time 35.23 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:48:31 PM PDT 24
Peak memory 200100 kb
Host smart-6778c632-e05d-4afd-b932-d51f79393fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484666101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1484666101
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2505521228
Short name T542
Test name
Test status
Simulation time 148505151178 ps
CPU time 431.24 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:55:06 PM PDT 24
Peak memory 216832 kb
Host smart-b83a5ee9-8677-4b61-b4cf-5ce2fdb16ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505521228 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2505521228
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1780649399
Short name T416
Test name
Test status
Simulation time 869643989 ps
CPU time 2.58 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:47:58 PM PDT 24
Peak memory 199368 kb
Host smart-6e295151-3bad-41eb-920f-aab84f3ab98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780649399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1780649399
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2904155620
Short name T820
Test name
Test status
Simulation time 46515219928 ps
CPU time 14.7 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:48:10 PM PDT 24
Peak memory 200184 kb
Host smart-c80394b2-d88c-4a69-9d2e-2b44e7b6901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904155620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2904155620
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.75567221
Short name T673
Test name
Test status
Simulation time 43983234 ps
CPU time 0.54 seconds
Started Jul 18 06:49:42 PM PDT 24
Finished Jul 18 06:49:46 PM PDT 24
Peak memory 195924 kb
Host smart-3b2e6fda-d672-4cb6-9cad-82995d504c28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75567221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.75567221
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3790023446
Short name T607
Test name
Test status
Simulation time 100004511640 ps
CPU time 38.87 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:50:26 PM PDT 24
Peak memory 200156 kb
Host smart-b5dca825-a79e-4490-b07d-aadf74c1a876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790023446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3790023446
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1855430465
Short name T736
Test name
Test status
Simulation time 27844817732 ps
CPU time 18.89 seconds
Started Jul 18 06:49:40 PM PDT 24
Finished Jul 18 06:50:00 PM PDT 24
Peak memory 200168 kb
Host smart-947e36df-2747-4a57-acbd-784af72e1e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855430465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1855430465
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.371442413
Short name T506
Test name
Test status
Simulation time 26528193929 ps
CPU time 14.38 seconds
Started Jul 18 06:49:53 PM PDT 24
Finished Jul 18 06:50:09 PM PDT 24
Peak memory 200180 kb
Host smart-b164050e-1d68-4317-989d-75b7a9c1c804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371442413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.371442413
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1208951907
Short name T518
Test name
Test status
Simulation time 334473116404 ps
CPU time 113.61 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:51:40 PM PDT 24
Peak memory 198360 kb
Host smart-be6f4ed2-d383-4609-ab1b-a3bdfccf5ba1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208951907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1208951907
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3068100575
Short name T267
Test name
Test status
Simulation time 130738001494 ps
CPU time 463.75 seconds
Started Jul 18 06:49:41 PM PDT 24
Finished Jul 18 06:57:27 PM PDT 24
Peak memory 200120 kb
Host smart-8aaeb9c8-12d7-4806-9381-9c7eb94993b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3068100575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3068100575
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.865488671
Short name T312
Test name
Test status
Simulation time 4147754107 ps
CPU time 4.05 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:49:50 PM PDT 24
Peak memory 199248 kb
Host smart-133e89e9-a465-44db-866a-c98687396867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865488671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.865488671
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3580664250
Short name T779
Test name
Test status
Simulation time 18370666056 ps
CPU time 31.53 seconds
Started Jul 18 06:49:41 PM PDT 24
Finished Jul 18 06:50:14 PM PDT 24
Peak memory 199524 kb
Host smart-4586120c-4670-4be2-b249-5a080f0400bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580664250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3580664250
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1285827305
Short name T742
Test name
Test status
Simulation time 8819530544 ps
CPU time 109.87 seconds
Started Jul 18 06:49:42 PM PDT 24
Finished Jul 18 06:51:35 PM PDT 24
Peak memory 200192 kb
Host smart-802e2959-8ca9-44e2-9997-3c4a551905e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285827305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1285827305
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2674658140
Short name T50
Test name
Test status
Simulation time 3039546454 ps
CPU time 14.91 seconds
Started Jul 18 06:49:53 PM PDT 24
Finished Jul 18 06:50:09 PM PDT 24
Peak memory 199116 kb
Host smart-323158dd-01a1-4f02-bfea-78261c340f00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2674658140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2674658140
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1929776938
Short name T1099
Test name
Test status
Simulation time 106756853979 ps
CPU time 151.41 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:52:18 PM PDT 24
Peak memory 200132 kb
Host smart-8d9da58e-88f3-4010-9450-dbeea4fdcb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929776938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1929776938
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.687433505
Short name T1013
Test name
Test status
Simulation time 26112722394 ps
CPU time 40.9 seconds
Started Jul 18 06:49:41 PM PDT 24
Finished Jul 18 06:50:23 PM PDT 24
Peak memory 196392 kb
Host smart-2d28f22f-f253-4575-b377-97daba259d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687433505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.687433505
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2646145768
Short name T655
Test name
Test status
Simulation time 132383757 ps
CPU time 0.81 seconds
Started Jul 18 06:49:41 PM PDT 24
Finished Jul 18 06:49:43 PM PDT 24
Peak memory 198404 kb
Host smart-3c0c08c0-f029-41e0-b2f8-c904679de792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646145768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2646145768
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2756301261
Short name T823
Test name
Test status
Simulation time 397294560231 ps
CPU time 360.98 seconds
Started Jul 18 06:49:44 PM PDT 24
Finished Jul 18 06:55:49 PM PDT 24
Peak memory 208512 kb
Host smart-30b4756e-538e-4c6e-8c72-b863b01ed366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756301261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2756301261
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1859940714
Short name T859
Test name
Test status
Simulation time 123570804748 ps
CPU time 517.87 seconds
Started Jul 18 06:49:42 PM PDT 24
Finished Jul 18 06:58:23 PM PDT 24
Peak memory 216716 kb
Host smart-4acd1c83-cad1-429d-a113-2a2a115e8aa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859940714 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1859940714
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3691511375
Short name T672
Test name
Test status
Simulation time 1094071557 ps
CPU time 2.2 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:49:49 PM PDT 24
Peak memory 199204 kb
Host smart-4c49b18b-66e0-47f1-a31a-6843b494864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691511375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3691511375
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.356375425
Short name T783
Test name
Test status
Simulation time 69704213742 ps
CPU time 23.03 seconds
Started Jul 18 06:49:41 PM PDT 24
Finished Jul 18 06:50:07 PM PDT 24
Peak memory 200148 kb
Host smart-4d8337db-ed40-4b11-9101-0f24bd1fd867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356375425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.356375425
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2997870022
Short name T788
Test name
Test status
Simulation time 42311953 ps
CPU time 0.56 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:49:47 PM PDT 24
Peak memory 195568 kb
Host smart-3155afef-e003-4218-bd8b-743c79ec72dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997870022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2997870022
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.51437004
Short name T897
Test name
Test status
Simulation time 74263280095 ps
CPU time 30.52 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:50:18 PM PDT 24
Peak memory 200192 kb
Host smart-97cf9d5a-34db-445f-865b-48e3bd8721b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51437004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.51437004
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3691463132
Short name T1121
Test name
Test status
Simulation time 128874040674 ps
CPU time 17.03 seconds
Started Jul 18 06:49:45 PM PDT 24
Finished Jul 18 06:50:07 PM PDT 24
Peak memory 200092 kb
Host smart-09cfc5f7-a853-4653-959f-20e5d423eb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691463132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3691463132
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.4122829931
Short name T857
Test name
Test status
Simulation time 61417019706 ps
CPU time 30.26 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:50:18 PM PDT 24
Peak memory 200180 kb
Host smart-9d82ef48-344e-466e-a785-a01776243f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122829931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.4122829931
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2109805689
Short name T1062
Test name
Test status
Simulation time 14611392379 ps
CPU time 7.97 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:49:55 PM PDT 24
Peak memory 197992 kb
Host smart-fb26459a-499b-4c6c-9f74-af6e4c4189aa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109805689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2109805689
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2069358115
Short name T380
Test name
Test status
Simulation time 74180022438 ps
CPU time 300.26 seconds
Started Jul 18 06:49:42 PM PDT 24
Finished Jul 18 06:54:45 PM PDT 24
Peak memory 200116 kb
Host smart-b3a54d42-4871-4238-ac32-6407f9e5ab59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2069358115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2069358115
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.585841803
Short name T577
Test name
Test status
Simulation time 8952872795 ps
CPU time 14.12 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:50:02 PM PDT 24
Peak memory 199856 kb
Host smart-2d13b32c-f66e-4ba7-a5f6-98d5d37fb8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585841803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.585841803
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.4239807679
Short name T394
Test name
Test status
Simulation time 26229738810 ps
CPU time 56.37 seconds
Started Jul 18 06:49:45 PM PDT 24
Finished Jul 18 06:50:45 PM PDT 24
Peak memory 199000 kb
Host smart-ca6ee0f1-1b17-45ce-b6e1-79049abbc6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239807679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.4239807679
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3088253625
Short name T441
Test name
Test status
Simulation time 13293759782 ps
CPU time 769.13 seconds
Started Jul 18 06:49:41 PM PDT 24
Finished Jul 18 07:02:33 PM PDT 24
Peak memory 200168 kb
Host smart-d26103fa-f308-4fb0-a87b-8872d4c0f7ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3088253625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3088253625
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3680259631
Short name T449
Test name
Test status
Simulation time 7069860912 ps
CPU time 65.1 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:50:52 PM PDT 24
Peak memory 198504 kb
Host smart-89a3594a-63fa-42de-b980-7b8c18f1a3bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3680259631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3680259631
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.519014772
Short name T894
Test name
Test status
Simulation time 161727276951 ps
CPU time 71.66 seconds
Started Jul 18 06:49:45 PM PDT 24
Finished Jul 18 06:51:01 PM PDT 24
Peak memory 199928 kb
Host smart-148389f9-38c1-48ad-8044-eed553181eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519014772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.519014772
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1869003797
Short name T378
Test name
Test status
Simulation time 4001190385 ps
CPU time 1.29 seconds
Started Jul 18 06:49:41 PM PDT 24
Finished Jul 18 06:49:45 PM PDT 24
Peak memory 196504 kb
Host smart-1f7b4b88-ea73-4ae0-b082-1eb1f206d4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869003797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1869003797
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1062545271
Short name T42
Test name
Test status
Simulation time 725057837 ps
CPU time 1.37 seconds
Started Jul 18 06:49:42 PM PDT 24
Finished Jul 18 06:49:46 PM PDT 24
Peak memory 198716 kb
Host smart-b2e4cb27-8611-4bd2-8183-1bb5963d4f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062545271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1062545271
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.365568285
Short name T1149
Test name
Test status
Simulation time 166315073222 ps
CPU time 312.32 seconds
Started Jul 18 06:49:42 PM PDT 24
Finished Jul 18 06:54:57 PM PDT 24
Peak memory 216200 kb
Host smart-569d2839-8676-466f-b93e-2c722461c4c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365568285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.365568285
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.281895620
Short name T310
Test name
Test status
Simulation time 53148757547 ps
CPU time 138.62 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:52:06 PM PDT 24
Peak memory 208608 kb
Host smart-42270d30-c123-4a91-a2d0-3626fa06a63a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281895620 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.281895620
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1188611081
Short name T332
Test name
Test status
Simulation time 885751006 ps
CPU time 1.85 seconds
Started Jul 18 06:49:44 PM PDT 24
Finished Jul 18 06:49:50 PM PDT 24
Peak memory 198428 kb
Host smart-884db9b0-1cdd-4c41-997a-118fdae47aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188611081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1188611081
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.399702895
Short name T8
Test name
Test status
Simulation time 50172828366 ps
CPU time 44.74 seconds
Started Jul 18 06:49:42 PM PDT 24
Finished Jul 18 06:50:30 PM PDT 24
Peak memory 200108 kb
Host smart-3e71e78a-fca5-46db-a9cd-86d22afe6a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399702895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.399702895
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.828776938
Short name T438
Test name
Test status
Simulation time 10965903 ps
CPU time 0.56 seconds
Started Jul 18 06:49:44 PM PDT 24
Finished Jul 18 06:49:48 PM PDT 24
Peak memory 195572 kb
Host smart-db64da85-edac-4683-a228-8a6dac6e100f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828776938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.828776938
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3434198930
Short name T912
Test name
Test status
Simulation time 64348534993 ps
CPU time 59.88 seconds
Started Jul 18 06:49:46 PM PDT 24
Finished Jul 18 06:50:50 PM PDT 24
Peak memory 200184 kb
Host smart-55c3fe52-e83d-4cd6-b077-e79b5643c660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434198930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3434198930
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.453722287
Short name T1039
Test name
Test status
Simulation time 36273891726 ps
CPU time 13.46 seconds
Started Jul 18 06:49:45 PM PDT 24
Finished Jul 18 06:50:03 PM PDT 24
Peak memory 200172 kb
Host smart-46dd32b0-014d-4b57-8d77-f81a0854dfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453722287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.453722287
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2393523690
Short name T399
Test name
Test status
Simulation time 8833345092 ps
CPU time 27.06 seconds
Started Jul 18 06:49:44 PM PDT 24
Finished Jul 18 06:50:15 PM PDT 24
Peak memory 200180 kb
Host smart-18b68f35-7fa2-47de-8894-7a523476187f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393523690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2393523690
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1679711144
Short name T336
Test name
Test status
Simulation time 25477710330 ps
CPU time 41.56 seconds
Started Jul 18 06:49:42 PM PDT 24
Finished Jul 18 06:50:26 PM PDT 24
Peak memory 199256 kb
Host smart-e8f0fed3-d8dc-4fc8-9ecd-eae431104f61
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679711144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1679711144
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2290797006
Short name T1004
Test name
Test status
Simulation time 88756365011 ps
CPU time 155.69 seconds
Started Jul 18 06:49:45 PM PDT 24
Finished Jul 18 06:52:25 PM PDT 24
Peak memory 200172 kb
Host smart-65ebbf26-bffd-4432-87a4-79e554cb56f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290797006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2290797006
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.448896220
Short name T957
Test name
Test status
Simulation time 8707717283 ps
CPU time 10.98 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:49:58 PM PDT 24
Peak memory 199144 kb
Host smart-c9fdd457-181e-411e-9a10-9a331f3d9265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448896220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.448896220
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1889132221
Short name T1116
Test name
Test status
Simulation time 277252503192 ps
CPU time 39.51 seconds
Started Jul 18 06:49:42 PM PDT 24
Finished Jul 18 06:50:25 PM PDT 24
Peak memory 200256 kb
Host smart-f41f4135-abbe-4ff1-83e1-4dfd8f35fa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889132221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1889132221
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1055998613
Short name T44
Test name
Test status
Simulation time 16057743892 ps
CPU time 918.08 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 07:05:05 PM PDT 24
Peak memory 200276 kb
Host smart-f4705f90-1c00-4881-9e9c-206eae7fbb49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1055998613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1055998613
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3874471083
Short name T370
Test name
Test status
Simulation time 4545273272 ps
CPU time 35.25 seconds
Started Jul 18 06:49:45 PM PDT 24
Finished Jul 18 06:50:25 PM PDT 24
Peak memory 199380 kb
Host smart-de728411-5c0b-4472-8ae8-99b070d48117
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874471083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3874471083
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.4049904325
Short name T643
Test name
Test status
Simulation time 115943124580 ps
CPU time 42.92 seconds
Started Jul 18 06:49:41 PM PDT 24
Finished Jul 18 06:50:25 PM PDT 24
Peak memory 200188 kb
Host smart-886f68f5-bb5b-49ac-b592-0c7c725d834a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049904325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.4049904325
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3170420417
Short name T306
Test name
Test status
Simulation time 1823818603 ps
CPU time 3.32 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:49:51 PM PDT 24
Peak memory 195872 kb
Host smart-975d2950-5657-42a4-98f3-4e22f33a5296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170420417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3170420417
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3618335224
Short name T928
Test name
Test status
Simulation time 267605909 ps
CPU time 1.53 seconds
Started Jul 18 06:49:44 PM PDT 24
Finished Jul 18 06:49:49 PM PDT 24
Peak memory 199248 kb
Host smart-a7af1267-2a57-4dd5-92fa-be2380aa0263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618335224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3618335224
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1428590726
Short name T494
Test name
Test status
Simulation time 28126331301 ps
CPU time 24.94 seconds
Started Jul 18 06:49:45 PM PDT 24
Finished Jul 18 06:50:14 PM PDT 24
Peak memory 200236 kb
Host smart-dbf220fb-15c5-4082-b1d9-7187ca9f6235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428590726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1428590726
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1894261762
Short name T504
Test name
Test status
Simulation time 52928808826 ps
CPU time 295.07 seconds
Started Jul 18 06:49:44 PM PDT 24
Finished Jul 18 06:54:43 PM PDT 24
Peak memory 211944 kb
Host smart-44fadb7f-fe01-4889-ae78-5f230e7fd9ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894261762 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1894261762
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3190795047
Short name T393
Test name
Test status
Simulation time 6692851667 ps
CPU time 13 seconds
Started Jul 18 06:49:45 PM PDT 24
Finished Jul 18 06:50:03 PM PDT 24
Peak memory 199884 kb
Host smart-d44bc3ec-8063-4af4-a9df-1cf413025e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190795047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3190795047
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1130371546
Short name T1119
Test name
Test status
Simulation time 66943643528 ps
CPU time 98.59 seconds
Started Jul 18 06:49:43 PM PDT 24
Finished Jul 18 06:51:25 PM PDT 24
Peak memory 200132 kb
Host smart-8e0bda89-2d39-4240-9169-75f626e10755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130371546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1130371546
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.771121726
Short name T373
Test name
Test status
Simulation time 14189221 ps
CPU time 0.64 seconds
Started Jul 18 06:50:03 PM PDT 24
Finished Jul 18 06:50:07 PM PDT 24
Peak memory 194832 kb
Host smart-6d077f52-8ab0-4720-bfe1-e1e1e541b24f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771121726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.771121726
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1170015030
Short name T1158
Test name
Test status
Simulation time 52135686155 ps
CPU time 22.02 seconds
Started Jul 18 06:49:58 PM PDT 24
Finished Jul 18 06:50:23 PM PDT 24
Peak memory 200108 kb
Host smart-ef19aab8-fc58-41a8-92c5-acae9e1b36c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170015030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1170015030
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2263847842
Short name T965
Test name
Test status
Simulation time 27570481585 ps
CPU time 11.34 seconds
Started Jul 18 06:50:01 PM PDT 24
Finished Jul 18 06:50:16 PM PDT 24
Peak memory 200060 kb
Host smart-0e95e867-8130-416b-b752-eebcc6c23c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263847842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2263847842
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.362035673
Short name T286
Test name
Test status
Simulation time 13464773869 ps
CPU time 12.47 seconds
Started Jul 18 06:50:00 PM PDT 24
Finished Jul 18 06:50:17 PM PDT 24
Peak memory 200132 kb
Host smart-88fc0c6d-6f2b-429a-aa67-bf8d9742a8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362035673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.362035673
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1018873719
Short name T1012
Test name
Test status
Simulation time 2018480931 ps
CPU time 3.55 seconds
Started Jul 18 06:49:58 PM PDT 24
Finished Jul 18 06:50:06 PM PDT 24
Peak memory 195872 kb
Host smart-bfd80f95-5d53-4894-91dd-66df0e4fc3d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018873719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1018873719
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1697500236
Short name T1047
Test name
Test status
Simulation time 127513333058 ps
CPU time 161.75 seconds
Started Jul 18 06:49:58 PM PDT 24
Finished Jul 18 06:52:42 PM PDT 24
Peak memory 200116 kb
Host smart-e5a482c3-4164-4d85-bb63-bdf8eb3df101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1697500236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1697500236
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.766801301
Short name T702
Test name
Test status
Simulation time 1004327948 ps
CPU time 0.99 seconds
Started Jul 18 06:50:02 PM PDT 24
Finished Jul 18 06:50:07 PM PDT 24
Peak memory 195672 kb
Host smart-813f1c46-b495-4345-9bcf-e7b01f086047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766801301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.766801301
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3241177668
Short name T508
Test name
Test status
Simulation time 9975281110 ps
CPU time 17.02 seconds
Started Jul 18 06:50:01 PM PDT 24
Finished Jul 18 06:50:22 PM PDT 24
Peak memory 198664 kb
Host smart-95e74ee4-e636-4e96-b93b-9075d2d4d246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241177668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3241177668
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2550729300
Short name T419
Test name
Test status
Simulation time 4997639826 ps
CPU time 137.06 seconds
Started Jul 18 06:49:58 PM PDT 24
Finished Jul 18 06:52:18 PM PDT 24
Peak memory 200148 kb
Host smart-5620444a-617c-49b4-9a70-d62fc5bc08ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2550729300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2550729300
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1034652947
Short name T769
Test name
Test status
Simulation time 2786779483 ps
CPU time 16.46 seconds
Started Jul 18 06:49:59 PM PDT 24
Finished Jul 18 06:50:20 PM PDT 24
Peak memory 198320 kb
Host smart-786ff32f-1dcd-4f72-8a5e-8eb05a9639f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034652947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1034652947
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2704255000
Short name T169
Test name
Test status
Simulation time 136189105252 ps
CPU time 24.06 seconds
Started Jul 18 06:50:09 PM PDT 24
Finished Jul 18 06:50:35 PM PDT 24
Peak memory 200168 kb
Host smart-f1018b1e-f4a6-4292-b629-df6dcf20bba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704255000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2704255000
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2692475376
Short name T1110
Test name
Test status
Simulation time 521641765 ps
CPU time 1.46 seconds
Started Jul 18 06:49:58 PM PDT 24
Finished Jul 18 06:50:02 PM PDT 24
Peak memory 195664 kb
Host smart-b8645d93-b154-4ec4-b2a1-9fcf2e407f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692475376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2692475376
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2802157876
Short name T1067
Test name
Test status
Simulation time 292076227 ps
CPU time 1.49 seconds
Started Jul 18 06:49:58 PM PDT 24
Finished Jul 18 06:50:02 PM PDT 24
Peak memory 198524 kb
Host smart-81144427-fba8-4450-8be9-b952e91ce68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802157876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2802157876
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3716859371
Short name T1100
Test name
Test status
Simulation time 395449781462 ps
CPU time 164.95 seconds
Started Jul 18 06:50:01 PM PDT 24
Finished Jul 18 06:52:50 PM PDT 24
Peak memory 208424 kb
Host smart-3290dacf-f1e5-4015-a2d0-c9e42168b2c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716859371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3716859371
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.711060704
Short name T970
Test name
Test status
Simulation time 279787288696 ps
CPU time 1490.27 seconds
Started Jul 18 06:49:58 PM PDT 24
Finished Jul 18 07:14:51 PM PDT 24
Peak memory 216916 kb
Host smart-d8904d66-4d90-473b-ac4b-ccdb29c6ce40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711060704 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.711060704
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.941016222
Short name T609
Test name
Test status
Simulation time 2604058435 ps
CPU time 2.77 seconds
Started Jul 18 06:49:57 PM PDT 24
Finished Jul 18 06:50:01 PM PDT 24
Peak memory 199952 kb
Host smart-7a708be5-1e53-4029-8706-e0d0ae4b7dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941016222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.941016222
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2100497766
Short name T303
Test name
Test status
Simulation time 81135857117 ps
CPU time 159.97 seconds
Started Jul 18 06:49:59 PM PDT 24
Finished Jul 18 06:52:43 PM PDT 24
Peak memory 200132 kb
Host smart-a0d47b07-041d-42e3-bea7-037de83698ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100497766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2100497766
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1385306763
Short name T791
Test name
Test status
Simulation time 41337518 ps
CPU time 0.55 seconds
Started Jul 18 06:50:01 PM PDT 24
Finished Jul 18 06:50:06 PM PDT 24
Peak memory 195564 kb
Host smart-7627fb53-e395-4597-950f-2c4ff5d50c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385306763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1385306763
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.303130418
Short name T150
Test name
Test status
Simulation time 39300202778 ps
CPU time 14.64 seconds
Started Jul 18 06:49:59 PM PDT 24
Finished Jul 18 06:50:17 PM PDT 24
Peak memory 199976 kb
Host smart-6726c88c-b0c7-416d-8066-a1178acce787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303130418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.303130418
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2744176490
Short name T1052
Test name
Test status
Simulation time 160225579432 ps
CPU time 213.09 seconds
Started Jul 18 06:49:57 PM PDT 24
Finished Jul 18 06:53:32 PM PDT 24
Peak memory 200204 kb
Host smart-6258a700-b0fe-44ae-81fb-02c8f858a33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744176490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2744176490
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3123836382
Short name T1109
Test name
Test status
Simulation time 59234358692 ps
CPU time 48.3 seconds
Started Jul 18 06:50:01 PM PDT 24
Finished Jul 18 06:50:53 PM PDT 24
Peak memory 200140 kb
Host smart-2e480b6e-dd97-4bc0-8602-404bbc3e8745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123836382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3123836382
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3710072168
Short name T1055
Test name
Test status
Simulation time 44869474304 ps
CPU time 21.15 seconds
Started Jul 18 06:50:01 PM PDT 24
Finished Jul 18 06:50:27 PM PDT 24
Peak memory 200016 kb
Host smart-4ae8f0b9-632d-490b-92be-5ac545fe371e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710072168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3710072168
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3320698036
Short name T1059
Test name
Test status
Simulation time 104284086146 ps
CPU time 174.12 seconds
Started Jul 18 06:49:58 PM PDT 24
Finished Jul 18 06:52:56 PM PDT 24
Peak memory 200120 kb
Host smart-b97202e5-7f7a-43c6-9cc6-1e7e5c5d2ab0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3320698036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3320698036
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1093433477
Short name T357
Test name
Test status
Simulation time 5158820865 ps
CPU time 3.79 seconds
Started Jul 18 06:50:02 PM PDT 24
Finished Jul 18 06:50:10 PM PDT 24
Peak memory 198968 kb
Host smart-97442a66-4a21-4fe3-9313-a7d368f035fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093433477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1093433477
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.514320982
Short name T991
Test name
Test status
Simulation time 20467871739 ps
CPU time 32.86 seconds
Started Jul 18 06:50:00 PM PDT 24
Finished Jul 18 06:50:37 PM PDT 24
Peak memory 200304 kb
Host smart-a7a0da7e-67f2-4bbe-aa55-4886e44fbc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514320982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.514320982
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.137878309
Short name T252
Test name
Test status
Simulation time 11891871778 ps
CPU time 142.2 seconds
Started Jul 18 06:49:58 PM PDT 24
Finished Jul 18 06:52:23 PM PDT 24
Peak memory 200272 kb
Host smart-ed3be2c5-739f-4c9f-b6a1-9f04d34b8a21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137878309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.137878309
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3797055764
Short name T351
Test name
Test status
Simulation time 6477769603 ps
CPU time 12.99 seconds
Started Jul 18 06:49:57 PM PDT 24
Finished Jul 18 06:50:12 PM PDT 24
Peak memory 199448 kb
Host smart-b4fa5518-7603-40be-a805-7c67d47ef42a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797055764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3797055764
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.601300047
Short name T730
Test name
Test status
Simulation time 184579531326 ps
CPU time 44.39 seconds
Started Jul 18 06:50:10 PM PDT 24
Finished Jul 18 06:50:56 PM PDT 24
Peak memory 199412 kb
Host smart-d28b5970-3eec-407d-a78a-25ff2f42897a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601300047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.601300047
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1982838356
Short name T1111
Test name
Test status
Simulation time 3207322567 ps
CPU time 1.83 seconds
Started Jul 18 06:49:59 PM PDT 24
Finished Jul 18 06:50:05 PM PDT 24
Peak memory 196740 kb
Host smart-5d37a55d-7c24-4b00-abb1-d9c86b6bf149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982838356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1982838356
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.117290371
Short name T345
Test name
Test status
Simulation time 130456745 ps
CPU time 0.79 seconds
Started Jul 18 06:50:12 PM PDT 24
Finished Jul 18 06:50:15 PM PDT 24
Peak memory 197252 kb
Host smart-346d21b2-c4fc-41d7-98e5-ecf7f9fd7a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117290371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.117290371
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.4150088891
Short name T1017
Test name
Test status
Simulation time 131195221263 ps
CPU time 375.03 seconds
Started Jul 18 06:49:58 PM PDT 24
Finished Jul 18 06:56:17 PM PDT 24
Peak memory 208488 kb
Host smart-80b7447c-f555-4675-a216-0f165ae67193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150088891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.4150088891
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2841349836
Short name T301
Test name
Test status
Simulation time 28290980218 ps
CPU time 572.34 seconds
Started Jul 18 06:50:01 PM PDT 24
Finished Jul 18 06:59:38 PM PDT 24
Peak memory 216204 kb
Host smart-fefd7736-d865-45b9-96c6-23557f248168
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841349836 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2841349836
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.485399520
Short name T804
Test name
Test status
Simulation time 7107367786 ps
CPU time 9.15 seconds
Started Jul 18 06:49:57 PM PDT 24
Finished Jul 18 06:50:08 PM PDT 24
Peak memory 200116 kb
Host smart-56d23015-a6c6-469b-9639-ddf057429362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485399520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.485399520
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1700577134
Short name T1105
Test name
Test status
Simulation time 131291686880 ps
CPU time 309.82 seconds
Started Jul 18 06:49:56 PM PDT 24
Finished Jul 18 06:55:07 PM PDT 24
Peak memory 200220 kb
Host smart-7471ede8-f68c-4977-ada9-faee85eebc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700577134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1700577134
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.137897206
Short name T369
Test name
Test status
Simulation time 12917571 ps
CPU time 0.63 seconds
Started Jul 18 06:50:03 PM PDT 24
Finished Jul 18 06:50:07 PM PDT 24
Peak memory 195872 kb
Host smart-ce338972-ba1d-41a2-858d-a2ffeb430c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137897206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.137897206
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1855328759
Short name T867
Test name
Test status
Simulation time 111861277282 ps
CPU time 148.81 seconds
Started Jul 18 06:49:57 PM PDT 24
Finished Jul 18 06:52:28 PM PDT 24
Peak memory 200096 kb
Host smart-fbf5a02d-ef51-4502-b4d6-cc6b65e14964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855328759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1855328759
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.854020528
Short name T386
Test name
Test status
Simulation time 32185367859 ps
CPU time 54.15 seconds
Started Jul 18 06:49:59 PM PDT 24
Finished Jul 18 06:50:57 PM PDT 24
Peak memory 200152 kb
Host smart-9cabd7a5-4cc3-4934-a535-39035ffd07be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854020528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.854020528
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.788787800
Short name T1027
Test name
Test status
Simulation time 29160818175 ps
CPU time 45.89 seconds
Started Jul 18 06:50:03 PM PDT 24
Finished Jul 18 06:50:52 PM PDT 24
Peak memory 200136 kb
Host smart-99ae07d2-96ca-4f2e-833f-5dc952d2f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788787800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.788787800
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3380605579
Short name T398
Test name
Test status
Simulation time 25696989029 ps
CPU time 29.83 seconds
Started Jul 18 06:50:01 PM PDT 24
Finished Jul 18 06:50:35 PM PDT 24
Peak memory 200184 kb
Host smart-3ba13be8-508e-4bff-a349-b8f3bdabc9ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380605579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3380605579
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1837520081
Short name T832
Test name
Test status
Simulation time 105757488887 ps
CPU time 188.62 seconds
Started Jul 18 06:49:59 PM PDT 24
Finished Jul 18 06:53:11 PM PDT 24
Peak memory 200176 kb
Host smart-b6b386c4-0f9a-40e9-9dac-537043b84a64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1837520081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1837520081
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.125965927
Short name T955
Test name
Test status
Simulation time 11298336049 ps
CPU time 6.87 seconds
Started Jul 18 06:50:02 PM PDT 24
Finished Jul 18 06:50:13 PM PDT 24
Peak memory 199884 kb
Host smart-ad894daf-40cd-4085-9f4a-1c142377d620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125965927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.125965927
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3128607616
Short name T475
Test name
Test status
Simulation time 45062405258 ps
CPU time 21.9 seconds
Started Jul 18 06:49:57 PM PDT 24
Finished Jul 18 06:50:21 PM PDT 24
Peak memory 200304 kb
Host smart-2ea21c7d-efab-43b7-ba07-74fe658ce8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128607616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3128607616
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.4033789931
Short name T423
Test name
Test status
Simulation time 10537991000 ps
CPU time 160.41 seconds
Started Jul 18 06:50:00 PM PDT 24
Finished Jul 18 06:52:45 PM PDT 24
Peak memory 200204 kb
Host smart-afaa11fd-51ae-4392-88f9-ea6f3e276879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4033789931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.4033789931
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1448651618
Short name T490
Test name
Test status
Simulation time 6556710956 ps
CPU time 54.13 seconds
Started Jul 18 06:50:00 PM PDT 24
Finished Jul 18 06:50:58 PM PDT 24
Peak memory 198916 kb
Host smart-e174c116-87f6-4787-be42-ffb8abb1df9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448651618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1448651618
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.684160699
Short name T979
Test name
Test status
Simulation time 72082606570 ps
CPU time 40.5 seconds
Started Jul 18 06:49:58 PM PDT 24
Finished Jul 18 06:50:41 PM PDT 24
Peak memory 200096 kb
Host smart-188ad3cb-0cc1-434a-8449-cc2c3fdc1b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684160699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.684160699
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3397739734
Short name T711
Test name
Test status
Simulation time 39459821418 ps
CPU time 27.61 seconds
Started Jul 18 06:50:01 PM PDT 24
Finished Jul 18 06:50:33 PM PDT 24
Peak memory 196176 kb
Host smart-917a3ed2-9912-4d56-b2be-46d88b6e9e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397739734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3397739734
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.4010928360
Short name T40
Test name
Test status
Simulation time 689159287 ps
CPU time 1.6 seconds
Started Jul 18 06:49:57 PM PDT 24
Finished Jul 18 06:50:00 PM PDT 24
Peak memory 198652 kb
Host smart-ce23b5e4-5c1f-4fca-9218-b845e032fe65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010928360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.4010928360
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.887531997
Short name T259
Test name
Test status
Simulation time 189861891398 ps
CPU time 307.53 seconds
Started Jul 18 06:50:09 PM PDT 24
Finished Jul 18 06:55:18 PM PDT 24
Peak memory 200176 kb
Host smart-7bf38eec-2e93-4a32-ace0-7bd9e37ed81a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887531997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.887531997
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.4087860459
Short name T1128
Test name
Test status
Simulation time 209733262611 ps
CPU time 555.39 seconds
Started Jul 18 06:49:59 PM PDT 24
Finished Jul 18 06:59:18 PM PDT 24
Peak memory 216192 kb
Host smart-6662b4f1-ce1c-4aa6-80b8-53c646fd49a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087860459 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.4087860459
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.932046564
Short name T1106
Test name
Test status
Simulation time 10348212542 ps
CPU time 8.61 seconds
Started Jul 18 06:50:09 PM PDT 24
Finished Jul 18 06:50:20 PM PDT 24
Peak memory 200148 kb
Host smart-6be29f27-7cb4-4e72-a136-ccc498f4e8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932046564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.932046564
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.889740384
Short name T1042
Test name
Test status
Simulation time 56638567982 ps
CPU time 64.14 seconds
Started Jul 18 06:50:01 PM PDT 24
Finished Jul 18 06:51:09 PM PDT 24
Peak memory 200192 kb
Host smart-b3854025-dc93-4c6b-a793-29244ce2406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889740384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.889740384
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.578497719
Short name T341
Test name
Test status
Simulation time 19999535 ps
CPU time 0.59 seconds
Started Jul 18 06:50:18 PM PDT 24
Finished Jul 18 06:50:21 PM PDT 24
Peak memory 195588 kb
Host smart-e6aa417b-726c-466f-a70d-e27251aca25f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578497719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.578497719
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3071204435
Short name T758
Test name
Test status
Simulation time 288864869205 ps
CPU time 516.06 seconds
Started Jul 18 06:50:14 PM PDT 24
Finished Jul 18 06:58:52 PM PDT 24
Peak memory 200160 kb
Host smart-27e5411e-d28a-49a4-a420-654d5c1fffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071204435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3071204435
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2070787906
Short name T838
Test name
Test status
Simulation time 20089814455 ps
CPU time 35.05 seconds
Started Jul 18 06:50:02 PM PDT 24
Finished Jul 18 06:50:41 PM PDT 24
Peak memory 200200 kb
Host smart-ad7e632c-896f-469e-98ef-095682ca5838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070787906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2070787906
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.231175326
Short name T612
Test name
Test status
Simulation time 176297405252 ps
CPU time 49.01 seconds
Started Jul 18 06:50:00 PM PDT 24
Finished Jul 18 06:50:53 PM PDT 24
Peak memory 200352 kb
Host smart-b9d4ba65-2974-4e5c-bd7b-1d8bb9cc4b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231175326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.231175326
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1412572697
Short name T751
Test name
Test status
Simulation time 22680778586 ps
CPU time 33.17 seconds
Started Jul 18 06:50:00 PM PDT 24
Finished Jul 18 06:50:38 PM PDT 24
Peak memory 200004 kb
Host smart-806fb5db-b702-4689-a11e-c32cd4259e85
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412572697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1412572697
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1719327856
Short name T495
Test name
Test status
Simulation time 50447196876 ps
CPU time 330.35 seconds
Started Jul 18 06:50:17 PM PDT 24
Finished Jul 18 06:55:49 PM PDT 24
Peak memory 200192 kb
Host smart-0babef15-e7f8-47f9-80eb-adbd97f4393c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719327856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1719327856
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.831585657
Short name T981
Test name
Test status
Simulation time 4174766473 ps
CPU time 3.27 seconds
Started Jul 18 06:50:20 PM PDT 24
Finished Jul 18 06:50:24 PM PDT 24
Peak memory 200120 kb
Host smart-724af3f9-5665-483f-8e45-29e57df5d2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831585657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.831585657
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2345880499
Short name T405
Test name
Test status
Simulation time 66762407203 ps
CPU time 164.21 seconds
Started Jul 18 06:50:00 PM PDT 24
Finished Jul 18 06:52:49 PM PDT 24
Peak memory 200424 kb
Host smart-07088e01-5a6e-49ce-a4a4-3cd6909cbfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345880499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2345880499
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.4088700743
Short name T678
Test name
Test status
Simulation time 13544347559 ps
CPU time 48.71 seconds
Started Jul 18 06:50:17 PM PDT 24
Finished Jul 18 06:51:08 PM PDT 24
Peak memory 200168 kb
Host smart-3267d968-67b4-49d3-ab9c-f3ee46607cc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4088700743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4088700743
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.4246970229
Short name T363
Test name
Test status
Simulation time 4829649397 ps
CPU time 7.22 seconds
Started Jul 18 06:50:02 PM PDT 24
Finished Jul 18 06:50:13 PM PDT 24
Peak memory 199352 kb
Host smart-d9b797bc-db71-451a-b2ed-f3654b82b028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246970229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.4246970229
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2077373294
Short name T750
Test name
Test status
Simulation time 115623206155 ps
CPU time 49.57 seconds
Started Jul 18 06:50:14 PM PDT 24
Finished Jul 18 06:51:06 PM PDT 24
Peak memory 200156 kb
Host smart-72927500-eff8-4c97-afc0-663ecd700a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077373294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2077373294
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1654047296
Short name T476
Test name
Test status
Simulation time 45133495449 ps
CPU time 15.47 seconds
Started Jul 18 06:50:17 PM PDT 24
Finished Jul 18 06:50:34 PM PDT 24
Peak memory 196692 kb
Host smart-3be6d807-3bb9-499b-b506-5490088add4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654047296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1654047296
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2630177658
Short name T348
Test name
Test status
Simulation time 490144175 ps
CPU time 1.77 seconds
Started Jul 18 06:50:14 PM PDT 24
Finished Jul 18 06:50:17 PM PDT 24
Peak memory 198952 kb
Host smart-88524970-1403-41e2-9ec2-f11fdef49ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630177658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2630177658
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.4205143289
Short name T34
Test name
Test status
Simulation time 25748441183 ps
CPU time 462.31 seconds
Started Jul 18 06:50:14 PM PDT 24
Finished Jul 18 06:57:58 PM PDT 24
Peak memory 213116 kb
Host smart-259bca18-a951-4374-9dd9-d6b5efdad29c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205143289 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.4205143289
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.806584419
Short name T839
Test name
Test status
Simulation time 6947445139 ps
CPU time 16.97 seconds
Started Jul 18 06:50:21 PM PDT 24
Finished Jul 18 06:50:40 PM PDT 24
Peak memory 199524 kb
Host smart-c8fcb146-cc47-4484-9dc3-4c511978ff90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806584419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.806584419
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2161473650
Short name T430
Test name
Test status
Simulation time 108818485620 ps
CPU time 39.32 seconds
Started Jul 18 06:50:02 PM PDT 24
Finished Jul 18 06:50:45 PM PDT 24
Peak memory 200132 kb
Host smart-72c5809b-aaa8-47b4-a0c0-ae6ac24249e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161473650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2161473650
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3114915521
Short name T362
Test name
Test status
Simulation time 44517259 ps
CPU time 0.56 seconds
Started Jul 18 06:50:15 PM PDT 24
Finished Jul 18 06:50:18 PM PDT 24
Peak memory 195572 kb
Host smart-bb194a6c-ac59-4547-9ecd-1aa3ddb3c182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114915521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3114915521
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3976131515
Short name T949
Test name
Test status
Simulation time 144913154697 ps
CPU time 139.33 seconds
Started Jul 18 06:50:21 PM PDT 24
Finished Jul 18 06:52:43 PM PDT 24
Peak memory 200192 kb
Host smart-3593bd39-7cf5-4146-be2b-9edc83b13c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976131515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3976131515
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3521238308
Short name T1014
Test name
Test status
Simulation time 18751604448 ps
CPU time 22.15 seconds
Started Jul 18 06:50:17 PM PDT 24
Finished Jul 18 06:50:41 PM PDT 24
Peak memory 199960 kb
Host smart-e9e3a8de-9785-47ab-9bc1-a0a1c7a208e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521238308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3521238308
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3659214254
Short name T214
Test name
Test status
Simulation time 26873897689 ps
CPU time 18.37 seconds
Started Jul 18 06:50:20 PM PDT 24
Finished Jul 18 06:50:40 PM PDT 24
Peak memory 200196 kb
Host smart-7d1588bc-66e4-4de2-b341-d263b77d1946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659214254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3659214254
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.4151365008
Short name T1156
Test name
Test status
Simulation time 9369534665 ps
CPU time 20.08 seconds
Started Jul 18 06:50:21 PM PDT 24
Finished Jul 18 06:50:43 PM PDT 24
Peak memory 200076 kb
Host smart-b3837bde-d62e-4dfe-b393-8a87b79116e1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151365008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.4151365008
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2167083096
Short name T1066
Test name
Test status
Simulation time 103904331290 ps
CPU time 122.33 seconds
Started Jul 18 06:50:15 PM PDT 24
Finished Jul 18 06:52:20 PM PDT 24
Peak memory 200160 kb
Host smart-95ec40a7-1bde-45da-9196-8e1ab276260b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167083096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2167083096
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1161251732
Short name T338
Test name
Test status
Simulation time 1746148381 ps
CPU time 1.69 seconds
Started Jul 18 06:50:22 PM PDT 24
Finished Jul 18 06:50:26 PM PDT 24
Peak memory 197304 kb
Host smart-15690f8f-1fa3-4674-826a-3869c030829d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161251732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1161251732
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.484049192
Short name T389
Test name
Test status
Simulation time 54317550620 ps
CPU time 92.79 seconds
Started Jul 18 06:50:17 PM PDT 24
Finished Jul 18 06:51:51 PM PDT 24
Peak memory 200308 kb
Host smart-2efe754f-058c-4065-af4c-2e21592bdedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484049192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.484049192
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2371785179
Short name T808
Test name
Test status
Simulation time 4652172514 ps
CPU time 240.26 seconds
Started Jul 18 06:50:14 PM PDT 24
Finished Jul 18 06:54:17 PM PDT 24
Peak memory 200176 kb
Host smart-de6e0a28-7f9c-403b-a82a-956424be4a9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371785179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2371785179
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3156179058
Short name T411
Test name
Test status
Simulation time 3666411710 ps
CPU time 27.94 seconds
Started Jul 18 06:50:14 PM PDT 24
Finished Jul 18 06:50:44 PM PDT 24
Peak memory 199280 kb
Host smart-68be3de1-11a1-429d-bae2-132a22deb7f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156179058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3156179058
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3072053642
Short name T608
Test name
Test status
Simulation time 132845126694 ps
CPU time 69.17 seconds
Started Jul 18 06:50:21 PM PDT 24
Finished Jul 18 06:51:31 PM PDT 24
Peak memory 200200 kb
Host smart-0ca3ee2f-1bf9-4030-a73d-cb2edf5d91fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072053642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3072053642
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3578758562
Short name T996
Test name
Test status
Simulation time 40802146684 ps
CPU time 28.11 seconds
Started Jul 18 06:50:14 PM PDT 24
Finished Jul 18 06:50:45 PM PDT 24
Peak memory 196212 kb
Host smart-aca43f33-d3eb-48ea-abae-342bca7c12d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578758562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3578758562
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.4151765637
Short name T968
Test name
Test status
Simulation time 429934062 ps
CPU time 1.84 seconds
Started Jul 18 06:50:14 PM PDT 24
Finished Jul 18 06:50:19 PM PDT 24
Peak memory 198912 kb
Host smart-9c937804-056b-44a2-869a-ae33383ee5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151765637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.4151765637
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1190493257
Short name T619
Test name
Test status
Simulation time 82663910813 ps
CPU time 501.17 seconds
Started Jul 18 06:50:21 PM PDT 24
Finished Jul 18 06:58:45 PM PDT 24
Peak memory 216728 kb
Host smart-b300b113-5660-4ab0-8d1d-87897bc4ed27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190493257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1190493257
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1871096864
Short name T747
Test name
Test status
Simulation time 6269434016 ps
CPU time 10.91 seconds
Started Jul 18 06:50:14 PM PDT 24
Finished Jul 18 06:50:27 PM PDT 24
Peak memory 199604 kb
Host smart-fa1aa274-140c-46fc-ba49-42d5fcacf063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871096864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1871096864
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1981841844
Short name T556
Test name
Test status
Simulation time 39175899116 ps
CPU time 34.13 seconds
Started Jul 18 06:50:15 PM PDT 24
Finished Jul 18 06:50:52 PM PDT 24
Peak memory 200140 kb
Host smart-902fbb5b-9ad9-46a8-989a-943c9a357347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981841844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1981841844
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2354628648
Short name T1038
Test name
Test status
Simulation time 13433221 ps
CPU time 0.57 seconds
Started Jul 18 06:50:29 PM PDT 24
Finished Jul 18 06:50:33 PM PDT 24
Peak memory 195588 kb
Host smart-25a685e5-f6f9-4ef9-89a2-fc55a24b5c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354628648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2354628648
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2853651769
Short name T383
Test name
Test status
Simulation time 44913213962 ps
CPU time 64.27 seconds
Started Jul 18 06:50:21 PM PDT 24
Finished Jul 18 06:51:28 PM PDT 24
Peak memory 200120 kb
Host smart-d153f9d8-f42c-4ec2-945c-9f60543cdebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853651769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2853651769
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1370176424
Short name T159
Test name
Test status
Simulation time 38733791363 ps
CPU time 13.58 seconds
Started Jul 18 06:50:14 PM PDT 24
Finished Jul 18 06:50:30 PM PDT 24
Peak memory 199960 kb
Host smart-ad64013d-414b-47af-b265-a13153c1abf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370176424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1370176424
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2549890922
Short name T264
Test name
Test status
Simulation time 198623029146 ps
CPU time 324.57 seconds
Started Jul 18 06:50:22 PM PDT 24
Finished Jul 18 06:55:48 PM PDT 24
Peak memory 200288 kb
Host smart-9802b7f4-d834-434a-8575-8b9f708ca39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549890922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2549890922
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3696658083
Short name T1058
Test name
Test status
Simulation time 11196944213 ps
CPU time 1.61 seconds
Started Jul 18 06:50:18 PM PDT 24
Finished Jul 18 06:50:21 PM PDT 24
Peak memory 198532 kb
Host smart-ee3caf99-5f94-45e1-8c02-fe2bc537c72c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696658083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3696658083
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1034576748
Short name T407
Test name
Test status
Simulation time 104124738683 ps
CPU time 399.16 seconds
Started Jul 18 06:50:14 PM PDT 24
Finished Jul 18 06:56:56 PM PDT 24
Peak memory 200172 kb
Host smart-f201d883-d7cd-4d64-b6d3-ad26796c9053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034576748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1034576748
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1256637365
Short name T539
Test name
Test status
Simulation time 4541963277 ps
CPU time 3.68 seconds
Started Jul 18 06:50:22 PM PDT 24
Finished Jul 18 06:50:28 PM PDT 24
Peak memory 200116 kb
Host smart-27920c9d-87cc-4e7c-96b5-4a382429bcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256637365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1256637365
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.497981502
Short name T511
Test name
Test status
Simulation time 159542088410 ps
CPU time 18.75 seconds
Started Jul 18 06:50:22 PM PDT 24
Finished Jul 18 06:50:43 PM PDT 24
Peak memory 199540 kb
Host smart-a0536e78-c64b-49d9-a7d8-13f0ae31c2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497981502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.497981502
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.564654354
Short name T631
Test name
Test status
Simulation time 20744504903 ps
CPU time 204.3 seconds
Started Jul 18 06:50:15 PM PDT 24
Finished Jul 18 06:53:41 PM PDT 24
Peak memory 200204 kb
Host smart-e4302e98-9f8a-40c3-a6fe-4967f1588fa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564654354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.564654354
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.787047460
Short name T663
Test name
Test status
Simulation time 3189607157 ps
CPU time 23.29 seconds
Started Jul 18 06:50:15 PM PDT 24
Finished Jul 18 06:50:41 PM PDT 24
Peak memory 199296 kb
Host smart-1585c283-0d5a-43f8-8007-d6bf4217b6a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787047460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.787047460
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1414491396
Short name T149
Test name
Test status
Simulation time 89982506935 ps
CPU time 24.13 seconds
Started Jul 18 06:50:15 PM PDT 24
Finished Jul 18 06:50:41 PM PDT 24
Peak memory 200096 kb
Host smart-944c487c-313a-4949-855c-fbb00b186b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414491396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1414491396
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2636217404
Short name T551
Test name
Test status
Simulation time 4918084670 ps
CPU time 1.57 seconds
Started Jul 18 06:50:14 PM PDT 24
Finished Jul 18 06:50:18 PM PDT 24
Peak memory 196496 kb
Host smart-8779364a-c671-4be1-9e83-68d420a78ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636217404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2636217404
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1246126102
Short name T570
Test name
Test status
Simulation time 628678724 ps
CPU time 1.65 seconds
Started Jul 18 06:50:21 PM PDT 24
Finished Jul 18 06:50:25 PM PDT 24
Peak memory 199012 kb
Host smart-cada5c5d-d9aa-480d-8189-fd0464312578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246126102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1246126102
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2508914752
Short name T962
Test name
Test status
Simulation time 121604152175 ps
CPU time 1142.07 seconds
Started Jul 18 06:50:29 PM PDT 24
Finished Jul 18 07:09:33 PM PDT 24
Peak memory 208524 kb
Host smart-5e3d602a-32c9-4b73-968d-42ac9f035299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508914752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2508914752
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3103236889
Short name T15
Test name
Test status
Simulation time 29455965677 ps
CPU time 293.79 seconds
Started Jul 18 06:50:15 PM PDT 24
Finished Jul 18 06:55:11 PM PDT 24
Peak memory 215940 kb
Host smart-74034012-3c5b-4f2c-80b8-f5942c9a9c39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103236889 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3103236889
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2285970363
Short name T402
Test name
Test status
Simulation time 805726604 ps
CPU time 1.86 seconds
Started Jul 18 06:50:21 PM PDT 24
Finished Jul 18 06:50:25 PM PDT 24
Peak memory 198632 kb
Host smart-b8fed6a9-cf20-4f8d-b304-d0448eb9929f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285970363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2285970363
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1338547461
Short name T458
Test name
Test status
Simulation time 76277084599 ps
CPU time 228.57 seconds
Started Jul 18 06:50:21 PM PDT 24
Finished Jul 18 06:54:12 PM PDT 24
Peak memory 200188 kb
Host smart-00b87d0e-829d-4c12-b398-1d03da401e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338547461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1338547461
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.910095037
Short name T29
Test name
Test status
Simulation time 48736558 ps
CPU time 0.56 seconds
Started Jul 18 06:50:28 PM PDT 24
Finished Jul 18 06:50:30 PM PDT 24
Peak memory 195872 kb
Host smart-a32e8ae9-b3de-4524-bf79-8369d0e73ac1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910095037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.910095037
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3870056768
Short name T318
Test name
Test status
Simulation time 15876852244 ps
CPU time 22.64 seconds
Started Jul 18 06:50:29 PM PDT 24
Finished Jul 18 06:50:55 PM PDT 24
Peak memory 199948 kb
Host smart-fa66d72a-ea31-4f09-9b80-6db9599b3331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870056768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3870056768
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2401360402
Short name T1180
Test name
Test status
Simulation time 160285073446 ps
CPU time 128.9 seconds
Started Jul 18 06:50:31 PM PDT 24
Finished Jul 18 06:52:44 PM PDT 24
Peak memory 200176 kb
Host smart-697eb269-dc0f-48b5-aee7-7b3b3207a13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401360402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2401360402
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3758245389
Short name T983
Test name
Test status
Simulation time 72737981541 ps
CPU time 32.76 seconds
Started Jul 18 06:50:32 PM PDT 24
Finished Jul 18 06:51:09 PM PDT 24
Peak memory 200148 kb
Host smart-60de1b60-2926-494a-bb0d-a4a64d334f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758245389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3758245389
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1117587411
Short name T943
Test name
Test status
Simulation time 272576912540 ps
CPU time 96.5 seconds
Started Jul 18 06:50:28 PM PDT 24
Finished Jul 18 06:52:06 PM PDT 24
Peak memory 199400 kb
Host smart-da5c8611-98cd-422b-b9bf-440ac895d961
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117587411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1117587411
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1079309126
Short name T356
Test name
Test status
Simulation time 170617654846 ps
CPU time 1457.96 seconds
Started Jul 18 06:50:31 PM PDT 24
Finished Jul 18 07:14:54 PM PDT 24
Peak memory 200180 kb
Host smart-4112d289-a201-4059-ad99-8b0e80b675ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1079309126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1079309126
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3659200985
Short name T587
Test name
Test status
Simulation time 13242824574 ps
CPU time 6.17 seconds
Started Jul 18 06:50:30 PM PDT 24
Finished Jul 18 06:50:41 PM PDT 24
Peak memory 198820 kb
Host smart-8bfe6688-0bd9-4fca-b8b9-a10d35f4c727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659200985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3659200985
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.968210909
Short name T654
Test name
Test status
Simulation time 120970209025 ps
CPU time 178.37 seconds
Started Jul 18 06:50:32 PM PDT 24
Finished Jul 18 06:53:35 PM PDT 24
Peak memory 200176 kb
Host smart-283c0a13-4507-4e92-9d5d-24294589c82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968210909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.968210909
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1838626153
Short name T344
Test name
Test status
Simulation time 3153665462 ps
CPU time 171.7 seconds
Started Jul 18 06:50:28 PM PDT 24
Finished Jul 18 06:53:22 PM PDT 24
Peak memory 200176 kb
Host smart-987f50e3-e352-4532-8daa-77c26165b77e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838626153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1838626153
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.4143838343
Short name T771
Test name
Test status
Simulation time 3807544673 ps
CPU time 7.02 seconds
Started Jul 18 06:50:30 PM PDT 24
Finished Jul 18 06:50:41 PM PDT 24
Peak memory 198272 kb
Host smart-da2ee58d-77b7-4a9b-9543-b4ccd4183f3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4143838343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.4143838343
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2671301280
Short name T921
Test name
Test status
Simulation time 51614500009 ps
CPU time 16.44 seconds
Started Jul 18 06:50:28 PM PDT 24
Finished Jul 18 06:50:46 PM PDT 24
Peak memory 200116 kb
Host smart-fd750bd8-c17b-4077-9077-0972c162cc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671301280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2671301280
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3815741802
Short name T371
Test name
Test status
Simulation time 28393843799 ps
CPU time 11.72 seconds
Started Jul 18 06:50:29 PM PDT 24
Finished Jul 18 06:50:42 PM PDT 24
Peak memory 196500 kb
Host smart-ae47c0a9-481d-49cf-89a2-d3a479cf1c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815741802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3815741802
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1392641099
Short name T288
Test name
Test status
Simulation time 840399287 ps
CPU time 4.53 seconds
Started Jul 18 06:50:32 PM PDT 24
Finished Jul 18 06:50:41 PM PDT 24
Peak memory 199756 kb
Host smart-f31a20bb-4e9a-493b-9274-9820763e98a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392641099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1392641099
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3937129756
Short name T951
Test name
Test status
Simulation time 267711570287 ps
CPU time 537.61 seconds
Started Jul 18 06:50:30 PM PDT 24
Finished Jul 18 06:59:32 PM PDT 24
Peak memory 200140 kb
Host smart-995dc9cf-d139-4d7b-a36f-de61e16947ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937129756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3937129756
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1251091012
Short name T537
Test name
Test status
Simulation time 344009513331 ps
CPU time 822.49 seconds
Started Jul 18 06:50:30 PM PDT 24
Finished Jul 18 07:04:17 PM PDT 24
Peak memory 225004 kb
Host smart-8bee1f31-5ede-47dd-8d90-ee92aaee4f49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251091012 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1251091012
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3712277921
Short name T390
Test name
Test status
Simulation time 1950828743 ps
CPU time 2.37 seconds
Started Jul 18 06:50:28 PM PDT 24
Finished Jul 18 06:50:32 PM PDT 24
Peak memory 200312 kb
Host smart-046a36aa-3cf9-4028-9a2b-1d1ce89b0856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712277921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3712277921
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.260376670
Short name T852
Test name
Test status
Simulation time 342420021111 ps
CPU time 108.37 seconds
Started Jul 18 06:50:30 PM PDT 24
Finished Jul 18 06:52:22 PM PDT 24
Peak memory 200156 kb
Host smart-3b2e1458-3aab-4648-9f6b-2d51e756f6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260376670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.260376670
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.155290355
Short name T1132
Test name
Test status
Simulation time 10604958 ps
CPU time 0.55 seconds
Started Jul 18 06:47:53 PM PDT 24
Finished Jul 18 06:47:58 PM PDT 24
Peak memory 194564 kb
Host smart-8da2b857-8ef8-4205-b813-8cfaf9429963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155290355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.155290355
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2172764340
Short name T682
Test name
Test status
Simulation time 28414133090 ps
CPU time 13.22 seconds
Started Jul 18 06:47:55 PM PDT 24
Finished Jul 18 06:48:11 PM PDT 24
Peak memory 200384 kb
Host smart-c0bf6907-cd98-42cf-8dba-6c8901e1dc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172764340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2172764340
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1092226388
Short name T1020
Test name
Test status
Simulation time 28213887933 ps
CPU time 46.47 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:48:55 PM PDT 24
Peak memory 200040 kb
Host smart-5d4d5996-3c37-4ac0-adbb-ba3cc34ca822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092226388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1092226388
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2167402902
Short name T43
Test name
Test status
Simulation time 68093142192 ps
CPU time 122.38 seconds
Started Jul 18 06:48:02 PM PDT 24
Finished Jul 18 06:50:07 PM PDT 24
Peak memory 200128 kb
Host smart-dcc08562-55fc-4679-8383-cde3b47a2e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167402902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2167402902
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.203696164
Short name T765
Test name
Test status
Simulation time 9250745702 ps
CPU time 3.58 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:48:06 PM PDT 24
Peak memory 200184 kb
Host smart-436faab4-4b0d-475a-b0f7-89ca2bd1ca08
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203696164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.203696164
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.4160395433
Short name T718
Test name
Test status
Simulation time 54044230640 ps
CPU time 449.19 seconds
Started Jul 18 06:47:54 PM PDT 24
Finished Jul 18 06:55:27 PM PDT 24
Peak memory 200164 kb
Host smart-c44cbd1e-238a-48b9-a336-574d525a0d00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4160395433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.4160395433
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2385213194
Short name T436
Test name
Test status
Simulation time 7415867825 ps
CPU time 5.06 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:48:13 PM PDT 24
Peak memory 197900 kb
Host smart-a8fd46bd-0790-438c-b6db-86157f886ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385213194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2385213194
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.4057457432
Short name T913
Test name
Test status
Simulation time 6373684620 ps
CPU time 10.96 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:48:19 PM PDT 24
Peak memory 199860 kb
Host smart-aa550f8f-c3b3-4f45-9a84-6c8bab7990e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057457432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.4057457432
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2242040141
Short name T978
Test name
Test status
Simulation time 7053833618 ps
CPU time 88.91 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:49:37 PM PDT 24
Peak memory 199744 kb
Host smart-7e0c0688-7348-457b-bc1e-94703da56ff0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2242040141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2242040141
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3885124924
Short name T565
Test name
Test status
Simulation time 3918385006 ps
CPU time 32.73 seconds
Started Jul 18 06:47:52 PM PDT 24
Finished Jul 18 06:48:30 PM PDT 24
Peak memory 200160 kb
Host smart-3fb53680-92fa-4ac2-b3a3-09d624a6923f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885124924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3885124924
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.757873228
Short name T849
Test name
Test status
Simulation time 29507525273 ps
CPU time 40.42 seconds
Started Jul 18 06:48:06 PM PDT 24
Finished Jul 18 06:48:50 PM PDT 24
Peak memory 199872 kb
Host smart-ef3252e8-9c52-4a17-9f27-b6f4220f46a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757873228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.757873228
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2260615787
Short name T540
Test name
Test status
Simulation time 2617176097 ps
CPU time 2.57 seconds
Started Jul 18 06:47:52 PM PDT 24
Finished Jul 18 06:48:00 PM PDT 24
Peak memory 196656 kb
Host smart-7bf7fc2e-01e9-4575-93f7-79d55ed88b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260615787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2260615787
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1418238786
Short name T32
Test name
Test status
Simulation time 60555166 ps
CPU time 0.89 seconds
Started Jul 18 06:47:53 PM PDT 24
Finished Jul 18 06:47:59 PM PDT 24
Peak memory 218596 kb
Host smart-db555aaa-b7e0-48ea-bab7-e5a94677de18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418238786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1418238786
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1997748622
Short name T550
Test name
Test status
Simulation time 299799915 ps
CPU time 1.54 seconds
Started Jul 18 06:47:54 PM PDT 24
Finished Jul 18 06:48:00 PM PDT 24
Peak memory 198804 kb
Host smart-98796ed3-6c21-433a-82f8-e914fd953fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997748622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1997748622
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1249983854
Short name T173
Test name
Test status
Simulation time 534224029431 ps
CPU time 369.85 seconds
Started Jul 18 06:47:54 PM PDT 24
Finished Jul 18 06:54:08 PM PDT 24
Peak memory 208688 kb
Host smart-23d49aaf-5293-4aaa-96b5-bdad53a850a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249983854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1249983854
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.249344808
Short name T745
Test name
Test status
Simulation time 74229992974 ps
CPU time 543.7 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:57:08 PM PDT 24
Peak memory 216824 kb
Host smart-3d732160-426c-4213-912f-67d555babce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249344808 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.249344808
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2683955606
Short name T427
Test name
Test status
Simulation time 7857315221 ps
CPU time 9.6 seconds
Started Jul 18 06:47:56 PM PDT 24
Finished Jul 18 06:48:08 PM PDT 24
Peak memory 200020 kb
Host smart-5b23f2fe-79b3-4ea1-843c-dfab633706b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683955606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2683955606
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1561754412
Short name T971
Test name
Test status
Simulation time 32996622212 ps
CPU time 27.22 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:48:31 PM PDT 24
Peak memory 200184 kb
Host smart-9e6d0083-ae26-4cdf-aea0-afa4f6bf9706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561754412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1561754412
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3364042729
Short name T333
Test name
Test status
Simulation time 38594467 ps
CPU time 0.55 seconds
Started Jul 18 06:50:29 PM PDT 24
Finished Jul 18 06:50:32 PM PDT 24
Peak memory 195024 kb
Host smart-1036e169-6c80-4393-b153-850b6caeb851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364042729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3364042729
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2445969451
Short name T179
Test name
Test status
Simulation time 93455181390 ps
CPU time 49.89 seconds
Started Jul 18 06:50:27 PM PDT 24
Finished Jul 18 06:51:18 PM PDT 24
Peak memory 200176 kb
Host smart-afbc2651-7c75-4994-9ad6-8d966fed38f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445969451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2445969451
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3053912474
Short name T500
Test name
Test status
Simulation time 15249137022 ps
CPU time 33.15 seconds
Started Jul 18 06:50:29 PM PDT 24
Finished Jul 18 06:51:06 PM PDT 24
Peak memory 200140 kb
Host smart-9c1f2058-8940-439e-85b4-f64357c9045c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053912474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3053912474
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.25747346
Short name T1095
Test name
Test status
Simulation time 118684724935 ps
CPU time 115.89 seconds
Started Jul 18 06:50:32 PM PDT 24
Finished Jul 18 06:52:32 PM PDT 24
Peak memory 200196 kb
Host smart-4e49d9de-aa47-4879-bc53-cc979aaec461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25747346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.25747346
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3154204899
Short name T514
Test name
Test status
Simulation time 36678303936 ps
CPU time 55.88 seconds
Started Jul 18 06:50:32 PM PDT 24
Finished Jul 18 06:51:32 PM PDT 24
Peak memory 196104 kb
Host smart-a2b4dc3c-e403-4029-8a3a-437c0df586c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154204899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3154204899
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.33072884
Short name T349
Test name
Test status
Simulation time 151775771189 ps
CPU time 390.08 seconds
Started Jul 18 06:50:29 PM PDT 24
Finished Jul 18 06:57:03 PM PDT 24
Peak memory 200168 kb
Host smart-5aa74a26-7894-4e9f-a719-b36dfc401a80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33072884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.33072884
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.16112053
Short name T830
Test name
Test status
Simulation time 1577510226 ps
CPU time 1.89 seconds
Started Jul 18 06:50:29 PM PDT 24
Finished Jul 18 06:50:34 PM PDT 24
Peak memory 197692 kb
Host smart-02fe5e80-2316-4339-bf8a-ae1f060a8464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16112053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.16112053
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2732622940
Short name T396
Test name
Test status
Simulation time 14576182759 ps
CPU time 5.92 seconds
Started Jul 18 06:50:32 PM PDT 24
Finished Jul 18 06:50:42 PM PDT 24
Peak memory 194788 kb
Host smart-e3fe77d9-be42-4c65-9578-f55566fd25fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732622940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2732622940
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3817096046
Short name T575
Test name
Test status
Simulation time 24801720792 ps
CPU time 323.69 seconds
Started Jul 18 06:50:28 PM PDT 24
Finished Jul 18 06:55:54 PM PDT 24
Peak memory 200076 kb
Host smart-99d65d3e-c672-4b7b-a73e-1a5afe2a6ef9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817096046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3817096046
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3932826063
Short name T900
Test name
Test status
Simulation time 1916279627 ps
CPU time 5.22 seconds
Started Jul 18 06:50:32 PM PDT 24
Finished Jul 18 06:50:42 PM PDT 24
Peak memory 198908 kb
Host smart-49c0867e-42b5-4bec-8eec-4caea3a96927
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3932826063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3932826063
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2433297710
Short name T471
Test name
Test status
Simulation time 160504695949 ps
CPU time 51.51 seconds
Started Jul 18 06:50:30 PM PDT 24
Finished Jul 18 06:51:27 PM PDT 24
Peak memory 200088 kb
Host smart-8fb76387-8135-4067-befc-74b1dd4850b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433297710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2433297710
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3792799448
Short name T298
Test name
Test status
Simulation time 6246866594 ps
CPU time 3.02 seconds
Started Jul 18 06:50:31 PM PDT 24
Finished Jul 18 06:50:38 PM PDT 24
Peak memory 197060 kb
Host smart-57810a2c-045e-424e-8c02-c4cceb2ec040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792799448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3792799448
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.342714322
Short name T802
Test name
Test status
Simulation time 720057869 ps
CPU time 2.25 seconds
Started Jul 18 06:50:28 PM PDT 24
Finished Jul 18 06:50:32 PM PDT 24
Peak memory 200188 kb
Host smart-47343aba-1bc2-4624-a48c-c733f566674c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342714322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.342714322
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2873254444
Short name T954
Test name
Test status
Simulation time 196648577573 ps
CPU time 719 seconds
Started Jul 18 06:50:30 PM PDT 24
Finished Jul 18 07:02:33 PM PDT 24
Peak memory 200064 kb
Host smart-02fb8980-78e4-4236-8c21-b9ddefd0c9dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873254444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2873254444
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2961200433
Short name T554
Test name
Test status
Simulation time 65360147443 ps
CPU time 579.65 seconds
Started Jul 18 06:50:30 PM PDT 24
Finished Jul 18 07:00:13 PM PDT 24
Peak memory 216692 kb
Host smart-3f19e6af-df9b-46c5-ae7d-8759420f8781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961200433 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2961200433
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3013365268
Short name T590
Test name
Test status
Simulation time 541505444 ps
CPU time 1.18 seconds
Started Jul 18 06:50:29 PM PDT 24
Finished Jul 18 06:50:33 PM PDT 24
Peak memory 198280 kb
Host smart-9b8086b0-69e9-4081-9a06-c2885792dc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013365268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3013365268
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1480113186
Short name T1075
Test name
Test status
Simulation time 107533864968 ps
CPU time 76.63 seconds
Started Jul 18 06:50:32 PM PDT 24
Finished Jul 18 06:51:53 PM PDT 24
Peak memory 200160 kb
Host smart-0198cc56-be27-4c75-a353-05e08ae37c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480113186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1480113186
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3712837815
Short name T1124
Test name
Test status
Simulation time 48511489 ps
CPU time 0.56 seconds
Started Jul 18 06:50:44 PM PDT 24
Finished Jul 18 06:50:47 PM PDT 24
Peak memory 195876 kb
Host smart-735bf276-1f97-416c-b328-d606c811daf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712837815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3712837815
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3132010218
Short name T786
Test name
Test status
Simulation time 49283531196 ps
CPU time 25.91 seconds
Started Jul 18 06:50:32 PM PDT 24
Finished Jul 18 06:51:02 PM PDT 24
Peak memory 200044 kb
Host smart-172ae521-0d82-48c6-ad03-c9f56e74f5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132010218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3132010218
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2066567998
Short name T692
Test name
Test status
Simulation time 18913275547 ps
CPU time 9.23 seconds
Started Jul 18 06:50:30 PM PDT 24
Finished Jul 18 06:50:44 PM PDT 24
Peak memory 199948 kb
Host smart-2ec054bb-75de-4458-a523-e487e8df7d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066567998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2066567998
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3632594140
Short name T279
Test name
Test status
Simulation time 58859660873 ps
CPU time 88.87 seconds
Started Jul 18 06:50:32 PM PDT 24
Finished Jul 18 06:52:05 PM PDT 24
Peak memory 199896 kb
Host smart-0d1701bf-9140-47f9-a110-5f1a8051c09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632594140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3632594140
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.848249626
Short name T1045
Test name
Test status
Simulation time 18801431863 ps
CPU time 25.34 seconds
Started Jul 18 06:50:45 PM PDT 24
Finished Jul 18 06:51:13 PM PDT 24
Peak memory 199544 kb
Host smart-0012c53c-30ac-4567-9b55-410fd0b6c625
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848249626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.848249626
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1863345550
Short name T746
Test name
Test status
Simulation time 155698499170 ps
CPU time 550.3 seconds
Started Jul 18 06:50:50 PM PDT 24
Finished Jul 18 07:00:02 PM PDT 24
Peak memory 200172 kb
Host smart-bb71e2e7-5976-4fa1-9468-433518457174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863345550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1863345550
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.985278111
Short name T470
Test name
Test status
Simulation time 9122139072 ps
CPU time 16.72 seconds
Started Jul 18 06:50:46 PM PDT 24
Finished Jul 18 06:51:06 PM PDT 24
Peak memory 199800 kb
Host smart-0feb9b72-83c0-457d-a638-88a5a3715846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985278111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.985278111
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1014940242
Short name T549
Test name
Test status
Simulation time 435596176570 ps
CPU time 48.98 seconds
Started Jul 18 06:50:46 PM PDT 24
Finished Jul 18 06:51:37 PM PDT 24
Peak memory 208452 kb
Host smart-9733556b-3228-4537-a12c-558e5f635c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014940242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1014940242
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1079259422
Short name T594
Test name
Test status
Simulation time 18414284960 ps
CPU time 259.25 seconds
Started Jul 18 06:50:46 PM PDT 24
Finished Jul 18 06:55:07 PM PDT 24
Peak memory 200132 kb
Host smart-7d17cd9b-858a-4de6-8f9b-3fae0896ba82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1079259422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1079259422
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1329441550
Short name T1165
Test name
Test status
Simulation time 1808963368 ps
CPU time 12.07 seconds
Started Jul 18 06:50:32 PM PDT 24
Finished Jul 18 06:50:49 PM PDT 24
Peak memory 198228 kb
Host smart-52f50f66-5827-44e7-90ec-b5acf334fdcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329441550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1329441550
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2070854324
Short name T413
Test name
Test status
Simulation time 48196786461 ps
CPU time 18.58 seconds
Started Jul 18 06:50:44 PM PDT 24
Finished Jul 18 06:51:04 PM PDT 24
Peak memory 200132 kb
Host smart-cef327e8-596a-4be6-932d-ab513d39aa8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070854324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2070854324
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3640593433
Short name T964
Test name
Test status
Simulation time 5117944000 ps
CPU time 7.65 seconds
Started Jul 18 06:50:46 PM PDT 24
Finished Jul 18 06:50:57 PM PDT 24
Peak memory 196984 kb
Host smart-b54450c1-93f5-4707-a44b-d26fbe19a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640593433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3640593433
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3500596773
Short name T331
Test name
Test status
Simulation time 90713968 ps
CPU time 0.8 seconds
Started Jul 18 06:50:31 PM PDT 24
Finished Jul 18 06:50:36 PM PDT 24
Peak memory 197008 kb
Host smart-416ecfb0-f918-4063-82d6-786dd783d8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500596773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3500596773
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.677165422
Short name T553
Test name
Test status
Simulation time 58251070968 ps
CPU time 202.08 seconds
Started Jul 18 06:50:45 PM PDT 24
Finished Jul 18 06:54:09 PM PDT 24
Peak memory 200180 kb
Host smart-0e8a6caa-1561-4e72-89cc-6a935dd53fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677165422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.677165422
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.862987738
Short name T1123
Test name
Test status
Simulation time 104858796910 ps
CPU time 288.47 seconds
Started Jul 18 06:50:48 PM PDT 24
Finished Jul 18 06:55:39 PM PDT 24
Peak memory 216688 kb
Host smart-57f8d340-616c-4ee0-834f-503f5cf14bb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862987738 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.862987738
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1029653037
Short name T743
Test name
Test status
Simulation time 2284168062 ps
CPU time 1.86 seconds
Started Jul 18 06:50:47 PM PDT 24
Finished Jul 18 06:50:52 PM PDT 24
Peak memory 198648 kb
Host smart-070106a7-2093-4961-8921-678dbc3d84cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029653037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1029653037
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2230759689
Short name T277
Test name
Test status
Simulation time 39466830137 ps
CPU time 42.48 seconds
Started Jul 18 06:50:31 PM PDT 24
Finished Jul 18 06:51:18 PM PDT 24
Peak memory 200172 kb
Host smart-f5d528ae-7dfe-4560-a1d3-f4dfa137b392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230759689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2230759689
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3029687282
Short name T941
Test name
Test status
Simulation time 12760514 ps
CPU time 0.57 seconds
Started Jul 18 06:50:51 PM PDT 24
Finished Jul 18 06:50:53 PM PDT 24
Peak memory 195564 kb
Host smart-1a16ab6f-e57c-426e-a0c8-c29c2d580b40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029687282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3029687282
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1506014022
Short name T131
Test name
Test status
Simulation time 98222293610 ps
CPU time 154.1 seconds
Started Jul 18 06:50:43 PM PDT 24
Finished Jul 18 06:53:19 PM PDT 24
Peak memory 200184 kb
Host smart-c2fe2c32-ebf7-4f17-8097-d4a4181bfc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506014022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1506014022
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1232853429
Short name T1057
Test name
Test status
Simulation time 102333487021 ps
CPU time 146.5 seconds
Started Jul 18 06:50:47 PM PDT 24
Finished Jul 18 06:53:16 PM PDT 24
Peak memory 200204 kb
Host smart-c7d7e319-9f7b-4bf1-a542-88e86077b432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232853429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1232853429
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3170718264
Short name T434
Test name
Test status
Simulation time 23995958683 ps
CPU time 41.89 seconds
Started Jul 18 06:50:49 PM PDT 24
Finished Jul 18 06:51:33 PM PDT 24
Peak memory 200124 kb
Host smart-135108bd-d401-4f2a-881d-a43e5619b517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170718264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3170718264
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3522812980
Short name T488
Test name
Test status
Simulation time 75274048987 ps
CPU time 134.83 seconds
Started Jul 18 06:50:48 PM PDT 24
Finished Jul 18 06:53:06 PM PDT 24
Peak memory 200172 kb
Host smart-bdf44714-8b7e-49d0-8f85-b8e84d49f489
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522812980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3522812980
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3882346321
Short name T466
Test name
Test status
Simulation time 100380602728 ps
CPU time 637.22 seconds
Started Jul 18 06:50:46 PM PDT 24
Finished Jul 18 07:01:25 PM PDT 24
Peak memory 200092 kb
Host smart-08c96224-4094-4a59-94cd-5d653b2a4170
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882346321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3882346321
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2507543201
Short name T467
Test name
Test status
Simulation time 1138553785 ps
CPU time 1.71 seconds
Started Jul 18 06:50:44 PM PDT 24
Finished Jul 18 06:50:48 PM PDT 24
Peak memory 196424 kb
Host smart-22deed9c-8fb0-46b2-8381-e8960e948412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507543201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2507543201
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3347264215
Short name T269
Test name
Test status
Simulation time 13204153081 ps
CPU time 32.32 seconds
Started Jul 18 06:50:48 PM PDT 24
Finished Jul 18 06:51:23 PM PDT 24
Peak memory 198252 kb
Host smart-cfcf8a85-5438-4708-824d-dd21e51b60fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347264215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3347264215
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.188015487
Short name T255
Test name
Test status
Simulation time 15898366167 ps
CPU time 667.59 seconds
Started Jul 18 06:50:46 PM PDT 24
Finished Jul 18 07:01:55 PM PDT 24
Peak memory 200204 kb
Host smart-f57ffc33-4084-48cd-8dda-69038f22e09b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188015487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.188015487
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2995999636
Short name T391
Test name
Test status
Simulation time 3605213785 ps
CPU time 26.81 seconds
Started Jul 18 06:50:42 PM PDT 24
Finished Jul 18 06:51:10 PM PDT 24
Peak memory 198172 kb
Host smart-258caa7d-77b6-4783-b964-87dc33dbf347
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995999636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2995999636
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2617204251
Short name T636
Test name
Test status
Simulation time 61031667413 ps
CPU time 83.15 seconds
Started Jul 18 06:50:43 PM PDT 24
Finished Jul 18 06:52:08 PM PDT 24
Peak memory 200200 kb
Host smart-a6e1886d-bc1c-4117-9d14-035a38af5753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617204251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2617204251
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1156644466
Short name T401
Test name
Test status
Simulation time 1825162784 ps
CPU time 1.34 seconds
Started Jul 18 06:50:44 PM PDT 24
Finished Jul 18 06:50:47 PM PDT 24
Peak memory 195856 kb
Host smart-93d24d7e-d307-4f95-9a47-93ee5ddaae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156644466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1156644466
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1974469011
Short name T420
Test name
Test status
Simulation time 11085347769 ps
CPU time 8.5 seconds
Started Jul 18 06:50:44 PM PDT 24
Finished Jul 18 06:50:54 PM PDT 24
Peak memory 200180 kb
Host smart-5c5f0aaa-cffe-4c2f-857c-162356387ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974469011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1974469011
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1950057490
Short name T740
Test name
Test status
Simulation time 996320110 ps
CPU time 1.6 seconds
Started Jul 18 06:50:43 PM PDT 24
Finished Jul 18 06:50:46 PM PDT 24
Peak memory 198536 kb
Host smart-9eb7e59b-ec4f-4cf4-bf5e-74061e31a944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950057490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1950057490
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.4210087434
Short name T866
Test name
Test status
Simulation time 5907046217 ps
CPU time 8.41 seconds
Started Jul 18 06:50:43 PM PDT 24
Finished Jul 18 06:50:52 PM PDT 24
Peak memory 196964 kb
Host smart-86170b80-97b5-4b37-bda2-e352ee1b9efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210087434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4210087434
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3615818720
Short name T1003
Test name
Test status
Simulation time 155689055 ps
CPU time 0.57 seconds
Started Jul 18 06:50:43 PM PDT 24
Finished Jul 18 06:50:45 PM PDT 24
Peak memory 195580 kb
Host smart-e2aa53fc-e638-4236-b09d-b07c9b6dba13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615818720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3615818720
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3674084302
Short name T694
Test name
Test status
Simulation time 53255375334 ps
CPU time 79.55 seconds
Started Jul 18 06:50:44 PM PDT 24
Finished Jul 18 06:52:06 PM PDT 24
Peak memory 200108 kb
Host smart-5ba93c90-3e59-43a3-9655-c761fe685e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674084302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3674084302
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3975160426
Short name T872
Test name
Test status
Simulation time 44701375996 ps
CPU time 30.83 seconds
Started Jul 18 06:50:46 PM PDT 24
Finished Jul 18 06:51:19 PM PDT 24
Peak memory 200108 kb
Host smart-89c00c5c-804a-4e63-9fab-c9f89b9e0112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975160426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3975160426
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1274817269
Short name T760
Test name
Test status
Simulation time 15811718725 ps
CPU time 23.92 seconds
Started Jul 18 06:50:46 PM PDT 24
Finished Jul 18 06:51:12 PM PDT 24
Peak memory 200112 kb
Host smart-0a3d9683-14ab-4cb9-bcfd-1fe0d2e9a69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274817269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1274817269
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3064364420
Short name T858
Test name
Test status
Simulation time 49912184770 ps
CPU time 8.99 seconds
Started Jul 18 06:50:51 PM PDT 24
Finished Jul 18 06:51:02 PM PDT 24
Peak memory 200176 kb
Host smart-15d44054-cb40-4446-beac-15c7e8efb668
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064364420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3064364420
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.4074844799
Short name T459
Test name
Test status
Simulation time 258624721279 ps
CPU time 164.97 seconds
Started Jul 18 06:50:47 PM PDT 24
Finished Jul 18 06:53:34 PM PDT 24
Peak memory 200172 kb
Host smart-7d8c581b-7012-4694-b0e9-e0189d2ca2b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074844799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4074844799
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2097688682
Short name T448
Test name
Test status
Simulation time 1800182822 ps
CPU time 0.91 seconds
Started Jul 18 06:50:51 PM PDT 24
Finished Jul 18 06:50:54 PM PDT 24
Peak memory 196412 kb
Host smart-b11aeceb-acfc-4893-b4f9-031f6f4088cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097688682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2097688682
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3604006640
Short name T435
Test name
Test status
Simulation time 10922693725 ps
CPU time 9.27 seconds
Started Jul 18 06:50:49 PM PDT 24
Finished Jul 18 06:51:01 PM PDT 24
Peak memory 200164 kb
Host smart-cc89277d-cd9f-488f-abe5-2477bcce3850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604006640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3604006640
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1099599536
Short name T819
Test name
Test status
Simulation time 18463987846 ps
CPU time 517.24 seconds
Started Jul 18 06:50:43 PM PDT 24
Finished Jul 18 06:59:22 PM PDT 24
Peak memory 200016 kb
Host smart-8f9ee5f8-68dc-4ae6-aaf0-0abf857f6f58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1099599536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1099599536
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2977789149
Short name T685
Test name
Test status
Simulation time 3684925897 ps
CPU time 30.12 seconds
Started Jul 18 06:50:49 PM PDT 24
Finished Jul 18 06:51:22 PM PDT 24
Peak memory 199484 kb
Host smart-ae6f84d5-d17b-49a3-b2f3-a275afd92f7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977789149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2977789149
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.69338790
Short name T1071
Test name
Test status
Simulation time 33822976104 ps
CPU time 91.64 seconds
Started Jul 18 06:50:46 PM PDT 24
Finished Jul 18 06:52:21 PM PDT 24
Peak memory 200144 kb
Host smart-e42e6afb-a4ac-4128-8475-d1f48446b31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69338790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.69338790
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3014674748
Short name T787
Test name
Test status
Simulation time 3947864366 ps
CPU time 3.53 seconds
Started Jul 18 06:50:47 PM PDT 24
Finished Jul 18 06:50:54 PM PDT 24
Peak memory 195808 kb
Host smart-ffeb4357-fba7-44dd-8965-b3dd5306cdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014674748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3014674748
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3222226448
Short name T444
Test name
Test status
Simulation time 282221350 ps
CPU time 1.54 seconds
Started Jul 18 06:50:47 PM PDT 24
Finished Jul 18 06:50:51 PM PDT 24
Peak memory 198672 kb
Host smart-5a274c26-cd60-4811-a8ec-128fd710c4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222226448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3222226448
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1138411246
Short name T302
Test name
Test status
Simulation time 180562198515 ps
CPU time 299.27 seconds
Started Jul 18 06:50:43 PM PDT 24
Finished Jul 18 06:55:44 PM PDT 24
Peak memory 200208 kb
Host smart-620ed5b6-8b4c-43a3-a242-12d305aa8022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138411246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1138411246
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1482578025
Short name T1097
Test name
Test status
Simulation time 245508351963 ps
CPU time 760.9 seconds
Started Jul 18 06:50:46 PM PDT 24
Finished Jul 18 07:03:29 PM PDT 24
Peak memory 225056 kb
Host smart-8e3d5739-2ef2-45f0-ade3-d6e9af98c717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482578025 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1482578025
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.747706622
Short name T560
Test name
Test status
Simulation time 6799256337 ps
CPU time 12.61 seconds
Started Jul 18 06:50:47 PM PDT 24
Finished Jul 18 06:51:03 PM PDT 24
Peak memory 200116 kb
Host smart-5420d31f-e002-4ee8-b95e-f56aca517093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747706622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.747706622
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3193813367
Short name T947
Test name
Test status
Simulation time 44622901790 ps
CPU time 36.15 seconds
Started Jul 18 06:50:46 PM PDT 24
Finished Jul 18 06:51:24 PM PDT 24
Peak memory 200148 kb
Host smart-27f60002-7393-475c-8220-c4e0d57f5991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193813367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3193813367
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1186419334
Short name T780
Test name
Test status
Simulation time 13527994 ps
CPU time 0.58 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:08 PM PDT 24
Peak memory 195592 kb
Host smart-ed03668b-5b33-4673-8e9e-ac7a2fcab92c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186419334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1186419334
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2398869783
Short name T258
Test name
Test status
Simulation time 27415631344 ps
CPU time 41.32 seconds
Started Jul 18 06:50:46 PM PDT 24
Finished Jul 18 06:51:29 PM PDT 24
Peak memory 200152 kb
Host smart-c8c3397e-6a1c-4c85-85f2-fcb0c1e7d344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398869783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2398869783
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.920539218
Short name T749
Test name
Test status
Simulation time 10219801665 ps
CPU time 14.38 seconds
Started Jul 18 06:51:01 PM PDT 24
Finished Jul 18 06:51:19 PM PDT 24
Peak memory 199508 kb
Host smart-6de20176-8381-48cf-8d27-fa2ccd3cc6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920539218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.920539218
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.2851987862
Short name T777
Test name
Test status
Simulation time 5483715592 ps
CPU time 6.97 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:14 PM PDT 24
Peak memory 196364 kb
Host smart-f432f6e5-34e4-4e79-8254-ffe35a08fe6d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851987862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2851987862
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2960835015
Short name T48
Test name
Test status
Simulation time 165536526116 ps
CPU time 307.01 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 06:56:13 PM PDT 24
Peak memory 200188 kb
Host smart-73670f4a-22a7-4295-95bd-fd9a5259228a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2960835015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2960835015
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3974269244
Short name T722
Test name
Test status
Simulation time 7168162204 ps
CPU time 2.03 seconds
Started Jul 18 06:51:01 PM PDT 24
Finished Jul 18 06:51:07 PM PDT 24
Peak memory 198524 kb
Host smart-2685b36c-aeff-46ba-968a-62b2575c7ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974269244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3974269244
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3724662545
Short name T1098
Test name
Test status
Simulation time 62600711231 ps
CPU time 15.6 seconds
Started Jul 18 06:51:01 PM PDT 24
Finished Jul 18 06:51:21 PM PDT 24
Peak memory 194736 kb
Host smart-cefba85a-ac54-4590-8357-fea617f187ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724662545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3724662545
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1427142079
Short name T634
Test name
Test status
Simulation time 22242957998 ps
CPU time 801.41 seconds
Started Jul 18 06:51:05 PM PDT 24
Finished Jul 18 07:04:30 PM PDT 24
Peak memory 200208 kb
Host smart-789de35d-1b14-45a4-b32b-61ba5fc7b05b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1427142079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1427142079
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2971818408
Short name T625
Test name
Test status
Simulation time 5048633167 ps
CPU time 19.44 seconds
Started Jul 18 06:51:00 PM PDT 24
Finished Jul 18 06:51:22 PM PDT 24
Peak memory 198920 kb
Host smart-5e522b3b-407a-4df6-877e-c3ad9d942129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971818408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2971818408
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.678940784
Short name T263
Test name
Test status
Simulation time 105643335136 ps
CPU time 41.23 seconds
Started Jul 18 06:51:00 PM PDT 24
Finished Jul 18 06:51:43 PM PDT 24
Peak memory 200188 kb
Host smart-a2341850-ef5f-40cb-ae2a-7862034b6db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678940784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.678940784
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1373905720
Short name T785
Test name
Test status
Simulation time 44885385151 ps
CPU time 15.18 seconds
Started Jul 18 06:50:59 PM PDT 24
Finished Jul 18 06:51:15 PM PDT 24
Peak memory 196020 kb
Host smart-f9810a4c-4a62-468c-a0bd-b50c2ae58d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373905720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1373905720
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3537801555
Short name T284
Test name
Test status
Simulation time 699094417 ps
CPU time 2.87 seconds
Started Jul 18 06:55:33 PM PDT 24
Finished Jul 18 06:55:42 PM PDT 24
Peak memory 199108 kb
Host smart-cddec497-0955-447f-8195-b1b267444189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537801555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3537801555
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1082361472
Short name T1162
Test name
Test status
Simulation time 218621455757 ps
CPU time 547.94 seconds
Started Jul 18 06:51:01 PM PDT 24
Finished Jul 18 07:00:13 PM PDT 24
Peak memory 200104 kb
Host smart-9c792999-991f-4e45-9828-b9e7ed4dabf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082361472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1082361472
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2650159694
Short name T1113
Test name
Test status
Simulation time 30413076340 ps
CPU time 384.3 seconds
Started Jul 18 06:51:01 PM PDT 24
Finished Jul 18 06:57:28 PM PDT 24
Peak memory 216352 kb
Host smart-c1e09f38-e3b8-4625-835a-033b8ebc38f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650159694 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2650159694
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.771718765
Short name T1049
Test name
Test status
Simulation time 2724581908 ps
CPU time 1.66 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:09 PM PDT 24
Peak memory 198908 kb
Host smart-51533643-520f-41ce-bcd5-45b16627d980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771718765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.771718765
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.993418890
Short name T844
Test name
Test status
Simulation time 63527324455 ps
CPU time 97.43 seconds
Started Jul 18 06:50:44 PM PDT 24
Finished Jul 18 06:52:23 PM PDT 24
Peak memory 200184 kb
Host smart-2309ca26-d264-4521-942a-d448795ea99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993418890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.993418890
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.448924270
Short name T956
Test name
Test status
Simulation time 15619015 ps
CPU time 0.6 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:07 PM PDT 24
Peak memory 195856 kb
Host smart-e3e905ab-e5e8-4759-ba1f-096c086428e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448924270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.448924270
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3083499233
Short name T432
Test name
Test status
Simulation time 29444988260 ps
CPU time 60.39 seconds
Started Jul 18 06:51:00 PM PDT 24
Finished Jul 18 06:52:02 PM PDT 24
Peak memory 200096 kb
Host smart-dbf41958-2286-45e6-8255-89bcdfc72dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083499233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3083499233
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3394341446
Short name T602
Test name
Test status
Simulation time 65651971303 ps
CPU time 57.54 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 06:52:04 PM PDT 24
Peak memory 200356 kb
Host smart-011f9b01-03c2-40bd-a178-2d8ac66d53ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394341446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3394341446
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.4196426402
Short name T152
Test name
Test status
Simulation time 35725679036 ps
CPU time 24.27 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:31 PM PDT 24
Peak memory 200184 kb
Host smart-a1a20440-188e-4d53-b1ac-1b5ba96ea3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196426402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.4196426402
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1325545329
Short name T958
Test name
Test status
Simulation time 73837337988 ps
CPU time 79.98 seconds
Started Jul 18 06:50:59 PM PDT 24
Finished Jul 18 06:52:20 PM PDT 24
Peak memory 200292 kb
Host smart-a4b10316-d951-4a9f-9640-9717503a6b73
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325545329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1325545329
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.377482158
Short name T270
Test name
Test status
Simulation time 128680977278 ps
CPU time 144.76 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:53:32 PM PDT 24
Peak memory 200116 kb
Host smart-cc45c9df-7c68-4227-8ec1-198b6462f09b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377482158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.377482158
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.861311278
Short name T528
Test name
Test status
Simulation time 7281433662 ps
CPU time 4.76 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 06:51:11 PM PDT 24
Peak memory 199916 kb
Host smart-07c39cfd-18ff-4b9e-91be-dae8456a58ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861311278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.861311278
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3257329927
Short name T840
Test name
Test status
Simulation time 38038278669 ps
CPU time 59.09 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 06:52:05 PM PDT 24
Peak memory 199996 kb
Host smart-1563c02f-35cb-43c9-ba8f-227ed43ec277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257329927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3257329927
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3177129098
Short name T728
Test name
Test status
Simulation time 15340589615 ps
CPU time 573.33 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 07:00:40 PM PDT 24
Peak memory 200188 kb
Host smart-ec91c3fa-4f64-47f8-929c-167359fee30e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177129098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3177129098
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.794423278
Short name T992
Test name
Test status
Simulation time 2335374219 ps
CPU time 4.4 seconds
Started Jul 18 06:51:01 PM PDT 24
Finished Jul 18 06:51:09 PM PDT 24
Peak memory 198232 kb
Host smart-8e71dfd3-94c8-41e4-aede-9903277cfab7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794423278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.794423278
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.4100641369
Short name T1145
Test name
Test status
Simulation time 28940468646 ps
CPU time 48.41 seconds
Started Jul 18 06:51:01 PM PDT 24
Finished Jul 18 06:51:52 PM PDT 24
Peak memory 199960 kb
Host smart-ef282679-ffae-47b2-aab6-78aff472ced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100641369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.4100641369
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3274765478
Short name T911
Test name
Test status
Simulation time 2063754491 ps
CPU time 3.65 seconds
Started Jul 18 06:51:05 PM PDT 24
Finished Jul 18 06:51:12 PM PDT 24
Peak memory 195848 kb
Host smart-93bf415a-e3ae-4eaf-8261-5d0f217acd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274765478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3274765478
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1027317856
Short name T868
Test name
Test status
Simulation time 454081296 ps
CPU time 2.51 seconds
Started Jul 18 06:51:01 PM PDT 24
Finished Jul 18 06:51:07 PM PDT 24
Peak memory 198964 kb
Host smart-92c467ba-35ff-4471-9330-b163431896ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027317856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1027317856
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.4051617971
Short name T976
Test name
Test status
Simulation time 355806730713 ps
CPU time 399.77 seconds
Started Jul 18 06:51:04 PM PDT 24
Finished Jul 18 06:57:48 PM PDT 24
Peak memory 216488 kb
Host smart-a3a6e546-eb73-49f0-82ff-c0336356dbcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051617971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.4051617971
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1337147396
Short name T1107
Test name
Test status
Simulation time 60785817872 ps
CPU time 392.85 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 06:57:38 PM PDT 24
Peak memory 208572 kb
Host smart-c5e612a9-222e-4f85-9b24-8a7e5a8de23c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337147396 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1337147396
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.509867906
Short name T499
Test name
Test status
Simulation time 3432330298 ps
CPU time 1.86 seconds
Started Jul 18 06:51:00 PM PDT 24
Finished Jul 18 06:51:05 PM PDT 24
Peak memory 199472 kb
Host smart-4cdbe1b7-b817-4879-bd7f-b41ad71e36c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509867906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.509867906
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3791159714
Short name T946
Test name
Test status
Simulation time 37708259568 ps
CPU time 14.57 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:21 PM PDT 24
Peak memory 199476 kb
Host smart-c0e65d3b-18bc-4a70-bbc8-36d889ef948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791159714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3791159714
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.4096286144
Short name T1108
Test name
Test status
Simulation time 49022342 ps
CPU time 0.59 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:08 PM PDT 24
Peak memory 195580 kb
Host smart-c913d259-8e85-4b50-844b-6dc381bd094d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096286144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4096286144
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1501282893
Short name T733
Test name
Test status
Simulation time 69173350242 ps
CPU time 95.01 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 06:52:41 PM PDT 24
Peak memory 200132 kb
Host smart-4c99296f-bff0-48f6-89d9-ef0e6995b3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501282893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1501282893
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.809848736
Short name T764
Test name
Test status
Simulation time 18993574570 ps
CPU time 29.19 seconds
Started Jul 18 06:51:01 PM PDT 24
Finished Jul 18 06:51:34 PM PDT 24
Peak memory 200196 kb
Host smart-3661c4e7-6565-42ee-bb47-77626f6b2afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809848736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.809848736
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.4103577037
Short name T691
Test name
Test status
Simulation time 85523977371 ps
CPU time 85.8 seconds
Started Jul 18 06:51:01 PM PDT 24
Finished Jul 18 06:52:30 PM PDT 24
Peak memory 200104 kb
Host smart-18c76a84-b839-4f01-9667-eee5ea2e36a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103577037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.4103577037
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3150415246
Short name T1037
Test name
Test status
Simulation time 226580969466 ps
CPU time 350.7 seconds
Started Jul 18 06:51:04 PM PDT 24
Finished Jul 18 06:56:59 PM PDT 24
Peak memory 200116 kb
Host smart-4381c4dc-c0ad-40a5-8a77-5288fc84d189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150415246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3150415246
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.4293485304
Short name T375
Test name
Test status
Simulation time 11093848623 ps
CPU time 12.07 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:19 PM PDT 24
Peak memory 198408 kb
Host smart-1aa38238-f9f1-44f5-a665-93febc2f79f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293485304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.4293485304
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3722047511
Short name T759
Test name
Test status
Simulation time 20057592989 ps
CPU time 31.18 seconds
Started Jul 18 06:51:01 PM PDT 24
Finished Jul 18 06:51:35 PM PDT 24
Peak memory 200296 kb
Host smart-cf72fd32-0f34-4424-91e2-90c88e189835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722047511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3722047511
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.639882883
Short name T960
Test name
Test status
Simulation time 17000160350 ps
CPU time 991.97 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 07:07:38 PM PDT 24
Peak memory 200128 kb
Host smart-4d83f51d-7bee-4a49-83a1-cea84f8a3761
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639882883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.639882883
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1469780821
Short name T687
Test name
Test status
Simulation time 4193928936 ps
CPU time 17.82 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:25 PM PDT 24
Peak memory 199376 kb
Host smart-a53f0bb2-175b-4336-b922-5109520cb94c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469780821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1469780821
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.4160490890
Short name T116
Test name
Test status
Simulation time 22909680831 ps
CPU time 32.44 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 06:51:38 PM PDT 24
Peak memory 200108 kb
Host smart-451eb575-ad27-4793-89b1-3dfc0e1b68a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160490890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4160490890
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.685765893
Short name T720
Test name
Test status
Simulation time 37396171585 ps
CPU time 52.52 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 06:51:59 PM PDT 24
Peak memory 196500 kb
Host smart-7568f250-0ef7-42f0-a96f-7280975e63c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685765893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.685765893
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3197991854
Short name T708
Test name
Test status
Simulation time 299001314 ps
CPU time 1.32 seconds
Started Jul 18 06:50:59 PM PDT 24
Finished Jul 18 06:51:02 PM PDT 24
Peak memory 199028 kb
Host smart-8c2ee004-f4c1-4bff-8ed8-0bdc48633cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197991854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3197991854
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2479605809
Short name T889
Test name
Test status
Simulation time 406786196679 ps
CPU time 623.13 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 07:01:29 PM PDT 24
Peak memory 200080 kb
Host smart-97565170-11c4-4dd2-a5a5-228a38977336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479605809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2479605809
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3005348540
Short name T163
Test name
Test status
Simulation time 120380646963 ps
CPU time 338.78 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:56:46 PM PDT 24
Peak memory 210152 kb
Host smart-e1669d8f-56e4-4596-89a1-f9e3a1e432c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005348540 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3005348540
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2838723071
Short name T541
Test name
Test status
Simulation time 6633772036 ps
CPU time 27.65 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:35 PM PDT 24
Peak memory 199828 kb
Host smart-5db6ab64-d4f1-4546-934b-3764f232c063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838723071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2838723071
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1754655506
Short name T1019
Test name
Test status
Simulation time 8095606555 ps
CPU time 12.61 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:19 PM PDT 24
Peak memory 199660 kb
Host smart-fdb8f3ac-6f91-46bd-a2da-aef0cb40b359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754655506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1754655506
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3901815939
Short name T343
Test name
Test status
Simulation time 34243255 ps
CPU time 0.55 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 06:51:24 PM PDT 24
Peak memory 195580 kb
Host smart-1cf72ad0-fb0d-443b-9585-5b8d7f990401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901815939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3901815939
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2661775389
Short name T460
Test name
Test status
Simulation time 42331849713 ps
CPU time 28.45 seconds
Started Jul 18 06:51:06 PM PDT 24
Finished Jul 18 06:51:37 PM PDT 24
Peak memory 200188 kb
Host smart-26c2902f-eb71-4429-b198-d02937cf3ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661775389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2661775389
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3958034391
Short name T162
Test name
Test status
Simulation time 9874210994 ps
CPU time 9.6 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 06:51:16 PM PDT 24
Peak memory 200164 kb
Host smart-160f3804-9ea7-4f6b-b9af-7405d34d930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958034391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3958034391
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2709450008
Short name T290
Test name
Test status
Simulation time 185013570679 ps
CPU time 395.04 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 06:57:41 PM PDT 24
Peak memory 200192 kb
Host smart-ee8d976b-f99d-4f01-97e6-9c7b99325e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709450008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2709450008
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.566139147
Short name T21
Test name
Test status
Simulation time 24705203785 ps
CPU time 9.8 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:17 PM PDT 24
Peak memory 200068 kb
Host smart-3f653540-f778-48c2-9c6d-c584a6b4023c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566139147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.566139147
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3577340829
Short name T421
Test name
Test status
Simulation time 116018309742 ps
CPU time 163.71 seconds
Started Jul 18 06:51:04 PM PDT 24
Finished Jul 18 06:53:52 PM PDT 24
Peak memory 200172 kb
Host smart-20dd91c9-7bd0-43e9-b171-1ddf3cc324e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577340829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3577340829
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2831022076
Short name T980
Test name
Test status
Simulation time 10230718046 ps
CPU time 19.27 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 06:51:25 PM PDT 24
Peak memory 199500 kb
Host smart-61d94261-9e12-4518-b929-9329896f29f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831022076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2831022076
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1744617484
Short name T782
Test name
Test status
Simulation time 27222321978 ps
CPU time 25.21 seconds
Started Jul 18 06:51:05 PM PDT 24
Finished Jul 18 06:51:34 PM PDT 24
Peak memory 200156 kb
Host smart-d55224ab-b11c-46cc-9d36-a7fff34d4129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744617484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1744617484
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1015482184
Short name T986
Test name
Test status
Simulation time 15505434168 ps
CPU time 567.29 seconds
Started Jul 18 06:51:05 PM PDT 24
Finished Jul 18 07:00:36 PM PDT 24
Peak memory 200176 kb
Host smart-bf16389b-70a3-4815-ab4e-c4ecb99f7c7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1015482184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1015482184
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2658938817
Short name T833
Test name
Test status
Simulation time 5622529455 ps
CPU time 52.22 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:52:00 PM PDT 24
Peak memory 199556 kb
Host smart-282e5fae-2082-4e50-8901-100f2525aef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2658938817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2658938817
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3555167087
Short name T622
Test name
Test status
Simulation time 191426678986 ps
CPU time 17.15 seconds
Started Jul 18 06:51:05 PM PDT 24
Finished Jul 18 06:51:26 PM PDT 24
Peak memory 198980 kb
Host smart-e496f0c9-f24d-427a-905f-b849486a4d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555167087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3555167087
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1239172193
Short name T296
Test name
Test status
Simulation time 41276535791 ps
CPU time 16.46 seconds
Started Jul 18 06:51:05 PM PDT 24
Finished Jul 18 06:51:25 PM PDT 24
Peak memory 196212 kb
Host smart-4ca3af13-5454-4fcc-a775-7763783a0ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239172193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1239172193
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1538384859
Short name T933
Test name
Test status
Simulation time 493203107 ps
CPU time 1.83 seconds
Started Jul 18 06:51:03 PM PDT 24
Finished Jul 18 06:51:09 PM PDT 24
Peak memory 199148 kb
Host smart-15d22e9e-0c9f-4388-b962-fc0b94401e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538384859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1538384859
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2346661435
Short name T122
Test name
Test status
Simulation time 350124892657 ps
CPU time 205.35 seconds
Started Jul 18 06:51:17 PM PDT 24
Finished Jul 18 06:54:45 PM PDT 24
Peak memory 200060 kb
Host smart-ef282468-e06f-45a0-b108-875b695e239b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346661435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2346661435
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2575072082
Short name T359
Test name
Test status
Simulation time 8216415663 ps
CPU time 13.91 seconds
Started Jul 18 06:51:05 PM PDT 24
Finished Jul 18 06:51:22 PM PDT 24
Peak memory 200088 kb
Host smart-fecee501-1348-47bc-b9dd-54f455c12d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575072082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2575072082
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3263108052
Short name T256
Test name
Test status
Simulation time 92238854219 ps
CPU time 38.88 seconds
Started Jul 18 06:51:02 PM PDT 24
Finished Jul 18 06:51:45 PM PDT 24
Peak memory 200188 kb
Host smart-a48c753f-f044-4725-a2e0-af36dc5bb023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263108052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3263108052
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2230205079
Short name T347
Test name
Test status
Simulation time 11786477 ps
CPU time 0.62 seconds
Started Jul 18 06:51:16 PM PDT 24
Finished Jul 18 06:51:18 PM PDT 24
Peak memory 195188 kb
Host smart-0cd0463e-daa9-48f7-81b8-454928ccaed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230205079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2230205079
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1132827802
Short name T46
Test name
Test status
Simulation time 20757966784 ps
CPU time 32.32 seconds
Started Jul 18 06:51:18 PM PDT 24
Finished Jul 18 06:51:54 PM PDT 24
Peak memory 200096 kb
Host smart-95f000e2-332c-446f-aae4-69ee543a0b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132827802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1132827802
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1435010591
Short name T114
Test name
Test status
Simulation time 124069338005 ps
CPU time 35.14 seconds
Started Jul 18 06:51:15 PM PDT 24
Finished Jul 18 06:51:52 PM PDT 24
Peak memory 200200 kb
Host smart-c783a2cd-9d58-4d11-bb03-02d819a65d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435010591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1435010591
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.650493695
Short name T222
Test name
Test status
Simulation time 75316922572 ps
CPU time 101.81 seconds
Started Jul 18 06:51:17 PM PDT 24
Finished Jul 18 06:53:01 PM PDT 24
Peak memory 200144 kb
Host smart-b4aa4769-eb1a-43f1-866e-48d91261323c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650493695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.650493695
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3312977780
Short name T531
Test name
Test status
Simulation time 56749290307 ps
CPU time 78.4 seconds
Started Jul 18 06:51:17 PM PDT 24
Finished Jul 18 06:52:38 PM PDT 24
Peak memory 200100 kb
Host smart-d10e41b7-3bbf-4ff7-8af0-fc1a143a4ff4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312977780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3312977780
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1404594375
Short name T365
Test name
Test status
Simulation time 132128151990 ps
CPU time 353.66 seconds
Started Jul 18 06:51:16 PM PDT 24
Finished Jul 18 06:57:12 PM PDT 24
Peak memory 200128 kb
Host smart-d95c4831-6ff2-49da-8a1f-26952bc128f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404594375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1404594375
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1551049676
Short name T1133
Test name
Test status
Simulation time 7508691736 ps
CPU time 11.12 seconds
Started Jul 18 06:51:18 PM PDT 24
Finished Jul 18 06:51:32 PM PDT 24
Peak memory 199784 kb
Host smart-90f50517-83f3-4871-a3ab-fff760953eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551049676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1551049676
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1471749614
Short name T628
Test name
Test status
Simulation time 101808787984 ps
CPU time 164.18 seconds
Started Jul 18 06:51:18 PM PDT 24
Finished Jul 18 06:54:05 PM PDT 24
Peak memory 200064 kb
Host smart-ede2e5ba-efad-4229-8cb8-3a8973dc7413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471749614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1471749614
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3782681047
Short name T648
Test name
Test status
Simulation time 29986556674 ps
CPU time 466.87 seconds
Started Jul 18 06:51:15 PM PDT 24
Finished Jul 18 06:59:03 PM PDT 24
Peak memory 200204 kb
Host smart-2c592bf0-9869-4d96-9843-9f35a8f641d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782681047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3782681047
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.879248955
Short name T545
Test name
Test status
Simulation time 6855241350 ps
CPU time 28.81 seconds
Started Jul 18 06:51:15 PM PDT 24
Finished Jul 18 06:51:45 PM PDT 24
Peak memory 199188 kb
Host smart-b3b14dc3-1001-4659-9e3e-c9345289bfc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879248955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.879248955
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1308479062
Short name T766
Test name
Test status
Simulation time 106177439579 ps
CPU time 141.8 seconds
Started Jul 18 06:51:16 PM PDT 24
Finished Jul 18 06:53:39 PM PDT 24
Peak memory 200132 kb
Host smart-ae33928f-c1d3-46bd-a898-248df24bd093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308479062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1308479062
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3269507235
Short name T1143
Test name
Test status
Simulation time 4110701410 ps
CPU time 7.07 seconds
Started Jul 18 06:51:17 PM PDT 24
Finished Jul 18 06:51:27 PM PDT 24
Peak memory 196504 kb
Host smart-9b292d6a-023b-4ac4-9f3c-0bee772fbb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269507235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3269507235
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1254018221
Short name T1009
Test name
Test status
Simulation time 695711904 ps
CPU time 2.62 seconds
Started Jul 18 06:51:16 PM PDT 24
Finished Jul 18 06:51:20 PM PDT 24
Peak memory 200048 kb
Host smart-102e5d32-2671-4c06-974d-94a3d0d3452b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254018221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1254018221
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2727090150
Short name T818
Test name
Test status
Simulation time 570284867095 ps
CPU time 2043.59 seconds
Started Jul 18 06:51:18 PM PDT 24
Finished Jul 18 07:25:25 PM PDT 24
Peak memory 208524 kb
Host smart-2d79123d-7627-49c5-b49c-2f7f516de015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727090150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2727090150
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1712518077
Short name T902
Test name
Test status
Simulation time 196904194381 ps
CPU time 738.96 seconds
Started Jul 18 06:51:17 PM PDT 24
Finished Jul 18 07:03:38 PM PDT 24
Peak memory 225008 kb
Host smart-dcbfec03-ddc3-4ca7-af48-cd4b8e27715f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712518077 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1712518077
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1130565967
Short name T465
Test name
Test status
Simulation time 717766780 ps
CPU time 2.77 seconds
Started Jul 18 06:51:17 PM PDT 24
Finished Jul 18 06:51:23 PM PDT 24
Peak memory 198620 kb
Host smart-aa11025b-3723-4b8d-9e85-1d148c64b9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130565967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1130565967
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.120095756
Short name T689
Test name
Test status
Simulation time 39859515323 ps
CPU time 16.63 seconds
Started Jul 18 06:51:18 PM PDT 24
Finished Jul 18 06:51:38 PM PDT 24
Peak memory 198152 kb
Host smart-d3a4af56-a10a-4764-a99a-8ceeeb9b0693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120095756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.120095756
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3745223920
Short name T847
Test name
Test status
Simulation time 38429226 ps
CPU time 0.56 seconds
Started Jul 18 06:51:18 PM PDT 24
Finished Jul 18 06:51:22 PM PDT 24
Peak memory 195852 kb
Host smart-e81448e8-b088-4785-8e7c-53d7fe49c01e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745223920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3745223920
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1505504135
Short name T491
Test name
Test status
Simulation time 336667913972 ps
CPU time 46.01 seconds
Started Jul 18 06:51:15 PM PDT 24
Finished Jul 18 06:52:02 PM PDT 24
Peak memory 200128 kb
Host smart-1e68a921-ec79-4c6b-9c59-13749ad31305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505504135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1505504135
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3576420844
Short name T770
Test name
Test status
Simulation time 102920984120 ps
CPU time 148.85 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 06:53:52 PM PDT 24
Peak memory 200108 kb
Host smart-de1236ef-174c-49b2-907d-144664a2f986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576420844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3576420844
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1400361104
Short name T1125
Test name
Test status
Simulation time 170157429273 ps
CPU time 266.06 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 06:55:49 PM PDT 24
Peak memory 200372 kb
Host smart-322fa87f-4372-4ad6-938d-5a01a77a4d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400361104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1400361104
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1073153733
Short name T115
Test name
Test status
Simulation time 257361672277 ps
CPU time 402.4 seconds
Started Jul 18 06:51:16 PM PDT 24
Finished Jul 18 06:58:01 PM PDT 24
Peak memory 200204 kb
Host smart-5de9f735-8b4b-420d-999d-632b8edacd0c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073153733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1073153733
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_loopback.1961155206
Short name T676
Test name
Test status
Simulation time 756471374 ps
CPU time 0.95 seconds
Started Jul 18 06:51:17 PM PDT 24
Finished Jul 18 06:51:20 PM PDT 24
Peak memory 197108 kb
Host smart-06f31106-bd97-4627-8f7e-43a053fb129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961155206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1961155206
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.336003067
Short name T249
Test name
Test status
Simulation time 95370752054 ps
CPU time 129.98 seconds
Started Jul 18 06:51:16 PM PDT 24
Finished Jul 18 06:53:27 PM PDT 24
Peak memory 199092 kb
Host smart-66f4b086-7f54-44ed-b027-fb7f90522fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336003067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.336003067
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3013319786
Short name T354
Test name
Test status
Simulation time 11569521201 ps
CPU time 712.28 seconds
Started Jul 18 06:51:16 PM PDT 24
Finished Jul 18 07:03:10 PM PDT 24
Peak memory 200172 kb
Host smart-cb7e2da1-cec7-464e-b5ce-6c4a1d7c79d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3013319786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3013319786
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1115873372
Short name T1135
Test name
Test status
Simulation time 5127856760 ps
CPU time 8.53 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 06:51:31 PM PDT 24
Peak memory 198136 kb
Host smart-27cfa598-9456-4ce5-b102-5d7b9c9b5f6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115873372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1115873372
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3218444691
Short name T862
Test name
Test status
Simulation time 250395706722 ps
CPU time 234.34 seconds
Started Jul 18 06:51:17 PM PDT 24
Finished Jul 18 06:55:13 PM PDT 24
Peak memory 200136 kb
Host smart-537319b2-2b01-4022-8731-4dc428d33954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218444691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3218444691
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.380749477
Short name T994
Test name
Test status
Simulation time 6246306403 ps
CPU time 1.4 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 06:51:24 PM PDT 24
Peak memory 196316 kb
Host smart-5cba964e-f284-4720-9879-ec563749e307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380749477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.380749477
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3734972003
Short name T1081
Test name
Test status
Simulation time 709251222 ps
CPU time 1.83 seconds
Started Jul 18 06:51:16 PM PDT 24
Finished Jul 18 06:51:20 PM PDT 24
Peak memory 200032 kb
Host smart-b4251780-a097-4db4-a5c1-67088a285e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734972003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3734972003
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.482885935
Short name T502
Test name
Test status
Simulation time 378604199911 ps
CPU time 365.82 seconds
Started Jul 18 06:51:17 PM PDT 24
Finished Jul 18 06:57:26 PM PDT 24
Peak memory 200180 kb
Host smart-c2c45237-8336-4f71-bbdd-e72441591a19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482885935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.482885935
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1323482661
Short name T184
Test name
Test status
Simulation time 227113274282 ps
CPU time 1232.68 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 07:11:56 PM PDT 24
Peak memory 226776 kb
Host smart-45741e1c-62fb-45a4-be4b-1ff9a787b6b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323482661 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1323482661
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.4034392794
Short name T19
Test name
Test status
Simulation time 1935709177 ps
CPU time 3.77 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 06:51:26 PM PDT 24
Peak memory 199944 kb
Host smart-db1ab361-252b-4554-a720-0636162d1d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034392794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4034392794
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.571147152
Short name T520
Test name
Test status
Simulation time 149614808697 ps
CPU time 54.05 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 06:52:17 PM PDT 24
Peak memory 200188 kb
Host smart-5e065730-09eb-4c96-8c82-032c68fa6ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571147152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.571147152
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2161495529
Short name T535
Test name
Test status
Simulation time 48649365 ps
CPU time 0.55 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:48:03 PM PDT 24
Peak memory 195008 kb
Host smart-54678e24-fdb5-4d3f-a59b-ed89036f8a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161495529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2161495529
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2198090491
Short name T731
Test name
Test status
Simulation time 84616260955 ps
CPU time 28.3 seconds
Started Jul 18 06:47:52 PM PDT 24
Finished Jul 18 06:48:26 PM PDT 24
Peak memory 200156 kb
Host smart-e4d1ce34-8404-4919-8040-e837c1ed0537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198090491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2198090491
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.894092158
Short name T107
Test name
Test status
Simulation time 68079609352 ps
CPU time 111.85 seconds
Started Jul 18 06:48:04 PM PDT 24
Finished Jul 18 06:49:59 PM PDT 24
Peak memory 200120 kb
Host smart-605084ff-0b42-4526-8a39-dec2f1e40b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894092158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.894092158
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.515738393
Short name T669
Test name
Test status
Simulation time 25709195587 ps
CPU time 27.78 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:48:31 PM PDT 24
Peak memory 200140 kb
Host smart-0edf3995-4693-42ce-961a-eb3734094ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515738393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.515738393
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1694311573
Short name T265
Test name
Test status
Simulation time 30960016077 ps
CPU time 50.25 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:48:53 PM PDT 24
Peak memory 200052 kb
Host smart-ae6dd54a-1094-4dcb-8651-aca8da6db8ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694311573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1694311573
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.258783705
Short name T593
Test name
Test status
Simulation time 239709758847 ps
CPU time 1905.42 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 07:19:48 PM PDT 24
Peak memory 200152 kb
Host smart-b44eb649-11e0-4f97-844f-72c4586de3da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258783705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.258783705
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2758618898
Short name T1115
Test name
Test status
Simulation time 5449047810 ps
CPU time 6.24 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:48:10 PM PDT 24
Peak memory 198568 kb
Host smart-76ec8095-20fb-404b-853c-437a9b05c810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758618898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2758618898
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.1670003697
Short name T670
Test name
Test status
Simulation time 100088189448 ps
CPU time 162.91 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:50:47 PM PDT 24
Peak memory 200220 kb
Host smart-0e9d09e9-3504-4079-8d22-42cca70fa894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670003697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1670003697
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.906441810
Short name T352
Test name
Test status
Simulation time 4542213072 ps
CPU time 199.38 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:51:28 PM PDT 24
Peak memory 199252 kb
Host smart-7aae989c-f5b2-42dd-aaa5-c851fa303618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906441810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.906441810
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3086365948
Short name T513
Test name
Test status
Simulation time 1489700853 ps
CPU time 5.83 seconds
Started Jul 18 06:47:53 PM PDT 24
Finished Jul 18 06:48:04 PM PDT 24
Peak memory 198188 kb
Host smart-01b82687-e39c-4ef1-b037-b017e1fe093f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086365948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3086365948
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.87445263
Short name T925
Test name
Test status
Simulation time 60306809872 ps
CPU time 32.34 seconds
Started Jul 18 06:48:07 PM PDT 24
Finished Jul 18 06:48:44 PM PDT 24
Peak memory 200180 kb
Host smart-8277cb03-ad6b-4cc7-9a21-b6d45f70ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87445263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.87445263
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1411312276
Short name T428
Test name
Test status
Simulation time 1648478969 ps
CPU time 3.29 seconds
Started Jul 18 06:47:51 PM PDT 24
Finished Jul 18 06:48:00 PM PDT 24
Peak memory 195864 kb
Host smart-0b64130a-c18f-42b6-aa93-88b17a493172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411312276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1411312276
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2910127066
Short name T734
Test name
Test status
Simulation time 814809130 ps
CPU time 1.45 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:48:06 PM PDT 24
Peak memory 198856 kb
Host smart-f78c690d-65b2-4152-8c04-88af96fb599f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910127066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2910127066
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1075485998
Short name T49
Test name
Test status
Simulation time 160716013985 ps
CPU time 243.28 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:52:06 PM PDT 24
Peak memory 216404 kb
Host smart-2b9a8f2e-36f6-43bf-b11c-badda5fde9b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075485998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1075485998
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2686995514
Short name T700
Test name
Test status
Simulation time 72537365573 ps
CPU time 916.55 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 07:03:20 PM PDT 24
Peak memory 215996 kb
Host smart-1676266b-4f39-4c58-9a15-b994dc844029
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686995514 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2686995514
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2606340566
Short name T304
Test name
Test status
Simulation time 582142805 ps
CPU time 1.85 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:48:06 PM PDT 24
Peak memory 198944 kb
Host smart-0b33b6cb-274c-4760-9bfa-a88a842c908a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606340566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2606340566
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.385438019
Short name T285
Test name
Test status
Simulation time 40746599368 ps
CPU time 71.27 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:49:20 PM PDT 24
Peak memory 200144 kb
Host smart-7b496c72-d0ca-4c7e-8866-f62af9c8e41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385438019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.385438019
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2156579786
Short name T653
Test name
Test status
Simulation time 9903951702 ps
CPU time 4.29 seconds
Started Jul 18 06:51:18 PM PDT 24
Finished Jul 18 06:51:26 PM PDT 24
Peak memory 199988 kb
Host smart-a25dafae-96bd-4740-a017-5c6485356093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156579786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2156579786
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3755192156
Short name T56
Test name
Test status
Simulation time 166205807065 ps
CPU time 758.92 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 07:04:02 PM PDT 24
Peak memory 229884 kb
Host smart-853407f0-2ab1-4146-8540-70079a9f502a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755192156 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3755192156
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2793835834
Short name T583
Test name
Test status
Simulation time 7286612114 ps
CPU time 11.53 seconds
Started Jul 18 06:51:22 PM PDT 24
Finished Jul 18 06:51:36 PM PDT 24
Peak memory 200112 kb
Host smart-0aeda5aa-6ea0-45cc-a56c-489f8f6ec04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793835834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2793835834
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3185917529
Short name T632
Test name
Test status
Simulation time 56668426662 ps
CPU time 120.17 seconds
Started Jul 18 06:51:21 PM PDT 24
Finished Jul 18 06:53:24 PM PDT 24
Peak memory 216676 kb
Host smart-b37894fc-6388-49c8-892c-b69621f6b03e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185917529 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3185917529
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1928566259
Short name T328
Test name
Test status
Simulation time 41499793201 ps
CPU time 62.11 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 06:52:24 PM PDT 24
Peak memory 200188 kb
Host smart-fbf7c091-609a-4150-853d-7443c875638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928566259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1928566259
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1497886940
Short name T39
Test name
Test status
Simulation time 24374254818 ps
CPU time 82.25 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 06:52:45 PM PDT 24
Peak memory 216696 kb
Host smart-eaa33afd-f291-4937-8f58-fca4ca2cde88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497886940 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1497886940
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1216668830
Short name T1089
Test name
Test status
Simulation time 152668765272 ps
CPU time 82.71 seconds
Started Jul 18 06:51:18 PM PDT 24
Finished Jul 18 06:52:44 PM PDT 24
Peak memory 200200 kb
Host smart-7dedee56-8904-48b1-bcec-2fbbdae1de6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216668830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1216668830
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1027814766
Short name T690
Test name
Test status
Simulation time 26278473884 ps
CPU time 202.82 seconds
Started Jul 18 06:51:18 PM PDT 24
Finished Jul 18 06:54:44 PM PDT 24
Peak memory 215788 kb
Host smart-61e5cd61-8408-4c3d-88e5-34a14e246287
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027814766 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1027814766
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1746597252
Short name T158
Test name
Test status
Simulation time 77148490817 ps
CPU time 25.41 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 06:51:48 PM PDT 24
Peak memory 200136 kb
Host smart-63572c63-9a31-4c2e-9776-02f70bd36e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746597252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1746597252
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1697580525
Short name T854
Test name
Test status
Simulation time 206761629961 ps
CPU time 1452.12 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 07:15:35 PM PDT 24
Peak memory 224072 kb
Host smart-e5a90d22-407c-4282-a4f9-33056e3bc42c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697580525 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1697580525
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.28054744
Short name T829
Test name
Test status
Simulation time 32535507520 ps
CPU time 22.96 seconds
Started Jul 18 06:51:22 PM PDT 24
Finished Jul 18 06:51:47 PM PDT 24
Peak memory 199208 kb
Host smart-8f9a67b1-3355-4ce8-947e-ff035f294d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28054744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.28054744
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.767956023
Short name T523
Test name
Test status
Simulation time 91263987671 ps
CPU time 136.05 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 06:53:39 PM PDT 24
Peak memory 200176 kb
Host smart-faedee1c-87da-4a6a-a902-68999b957554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767956023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.767956023
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.81477987
Short name T963
Test name
Test status
Simulation time 77434527945 ps
CPU time 1354.25 seconds
Started Jul 18 06:51:15 PM PDT 24
Finished Jul 18 07:13:51 PM PDT 24
Peak memory 224908 kb
Host smart-a2678474-9d11-4fe7-b732-b9e31ee239f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81477987 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.81477987
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.139251736
Short name T982
Test name
Test status
Simulation time 135984404369 ps
CPU time 47.45 seconds
Started Jul 18 06:51:22 PM PDT 24
Finished Jul 18 06:52:12 PM PDT 24
Peak memory 200176 kb
Host smart-b5cdf525-bc7f-4c37-a58e-b9a6bc6bc057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139251736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.139251736
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.450507480
Short name T563
Test name
Test status
Simulation time 22865330531 ps
CPU time 298.86 seconds
Started Jul 18 06:51:20 PM PDT 24
Finished Jul 18 06:56:22 PM PDT 24
Peak memory 216668 kb
Host smart-75144f3e-ca7f-41f1-a38e-773f790965a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450507480 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.450507480
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1066047160
Short name T118
Test name
Test status
Simulation time 24599159019 ps
CPU time 18.06 seconds
Started Jul 18 06:51:17 PM PDT 24
Finished Jul 18 06:51:38 PM PDT 24
Peak memory 200196 kb
Host smart-e45090f7-de34-426b-8793-53e4c8374da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066047160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1066047160
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3768386130
Short name T1161
Test name
Test status
Simulation time 26942489857 ps
CPU time 169.54 seconds
Started Jul 18 06:51:21 PM PDT 24
Finished Jul 18 06:54:14 PM PDT 24
Peak memory 216128 kb
Host smart-098c2a0d-830f-406f-8db2-06f71309cb45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768386130 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3768386130
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3838221151
Short name T266
Test name
Test status
Simulation time 102170892607 ps
CPU time 339.06 seconds
Started Jul 18 06:51:19 PM PDT 24
Finished Jul 18 06:57:02 PM PDT 24
Peak memory 200172 kb
Host smart-6eb7bb3f-0178-45f0-8a32-a66735a6da74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838221151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3838221151
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.261879547
Short name T60
Test name
Test status
Simulation time 195271103166 ps
CPU time 3313.24 seconds
Started Jul 18 06:51:34 PM PDT 24
Finished Jul 18 07:46:52 PM PDT 24
Peak memory 246088 kb
Host smart-1cca9e5d-c9a5-45b1-bee8-3f8960ca74a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261879547 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.261879547
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3302618660
Short name T989
Test name
Test status
Simulation time 42951288 ps
CPU time 0.61 seconds
Started Jul 18 06:48:02 PM PDT 24
Finished Jul 18 06:48:05 PM PDT 24
Peak memory 195592 kb
Host smart-d14760e3-032c-4dc0-a3b9-82e7d9a2b984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302618660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3302618660
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.708053018
Short name T1163
Test name
Test status
Simulation time 100703360274 ps
CPU time 138.59 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:50:27 PM PDT 24
Peak memory 199968 kb
Host smart-1e2e0342-9182-4ab8-b417-0e5f8cfb0b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708053018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.708053018
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.4021760452
Short name T591
Test name
Test status
Simulation time 24605481549 ps
CPU time 11.11 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:48:19 PM PDT 24
Peak memory 199872 kb
Host smart-d5d277b3-cf2e-4d0c-a28d-2f7317a9239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021760452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.4021760452
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2759013777
Short name T527
Test name
Test status
Simulation time 85553919593 ps
CPU time 69.41 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:49:12 PM PDT 24
Peak memory 200048 kb
Host smart-2b2f5d51-49bd-4176-a0d1-877e26547dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759013777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2759013777
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1804987708
Short name T799
Test name
Test status
Simulation time 15083030679 ps
CPU time 6.81 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:48:15 PM PDT 24
Peak memory 197024 kb
Host smart-2a098470-a5ab-4f7b-aec0-e1b47fbe8450
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804987708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1804987708
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2372657376
Short name T1155
Test name
Test status
Simulation time 76725500672 ps
CPU time 259.9 seconds
Started Jul 18 06:48:06 PM PDT 24
Finished Jul 18 06:52:30 PM PDT 24
Peak memory 200048 kb
Host smart-ae8dfdb2-b93d-4bbb-8055-c345bfb9682e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2372657376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2372657376
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1255100382
Short name T684
Test name
Test status
Simulation time 4297418290 ps
CPU time 6.95 seconds
Started Jul 18 06:48:02 PM PDT 24
Finished Jul 18 06:48:12 PM PDT 24
Peak memory 198348 kb
Host smart-9953fe6f-a5f2-4c8e-b023-8f1a08efe4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255100382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1255100382
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1613954786
Short name T392
Test name
Test status
Simulation time 82551036027 ps
CPU time 14.64 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:48:23 PM PDT 24
Peak memory 200304 kb
Host smart-5a59e66c-4343-432b-9615-d00f4417ceb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613954786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1613954786
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3903277769
Short name T493
Test name
Test status
Simulation time 12010532087 ps
CPU time 630.02 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:58:38 PM PDT 24
Peak memory 200176 kb
Host smart-2e42cf3e-e9d6-4b21-8018-e2ef04077f27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903277769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3903277769
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1045933397
Short name T105
Test name
Test status
Simulation time 7443738408 ps
CPU time 15.6 seconds
Started Jul 18 06:48:03 PM PDT 24
Finished Jul 18 06:48:21 PM PDT 24
Peak memory 199224 kb
Host smart-a4752b7f-85bf-49ff-8871-b4a299eaaa18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1045933397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1045933397
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1139701
Short name T1157
Test name
Test status
Simulation time 82532184076 ps
CPU time 47.49 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:48:51 PM PDT 24
Peak memory 200084 kb
Host smart-f9f6e071-ed76-4f84-8c48-83ff0ec8814f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1139701
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2636660582
Short name T1025
Test name
Test status
Simulation time 3223040978 ps
CPU time 1.79 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:48:10 PM PDT 24
Peak memory 196220 kb
Host smart-2b0466dc-b724-44b7-abf8-55dfb3ad627a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636660582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2636660582
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2008016011
Short name T442
Test name
Test status
Simulation time 532960200 ps
CPU time 3.22 seconds
Started Jul 18 06:48:08 PM PDT 24
Finished Jul 18 06:48:15 PM PDT 24
Peak memory 198588 kb
Host smart-30113410-d0e0-4623-ab37-a9caf38ebcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008016011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2008016011
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1082112408
Short name T557
Test name
Test status
Simulation time 85510072467 ps
CPU time 136.86 seconds
Started Jul 18 06:48:11 PM PDT 24
Finished Jul 18 06:50:31 PM PDT 24
Peak memory 199896 kb
Host smart-4c4ac5dd-abac-4ff7-92aa-df0ec6fd9ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082112408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1082112408
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3637599209
Short name T316
Test name
Test status
Simulation time 44582032820 ps
CPU time 654.16 seconds
Started Jul 18 06:48:03 PM PDT 24
Finished Jul 18 06:59:01 PM PDT 24
Peak memory 216448 kb
Host smart-04e91966-892b-4ab7-92f9-e265cf3e947e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637599209 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3637599209
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3522342464
Short name T445
Test name
Test status
Simulation time 793623548 ps
CPU time 2.12 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:48:10 PM PDT 24
Peak memory 198552 kb
Host smart-287629f6-9b15-47e6-ad7d-08127a91efab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522342464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3522342464
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2992196428
Short name T250
Test name
Test status
Simulation time 73865761007 ps
CPU time 53.15 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:49:01 PM PDT 24
Peak memory 200184 kb
Host smart-7c64a7fd-25ad-4080-b4c4-5d5d1dab2f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992196428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2992196428
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.309455965
Short name T1031
Test name
Test status
Simulation time 33829787965 ps
CPU time 16.05 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 06:51:52 PM PDT 24
Peak memory 200100 kb
Host smart-3004a30e-c05f-46dd-8757-1df6dbdd8e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309455965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.309455965
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2993610088
Short name T579
Test name
Test status
Simulation time 58081864424 ps
CPU time 48.97 seconds
Started Jul 18 06:51:34 PM PDT 24
Finished Jul 18 06:52:28 PM PDT 24
Peak memory 200196 kb
Host smart-fc49dd19-73c9-4c6a-a0e4-6105ba4a5a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993610088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2993610088
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3629513622
Short name T62
Test name
Test status
Simulation time 365404151227 ps
CPU time 901.32 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 07:06:38 PM PDT 24
Peak memory 216868 kb
Host smart-0587da6f-354f-478b-9c5c-8dbaeb4fe0d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629513622 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3629513622
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1037795834
Short name T61
Test name
Test status
Simulation time 64946933147 ps
CPU time 415.33 seconds
Started Jul 18 06:51:34 PM PDT 24
Finished Jul 18 06:58:34 PM PDT 24
Peak memory 216700 kb
Host smart-0c53048c-92ef-4505-92c8-54557563d2ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037795834 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1037795834
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2437080243
Short name T1154
Test name
Test status
Simulation time 29307880559 ps
CPU time 12.68 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 06:51:50 PM PDT 24
Peak memory 200140 kb
Host smart-8835897c-b9c9-4675-bcb0-e8b80af58247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437080243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2437080243
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1438126927
Short name T533
Test name
Test status
Simulation time 43762563484 ps
CPU time 461.34 seconds
Started Jul 18 06:51:39 PM PDT 24
Finished Jul 18 06:59:22 PM PDT 24
Peak memory 216780 kb
Host smart-fa2f7816-b851-432c-bcbc-7abed02969cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438126927 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1438126927
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.4150894417
Short name T157
Test name
Test status
Simulation time 17275884154 ps
CPU time 145.61 seconds
Started Jul 18 06:51:34 PM PDT 24
Finished Jul 18 06:54:04 PM PDT 24
Peak memory 216820 kb
Host smart-c527da63-1cc9-46f1-9e18-b690710461e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150894417 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.4150894417
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2913160904
Short name T993
Test name
Test status
Simulation time 24780292756 ps
CPU time 41.67 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 06:52:18 PM PDT 24
Peak memory 200132 kb
Host smart-1c165d3f-0c17-4228-8f42-339cc58c4b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913160904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2913160904
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.4114920768
Short name T1129
Test name
Test status
Simulation time 50074030033 ps
CPU time 921.51 seconds
Started Jul 18 06:51:34 PM PDT 24
Finished Jul 18 07:07:00 PM PDT 24
Peak memory 226640 kb
Host smart-4f3389b1-dc42-446b-a897-cc1da1659e85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114920768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.4114920768
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.4260648785
Short name T186
Test name
Test status
Simulation time 21058872194 ps
CPU time 16.43 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 06:51:52 PM PDT 24
Peak memory 200196 kb
Host smart-5eef2801-0d5f-48d7-8302-ce34a6f16703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260648785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.4260648785
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.844361335
Short name T1151
Test name
Test status
Simulation time 187735169578 ps
CPU time 1814.76 seconds
Started Jul 18 06:51:33 PM PDT 24
Finished Jul 18 07:21:52 PM PDT 24
Peak memory 218608 kb
Host smart-d5fa42ce-b99c-4743-b25b-19542cf19abd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844361335 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.844361335
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.844369922
Short name T148
Test name
Test status
Simulation time 193246025790 ps
CPU time 124.93 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 06:53:42 PM PDT 24
Peak memory 200180 kb
Host smart-70d3cc4c-5e8a-4f38-a4b3-116fe2fc392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844369922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.844369922
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2305896592
Short name T425
Test name
Test status
Simulation time 13254333692 ps
CPU time 232.69 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 06:55:30 PM PDT 24
Peak memory 210740 kb
Host smart-965e7073-5351-4ee8-a1e9-14b95ed30c31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305896592 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2305896592
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.132253460
Short name T182
Test name
Test status
Simulation time 14689332136 ps
CPU time 23.05 seconds
Started Jul 18 06:51:29 PM PDT 24
Finished Jul 18 06:51:53 PM PDT 24
Peak memory 200196 kb
Host smart-71237f95-912f-4372-aee8-b882e784884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132253460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.132253460
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.747574210
Short name T199
Test name
Test status
Simulation time 50436964263 ps
CPU time 80.48 seconds
Started Jul 18 06:51:36 PM PDT 24
Finished Jul 18 06:53:00 PM PDT 24
Peak memory 200220 kb
Host smart-35657307-84b4-4cd5-8fcf-2c5eec5cd521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747574210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.747574210
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1131927703
Short name T827
Test name
Test status
Simulation time 12315784907 ps
CPU time 156.63 seconds
Started Jul 18 06:51:30 PM PDT 24
Finished Jul 18 06:54:10 PM PDT 24
Peak memory 216520 kb
Host smart-0f8364a8-87f8-4a53-98ee-ab4bf3555870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131927703 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1131927703
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.618267240
Short name T940
Test name
Test status
Simulation time 29691977 ps
CPU time 0.59 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:48:03 PM PDT 24
Peak memory 195552 kb
Host smart-4f76fc13-0073-40fc-91c6-a257cd6c5573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618267240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.618267240
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.970301059
Short name T479
Test name
Test status
Simulation time 19588286615 ps
CPU time 29.21 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:48:38 PM PDT 24
Peak memory 199620 kb
Host smart-fce58b78-da25-4876-99ff-01e7f2f00fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970301059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.970301059
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3599861057
Short name T973
Test name
Test status
Simulation time 63704039956 ps
CPU time 24.49 seconds
Started Jul 18 06:48:02 PM PDT 24
Finished Jul 18 06:48:30 PM PDT 24
Peak memory 200144 kb
Host smart-b7e9d81a-b43d-4867-bbf4-a7cd08c16e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599861057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3599861057
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.545683141
Short name T723
Test name
Test status
Simulation time 13241205040 ps
CPU time 20.23 seconds
Started Jul 18 06:48:04 PM PDT 24
Finished Jul 18 06:48:27 PM PDT 24
Peak memory 199352 kb
Host smart-8ac903ec-8ae3-4862-a1e4-e8092ae3822a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545683141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.545683141
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.503004584
Short name T725
Test name
Test status
Simulation time 134019350408 ps
CPU time 57.27 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:49:01 PM PDT 24
Peak memory 200208 kb
Host smart-7e26d112-cc94-4fcf-a81a-38514d66126a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503004584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.503004584
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3906670910
Short name T1130
Test name
Test status
Simulation time 70063653920 ps
CPU time 163.27 seconds
Started Jul 18 06:48:04 PM PDT 24
Finished Jul 18 06:50:50 PM PDT 24
Peak memory 200136 kb
Host smart-46c42540-dcd5-459c-9b78-8c4c3f327517
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906670910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3906670910
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3068055729
Short name T72
Test name
Test status
Simulation time 4154137543 ps
CPU time 1.53 seconds
Started Jul 18 06:48:11 PM PDT 24
Finished Jul 18 06:48:15 PM PDT 24
Peak memory 197668 kb
Host smart-51c4f1da-1584-4720-81d6-b8d805f152be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068055729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3068055729
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3685536171
Short name T984
Test name
Test status
Simulation time 52009329609 ps
CPU time 16.58 seconds
Started Jul 18 06:47:55 PM PDT 24
Finished Jul 18 06:48:15 PM PDT 24
Peak memory 200288 kb
Host smart-85c9b88a-58fe-42c1-92e9-fde69482482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685536171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3685536171
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1295565999
Short name T906
Test name
Test status
Simulation time 10641312644 ps
CPU time 314.3 seconds
Started Jul 18 06:48:02 PM PDT 24
Finished Jul 18 06:53:19 PM PDT 24
Peak memory 200152 kb
Host smart-f53d3fa8-230a-42d5-b2ee-15a78b83bf63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295565999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1295565999
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2229739869
Short name T1127
Test name
Test status
Simulation time 3036710627 ps
CPU time 8.47 seconds
Started Jul 18 06:48:07 PM PDT 24
Finished Jul 18 06:48:19 PM PDT 24
Peak memory 198564 kb
Host smart-7ecdccfa-ce3c-4c94-8503-5ec208f42e39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229739869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2229739869
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2654385110
Short name T566
Test name
Test status
Simulation time 33149831489 ps
CPU time 58.92 seconds
Started Jul 18 06:48:12 PM PDT 24
Finished Jul 18 06:49:13 PM PDT 24
Peak memory 200096 kb
Host smart-e1723e48-5765-4ed4-912a-fbb23b1b2980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654385110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2654385110
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2150747882
Short name T929
Test name
Test status
Simulation time 2779365353 ps
CPU time 1.82 seconds
Started Jul 18 06:48:02 PM PDT 24
Finished Jul 18 06:48:07 PM PDT 24
Peak memory 196688 kb
Host smart-f9b816ea-27a2-4f01-8928-ee6cee774eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150747882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2150747882
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.245412644
Short name T381
Test name
Test status
Simulation time 690809338 ps
CPU time 1.98 seconds
Started Jul 18 06:48:04 PM PDT 24
Finished Jul 18 06:48:09 PM PDT 24
Peak memory 198944 kb
Host smart-cef32d2f-1e9d-4122-9a38-3152fefa52b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245412644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.245412644
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.672077643
Short name T165
Test name
Test status
Simulation time 404744741678 ps
CPU time 149.97 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:50:32 PM PDT 24
Peak memory 208640 kb
Host smart-c4846ef2-82f9-4582-91a6-34246884c61e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672077643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.672077643
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.836311355
Short name T598
Test name
Test status
Simulation time 93061293027 ps
CPU time 312.84 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:53:15 PM PDT 24
Peak memory 216792 kb
Host smart-35c10c2e-4b7e-4e8e-bd94-bcdd9dbb3c6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836311355 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.836311355
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1573721590
Short name T406
Test name
Test status
Simulation time 542199588 ps
CPU time 1.93 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:48:06 PM PDT 24
Peak memory 199728 kb
Host smart-ca59e652-4950-4711-9a62-d7e508b184f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573721590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1573721590
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.964557065
Short name T106
Test name
Test status
Simulation time 14288444702 ps
CPU time 18.84 seconds
Started Jul 18 06:48:02 PM PDT 24
Finished Jul 18 06:48:24 PM PDT 24
Peak memory 200000 kb
Host smart-ddbf5ef6-aaca-4e00-9fba-7b2c998cee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964557065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.964557065
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3981981074
Short name T233
Test name
Test status
Simulation time 88293589011 ps
CPU time 113.48 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 06:53:30 PM PDT 24
Peak memory 200164 kb
Host smart-2901bdd2-951c-42a6-b4da-9c1933683992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981981074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3981981074
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3892879634
Short name T916
Test name
Test status
Simulation time 139015295468 ps
CPU time 611.57 seconds
Started Jul 18 06:51:30 PM PDT 24
Finished Jul 18 07:01:45 PM PDT 24
Peak memory 216716 kb
Host smart-1bdf75aa-92e5-4f62-98be-6af0c4b56c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892879634 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3892879634
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.520036915
Short name T454
Test name
Test status
Simulation time 61471337231 ps
CPU time 26.37 seconds
Started Jul 18 06:51:33 PM PDT 24
Finished Jul 18 06:52:04 PM PDT 24
Peak memory 200212 kb
Host smart-53da775c-795b-4efa-a59e-af94763c09db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520036915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.520036915
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2530809830
Short name T942
Test name
Test status
Simulation time 59778582967 ps
CPU time 680.41 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 07:02:57 PM PDT 24
Peak memory 216700 kb
Host smart-ede08563-a0cd-4f69-ab21-ec034b6aef73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530809830 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2530809830
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.4074894006
Short name T521
Test name
Test status
Simulation time 70725850765 ps
CPU time 24.49 seconds
Started Jul 18 06:51:31 PM PDT 24
Finished Jul 18 06:51:59 PM PDT 24
Peak memory 200168 kb
Host smart-b1f5124a-35b0-4981-97a2-74aecc816974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074894006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.4074894006
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3179686048
Short name T880
Test name
Test status
Simulation time 85767992092 ps
CPU time 255.88 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 06:55:52 PM PDT 24
Peak memory 216692 kb
Host smart-7270d91f-efe4-4ab7-9539-e50e7a1529f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179686048 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3179686048
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2779634711
Short name T699
Test name
Test status
Simulation time 31234246019 ps
CPU time 14.39 seconds
Started Jul 18 06:51:33 PM PDT 24
Finished Jul 18 06:51:52 PM PDT 24
Peak memory 200196 kb
Host smart-eea1ace1-bd70-45e4-a4d3-41456a49a82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779634711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2779634711
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3242084507
Short name T1015
Test name
Test status
Simulation time 42324114848 ps
CPU time 622.03 seconds
Started Jul 18 06:51:37 PM PDT 24
Finished Jul 18 07:02:02 PM PDT 24
Peak memory 216896 kb
Host smart-60b40682-2b55-4484-a053-86e54a60d5f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242084507 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3242084507
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2739205328
Short name T1096
Test name
Test status
Simulation time 41174045662 ps
CPU time 102.39 seconds
Started Jul 18 06:51:34 PM PDT 24
Finished Jul 18 06:53:21 PM PDT 24
Peak memory 212060 kb
Host smart-440cbdb6-e388-4310-9c42-008cc50306c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739205328 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2739205328
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3381027034
Short name T705
Test name
Test status
Simulation time 53723505573 ps
CPU time 44.37 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 06:52:21 PM PDT 24
Peak memory 200192 kb
Host smart-ce73199b-3d94-4cf5-8873-497da338c0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381027034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3381027034
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3664938481
Short name T1033
Test name
Test status
Simulation time 707233401737 ps
CPU time 954.66 seconds
Started Jul 18 06:51:31 PM PDT 24
Finished Jul 18 07:07:29 PM PDT 24
Peak memory 225048 kb
Host smart-62b08c0c-43ec-4948-9398-47a450434e2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664938481 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3664938481
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1931744555
Short name T218
Test name
Test status
Simulation time 354258598657 ps
CPU time 39.85 seconds
Started Jul 18 06:51:36 PM PDT 24
Finished Jul 18 06:52:19 PM PDT 24
Peak memory 200312 kb
Host smart-bd2610a6-f9c1-4ae8-9e0c-3e2ea5a39b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931744555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1931744555
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3277207657
Short name T1152
Test name
Test status
Simulation time 73624405665 ps
CPU time 21.23 seconds
Started Jul 18 06:51:35 PM PDT 24
Finished Jul 18 06:52:01 PM PDT 24
Peak memory 199072 kb
Host smart-adbd0fba-1214-4b0e-9516-3bb1dc2a5894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277207657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3277207657
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3686288334
Short name T623
Test name
Test status
Simulation time 228931129679 ps
CPU time 1377.21 seconds
Started Jul 18 06:51:40 PM PDT 24
Finished Jul 18 07:14:38 PM PDT 24
Peak memory 229720 kb
Host smart-16b2a3e2-4882-4410-9d6c-dbfc8f74e767
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686288334 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3686288334
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1855997821
Short name T268
Test name
Test status
Simulation time 160335438594 ps
CPU time 241.58 seconds
Started Jul 18 06:51:33 PM PDT 24
Finished Jul 18 06:55:40 PM PDT 24
Peak memory 200120 kb
Host smart-f30b0b63-3b80-4b2b-a54a-fbc4f3636bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855997821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1855997821
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1450762251
Short name T501
Test name
Test status
Simulation time 103918891387 ps
CPU time 369.3 seconds
Started Jul 18 06:51:35 PM PDT 24
Finished Jul 18 06:57:49 PM PDT 24
Peak memory 208500 kb
Host smart-6ad16a10-81d5-4710-af34-25c48d7d919a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450762251 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1450762251
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.358049168
Short name T801
Test name
Test status
Simulation time 23893244 ps
CPU time 0.6 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:48:04 PM PDT 24
Peak memory 195576 kb
Host smart-17bf85c5-f00a-4e3b-aaca-45481ab09f52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358049168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.358049168
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2126638724
Short name T677
Test name
Test status
Simulation time 122875976989 ps
CPU time 55.36 seconds
Started Jul 18 06:47:59 PM PDT 24
Finished Jul 18 06:48:56 PM PDT 24
Peak memory 200156 kb
Host smart-79a29002-a178-4c93-8f56-ad4649cef510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126638724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2126638724
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1226702795
Short name T709
Test name
Test status
Simulation time 27418936648 ps
CPU time 24.85 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:48:27 PM PDT 24
Peak memory 200208 kb
Host smart-3c3ae8aa-7aaa-4b65-9ce9-d0a7a29fdd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226702795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1226702795
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3890103067
Short name T117
Test name
Test status
Simulation time 294114773512 ps
CPU time 48.86 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:48:53 PM PDT 24
Peak memory 199960 kb
Host smart-813c49ae-8a79-4802-a47e-c33358322c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890103067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3890103067
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3589136201
Short name T627
Test name
Test status
Simulation time 28781155942 ps
CPU time 12.44 seconds
Started Jul 18 06:47:59 PM PDT 24
Finished Jul 18 06:48:14 PM PDT 24
Peak memory 200104 kb
Host smart-9da132fd-f65c-4c6b-a3d1-8a111e5f9c6f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589136201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3589136201
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3465624704
Short name T910
Test name
Test status
Simulation time 111737754457 ps
CPU time 329.85 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:53:32 PM PDT 24
Peak memory 200112 kb
Host smart-df9bfffb-49d0-46ee-9d22-3e2eddd8f39d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3465624704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3465624704
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2838625222
Short name T353
Test name
Test status
Simulation time 113260994 ps
CPU time 0.95 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:48:03 PM PDT 24
Peak memory 198616 kb
Host smart-b9abb56a-774c-4af9-9be7-ee4a8e5d9435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838625222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2838625222
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2274837259
Short name T738
Test name
Test status
Simulation time 46195916611 ps
CPU time 77.44 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:49:21 PM PDT 24
Peak memory 208444 kb
Host smart-28db0cfd-c7ed-435c-af26-46c69ca617cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274837259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2274837259
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.547564972
Short name T599
Test name
Test status
Simulation time 18617806820 ps
CPU time 543.61 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:57:06 PM PDT 24
Peak memory 200136 kb
Host smart-b2c292fa-aff3-4701-a433-388f1ad851d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=547564972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.547564972
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3308696204
Short name T882
Test name
Test status
Simulation time 6475099634 ps
CPU time 49.19 seconds
Started Jul 18 06:47:53 PM PDT 24
Finished Jul 18 06:48:47 PM PDT 24
Peak memory 199544 kb
Host smart-0ebb7408-210f-4fb8-88cb-e2dba0017668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308696204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3308696204
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.163073308
Short name T922
Test name
Test status
Simulation time 28411216058 ps
CPU time 46.72 seconds
Started Jul 18 06:47:59 PM PDT 24
Finished Jul 18 06:48:47 PM PDT 24
Peak memory 200148 kb
Host smart-73bdf0b2-84bd-44a6-822d-43f2fb6cbe0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163073308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.163073308
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.697202394
Short name T561
Test name
Test status
Simulation time 1688719434 ps
CPU time 3.24 seconds
Started Jul 18 06:47:59 PM PDT 24
Finished Jul 18 06:48:04 PM PDT 24
Peak memory 195680 kb
Host smart-48ee4179-ee29-4363-9c46-969309874e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697202394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.697202394
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.311793554
Short name T581
Test name
Test status
Simulation time 735222093 ps
CPU time 1.32 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:48:03 PM PDT 24
Peak memory 199072 kb
Host smart-ac521daa-9ea6-4bef-9666-30acaf463695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311793554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.311793554
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.184336648
Short name T810
Test name
Test status
Simulation time 431168144081 ps
CPU time 226.74 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:51:50 PM PDT 24
Peak memory 215864 kb
Host smart-bab8ddeb-5109-4876-867c-098ac8451427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184336648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.184336648
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3134066662
Short name T875
Test name
Test status
Simulation time 1121350848 ps
CPU time 2.48 seconds
Started Jul 18 06:48:04 PM PDT 24
Finished Jul 18 06:48:10 PM PDT 24
Peak memory 199972 kb
Host smart-6fc7e80d-0e28-4376-bdfe-703ffd5a4d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134066662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3134066662
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2741911361
Short name T757
Test name
Test status
Simulation time 10344251114 ps
CPU time 8.65 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:48:13 PM PDT 24
Peak memory 198088 kb
Host smart-29705edf-4734-44b7-a93d-5b5476daa77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741911361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2741911361
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2787876211
Short name T133
Test name
Test status
Simulation time 16379213890 ps
CPU time 14.78 seconds
Started Jul 18 06:51:34 PM PDT 24
Finished Jul 18 06:51:53 PM PDT 24
Peak memory 200188 kb
Host smart-65dc7b83-7e75-47ed-bc7d-73ed9c4fdfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787876211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2787876211
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1365215429
Short name T38
Test name
Test status
Simulation time 53827299199 ps
CPU time 582.54 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 07:01:19 PM PDT 24
Peak memory 216864 kb
Host smart-15194a80-161a-46f5-81c4-e6256404fed5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365215429 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1365215429
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3539441854
Short name T1170
Test name
Test status
Simulation time 57541715977 ps
CPU time 96.04 seconds
Started Jul 18 06:51:34 PM PDT 24
Finished Jul 18 06:53:15 PM PDT 24
Peak memory 200136 kb
Host smart-6b104dd0-1865-4f2b-82ad-e4219217ea18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539441854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3539441854
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3906980749
Short name T985
Test name
Test status
Simulation time 702090719440 ps
CPU time 609.48 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 07:01:46 PM PDT 24
Peak memory 217020 kb
Host smart-8e4a7925-7494-439e-b995-1b0167c870da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906980749 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3906980749
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3846403749
Short name T193
Test name
Test status
Simulation time 32705519612 ps
CPU time 55 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 06:52:31 PM PDT 24
Peak memory 200176 kb
Host smart-aa53805e-b634-4ed2-9483-fff2a9b68b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846403749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3846403749
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1032180363
Short name T422
Test name
Test status
Simulation time 19700306369 ps
CPU time 27.01 seconds
Started Jul 18 06:51:32 PM PDT 24
Finished Jul 18 06:52:03 PM PDT 24
Peak memory 200196 kb
Host smart-48f14bb6-feb6-4a18-9185-688459488c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032180363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1032180363
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.453295331
Short name T855
Test name
Test status
Simulation time 76616572021 ps
CPU time 715.21 seconds
Started Jul 18 06:51:40 PM PDT 24
Finished Jul 18 07:03:36 PM PDT 24
Peak memory 216660 kb
Host smart-2e10d7d9-8c70-4f1b-9254-f67ad9778c11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453295331 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.453295331
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3717567472
Short name T1051
Test name
Test status
Simulation time 71136791451 ps
CPU time 43.41 seconds
Started Jul 18 06:51:39 PM PDT 24
Finished Jul 18 06:52:24 PM PDT 24
Peak memory 200140 kb
Host smart-ae50a9ff-f4f1-4700-bcda-cb34e5eae1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717567472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3717567472
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1140797009
Short name T930
Test name
Test status
Simulation time 71573637097 ps
CPU time 29.61 seconds
Started Jul 18 06:51:40 PM PDT 24
Finished Jul 18 06:52:11 PM PDT 24
Peak memory 199880 kb
Host smart-68205441-b600-418a-9789-f53e1dfa3736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140797009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1140797009
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.4155223227
Short name T870
Test name
Test status
Simulation time 19384736302 ps
CPU time 190.52 seconds
Started Jul 18 06:51:38 PM PDT 24
Finished Jul 18 06:54:51 PM PDT 24
Peak memory 216860 kb
Host smart-eeddae5f-9f8b-44ff-ada9-634d5406b60d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155223227 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.4155223227
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1805031601
Short name T314
Test name
Test status
Simulation time 21700488715 ps
CPU time 28.42 seconds
Started Jul 18 06:51:37 PM PDT 24
Finished Jul 18 06:52:08 PM PDT 24
Peak memory 198900 kb
Host smart-038def1a-5dc5-486d-97d7-8416b078e0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805031601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1805031601
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1458069120
Short name T109
Test name
Test status
Simulation time 113003947789 ps
CPU time 358.73 seconds
Started Jul 18 06:51:55 PM PDT 24
Finished Jul 18 06:57:55 PM PDT 24
Peak memory 216464 kb
Host smart-e1bbe685-15c8-4102-9d13-b25fcec42748
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458069120 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1458069120
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2032051246
Short name T125
Test name
Test status
Simulation time 229634241884 ps
CPU time 62.31 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 06:53:02 PM PDT 24
Peak memory 200192 kb
Host smart-81e7956d-b093-4df3-a0d1-8a857dfa2358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032051246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2032051246
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1182423984
Short name T1068
Test name
Test status
Simulation time 190155666123 ps
CPU time 966.63 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 07:08:07 PM PDT 24
Peak memory 229592 kb
Host smart-2212b31c-7486-4787-a198-162bf20411ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182423984 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1182423984
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.871358988
Short name T1024
Test name
Test status
Simulation time 133482086818 ps
CPU time 13.22 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 06:52:12 PM PDT 24
Peak memory 200172 kb
Host smart-223eac6d-f0f0-485b-9881-f436780c6f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871358988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.871358988
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2359303268
Short name T675
Test name
Test status
Simulation time 35562269792 ps
CPU time 379.74 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 06:58:20 PM PDT 24
Peak memory 216728 kb
Host smart-c23d0ccb-64cb-44b2-9c27-4db8711e73ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359303268 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2359303268
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.465337932
Short name T1002
Test name
Test status
Simulation time 17528062870 ps
CPU time 33.02 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 06:52:32 PM PDT 24
Peak memory 200132 kb
Host smart-c050d522-38e3-472e-8c2f-1b463bdd8e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465337932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.465337932
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3163133901
Short name T842
Test name
Test status
Simulation time 295621013327 ps
CPU time 203.26 seconds
Started Jul 18 06:51:55 PM PDT 24
Finished Jul 18 06:55:20 PM PDT 24
Peak memory 209552 kb
Host smart-95d27635-dee9-4ab9-a08a-d5fa16483ee0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163133901 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3163133901
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3129223593
Short name T739
Test name
Test status
Simulation time 55962618 ps
CPU time 0.57 seconds
Started Jul 18 06:48:06 PM PDT 24
Finished Jul 18 06:48:10 PM PDT 24
Peak memory 195644 kb
Host smart-61b8e68e-4825-4884-a9dc-20d583607776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129223593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3129223593
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2819333417
Short name T899
Test name
Test status
Simulation time 21652808263 ps
CPU time 9.32 seconds
Started Jul 18 06:48:01 PM PDT 24
Finished Jul 18 06:48:14 PM PDT 24
Peak memory 200192 kb
Host smart-11839fbb-541c-42aa-9786-976bafb54e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819333417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2819333417
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.962255692
Short name T701
Test name
Test status
Simulation time 180867702689 ps
CPU time 345.57 seconds
Started Jul 18 06:48:06 PM PDT 24
Finished Jul 18 06:53:55 PM PDT 24
Peak memory 200140 kb
Host smart-92c69c0b-c093-45db-905f-ad4719b58c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962255692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.962255692
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_intr.528616231
Short name T1159
Test name
Test status
Simulation time 239623591693 ps
CPU time 108.09 seconds
Started Jul 18 06:48:04 PM PDT 24
Finished Jul 18 06:49:55 PM PDT 24
Peak memory 200200 kb
Host smart-c331dce1-0d74-42ed-a482-70edbe1832f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528616231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.528616231
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2082296546
Short name T881
Test name
Test status
Simulation time 128336390961 ps
CPU time 485.46 seconds
Started Jul 18 06:48:09 PM PDT 24
Finished Jul 18 06:56:18 PM PDT 24
Peak memory 200176 kb
Host smart-324dd2fd-897e-4dce-9460-8d4b688b9e53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082296546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2082296546
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3481962848
Short name T927
Test name
Test status
Simulation time 11825772343 ps
CPU time 5.22 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:48:13 PM PDT 24
Peak memory 200168 kb
Host smart-1e5f427f-3882-4cf7-ba97-9f479e7b4b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481962848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3481962848
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3533644649
Short name T869
Test name
Test status
Simulation time 60511128040 ps
CPU time 63.07 seconds
Started Jul 18 06:48:06 PM PDT 24
Finished Jul 18 06:49:13 PM PDT 24
Peak memory 200252 kb
Host smart-1a5ca7ce-e7ff-4ddf-974b-999e6eb83170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533644649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3533644649
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.405551574
Short name T1074
Test name
Test status
Simulation time 22790687389 ps
CPU time 75.86 seconds
Started Jul 18 06:48:08 PM PDT 24
Finished Jul 18 06:49:28 PM PDT 24
Peak memory 200144 kb
Host smart-90e904c0-ccd0-476c-ae0c-57d8d5730d48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405551574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.405551574
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3190419852
Short name T18
Test name
Test status
Simulation time 2226806737 ps
CPU time 9.12 seconds
Started Jul 18 06:48:04 PM PDT 24
Finished Jul 18 06:48:16 PM PDT 24
Peak memory 198352 kb
Host smart-8f1a7836-f49a-477f-9599-a74352cd0ab4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190419852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3190419852
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.301032429
Short name T3
Test name
Test status
Simulation time 23923616364 ps
CPU time 39.66 seconds
Started Jul 18 06:48:09 PM PDT 24
Finished Jul 18 06:48:52 PM PDT 24
Peak memory 200184 kb
Host smart-352598ee-8abe-4c37-b4d8-5578dbca8b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301032429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.301032429
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3368540337
Short name T472
Test name
Test status
Simulation time 2046902449 ps
CPU time 2.41 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:48:10 PM PDT 24
Peak memory 195688 kb
Host smart-208b2006-4f2c-444b-8229-2074c753618e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368540337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3368540337
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.4068405499
Short name T1028
Test name
Test status
Simulation time 907411106 ps
CPU time 1.66 seconds
Started Jul 18 06:48:05 PM PDT 24
Finished Jul 18 06:48:10 PM PDT 24
Peak memory 198632 kb
Host smart-11b38361-a486-41eb-9632-b3bee9fdf0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068405499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.4068405499
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2220792450
Short name T443
Test name
Test status
Simulation time 134113980254 ps
CPU time 239.05 seconds
Started Jul 18 06:48:08 PM PDT 24
Finished Jul 18 06:52:11 PM PDT 24
Peak memory 200180 kb
Host smart-4aaba5e6-25a7-4495-a837-3bf35343c1f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220792450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2220792450
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3532537832
Short name T171
Test name
Test status
Simulation time 244298938550 ps
CPU time 836.42 seconds
Started Jul 18 06:48:07 PM PDT 24
Finished Jul 18 07:02:08 PM PDT 24
Peak memory 225036 kb
Host smart-f8c13df5-28aa-42ad-9795-c85e71d69a28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532537832 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3532537832
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.4033453777
Short name T1169
Test name
Test status
Simulation time 7987545730 ps
CPU time 16.42 seconds
Started Jul 18 06:48:06 PM PDT 24
Finished Jul 18 06:48:27 PM PDT 24
Peak memory 200156 kb
Host smart-31d16387-7d2c-4c7a-a8a2-94dfa305f93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033453777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.4033453777
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3771276267
Short name T1153
Test name
Test status
Simulation time 15352117036 ps
CPU time 24.24 seconds
Started Jul 18 06:48:00 PM PDT 24
Finished Jul 18 06:48:27 PM PDT 24
Peak memory 199732 kb
Host smart-716b29c6-23ca-43c5-aef0-c39a37ce64b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771276267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3771276267
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3617695459
Short name T761
Test name
Test status
Simulation time 87965085994 ps
CPU time 28.48 seconds
Started Jul 18 06:51:55 PM PDT 24
Finished Jul 18 06:52:25 PM PDT 24
Peak memory 200200 kb
Host smart-d70f6416-c92d-4256-9ff2-4272e9457a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617695459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3617695459
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1878422037
Short name T134
Test name
Test status
Simulation time 30520585169 ps
CPU time 368.65 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 06:58:09 PM PDT 24
Peak memory 214416 kb
Host smart-cd27f0e4-4b37-4659-b77c-d71699c5ee1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878422037 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1878422037
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3020746235
Short name T650
Test name
Test status
Simulation time 143151296490 ps
CPU time 204.3 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 06:55:22 PM PDT 24
Peak memory 200120 kb
Host smart-f008c75a-368e-4532-a18f-6f2875310571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020746235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3020746235
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1780039523
Short name T183
Test name
Test status
Simulation time 130210126288 ps
CPU time 181.1 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 06:54:58 PM PDT 24
Peak memory 200108 kb
Host smart-e4e4a632-fd9b-4027-9580-df82a64ba1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780039523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1780039523
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1281620611
Short name T659
Test name
Test status
Simulation time 69841084324 ps
CPU time 787.78 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 07:05:07 PM PDT 24
Peak memory 231660 kb
Host smart-25f96788-47d7-49a0-b2ff-e9410de2bd2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281620611 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1281620611
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2422717712
Short name T753
Test name
Test status
Simulation time 72457601809 ps
CPU time 30 seconds
Started Jul 18 06:51:58 PM PDT 24
Finished Jul 18 06:52:30 PM PDT 24
Peak memory 200204 kb
Host smart-06ba92da-7267-47d7-a3b4-e3b14f7bd112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422717712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2422717712
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.893751957
Short name T944
Test name
Test status
Simulation time 97115849750 ps
CPU time 913.92 seconds
Started Jul 18 06:51:55 PM PDT 24
Finished Jul 18 07:07:10 PM PDT 24
Peak memory 225016 kb
Host smart-882289ce-4a8b-4870-834d-d9bd6df76441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893751957 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.893751957
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2987118902
Short name T945
Test name
Test status
Simulation time 83908529718 ps
CPU time 29.42 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 06:52:28 PM PDT 24
Peak memory 200188 kb
Host smart-48354fd3-23e0-49e2-ac6a-c1da084568c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987118902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2987118902
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.296688063
Short name T744
Test name
Test status
Simulation time 160859732272 ps
CPU time 563.49 seconds
Started Jul 18 06:51:55 PM PDT 24
Finished Jul 18 07:01:20 PM PDT 24
Peak memory 216672 kb
Host smart-eb51fdd4-bc49-43f5-bcfd-8291dbaf4404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296688063 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.296688063
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3978724848
Short name T198
Test name
Test status
Simulation time 18217162746 ps
CPU time 27.08 seconds
Started Jul 18 06:51:54 PM PDT 24
Finished Jul 18 06:52:22 PM PDT 24
Peak memory 200160 kb
Host smart-0989db3f-72a6-478e-b2dd-e31d339ccb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978724848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3978724848
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.609522698
Short name T505
Test name
Test status
Simulation time 42280713660 ps
CPU time 537.73 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 07:00:56 PM PDT 24
Peak memory 216828 kb
Host smart-d15919ae-98d8-48c5-9318-f17e954c37ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609522698 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.609522698
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3055497656
Short name T1065
Test name
Test status
Simulation time 93476165536 ps
CPU time 181.41 seconds
Started Jul 18 06:51:56 PM PDT 24
Finished Jul 18 06:54:59 PM PDT 24
Peak memory 216700 kb
Host smart-332a0d27-a1c3-4897-82d8-b2f6cfbc81b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055497656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3055497656
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3650440034
Short name T614
Test name
Test status
Simulation time 109251090471 ps
CPU time 53.65 seconds
Started Jul 18 06:51:55 PM PDT 24
Finished Jul 18 06:52:49 PM PDT 24
Peak memory 200132 kb
Host smart-378a3248-f2a8-42ef-9506-5a082e8432c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650440034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3650440034
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1631504613
Short name T37
Test name
Test status
Simulation time 98192101257 ps
CPU time 1807.43 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 07:22:07 PM PDT 24
Peak memory 226896 kb
Host smart-7f2b3595-daa3-41bb-b3b9-5c06f14a0f41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631504613 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1631504613
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.508465030
Short name T792
Test name
Test status
Simulation time 99550256344 ps
CPU time 58.76 seconds
Started Jul 18 06:51:58 PM PDT 24
Finished Jul 18 06:52:59 PM PDT 24
Peak memory 200128 kb
Host smart-fb7ef825-ea10-44bb-974f-05356ad37737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508465030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.508465030
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3544649460
Short name T656
Test name
Test status
Simulation time 38156056595 ps
CPU time 228.17 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 06:55:47 PM PDT 24
Peak memory 215944 kb
Host smart-2a5b9fc4-db29-4218-b54a-038edb2e658a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544649460 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3544649460
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3736903025
Short name T227
Test name
Test status
Simulation time 44949097037 ps
CPU time 44.73 seconds
Started Jul 18 06:51:57 PM PDT 24
Finished Jul 18 06:52:44 PM PDT 24
Peak memory 200128 kb
Host smart-8e443ad8-d374-45b7-b010-f39d1352c41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736903025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3736903025
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2647184632
Short name T595
Test name
Test status
Simulation time 87284877642 ps
CPU time 339.11 seconds
Started Jul 18 06:51:55 PM PDT 24
Finished Jul 18 06:57:35 PM PDT 24
Peak memory 216736 kb
Host smart-d3d8ec59-f113-462f-ab06-74adbbb697f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647184632 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2647184632
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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