Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	117797	1			T1	142		T3	23		T4	100
all_values[1]	117797	1			T1	142		T3	23		T4	100
all_values[2]	117797	1			T1	142		T3	23		T4	100
all_values[3]	117797	1			T1	142		T3	23		T4	100
all_values[4]	117797	1			T1	142		T3	23		T4	100
all_values[5]	117797	1			T1	142		T3	23		T4	100
all_values[6]	117797	1			T1	142		T3	23		T4	100
all_values[7]	117797	1			T1	142		T3	23		T4	100
all_values[8]	117797	1			T1	142		T3	23		T4	100

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

528449

1

T1

674

T3

84

T4

600

auto[1]

531724

1

T1

604

T3

123

T4

300

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

962384

1

T1

1232

T3

186

T4

658

auto[1]

97789

1

T1

46

T3

21

T4

242

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	32867	1			T1	48		T4	8		T6	7
all_values[0]	auto[0]	auto[1]	22558	1			T1	2		T4	92		T6	2
all_values[0]	auto[1]	auto[0]	36369	1			T1	73		T3	14		T6	1
all_values[0]	auto[1]	auto[1]	26003	1			T1	19		T3	9		T6	4
all_values[1]	auto[0]	auto[0]	58487	1			T1	80		T4	37		T6	13
all_values[1]	auto[0]	auto[1]	1612	1			T4	44		T6	1		T8	5
all_values[1]	auto[1]	auto[0]	55878	1			T1	62		T3	23		T4	19
all_values[1]	auto[1]	auto[1]	1820	1			T8	4		T13	3		T32	4
all_values[2]	auto[0]	auto[0]	57523	1			T1	57		T3	14		T4	56
all_values[2]	auto[0]	auto[1]	2854	1			T1	1		T6	4		T7	2
all_values[2]	auto[1]	auto[0]	54819	1			T1	79		T3	8		T4	44
all_values[2]	auto[1]	auto[1]	2601	1			T1	5		T3	1		T7	1
all_values[3]	auto[0]	auto[0]	57373	1			T1	130		T4	43		T6	10
all_values[3]	auto[0]	auto[1]	305	1			T4	1		T8	3		T9	1
all_values[3]	auto[1]	auto[0]	59838	1			T1	12		T3	21		T4	53
all_values[3]	auto[1]	auto[1]	281	1			T3	2		T4	3		T8	2
all_values[4]	auto[0]	auto[0]	59756	1			T1	48		T3	14		T4	83
all_values[4]	auto[0]	auto[1]	413	1			T4	10		T8	2		T16	2
all_values[4]	auto[1]	auto[0]	57080	1			T1	94		T3	9		T4	6
all_values[4]	auto[1]	auto[1]	548	1			T4	1		T8	4		T14	6
all_values[5]	auto[0]	auto[0]	56912	1			T1	62		T3	14		T4	44
all_values[5]	auto[0]	auto[1]	183	1			T8	6		T16	1		T27	1
all_values[5]	auto[1]	auto[0]	60514	1			T1	80		T3	9		T4	56
all_values[5]	auto[1]	auto[1]	188	1			T8	1		T16	3		T27	2
all_values[6]	auto[0]	auto[0]	60227	1			T1	72		T3	14		T4	70
all_values[6]	auto[0]	auto[1]	212	1			T8	2		T16	2		T29	3
all_values[6]	auto[1]	auto[0]	57180	1			T1	70		T3	9		T4	30
all_values[6]	auto[1]	auto[1]	178	1			T8	4		T16	2		T27	1
all_values[7]	auto[0]	auto[0]	59063	1			T1	69		T3	14		T4	92
all_values[7]	auto[0]	auto[1]	359	1			T4	1		T8	2		T9	1
all_values[7]	auto[1]	auto[0]	58010	1			T1	73		T3	9		T4	7
all_values[7]	auto[1]	auto[1]	365	1			T8	1		T9	1		T14	1
all_values[8]	auto[0]	auto[0]	38437	1			T1	88		T3	14		T4	6
all_values[8]	auto[0]	auto[1]	19308	1			T1	17		T4	13		T6	1
all_values[8]	auto[1]	auto[0]	42051	1			T1	35		T4	4		T7	1
all_values[8]	auto[1]	auto[1]	18001	1			T1	2		T3	9		T4	77