Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2177	1			T3	2		T6	1		T7	1
auto[BaudRate115200]	1929	1			T4	2		T7	1		T8	2
auto[BaudRate230400]	2001	1			T6	1		T8	3		T11	6
auto[BaudRate128Kbps]	2001	1			T4	2		T6	2		T8	4
auto[BaudRate256Kbps]	2148	1			T1	6		T3	1		T7	1
auto[BaudRate1Mbps]	1770	1			T1	3		T3	2		T6	2
auto[BaudRate1p5Mbps]	1326	1			T1	1		T3	2		T6	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1235	1			T9	10		T129	10		T145	9
freqs[25]	942	1			T6	7		T8	23		T303	2
freqs[48]	657	1			T271	6		T174	9		T326	9
freqs[50]	722	1			T148	7		T18	27		T19	11
freqs[100]	1094	1			T1	10		T10	13		T12	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	218	1			T9	2		T129	1		T145	1
auto[BaudRate9600]	freqs[25]	101	1			T6	1		T312	1		T128	1
auto[BaudRate9600]	freqs[48]	84	1			T174	1		T326	1		T112	2
auto[BaudRate9600]	freqs[50]	96	1			T148	1		T18	4		T19	3
auto[BaudRate9600]	freqs[100]	237	1			T10	13		T276	1		T196	2
auto[BaudRate115200]	freqs[24]	161	1			T9	1		T145	1		T37	1
auto[BaudRate115200]	freqs[25]	149	1			T8	2		T312	1		T128	2
auto[BaudRate115200]	freqs[48]	104	1			T174	1		T326	1		T112	5
auto[BaudRate115200]	freqs[50]	107	1			T148	1		T18	5		T47	1
auto[BaudRate115200]	freqs[100]	120	1			T12	1		T142	1		T122	2
auto[BaudRate230400]	freqs[24]	179	1			T129	2		T37	1		T126	2
auto[BaudRate230400]	freqs[25]	143	1			T6	1		T8	3		T303	1
auto[BaudRate230400]	freqs[48]	89	1			T271	1		T174	1		T112	3
auto[BaudRate230400]	freqs[50]	82	1			T148	2		T18	3		T47	1
auto[BaudRate230400]	freqs[100]	128	1			T12	1		T142	1		T122	4
auto[BaudRate128Kbps]	freqs[24]	190	1			T9	3		T145	2		T37	1
auto[BaudRate128Kbps]	freqs[25]	150	1			T6	2		T8	4		T128	2
auto[BaudRate128Kbps]	freqs[48]	111	1			T271	2		T174	2		T326	3
auto[BaudRate128Kbps]	freqs[50]	106	1			T18	5		T19	5		T47	2
auto[BaudRate128Kbps]	freqs[100]	138	1			T142	1		T122	1		T140	2
auto[BaudRate256Kbps]	freqs[24]	218	1			T9	2		T129	5		T145	1
auto[BaudRate256Kbps]	freqs[25]	158	1			T8	7		T128	1		T40	1
auto[BaudRate256Kbps]	freqs[48]	99	1			T174	1		T112	5		T151	3
auto[BaudRate256Kbps]	freqs[50]	110	1			T18	5		T45	1		T46	3
auto[BaudRate256Kbps]	freqs[100]	142	1			T1	6		T142	1		T196	1
auto[BaudRate1Mbps]	freqs[24]	179	1			T9	1		T129	2		T145	4
auto[BaudRate1Mbps]	freqs[25]	169	1			T6	2		T8	5		T303	1
auto[BaudRate1Mbps]	freqs[48]	90	1			T271	2		T174	2		T326	2
auto[BaudRate1Mbps]	freqs[50]	117	1			T148	1		T18	2		T19	3
auto[BaudRate1Mbps]	freqs[100]	145	1			T1	3		T122	1		T140	2
auto[BaudRate1p5Mbps]	freqs[25]	72	1			T6	1		T8	2		T40	2
auto[BaudRate1p5Mbps]	freqs[48]	80	1			T271	1		T174	1		T326	2
auto[BaudRate1p5Mbps]	freqs[50]	104	1			T148	2		T18	3		T45	1
auto[BaudRate1p5Mbps]	freqs[100]	184	1			T1	1		T142	1		T276	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded