Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	6	124	95.38

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	6	124	95.38	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	32917418	1			T1	314889		T3	20		T4	970
all_levels[1]	210087	1			T1	1486		T6	7		T7	76
all_levels[2]	2448	1			T3	1		T6	4		T7	5
all_levels[3]	1081	1			T6	4		T11	1		T12	3
all_levels[4]	739	1			T6	1		T8	1		T9	2
all_levels[5]	543	1			T6	1		T9	3		T11	2
all_levels[6]	419	1			T6	3		T11	1		T13	1
all_levels[7]	349	1			T3	1		T6	1		T12	1
all_levels[8]	328	1			T6	1		T8	1		T139	1
all_levels[9]	238	1			T9	1		T32	1		T33	2
all_levels[10]	228	1			T6	2		T32	1		T17	1
all_levels[11]	200	1			T8	1		T32	3		T18	2
all_levels[12]	156	1			T13	1		T32	2		T33	1
all_levels[13]	155	1			T6	1		T13	1		T140	1
all_levels[14]	148	1			T8	1		T32	1		T26	1
all_levels[15]	122	1			T8	1		T13	1		T17	1
all_levels[16]	110	1			T18	1		T141	1		T142	1
all_levels[17]	106	1			T8	1		T32	1		T142	1
all_levels[18]	79	1			T17	1		T139	1		T141	2
all_levels[19]	87	1			T3	1		T13	2		T143	2
all_levels[20]	83	1			T127	1		T140	1		T40	3
all_levels[21]	80	1			T142	1		T127	1		T29	1
all_levels[22]	54	1			T17	1		T16	1		T27	1
all_levels[23]	51	1			T127	1		T132	1		T144	1
all_levels[24]	55	1			T8	2		T13	3		T33	1
all_levels[25]	41	1			T33	1		T18	2		T141	1
all_levels[26]	54	1			T3	1		T17	2		T127	1
all_levels[27]	42	1			T18	1		T128	3		T16	1
all_levels[28]	41	1			T17	2		T127	1		T132	1
all_levels[29]	45	1			T8	1		T145	1		T127	1
all_levels[30]	44	1			T30	1		T146	1		T147	1
all_levels[31]	46	1			T148	1		T142	1		T42	1
all_levels[32]	40	1			T148	1		T142	1		T129	2
all_levels[33]	31	1			T148	3		T149	1		T103	1
all_levels[34]	39	1			T32	1		T18	1		T150	1
all_levels[35]	29	1			T16	1		T70	3		T72	2
all_levels[36]	26	1			T128	1		T16	1		T30	1
all_levels[37]	21	1			T151	1		T152	1		T153	1
all_levels[38]	17	1			T70	2		T153	1		T154	1
all_levels[39]	16	1			T141	1		T72	1		T155	1
all_levels[40]	21	1			T145	1		T49	1		T137	1
all_levels[41]	19	1			T145	1		T16	1		T156	1
all_levels[42]	14	1			T153	1		T157	3		T158	1
all_levels[43]	18	1			T30	1		T72	1		T155	2
all_levels[44]	13	1			T159	1		T160	1		T161	1
all_levels[45]	14	1			T17	1		T49	1		T70	1
all_levels[46]	6	1			T162	1		T163	1		T164	1
all_levels[47]	16	1			T165	1		T166	1		T167	1
all_levels[48]	13	1			T8	1		T128	3		T30	1
all_levels[49]	4	1			T149	1		T168	1		T169	1
all_levels[50]	14	1			T132	3		T144	1		T103	1
all_levels[51]	11	1			T170	1		T171	1		T172	1
all_levels[52]	13	1			T6	1		T30	1		T137	1
all_levels[53]	9	1			T18	1		T30	1		T173	1
all_levels[54]	22	1			T174	1		T72	1		T175	3
all_levels[55]	11	1			T72	3		T156	1		T135	1
all_levels[56]	9	1			T30	2		T176	1		T177	2
all_levels[57]	6	1			T178	1		T179	1		T164	1
all_levels[58]	10	1			T17	1		T142	1		T72	1
all_levels[59]	8	1			T180	1		T134	1		T181	1
all_levels[60]	10	1			T137	1		T156	2		T169	2
all_levels[61]	9	1			T151	1		T182	3		T183	1
all_levels[62]	13	1			T6	1		T72	2		T169	2
all_levels[63]	3	1			T148	1		T184	1		T182	1
all_levels[64]	121	1			T3	2		T9	1		T148	3

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33131502

1

T1

316375

T3

26

T4

932

auto[1]

4801

1

T4

38

T6

7

T7

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	6	124	95.38	6

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[49]]	[auto[1]]	0	1	1
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	32913142	1			T1	314889		T3	20		T4	932
all_levels[0]	auto[1]	4276	1			T4	38		T6	5		T7	5
all_levels[1]	auto[0]	210009	1			T1	1486		T6	6		T7	76
all_levels[1]	auto[1]	78	1			T6	1		T129	1		T128	1
all_levels[2]	auto[0]	2411	1			T3	1		T6	4		T7	5
all_levels[2]	auto[1]	37	1			T148	2		T140	1		T185	1
all_levels[3]	auto[0]	1067	1			T6	4		T11	1		T12	3
all_levels[3]	auto[1]	14	1			T30	1		T186	2		T187	2
all_levels[4]	auto[0]	714	1			T6	1		T8	1		T9	2
all_levels[4]	auto[1]	25	1			T188	5		T157	2		T189	1
all_levels[5]	auto[0]	518	1			T6	1		T9	3		T11	2
all_levels[5]	auto[1]	25	1			T174	3		T73	1		T190	2
all_levels[6]	auto[0]	405	1			T6	2		T11	1		T13	1
all_levels[6]	auto[1]	14	1			T6	1		T127	1		T132	1
all_levels[7]	auto[0]	331	1			T3	1		T6	1		T12	1
all_levels[7]	auto[1]	18	1			T40	1		T191	2		T192	1
all_levels[8]	auto[0]	311	1			T6	1		T8	1		T139	1
all_levels[8]	auto[1]	17	1			T76	1		T193	1		T162	4
all_levels[9]	auto[0]	231	1			T9	1		T32	1		T33	2
all_levels[9]	auto[1]	7	1			T70	1		T194	1		T195	1
all_levels[10]	auto[0]	207	1			T6	2		T32	1		T17	1
all_levels[10]	auto[1]	21	1			T196	2		T38	1		T174	1
all_levels[11]	auto[0]	180	1			T8	1		T32	3		T18	2
all_levels[11]	auto[1]	20	1			T40	1		T180	1		T197	1
all_levels[12]	auto[0]	146	1			T13	1		T32	2		T33	1
all_levels[12]	auto[1]	10	1			T198	3		T178	1		T199	1
all_levels[13]	auto[0]	141	1			T6	1		T13	1		T140	1
all_levels[13]	auto[1]	14	1			T200	4		T201	1		T202	1
all_levels[14]	auto[0]	137	1			T8	1		T32	1		T26	1
all_levels[14]	auto[1]	11	1			T71	3		T187	1		T203	1
all_levels[15]	auto[0]	106	1			T8	1		T13	1		T17	1
all_levels[15]	auto[1]	16	1			T178	1		T204	2		T203	1
all_levels[16]	auto[0]	95	1			T18	1		T141	1		T142	1
all_levels[16]	auto[1]	15	1			T205	2		T186	1		T206	1
all_levels[17]	auto[0]	101	1			T8	1		T32	1		T142	1
all_levels[17]	auto[1]	5	1			T207	1		T208	2		T209	1
all_levels[18]	auto[0]	73	1			T17	1		T139	1		T141	2
all_levels[18]	auto[1]	6	1			T146	3		T191	1		T210	1
all_levels[19]	auto[0]	76	1			T3	1		T13	2		T143	1
all_levels[19]	auto[1]	11	1			T143	1		T140	1		T211	1
all_levels[20]	auto[0]	75	1			T127	1		T140	1		T40	1
all_levels[20]	auto[1]	8	1			T40	2		T212	1		T213	4
all_levels[21]	auto[0]	75	1			T142	1		T127	1		T29	1
all_levels[21]	auto[1]	5	1			T214	1		T187	1		T162	1
all_levels[22]	auto[0]	51	1			T17	1		T16	1		T27	1
all_levels[22]	auto[1]	3	1			T215	1		T216	1		T217	1
all_levels[23]	auto[0]	50	1			T127	1		T132	1		T144	1
all_levels[23]	auto[1]	1	1			T218	1		-	-		-	-
all_levels[24]	auto[0]	53	1			T8	2		T13	2		T33	1
all_levels[24]	auto[1]	2	1			T13	1		T219	1		-	-
all_levels[25]	auto[0]	40	1			T33	1		T18	2		T141	1
all_levels[25]	auto[1]	1	1			T220	1		-	-		-	-
all_levels[26]	auto[0]	46	1			T3	1		T17	2		T127	1
all_levels[26]	auto[1]	8	1			T120	4		T159	1		T221	1
all_levels[27]	auto[0]	40	1			T18	1		T128	1		T16	1
all_levels[27]	auto[1]	2	1			T128	2		-	-		-	-
all_levels[28]	auto[0]	39	1			T17	2		T127	1		T132	1
all_levels[28]	auto[1]	2	1			T189	1		T222	1		-	-
all_levels[29]	auto[0]	37	1			T8	1		T145	1		T127	1
all_levels[29]	auto[1]	8	1			T163	2		T223	1		T220	1
all_levels[30]	auto[0]	40	1			T30	1		T146	1		T147	1
all_levels[30]	auto[1]	4	1			T224	1		T225	1		T226	1
all_levels[31]	auto[0]	35	1			T148	1		T142	1		T42	1
all_levels[31]	auto[1]	11	1			T131	1		T227	3		T228	3
all_levels[32]	auto[0]	31	1			T148	1		T142	1		T129	1
all_levels[32]	auto[1]	9	1			T129	1		T229	1		T194	2
all_levels[33]	auto[0]	28	1			T148	1		T149	1		T103	1
all_levels[33]	auto[1]	3	1			T148	2		T109	1		-	-
all_levels[34]	auto[0]	31	1			T32	1		T18	1		T150	1
all_levels[34]	auto[1]	8	1			T103	1		T230	4		T231	2
all_levels[35]	auto[0]	25	1			T16	1		T70	3		T72	1
all_levels[35]	auto[1]	4	1			T72	1		T232	2		T233	1
all_levels[36]	auto[0]	22	1			T128	1		T16	1		T30	1
all_levels[36]	auto[1]	4	1			T149	1		T234	3		-	-
all_levels[37]	auto[0]	20	1			T151	1		T152	1		T153	1
all_levels[37]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[38]	auto[0]	15	1			T70	1		T153	1		T154	1
all_levels[38]	auto[1]	2	1			T70	1		T236	1		-	-
all_levels[39]	auto[0]	14	1			T141	1		T72	1		T155	1
all_levels[39]	auto[1]	2	1			T237	1		T238	1		-	-
all_levels[40]	auto[0]	15	1			T145	1		T49	1		T137	1
all_levels[40]	auto[1]	6	1			T154	2		T239	1		T240	3
all_levels[41]	auto[0]	17	1			T145	1		T16	1		T156	1
all_levels[41]	auto[1]	2	1			T241	2		-	-		-	-
all_levels[42]	auto[0]	12	1			T153	1		T157	2		T158	1
all_levels[42]	auto[1]	2	1			T157	1		T242	1		-	-
all_levels[43]	auto[0]	14	1			T30	1		T72	1		T155	1
all_levels[43]	auto[1]	4	1			T155	1		T219	3		-	-
all_levels[44]	auto[0]	11	1			T159	1		T160	1		T161	1
all_levels[44]	auto[1]	2	1			T243	2		-	-		-	-
all_levels[45]	auto[0]	12	1			T17	1		T49	1		T70	1
all_levels[45]	auto[1]	2	1			T236	1		T244	1		-	-
all_levels[46]	auto[0]	6	1			T162	1		T163	1		T164	1
all_levels[47]	auto[0]	10	1			T165	1		T166	1		T167	1
all_levels[47]	auto[1]	6	1			T216	2		T245	1		T246	1
all_levels[48]	auto[0]	8	1			T8	1		T128	1		T30	1
all_levels[48]	auto[1]	5	1			T128	2		T247	2		T167	1
all_levels[49]	auto[0]	4	1			T149	1		T168	1		T169	1
all_levels[50]	auto[0]	11	1			T132	1		T144	1		T103	1
all_levels[50]	auto[1]	3	1			T132	2		T248	1		-	-
all_levels[51]	auto[0]	11	1			T170	1		T171	1		T172	1
all_levels[52]	auto[0]	12	1			T6	1		T30	1		T137	1
all_levels[52]	auto[1]	1	1			T249	1		-	-		-	-
all_levels[53]	auto[0]	8	1			T18	1		T30	1		T173	1
all_levels[53]	auto[1]	1	1			T250	1		-	-		-	-
all_levels[54]	auto[0]	21	1			T174	1		T72	1		T175	3
all_levels[54]	auto[1]	1	1			T251	1		-	-		-	-
all_levels[55]	auto[0]	7	1			T72	1		T156	1		T135	1
all_levels[55]	auto[1]	4	1			T72	2		T155	2		-	-
all_levels[56]	auto[0]	7	1			T30	1		T176	1		T177	1
all_levels[56]	auto[1]	2	1			T30	1		T177	1		-	-
all_levels[57]	auto[0]	6	1			T178	1		T179	1		T164	1
all_levels[58]	auto[0]	8	1			T17	1		T142	1		T72	1
all_levels[58]	auto[1]	2	1			T252	2		-	-		-	-
all_levels[59]	auto[0]	8	1			T180	1		T134	1		T181	1
all_levels[60]	auto[0]	8	1			T137	1		T156	2		T169	2
all_levels[60]	auto[1]	2	1			T253	1		T254	1		-	-
all_levels[61]	auto[0]	7	1			T151	1		T182	1		T183	1
all_levels[61]	auto[1]	2	1			T182	2		-	-		-	-
all_levels[62]	auto[0]	11	1			T6	1		T72	1		T169	2
all_levels[62]	auto[1]	2	1			T72	1		T255	1		-	-
all_levels[63]	auto[0]	3	1			T148	1		T184	1		T182	1
all_levels[64]	auto[0]	97	1			T3	2		T9	1		T148	2
all_levels[64]	auto[1]	24	1			T148	1		T192	1		T256	3