Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	117797	1			T1	142		T3	23		T4	100
all_pins[1]	117797	1			T1	142		T3	23		T4	100
all_pins[2]	117797	1			T1	142		T3	23		T4	100
all_pins[3]	117797	1			T1	142		T3	23		T4	100
all_pins[4]	117797	1			T1	142		T3	23		T4	100
all_pins[5]	117797	1			T1	142		T3	23		T4	100
all_pins[6]	117797	1			T1	142		T3	23		T4	100
all_pins[7]	117797	1			T1	142		T3	23		T4	100
all_pins[8]	117797	1			T1	142		T3	23		T4	100

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1009255	1			T1	1252		T3	181		T4	811
values[0x1]	50918	1			T1	26		T3	26		T4	89
transitions[0x0=>0x1]	40435	1			T1	26		T3	17		T4	88
transitions[0x1=>0x0]	40206	1			T1	26		T3	16		T4	89

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	91725	1			T1	123		T3	14		T4	100
all_pins[0]	values[0x1]	26072	1			T1	19		T3	9		T6	4
all_pins[0]	transitions[0x0=>0x1]	25386	1			T1	19		T3	9		T6	4
all_pins[0]	transitions[0x1=>0x0]	1130	1			T13	3		T32	4		T14	2
all_pins[1]	values[0x0]	115981	1			T1	142		T3	23		T4	100
all_pins[1]	values[0x1]	1816	1			T8	4		T13	3		T32	4
all_pins[1]	transitions[0x0=>0x1]	1714	1			T8	4		T13	3		T14	2
all_pins[1]	transitions[0x1=>0x0]	2539	1			T1	5		T3	1		T4	4
all_pins[2]	values[0x0]	115156	1			T1	137		T3	22		T4	96
all_pins[2]	values[0x1]	2641	1			T1	5		T3	1		T4	4
all_pins[2]	transitions[0x0=>0x1]	2586	1			T1	5		T4	4		T7	1
all_pins[2]	transitions[0x1=>0x0]	226	1			T3	1		T4	3		T8	2
all_pins[3]	values[0x0]	117516	1			T1	142		T3	21		T4	97
all_pins[3]	values[0x1]	281	1			T3	2		T4	3		T8	2
all_pins[3]	transitions[0x0=>0x1]	238	1			T3	2		T4	3		T8	2
all_pins[3]	transitions[0x1=>0x0]	505	1			T4	1		T8	4		T14	6
all_pins[4]	values[0x0]	117249	1			T1	142		T3	23		T4	99
all_pins[4]	values[0x1]	548	1			T4	1		T8	4		T14	6
all_pins[4]	transitions[0x0=>0x1]	472	1			T4	1		T8	4		T14	6
all_pins[4]	transitions[0x1=>0x0]	171	1			T4	2		T8	1		T16	3
all_pins[5]	values[0x0]	117550	1			T1	142		T3	23		T4	98
all_pins[5]	values[0x1]	247	1			T4	2		T8	1		T16	4
all_pins[5]	transitions[0x0=>0x1]	205	1			T4	2		T8	1		T16	4
all_pins[5]	transitions[0x1=>0x0]	825	1			T3	5		T4	2		T8	4
all_pins[6]	values[0x0]	116930	1			T1	142		T3	18		T4	98
all_pins[6]	values[0x1]	867	1			T3	5		T4	2		T8	4
all_pins[6]	transitions[0x0=>0x1]	818	1			T3	5		T4	2		T8	4
all_pins[6]	transitions[0x1=>0x0]	316	1			T8	1		T9	1		T14	1
all_pins[7]	values[0x0]	117432	1			T1	142		T3	23		T4	100
all_pins[7]	values[0x1]	365	1			T8	1		T9	1		T14	1
all_pins[7]	transitions[0x0=>0x1]	188	1			T8	1		T9	1		T14	1
all_pins[7]	transitions[0x1=>0x0]	17904	1			T1	2		T3	9		T4	77
all_pins[8]	values[0x0]	99716	1			T1	140		T3	14		T4	23
all_pins[8]	values[0x1]	18081	1			T1	2		T3	9		T4	77
all_pins[8]	transitions[0x0=>0x1]	8828	1			T1	2		T3	1		T4	76
all_pins[8]	transitions[0x1=>0x0]	16590	1			T1	19		T8	19		T11	17