Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8676094	1			T1	15610		T3	4		T4	17
all_levels[1]	2004321	1			T1	296		T3	5		T6	37
all_levels[2]	334577	1			T1	274		T7	1		T8	45
all_levels[3]	225914	1			T1	293		T7	1		T8	45
all_levels[4]	400398	1			T1	264		T6	2		T8	51
all_levels[5]	295023	1			T1	284		T3	1		T8	42
all_levels[6]	319188	1			T1	290		T3	2		T8	37
all_levels[7]	219408	1			T1	291		T3	1		T4	20
all_levels[8]	405370	1			T1	302		T3	1		T4	931
all_levels[9]	531379	1			T1	272		T7	2		T8	40
all_levels[10]	230400	1			T1	269		T6	7		T8	40
all_levels[11]	201450	1			T1	303		T8	43		T13	2
all_levels[12]	284381	1			T1	292		T8	38		T9	1
all_levels[13]	197620	1			T1	307		T3	2		T8	49
all_levels[14]	285568	1			T1	312		T7	290		T8	44
all_levels[15]	361582	1			T1	296		T8	39		T9	3
all_levels[16]	268775	1			T1	275		T8	50		T9	1
all_levels[17]	496739	1			T1	298		T8	50		T33	2
all_levels[18]	231177	1			T1	296		T8	48		T11	12
all_levels[19]	328318	1			T1	291		T8	46		T33	2
all_levels[20]	331313	1			T1	296		T7	1		T8	42
all_levels[21]	381481	1			T1	274		T8	41		T9	1
all_levels[22]	168048	1			T1	277		T8	41		T33	2
all_levels[23]	279580	1			T1	278		T8	57		T9	3
all_levels[24]	330674	1			T1	261		T8	42		T260	190
all_levels[25]	276094	1			T1	275		T8	38		T9	2
all_levels[26]	269681	1			T1	274		T8	49		T9	1
all_levels[27]	363934	1			T1	295		T8	45		T13	2
all_levels[28]	206458	1			T1	278		T8	48		T9	1
all_levels[29]	274265	1			T1	287		T8	49		T260	181
all_levels[30]	521900	1			T1	271		T8	39		T260	176
all_levels[31]	620314	1			T1	10311		T8	529		T260	4591
all_levels[32]	12814601	1			T1	281883		T3	10		T8	8705

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33131502

1

T1

316375

T3

26

T4

932

auto[1]

4523

1

T4

36

T6

6

T7

5

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8673506	1			T1	15610		T3	4		T6	3
all_levels[0]	auto[1]	2588	1			T4	17		T6	3		T7	3
all_levels[1]	auto[0]	2003892	1			T1	296		T3	5		T6	36
all_levels[1]	auto[1]	429	1			T6	1		T12	1		T139	1
all_levels[2]	auto[0]	334518	1			T1	274		T7	1		T8	45
all_levels[2]	auto[1]	59	1			T33	1		T259	1		T143	1
all_levels[3]	auto[0]	225773	1			T1	293		T7	1		T8	45
all_levels[3]	auto[1]	141	1			T15	1		T16	7		T130	8
all_levels[4]	auto[0]	400350	1			T1	264		T6	2		T8	51
all_levels[4]	auto[1]	48	1			T143	2		T149	2		T70	1
all_levels[5]	auto[0]	295003	1			T1	284		T3	1		T8	42
all_levels[5]	auto[1]	20	1			T73	1		T107	1		T330	1
all_levels[6]	auto[0]	319160	1			T1	290		T3	2		T8	37
all_levels[6]	auto[1]	28	1			T229	1		T191	2		T227	1
all_levels[7]	auto[0]	219305	1			T1	291		T3	1		T4	1
all_levels[7]	auto[1]	103	1			T4	19		T14	4		T196	1
all_levels[8]	auto[0]	405332	1			T1	302		T3	1		T4	931
all_levels[8]	auto[1]	38	1			T7	1		T13	1		T311	1
all_levels[9]	auto[0]	531340	1			T1	272		T7	2		T8	40
all_levels[9]	auto[1]	39	1			T39	1		T262	1		T104	1
all_levels[10]	auto[0]	230376	1			T1	269		T6	5		T8	40
all_levels[10]	auto[1]	24	1			T6	2		T147	3		T177	1
all_levels[11]	auto[0]	201424	1			T1	303		T8	43		T13	2
all_levels[11]	auto[1]	26	1			T129	2		T30	2		T137	1
all_levels[12]	auto[0]	284359	1			T1	292		T8	38		T9	1
all_levels[12]	auto[1]	22	1			T129	1		T37	1		T71	1
all_levels[13]	auto[0]	197594	1			T1	307		T3	2		T8	49
all_levels[13]	auto[1]	26	1			T139	1		T305	1		T321	2
all_levels[14]	auto[0]	285552	1			T1	312		T7	289		T8	44
all_levels[14]	auto[1]	16	1			T7	1		T207	3		T72	1
all_levels[15]	auto[0]	361456	1			T1	296		T8	39		T9	2
all_levels[15]	auto[1]	126	1			T9	1		T265	1		T266	5
all_levels[16]	auto[0]	268746	1			T1	275		T8	50		T9	1
all_levels[16]	auto[1]	29	1			T148	1		T274	1		T27	1
all_levels[17]	auto[0]	496712	1			T1	298		T8	50		T33	2
all_levels[17]	auto[1]	27	1			T42	1		T30	1		T76	1
all_levels[18]	auto[0]	231152	1			T1	296		T8	48		T11	12
all_levels[18]	auto[1]	25	1			T323	1		T133	1		T331	1
all_levels[19]	auto[0]	328300	1			T1	291		T8	46		T33	2
all_levels[19]	auto[1]	18	1			T124	1		T294	1		T262	1
all_levels[20]	auto[0]	331290	1			T1	296		T7	1		T8	42
all_levels[20]	auto[1]	23	1			T140	2		T174	1		T198	1
all_levels[21]	auto[0]	381466	1			T1	274		T8	41		T9	1
all_levels[21]	auto[1]	15	1			T149	1		T214	1		T165	1
all_levels[22]	auto[0]	168025	1			T1	277		T8	41		T33	2
all_levels[22]	auto[1]	23	1			T40	1		T291	1		T326	4
all_levels[23]	auto[0]	279560	1			T1	278		T8	57		T9	3
all_levels[23]	auto[1]	20	1			T196	1		T109	3		T208	1
all_levels[24]	auto[0]	330659	1			T1	261		T8	42		T260	190
all_levels[24]	auto[1]	15	1			T274	1		T132	1		T332	2
all_levels[25]	auto[0]	276076	1			T1	275		T8	38		T9	2
all_levels[25]	auto[1]	18	1			T281	1		T333	1		T157	2
all_levels[26]	auto[0]	269663	1			T1	274		T8	49		T9	1
all_levels[26]	auto[1]	18	1			T148	1		T120	3		T299	1
all_levels[27]	auto[0]	363916	1			T1	295		T8	45		T13	2
all_levels[27]	auto[1]	18	1			T334	1		T146	1		T198	2
all_levels[28]	auto[0]	206444	1			T1	278		T8	48		T9	1
all_levels[28]	auto[1]	14	1			T174	4		T335	3		T167	1
all_levels[29]	auto[0]	274246	1			T1	287		T8	49		T260	181
all_levels[29]	auto[1]	19	1			T191	1		T264	1		T175	2
all_levels[30]	auto[0]	521881	1			T1	271		T8	39		T260	176
all_levels[30]	auto[1]	19	1			T106	2		T157	1		T336	1
all_levels[31]	auto[0]	620297	1			T1	10311		T8	529		T260	4591
all_levels[31]	auto[1]	17	1			T30	1		T229	1		T176	1
all_levels[32]	auto[0]	12814129	1			T1	281883		T3	10		T8	8705
all_levels[32]	auto[1]	472	1			T11	1		T13	3		T32	1