Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	785	1			T8	8		T16	7		T27	4
all_values[1]	785	1			T8	8		T16	7		T27	4
all_values[2]	785	1			T8	8		T16	7		T27	4
all_values[3]	785	1			T8	8		T16	7		T27	4
all_values[4]	785	1			T8	8		T16	7		T27	4
all_values[5]	785	1			T8	8		T16	7		T27	4
all_values[6]	785	1			T8	8		T16	7		T27	4
all_values[7]	785	1			T8	8		T16	7		T27	4
all_values[8]	785	1			T8	8		T16	7		T27	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3808

1

T8

45

T16

30

T27

18

auto[1]

3257

1

T8

27

T16

33

T27

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2281

1

T8

26

T16

26

T27

7

auto[1]

4784

1

T8

46

T16

37

T27

29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4162

1

T8

47

T16

39

T27

17

auto[1]

2903

1

T8

25

T16

24

T27

19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	267	1			T8	2		T29	4		T49	8
all_values[0]	auto[0]	auto[1]	auto[1]	206	1			T8	3		T16	2		T27	2
all_values[0]	auto[1]	auto[0]	auto[1]	186	1			T8	1		T16	2		T27	1
all_values[0]	auto[1]	auto[1]	auto[1]	126	1			T8	2		T16	3		T27	1
all_values[1]	auto[0]	auto[0]	auto[0]	248	1			T8	6		T16	2		T29	4
all_values[1]	auto[0]	auto[1]	auto[0]	235	1			T16	3		T27	1		T49	5
all_values[1]	auto[1]	auto[0]	auto[1]	156	1			T8	1		T16	1		T27	2
all_values[1]	auto[1]	auto[1]	auto[1]	146	1			T8	1		T16	1		T27	1
all_values[2]	auto[0]	auto[0]	auto[0]	163	1			T8	3		T16	2		T49	6
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T8	1		T29	2		T49	2
all_values[2]	auto[0]	auto[1]	auto[0]	133	1			T8	2		T16	4		T29	3
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T27	2		T29	2		T49	3
all_values[2]	auto[1]	auto[0]	auto[1]	177	1			T27	2		T29	3		T49	7
all_values[2]	auto[1]	auto[1]	auto[1]	150	1			T8	2		T16	1		T29	1
all_values[3]	auto[0]	auto[0]	auto[0]	164	1			T8	3		T16	1		T27	1
all_values[3]	auto[0]	auto[0]	auto[1]	79	1			T8	1		T16	1		T27	1
all_values[3]	auto[0]	auto[1]	auto[0]	151	1			T8	1		T16	2		T29	1
all_values[3]	auto[0]	auto[1]	auto[1]	84	1			T8	1		T29	4		T49	1
all_values[3]	auto[1]	auto[0]	auto[1]	192	1			T8	1		T16	2		T27	1
all_values[3]	auto[1]	auto[1]	auto[1]	115	1			T8	1		T16	1		T27	1
all_values[4]	auto[0]	auto[0]	auto[0]	161	1			T8	2		T16	1		T29	1
all_values[4]	auto[0]	auto[0]	auto[1]	79	1			T16	1		T27	1		T29	4
all_values[4]	auto[0]	auto[1]	auto[0]	122	1			T8	1		T16	1		T29	1
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T49	5		T135	1		T136	2
all_values[4]	auto[1]	auto[0]	auto[1]	187	1			T8	5		T16	4		T27	2
all_values[4]	auto[1]	auto[1]	auto[1]	155	1			T27	1		T49	8		T137	2
all_values[5]	auto[0]	auto[0]	auto[0]	170	1			T8	1		T16	1		T29	6
all_values[5]	auto[0]	auto[0]	auto[1]	77	1			T8	2		T49	1		T137	2
all_values[5]	auto[0]	auto[1]	auto[0]	135	1			T16	2		T29	2		T49	8
all_values[5]	auto[0]	auto[1]	auto[1]	87	1			T8	1		T16	1		T27	1
all_values[5]	auto[1]	auto[0]	auto[1]	167	1			T8	4		T16	1		T27	2
all_values[5]	auto[1]	auto[1]	auto[1]	149	1			T16	2		T27	1		T29	2
all_values[6]	auto[0]	auto[0]	auto[0]	155	1			T8	1		T27	3		T29	2
all_values[6]	auto[0]	auto[0]	auto[1]	89	1			T8	1		T16	1		T29	2
all_values[6]	auto[0]	auto[1]	auto[0]	128	1			T8	1		T16	3		T49	2
all_values[6]	auto[0]	auto[1]	auto[1]	68	1			T8	2		T16	1		T29	1
all_values[6]	auto[1]	auto[0]	auto[1]	196	1			T8	2		T16	1		T29	2
all_values[6]	auto[1]	auto[1]	auto[1]	149	1			T8	1		T16	1		T27	1
all_values[7]	auto[0]	auto[0]	auto[0]	173	1			T8	2		T16	3		T29	1
all_values[7]	auto[0]	auto[0]	auto[1]	75	1			T8	2		T16	1		T49	2
all_values[7]	auto[0]	auto[1]	auto[0]	143	1			T8	3		T16	1		T27	2
all_values[7]	auto[0]	auto[1]	auto[1]	78	1			T27	1		T29	3		T49	2
all_values[7]	auto[1]	auto[0]	auto[1]	178	1			T8	1		T16	2		T27	1
all_values[7]	auto[1]	auto[1]	auto[1]	138	1			T29	3		T49	7		T112	1
all_values[8]	auto[0]	auto[0]	auto[1]	217	1			T8	3		T16	3		T29	4
all_values[8]	auto[0]	auto[1]	auto[1]	232	1			T8	2		T16	2		T27	2
all_values[8]	auto[1]	auto[0]	auto[1]	182	1			T27	1		T29	3		T49	6
all_values[8]	auto[1]	auto[1]	auto[1]	154	1			T8	3		T16	2		T27	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal