Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.13 99.10 97.65 100.00 98.38 100.00 99.64


Total test records in report: 1315
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T1257 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3595068472 Jul 19 04:28:55 PM PDT 24 Jul 19 04:28:59 PM PDT 24 31036408 ps
T1258 /workspace/coverage/cover_reg_top/6.uart_csr_rw.4273857878 Jul 19 04:28:52 PM PDT 24 Jul 19 04:28:55 PM PDT 24 88302955 ps
T1259 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3300356239 Jul 19 04:29:06 PM PDT 24 Jul 19 04:29:09 PM PDT 24 33135164 ps
T1260 /workspace/coverage/cover_reg_top/11.uart_csr_rw.4024953774 Jul 19 04:28:55 PM PDT 24 Jul 19 04:28:58 PM PDT 24 47333880 ps
T62 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2995647019 Jul 19 04:28:48 PM PDT 24 Jul 19 04:28:52 PM PDT 24 974282364 ps
T1261 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3638508071 Jul 19 04:28:48 PM PDT 24 Jul 19 04:28:50 PM PDT 24 71586526 ps
T1262 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1528636001 Jul 19 04:29:05 PM PDT 24 Jul 19 04:29:09 PM PDT 24 113732089 ps
T1263 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3018328746 Jul 19 04:28:43 PM PDT 24 Jul 19 04:28:46 PM PDT 24 115964255 ps
T1264 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3028114877 Jul 19 04:28:50 PM PDT 24 Jul 19 04:28:54 PM PDT 24 49174860 ps
T1265 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1781807410 Jul 19 04:28:57 PM PDT 24 Jul 19 04:29:02 PM PDT 24 19245089 ps
T1266 /workspace/coverage/cover_reg_top/0.uart_csr_rw.1512255954 Jul 19 04:28:38 PM PDT 24 Jul 19 04:28:41 PM PDT 24 129619579 ps
T1267 /workspace/coverage/cover_reg_top/16.uart_tl_errors.4273203788 Jul 19 04:29:07 PM PDT 24 Jul 19 04:29:11 PM PDT 24 104304062 ps
T1268 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3147296685 Jul 19 04:28:54 PM PDT 24 Jul 19 04:28:57 PM PDT 24 17913813 ps
T1269 /workspace/coverage/cover_reg_top/22.uart_intr_test.1339455737 Jul 19 04:29:17 PM PDT 24 Jul 19 04:29:20 PM PDT 24 29380192 ps
T1270 /workspace/coverage/cover_reg_top/1.uart_tl_errors.2500553024 Jul 19 04:28:45 PM PDT 24 Jul 19 04:28:48 PM PDT 24 113012778 ps
T1271 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3204363263 Jul 19 04:29:05 PM PDT 24 Jul 19 04:29:09 PM PDT 24 561455539 ps
T63 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.929594927 Jul 19 04:28:40 PM PDT 24 Jul 19 04:28:43 PM PDT 24 92826575 ps
T1272 /workspace/coverage/cover_reg_top/25.uart_intr_test.1049981072 Jul 19 04:29:17 PM PDT 24 Jul 19 04:29:20 PM PDT 24 52214223 ps
T1273 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2530013609 Jul 19 04:28:57 PM PDT 24 Jul 19 04:29:02 PM PDT 24 54570854 ps
T1274 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3545123331 Jul 19 04:28:45 PM PDT 24 Jul 19 04:28:48 PM PDT 24 85276432 ps
T1275 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2639406262 Jul 19 04:28:44 PM PDT 24 Jul 19 04:28:49 PM PDT 24 253278981 ps
T1276 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.302024242 Jul 19 04:29:12 PM PDT 24 Jul 19 04:29:15 PM PDT 24 125583071 ps
T1277 /workspace/coverage/cover_reg_top/33.uart_intr_test.3424410290 Jul 19 04:29:17 PM PDT 24 Jul 19 04:29:19 PM PDT 24 33158084 ps
T1278 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2888864687 Jul 19 04:30:08 PM PDT 24 Jul 19 04:30:19 PM PDT 24 49926923 ps
T1279 /workspace/coverage/cover_reg_top/45.uart_intr_test.4054992071 Jul 19 04:29:21 PM PDT 24 Jul 19 04:29:23 PM PDT 24 15125720 ps
T1280 /workspace/coverage/cover_reg_top/4.uart_tl_errors.4240309265 Jul 19 04:28:47 PM PDT 24 Jul 19 04:28:49 PM PDT 24 163694576 ps
T1281 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2804030616 Jul 19 04:28:54 PM PDT 24 Jul 19 04:28:57 PM PDT 24 26608694 ps
T1282 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3988066486 Jul 19 04:28:56 PM PDT 24 Jul 19 04:29:00 PM PDT 24 49071119 ps
T64 /workspace/coverage/cover_reg_top/1.uart_csr_rw.454196913 Jul 19 04:28:43 PM PDT 24 Jul 19 04:28:46 PM PDT 24 38659247 ps
T1283 /workspace/coverage/cover_reg_top/4.uart_intr_test.583092911 Jul 19 04:28:47 PM PDT 24 Jul 19 04:28:49 PM PDT 24 37768305 ps
T1284 /workspace/coverage/cover_reg_top/0.uart_intr_test.124999147 Jul 19 04:28:31 PM PDT 24 Jul 19 04:28:37 PM PDT 24 39294683 ps
T1285 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.261133553 Jul 19 04:28:52 PM PDT 24 Jul 19 04:28:55 PM PDT 24 21524126 ps
T1286 /workspace/coverage/cover_reg_top/28.uart_intr_test.910817785 Jul 19 04:29:18 PM PDT 24 Jul 19 04:29:21 PM PDT 24 14913240 ps
T1287 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1328010947 Jul 19 04:28:54 PM PDT 24 Jul 19 04:28:57 PM PDT 24 17352032 ps
T1288 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1303520910 Jul 19 04:29:00 PM PDT 24 Jul 19 04:29:04 PM PDT 24 73030788 ps
T1289 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1556135500 Jul 19 04:28:55 PM PDT 24 Jul 19 04:28:59 PM PDT 24 238116329 ps
T1290 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2586601812 Jul 19 04:28:58 PM PDT 24 Jul 19 04:29:02 PM PDT 24 81100285 ps
T99 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1339273349 Jul 19 04:28:54 PM PDT 24 Jul 19 04:28:58 PM PDT 24 1000605374 ps
T1291 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.420482640 Jul 19 04:29:03 PM PDT 24 Jul 19 04:29:06 PM PDT 24 63432538 ps
T1292 /workspace/coverage/cover_reg_top/17.uart_tl_errors.661810530 Jul 19 04:29:05 PM PDT 24 Jul 19 04:29:09 PM PDT 24 67057121 ps
T1293 /workspace/coverage/cover_reg_top/14.uart_intr_test.1152333242 Jul 19 04:29:04 PM PDT 24 Jul 19 04:29:07 PM PDT 24 36004587 ps
T1294 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2141236625 Jul 19 04:30:19 PM PDT 24 Jul 19 04:30:26 PM PDT 24 27391164 ps
T1295 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2283269781 Jul 19 04:28:55 PM PDT 24 Jul 19 04:29:00 PM PDT 24 30478758 ps
T1296 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1761304527 Jul 19 04:29:04 PM PDT 24 Jul 19 04:29:08 PM PDT 24 47401099 ps
T1297 /workspace/coverage/cover_reg_top/34.uart_intr_test.517383092 Jul 19 04:29:19 PM PDT 24 Jul 19 04:29:22 PM PDT 24 11747009 ps
T1298 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.5968685 Jul 19 04:28:49 PM PDT 24 Jul 19 04:28:52 PM PDT 24 29558489 ps
T1299 /workspace/coverage/cover_reg_top/12.uart_intr_test.1731011771 Jul 19 04:28:57 PM PDT 24 Jul 19 04:29:01 PM PDT 24 58887128 ps
T1300 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1963237658 Jul 19 04:29:12 PM PDT 24 Jul 19 04:29:14 PM PDT 24 39310343 ps
T1301 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2078612176 Jul 19 04:28:55 PM PDT 24 Jul 19 04:28:59 PM PDT 24 179585259 ps
T65 /workspace/coverage/cover_reg_top/8.uart_csr_rw.2989522061 Jul 19 04:28:55 PM PDT 24 Jul 19 04:28:59 PM PDT 24 33316261 ps
T66 /workspace/coverage/cover_reg_top/16.uart_csr_rw.977865115 Jul 19 04:29:06 PM PDT 24 Jul 19 04:29:09 PM PDT 24 14312224 ps
T1302 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3796029181 Jul 19 04:29:12 PM PDT 24 Jul 19 04:29:14 PM PDT 24 125142300 ps
T1303 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1381777467 Jul 19 04:28:37 PM PDT 24 Jul 19 04:28:39 PM PDT 24 22029002 ps
T1304 /workspace/coverage/cover_reg_top/46.uart_intr_test.2776254374 Jul 19 04:29:17 PM PDT 24 Jul 19 04:29:20 PM PDT 24 40781444 ps
T1305 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2791498140 Jul 19 04:29:09 PM PDT 24 Jul 19 04:29:11 PM PDT 24 99276178 ps
T1306 /workspace/coverage/cover_reg_top/43.uart_intr_test.1947069218 Jul 19 04:29:17 PM PDT 24 Jul 19 04:29:19 PM PDT 24 11127524 ps
T1307 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.271217139 Jul 19 04:29:04 PM PDT 24 Jul 19 04:29:07 PM PDT 24 42982223 ps
T1308 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2060453802 Jul 19 04:28:47 PM PDT 24 Jul 19 04:28:49 PM PDT 24 56629095 ps
T1309 /workspace/coverage/cover_reg_top/8.uart_intr_test.964522398 Jul 19 04:28:54 PM PDT 24 Jul 19 04:28:57 PM PDT 24 59124852 ps
T1310 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2453613826 Jul 19 04:29:15 PM PDT 24 Jul 19 04:29:18 PM PDT 24 174176252 ps
T1311 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1551499156 Jul 19 04:28:56 PM PDT 24 Jul 19 04:29:01 PM PDT 24 33084993 ps
T1312 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3768660699 Jul 19 04:29:09 PM PDT 24 Jul 19 04:29:11 PM PDT 24 17733604 ps
T1313 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.927333008 Jul 19 04:29:12 PM PDT 24 Jul 19 04:29:15 PM PDT 24 34284049 ps
T1314 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2139930944 Jul 19 04:28:54 PM PDT 24 Jul 19 04:28:57 PM PDT 24 29022935 ps
T1315 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1949400301 Jul 19 04:29:03 PM PDT 24 Jul 19 04:29:06 PM PDT 24 15405360 ps

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1586171498
Short name T8
Test name
Test status
Simulation time 84413942965 ps
CPU time 343.64 seconds
Started Jul 19 04:27:45 PM PDT 24
Finished Jul 19 04:33:33 PM PDT 24
Peak memory 216480 kb
Host smart-865fd751-21a0-4c19-b4e9-3867f9ce75fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586171498 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1586171498
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.4135771201
Short name T72
Test name
Test status
Simulation time 413306370103 ps
CPU time 1467.71 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:52:24 PM PDT 24
Peak memory 231564 kb
Host smart-68fdd973-a766-4a53-9b72-b05ad8744201
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135771201 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.4135771201
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all.3501086130
Short name T262
Test name
Test status
Simulation time 353803922748 ps
CPU time 722.13 seconds
Started Jul 19 04:26:11 PM PDT 24
Finished Jul 19 04:38:28 PM PDT 24
Peak memory 208404 kb
Host smart-33e12b98-0682-4176-a82e-1d665f235115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501086130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3501086130
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all.2344698965
Short name T17
Test name
Test status
Simulation time 592853491616 ps
CPU time 611.55 seconds
Started Jul 19 04:25:28 PM PDT 24
Finished Jul 19 04:35:58 PM PDT 24
Peak memory 199856 kb
Host smart-1eea1a37-3d86-4d31-a27f-4c606c5e367b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344698965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2344698965
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all.2003884731
Short name T266
Test name
Test status
Simulation time 102293527999 ps
CPU time 728.78 seconds
Started Jul 19 04:26:53 PM PDT 24
Finished Jul 19 04:39:06 PM PDT 24
Peak memory 199860 kb
Host smart-0bf46324-aa29-43ab-b452-6b251f429d7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003884731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2003884731
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1061084367
Short name T29
Test name
Test status
Simulation time 219403999187 ps
CPU time 674.24 seconds
Started Jul 19 04:26:43 PM PDT 24
Finished Jul 19 04:38:03 PM PDT 24
Peak memory 224764 kb
Host smart-ca56233b-b305-421b-b605-9a5b354f33cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061084367 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1061084367
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2336515038
Short name T23
Test name
Test status
Simulation time 51996420 ps
CPU time 0.81 seconds
Started Jul 19 04:25:09 PM PDT 24
Finished Jul 19 04:25:32 PM PDT 24
Peak memory 218148 kb
Host smart-38ea335f-a197-462c-bc7a-39d9feb26b8c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336515038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2336515038
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/13.uart_stress_all.1096135947
Short name T229
Test name
Test status
Simulation time 669801345104 ps
CPU time 955.04 seconds
Started Jul 19 04:25:52 PM PDT 24
Finished Jul 19 04:42:03 PM PDT 24
Peak memory 199932 kb
Host smart-f3f9e46e-7481-45a8-b3f1-9b96da4c7b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096135947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1096135947
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3977267582
Short name T11
Test name
Test status
Simulation time 45878620697 ps
CPU time 69.8 seconds
Started Jul 19 04:27:10 PM PDT 24
Finished Jul 19 04:28:26 PM PDT 24
Peak memory 199856 kb
Host smart-00c8f9fa-9c98-4a4e-bb2c-9a6db4eacd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977267582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3977267582
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.4038161514
Short name T112
Test name
Test status
Simulation time 66986703292 ps
CPU time 318.1 seconds
Started Jul 19 04:27:34 PM PDT 24
Finished Jul 19 04:32:55 PM PDT 24
Peak memory 216624 kb
Host smart-d16e42ce-35cd-4e1b-828e-81ea7f1d9484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038161514 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.4038161514
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.320120776
Short name T141
Test name
Test status
Simulation time 158440771221 ps
CPU time 15.1 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:26:09 PM PDT 24
Peak memory 199880 kb
Host smart-ef4a9293-ad46-47b1-9e63-26cccb14b7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320120776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.320120776
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_stress_all.1336675859
Short name T291
Test name
Test status
Simulation time 179151431463 ps
CPU time 1130.88 seconds
Started Jul 19 04:25:54 PM PDT 24
Finished Jul 19 04:45:00 PM PDT 24
Peak memory 216440 kb
Host smart-8eea56cd-2eef-4ebb-90c8-53add54c98fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336675859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1336675859
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2415359002
Short name T49
Test name
Test status
Simulation time 161156881769 ps
CPU time 448.96 seconds
Started Jul 19 04:25:16 PM PDT 24
Finished Jul 19 04:33:05 PM PDT 24
Peak memory 224852 kb
Host smart-48cbf061-1e8b-42c6-b383-cf53515e91dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415359002 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2415359002
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3368072560
Short name T136
Test name
Test status
Simulation time 477538849111 ps
CPU time 1131.65 seconds
Started Jul 19 04:27:40 PM PDT 24
Finished Jul 19 04:46:38 PM PDT 24
Peak memory 216428 kb
Host smart-16ea264e-8fb0-4ea7-b7c0-e8b92dea366f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368072560 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3368072560
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.4138925463
Short name T93
Test name
Test status
Simulation time 94581156 ps
CPU time 1.29 seconds
Started Jul 19 04:29:06 PM PDT 24
Finished Jul 19 04:29:10 PM PDT 24
Peak memory 200072 kb
Host smart-9182ced1-4427-4697-9ac6-6468857662d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138925463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.4138925463
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1762965233
Short name T16
Test name
Test status
Simulation time 89249317909 ps
CPU time 233.37 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:30:27 PM PDT 24
Peak memory 216392 kb
Host smart-178fc8d0-51fc-4ea8-946d-fd9ddf0d494c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762965233 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1762965233
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1750094796
Short name T151
Test name
Test status
Simulation time 170834579569 ps
CPU time 299.2 seconds
Started Jul 19 04:26:10 PM PDT 24
Finished Jul 19 04:31:23 PM PDT 24
Peak memory 200068 kb
Host smart-f9c7c59c-2d57-4cbf-944c-070991cb784d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750094796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1750094796
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3457185822
Short name T30
Test name
Test status
Simulation time 125329340403 ps
CPU time 280.14 seconds
Started Jul 19 04:25:22 PM PDT 24
Finished Jul 19 04:30:22 PM PDT 24
Peak memory 216640 kb
Host smart-35a2e39f-52fa-4a4c-9e23-42707f5c4a44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457185822 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3457185822
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.4176425035
Short name T348
Test name
Test status
Simulation time 11980801 ps
CPU time 0.54 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:26:00 PM PDT 24
Peak memory 195412 kb
Host smart-8f8a6917-acef-4ca1-9acf-9996b8fa74e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176425035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4176425035
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2289166340
Short name T282
Test name
Test status
Simulation time 360834994527 ps
CPU time 81.57 seconds
Started Jul 19 04:26:47 PM PDT 24
Finished Jul 19 04:28:12 PM PDT 24
Peak memory 199912 kb
Host smart-f85dd99b-ff37-46cd-b685-98f2ac0528f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289166340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2289166340
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_perf.4171834714
Short name T122
Test name
Test status
Simulation time 21369466917 ps
CPU time 1258.64 seconds
Started Jul 19 04:27:35 PM PDT 24
Finished Jul 19 04:48:38 PM PDT 24
Peak memory 199880 kb
Host smart-3508e7a4-4275-498c-bfa7-d8b999a08525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171834714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.4171834714
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.929594927
Short name T63
Test name
Test status
Simulation time 92826575 ps
CPU time 0.64 seconds
Started Jul 19 04:28:40 PM PDT 24
Finished Jul 19 04:28:43 PM PDT 24
Peak memory 195728 kb
Host smart-572248bc-7b15-4046-a188-cd86057e8a7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929594927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.929594927
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1234364741
Short name T84
Test name
Test status
Simulation time 44064931 ps
CPU time 0.64 seconds
Started Jul 19 04:28:40 PM PDT 24
Finished Jul 19 04:28:43 PM PDT 24
Peak memory 196544 kb
Host smart-7122b95b-c8c0-4e39-bfe1-5ee08612aa91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234364741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1234364741
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/15.uart_stress_all.3855454441
Short name T137
Test name
Test status
Simulation time 462175392679 ps
CPU time 152.5 seconds
Started Jul 19 04:25:50 PM PDT 24
Finished Jul 19 04:28:39 PM PDT 24
Peak memory 199928 kb
Host smart-7cb71077-e42f-496a-991b-c74f32f008a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855454441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3855454441
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all.3232590349
Short name T281
Test name
Test status
Simulation time 240220539484 ps
CPU time 1065.83 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:44:29 PM PDT 24
Peak memory 199968 kb
Host smart-898e5a78-ba2e-4280-8942-7203f9ee37ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232590349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3232590349
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2442385865
Short name T148
Test name
Test status
Simulation time 101808087541 ps
CPU time 82.86 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:29:45 PM PDT 24
Peak memory 199932 kb
Host smart-6c3fb9eb-4660-4e51-96db-94a4c00eaeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442385865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2442385865
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1846771369
Short name T70
Test name
Test status
Simulation time 58825479364 ps
CPU time 90.21 seconds
Started Jul 19 04:27:53 PM PDT 24
Finished Jul 19 04:29:29 PM PDT 24
Peak memory 200020 kb
Host smart-55b7d4f3-e3ef-494c-9757-488911826560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846771369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1846771369
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1055305697
Short name T103
Test name
Test status
Simulation time 269203852183 ps
CPU time 676.82 seconds
Started Jul 19 04:28:07 PM PDT 24
Finished Jul 19 04:39:26 PM PDT 24
Peak memory 199968 kb
Host smart-4623bb4b-ca47-4695-99f0-738de201cdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055305697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1055305697
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3897996861
Short name T384
Test name
Test status
Simulation time 122674501867 ps
CPU time 214.51 seconds
Started Jul 19 04:26:12 PM PDT 24
Finished Jul 19 04:30:01 PM PDT 24
Peak memory 199900 kb
Host smart-61da710c-261d-45f4-8f22-deb6053dcd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897996861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3897996861
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_stress_all.2660951238
Short name T164
Test name
Test status
Simulation time 274215150895 ps
CPU time 231.8 seconds
Started Jul 19 04:26:44 PM PDT 24
Finished Jul 19 04:30:41 PM PDT 24
Peak memory 199900 kb
Host smart-1ae2a889-77c1-44f4-a6cd-ce6abbc6dc11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660951238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2660951238
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3143463644
Short name T90
Test name
Test status
Simulation time 148171168 ps
CPU time 1.25 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 200144 kb
Host smart-9edd7a40-a813-4d6f-aea0-6a12e340753e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143463644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3143463644
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1540030260
Short name T191
Test name
Test status
Simulation time 25443273447 ps
CPU time 38.56 seconds
Started Jul 19 04:28:05 PM PDT 24
Finished Jul 19 04:28:46 PM PDT 24
Peak memory 199980 kb
Host smart-65765660-136f-4297-8114-7dd5a1e9409b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540030260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1540030260
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3167590220
Short name T157
Test name
Test status
Simulation time 18332150297 ps
CPU time 32.96 seconds
Started Jul 19 04:28:09 PM PDT 24
Finished Jul 19 04:28:45 PM PDT 24
Peak memory 199984 kb
Host smart-85c3344e-4bbe-4652-976c-548393856cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167590220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3167590220
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_stress_all.4225749621
Short name T172
Test name
Test status
Simulation time 671030205243 ps
CPU time 668.47 seconds
Started Jul 19 04:26:24 PM PDT 24
Finished Jul 19 04:37:44 PM PDT 24
Peak memory 199972 kb
Host smart-64357028-e575-4a31-a2e7-5da0140ec03d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225749621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.4225749621
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3634203990
Short name T167
Test name
Test status
Simulation time 54242971575 ps
CPU time 171.43 seconds
Started Jul 19 04:27:35 PM PDT 24
Finished Jul 19 04:30:31 PM PDT 24
Peak memory 199920 kb
Host smart-0fac22a1-7e91-4774-b725-994f3ab4f294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634203990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3634203990
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.718416441
Short name T149
Test name
Test status
Simulation time 32245265530 ps
CPU time 28.96 seconds
Started Jul 19 04:27:54 PM PDT 24
Finished Jul 19 04:28:30 PM PDT 24
Peak memory 199988 kb
Host smart-97e18a0f-15f4-42fb-a40b-3b7d680bf561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718416441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.718416441
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1466120549
Short name T52
Test name
Test status
Simulation time 155979238309 ps
CPU time 511.75 seconds
Started Jul 19 04:27:52 PM PDT 24
Finished Jul 19 04:36:30 PM PDT 24
Peak memory 216808 kb
Host smart-a6308b6b-09b3-42b8-9fc0-bf0165a31ee3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466120549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1466120549
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3665246971
Short name T187
Test name
Test status
Simulation time 26968677013 ps
CPU time 40.77 seconds
Started Jul 19 04:28:32 PM PDT 24
Finished Jul 19 04:29:17 PM PDT 24
Peak memory 199988 kb
Host smart-692888f4-b9a2-4833-8448-93b875fcd9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665246971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3665246971
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.315122036
Short name T199
Test name
Test status
Simulation time 412072135301 ps
CPU time 158.87 seconds
Started Jul 19 04:24:59 PM PDT 24
Finished Jul 19 04:28:04 PM PDT 24
Peak memory 199904 kb
Host smart-f77fa320-8a79-42da-8490-d8c782430032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315122036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.315122036
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2852539309
Short name T190
Test name
Test status
Simulation time 33027624521 ps
CPU time 51.38 seconds
Started Jul 19 04:27:56 PM PDT 24
Finished Jul 19 04:28:53 PM PDT 24
Peak memory 200320 kb
Host smart-a57310a4-460a-4b6c-b25f-3d3230d58d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852539309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2852539309
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all.897266077
Short name T284
Test name
Test status
Simulation time 296235982150 ps
CPU time 203.67 seconds
Started Jul 19 04:26:05 PM PDT 24
Finished Jul 19 04:29:44 PM PDT 24
Peak memory 199968 kb
Host smart-e0f916cc-7c2d-49cd-afe6-0e4d083bf1cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897266077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.897266077
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.608954709
Short name T169
Test name
Test status
Simulation time 184786424824 ps
CPU time 25.85 seconds
Started Jul 19 04:24:42 PM PDT 24
Finished Jul 19 04:25:43 PM PDT 24
Peak memory 199904 kb
Host smart-3585300c-740b-4f31-b455-d809d7bf9901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608954709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.608954709
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.4036388236
Short name T211
Test name
Test status
Simulation time 185557200953 ps
CPU time 50.76 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:28:47 PM PDT 24
Peak memory 200016 kb
Host smart-47babd42-17af-4684-aafc-8eeef4a0df21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036388236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.4036388236
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.654803729
Short name T131
Test name
Test status
Simulation time 71588639630 ps
CPU time 26.91 seconds
Started Jul 19 04:28:11 PM PDT 24
Finished Jul 19 04:28:40 PM PDT 24
Peak memory 199936 kb
Host smart-ff8a766e-4e91-482c-8214-d8f303f276ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654803729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.654803729
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.174860913
Short name T206
Test name
Test status
Simulation time 129802756982 ps
CPU time 57.45 seconds
Started Jul 19 04:28:03 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 199992 kb
Host smart-9b7e9e1f-3a85-4fde-ad98-cb2a25846380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174860913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.174860913
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.457562655
Short name T120
Test name
Test status
Simulation time 92494861601 ps
CPU time 21.09 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:26:36 PM PDT 24
Peak memory 199960 kb
Host smart-b30d0409-d2cf-4b60-870d-00f274d6d1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457562655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.457562655
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2492987588
Short name T643
Test name
Test status
Simulation time 201357366710 ps
CPU time 268.45 seconds
Started Jul 19 04:28:08 PM PDT 24
Finished Jul 19 04:32:39 PM PDT 24
Peak memory 199964 kb
Host smart-22778ee4-2286-4402-ba57-890c45b9e43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492987588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2492987588
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1764560924
Short name T220
Test name
Test status
Simulation time 31860458738 ps
CPU time 51.1 seconds
Started Jul 19 04:28:21 PM PDT 24
Finished Jul 19 04:29:14 PM PDT 24
Peak memory 199944 kb
Host smart-d4c02eba-114f-45c6-8c58-ff4a49da94e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764560924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1764560924
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1030484330
Short name T216
Test name
Test status
Simulation time 59469324918 ps
CPU time 39.08 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:29:01 PM PDT 24
Peak memory 199948 kb
Host smart-080cad61-e36e-4cb3-b901-2a3721618c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030484330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1030484330
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2911860482
Short name T13
Test name
Test status
Simulation time 56855535194 ps
CPU time 61.39 seconds
Started Jul 19 04:28:21 PM PDT 24
Finished Jul 19 04:29:25 PM PDT 24
Peak memory 199944 kb
Host smart-31ed4a24-e13d-4bdf-b723-5a4c498bcb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911860482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2911860482
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2617601973
Short name T182
Test name
Test status
Simulation time 34583411216 ps
CPU time 54.29 seconds
Started Jul 19 04:28:28 PM PDT 24
Finished Jul 19 04:29:25 PM PDT 24
Peak memory 199988 kb
Host smart-1f3d81ff-d813-4165-b99f-4e740ca14bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617601973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2617601973
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.514202
Short name T654
Test name
Test status
Simulation time 39665332133 ps
CPU time 66.28 seconds
Started Jul 19 04:25:01 PM PDT 24
Finished Jul 19 04:26:33 PM PDT 24
Peak memory 199924 kb
Host smart-3a565b94-1b1a-49d9-a9bd-4d3e98b63b48
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.514202
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2619283275
Short name T315
Test name
Test status
Simulation time 123501430692 ps
CPU time 35.24 seconds
Started Jul 19 04:27:53 PM PDT 24
Finished Jul 19 04:28:34 PM PDT 24
Peak memory 199824 kb
Host smart-d9b6eac8-4bad-4c63-8584-a5056c1de19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619283275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2619283275
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2373961719
Short name T202
Test name
Test status
Simulation time 17329660209 ps
CPU time 14.77 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:28:10 PM PDT 24
Peak memory 199908 kb
Host smart-bf34d5e3-bd9d-4fe6-bcfb-23d558631501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373961719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2373961719
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1646620330
Short name T207
Test name
Test status
Simulation time 104707168981 ps
CPU time 82.11 seconds
Started Jul 19 04:28:02 PM PDT 24
Finished Jul 19 04:29:26 PM PDT 24
Peak memory 199992 kb
Host smart-60185a50-3c45-4e2f-a6d2-6e4e3957c5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646620330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1646620330
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.372756610
Short name T254
Test name
Test status
Simulation time 114976554535 ps
CPU time 98.57 seconds
Started Jul 19 04:27:54 PM PDT 24
Finished Jul 19 04:29:39 PM PDT 24
Peak memory 199988 kb
Host smart-20a7af19-895a-4e5c-817c-12bda4433afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372756610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.372756610
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2168392943
Short name T243
Test name
Test status
Simulation time 16179812674 ps
CPU time 33.93 seconds
Started Jul 19 04:28:11 PM PDT 24
Finished Jul 19 04:28:47 PM PDT 24
Peak memory 199940 kb
Host smart-98228130-df3f-4230-a60f-38a2f61297dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168392943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2168392943
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.3177404734
Short name T173
Test name
Test status
Simulation time 272252997538 ps
CPU time 140.34 seconds
Started Jul 19 04:25:51 PM PDT 24
Finished Jul 19 04:28:27 PM PDT 24
Peak memory 199616 kb
Host smart-dbb66a42-1dbe-47a8-881c-8bfc127affb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177404734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3177404734
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.595103820
Short name T235
Test name
Test status
Simulation time 201530477286 ps
CPU time 29.33 seconds
Started Jul 19 04:27:56 PM PDT 24
Finished Jul 19 04:28:31 PM PDT 24
Peak memory 199928 kb
Host smart-88516c89-3975-4b85-8f42-4677304d39e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595103820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.595103820
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.4260557159
Short name T226
Test name
Test status
Simulation time 16010931557 ps
CPU time 25.89 seconds
Started Jul 19 04:28:11 PM PDT 24
Finished Jul 19 04:28:39 PM PDT 24
Peak memory 199992 kb
Host smart-b26d6ade-eca9-4b62-aea4-7163ca1a2a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260557159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.4260557159
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1013595124
Short name T222
Test name
Test status
Simulation time 246420099326 ps
CPU time 26.91 seconds
Started Jul 19 04:28:10 PM PDT 24
Finished Jul 19 04:28:40 PM PDT 24
Peak memory 200216 kb
Host smart-9846d810-f094-4fa4-a342-09876fdad51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013595124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1013595124
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2677956844
Short name T240
Test name
Test status
Simulation time 20897531793 ps
CPU time 37.39 seconds
Started Jul 19 04:28:22 PM PDT 24
Finished Jul 19 04:29:01 PM PDT 24
Peak memory 199840 kb
Host smart-f0858679-47ac-43fb-a3b1-b83306c4b1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677956844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2677956844
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3108029173
Short name T251
Test name
Test status
Simulation time 157632288991 ps
CPU time 23.48 seconds
Started Jul 19 04:28:32 PM PDT 24
Finished Jul 19 04:29:00 PM PDT 24
Peak memory 199928 kb
Host smart-35612a51-494f-4b82-ba0d-c5de23516b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108029173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3108029173
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3289704540
Short name T132
Test name
Test status
Simulation time 174299314005 ps
CPU time 330.02 seconds
Started Jul 19 04:28:27 PM PDT 24
Finished Jul 19 04:33:59 PM PDT 24
Peak memory 200024 kb
Host smart-f1684323-57a4-4079-8697-7f0e21410b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289704540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3289704540
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2777141578
Short name T249
Test name
Test status
Simulation time 63107300551 ps
CPU time 86.67 seconds
Started Jul 19 04:28:28 PM PDT 24
Finished Jul 19 04:29:59 PM PDT 24
Peak memory 199904 kb
Host smart-aab0321f-bd2e-4872-95ed-138b2ad938db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777141578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2777141578
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.2695400108
Short name T219
Test name
Test status
Simulation time 79672870330 ps
CPU time 190.9 seconds
Started Jul 19 04:26:13 PM PDT 24
Finished Jul 19 04:29:37 PM PDT 24
Peak memory 199972 kb
Host smart-23197847-6ee7-43f1-bb08-4c3b018c40c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695400108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2695400108
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1412622289
Short name T237
Test name
Test status
Simulation time 29537300367 ps
CPU time 41.41 seconds
Started Jul 19 04:28:31 PM PDT 24
Finished Jul 19 04:29:17 PM PDT 24
Peak memory 199964 kb
Host smart-5f9e4ae9-9ce6-437c-847a-82a2e6ffe631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412622289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1412622289
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1834287027
Short name T241
Test name
Test status
Simulation time 89785380197 ps
CPU time 78.48 seconds
Started Jul 19 04:26:10 PM PDT 24
Finished Jul 19 04:27:43 PM PDT 24
Peak memory 199936 kb
Host smart-3aaa0f73-ae02-48f9-b5a4-7f9c3290e143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834287027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1834287027
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3387425167
Short name T252
Test name
Test status
Simulation time 99752069451 ps
CPU time 77.87 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:27:51 PM PDT 24
Peak memory 199960 kb
Host smart-68aa12f5-6e24-4219-b6cf-38c51e410206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387425167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3387425167
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.450854275
Short name T218
Test name
Test status
Simulation time 20159937602 ps
CPU time 43.56 seconds
Started Jul 19 04:26:58 PM PDT 24
Finished Jul 19 04:27:47 PM PDT 24
Peak memory 199904 kb
Host smart-ac0c25f6-2aad-4661-b15b-0e37d2ad7d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450854275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.450854275
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all.136128502
Short name T236
Test name
Test status
Simulation time 414181904874 ps
CPU time 1309.63 seconds
Started Jul 19 04:27:06 PM PDT 24
Finished Jul 19 04:49:02 PM PDT 24
Peak memory 199920 kb
Host smart-cf6c5d99-1697-41f9-bb4d-ce335d588607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136128502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.136128502
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3152891960
Short name T128
Test name
Test status
Simulation time 149505557983 ps
CPU time 60.66 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:28:41 PM PDT 24
Peak memory 199952 kb
Host smart-5bc8e8c0-723c-4e3d-ab97-df85e37631d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152891960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3152891960
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1929076638
Short name T250
Test name
Test status
Simulation time 56641616653 ps
CPU time 51.52 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:28:37 PM PDT 24
Peak memory 199964 kb
Host smart-36859786-035f-4df7-b921-f39122c71118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929076638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1929076638
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3018328746
Short name T1263
Test name
Test status
Simulation time 115964255 ps
CPU time 0.79 seconds
Started Jul 19 04:28:43 PM PDT 24
Finished Jul 19 04:28:46 PM PDT 24
Peak memory 196844 kb
Host smart-de2c3310-cd96-4a04-b2b9-09c683134b93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018328746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3018328746
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2512375554
Short name T1187
Test name
Test status
Simulation time 183012166 ps
CPU time 2.39 seconds
Started Jul 19 04:28:39 PM PDT 24
Finished Jul 19 04:28:44 PM PDT 24
Peak memory 198428 kb
Host smart-6e8aa42a-30c5-486f-9b34-aadc654c7621
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512375554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2512375554
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.370095824
Short name T1211
Test name
Test status
Simulation time 13826739 ps
CPU time 0.58 seconds
Started Jul 19 04:30:16 PM PDT 24
Finished Jul 19 04:30:24 PM PDT 24
Peak memory 195900 kb
Host smart-d7d25e33-a325-49e0-a9f3-4f92454a7b92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370095824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.370095824
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2278960253
Short name T1214
Test name
Test status
Simulation time 27419175 ps
CPU time 0.72 seconds
Started Jul 19 04:28:42 PM PDT 24
Finished Jul 19 04:28:45 PM PDT 24
Peak memory 199444 kb
Host smart-0e36d5c0-9b44-447f-8cd1-6c5a00911301
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278960253 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2278960253
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1512255954
Short name T1266
Test name
Test status
Simulation time 129619579 ps
CPU time 0.57 seconds
Started Jul 19 04:28:38 PM PDT 24
Finished Jul 19 04:28:41 PM PDT 24
Peak memory 196132 kb
Host smart-d94717fd-131e-4ba1-b446-f46e0108b32d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512255954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1512255954
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.124999147
Short name T1284
Test name
Test status
Simulation time 39294683 ps
CPU time 0.61 seconds
Started Jul 19 04:28:31 PM PDT 24
Finished Jul 19 04:28:37 PM PDT 24
Peak memory 195212 kb
Host smart-453a2988-e940-4a84-8030-081b78d9b6c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124999147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.124999147
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.529081624
Short name T1249
Test name
Test status
Simulation time 23011666 ps
CPU time 0.65 seconds
Started Jul 19 04:28:38 PM PDT 24
Finished Jul 19 04:28:40 PM PDT 24
Peak memory 196476 kb
Host smart-ec2fb6a1-8e5b-4c0a-9fa5-85912045d03a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529081624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.529081624
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2141236625
Short name T1294
Test name
Test status
Simulation time 27391164 ps
CPU time 1.19 seconds
Started Jul 19 04:30:19 PM PDT 24
Finished Jul 19 04:30:26 PM PDT 24
Peak memory 200604 kb
Host smart-cd04e457-b8ad-4127-ad2d-4e78788ce2c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141236625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2141236625
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.888725445
Short name T92
Test name
Test status
Simulation time 40369042 ps
CPU time 0.9 seconds
Started Jul 19 04:30:19 PM PDT 24
Finished Jul 19 04:30:26 PM PDT 24
Peak memory 199700 kb
Host smart-c28856c0-37d4-4443-bd60-e8ec1d99d4f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888725445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.888725445
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.583304790
Short name T1203
Test name
Test status
Simulation time 204855671 ps
CPU time 1.4 seconds
Started Jul 19 04:28:38 PM PDT 24
Finished Jul 19 04:28:42 PM PDT 24
Peak memory 199140 kb
Host smart-b254bbcb-73c7-4547-80dd-bd126990b0ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583304790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.583304790
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1889552555
Short name T1239
Test name
Test status
Simulation time 14967316 ps
CPU time 0.65 seconds
Started Jul 19 04:28:40 PM PDT 24
Finished Jul 19 04:28:43 PM PDT 24
Peak memory 196140 kb
Host smart-fc34b848-e743-4412-8b11-de45945546a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889552555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1889552555
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1017600179
Short name T1194
Test name
Test status
Simulation time 17134620 ps
CPU time 0.65 seconds
Started Jul 19 04:28:44 PM PDT 24
Finished Jul 19 04:28:47 PM PDT 24
Peak memory 197436 kb
Host smart-4dfce621-2dc1-4881-82bb-50c091a089ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017600179 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1017600179
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.454196913
Short name T64
Test name
Test status
Simulation time 38659247 ps
CPU time 0.6 seconds
Started Jul 19 04:28:43 PM PDT 24
Finished Jul 19 04:28:46 PM PDT 24
Peak memory 195524 kb
Host smart-b3b080a3-fb56-4120-996e-92eab7429932
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454196913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.454196913
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3306180409
Short name T1228
Test name
Test status
Simulation time 11516713 ps
CPU time 0.56 seconds
Started Jul 19 04:28:38 PM PDT 24
Finished Jul 19 04:28:41 PM PDT 24
Peak memory 195200 kb
Host smart-fce9ffe0-5450-4f3b-bc99-f5ca78d9fe97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306180409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3306180409
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2500553024
Short name T1270
Test name
Test status
Simulation time 113012778 ps
CPU time 1.57 seconds
Started Jul 19 04:28:45 PM PDT 24
Finished Jul 19 04:28:48 PM PDT 24
Peak memory 200836 kb
Host smart-1d8b780c-53fe-469f-b095-0f3126e62871
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500553024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2500553024
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3214483796
Short name T97
Test name
Test status
Simulation time 169104808 ps
CPU time 1.25 seconds
Started Jul 19 04:28:41 PM PDT 24
Finished Jul 19 04:28:44 PM PDT 24
Peak memory 200036 kb
Host smart-95c42c63-79e7-4a7e-8817-0f9e4dc0a328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214483796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3214483796
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3341346264
Short name T1184
Test name
Test status
Simulation time 19794309 ps
CPU time 0.65 seconds
Started Jul 19 04:28:54 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 198224 kb
Host smart-dee8d03a-c20a-4abc-8f3a-be4d0255ddd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341346264 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3341346264
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3595068472
Short name T1257
Test name
Test status
Simulation time 31036408 ps
CPU time 0.63 seconds
Started Jul 19 04:28:55 PM PDT 24
Finished Jul 19 04:28:59 PM PDT 24
Peak memory 196224 kb
Host smart-5c6d4eaf-c0f4-48c8-b036-39679885efc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595068472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3595068472
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2141421596
Short name T1198
Test name
Test status
Simulation time 10807330 ps
CPU time 0.62 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:01 PM PDT 24
Peak memory 195384 kb
Host smart-0284d5fd-b812-4062-87de-ce5f17a91255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141421596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2141421596
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3988066486
Short name T1282
Test name
Test status
Simulation time 49071119 ps
CPU time 0.69 seconds
Started Jul 19 04:28:56 PM PDT 24
Finished Jul 19 04:29:00 PM PDT 24
Peak memory 197720 kb
Host smart-780ff5df-5277-488d-a6ef-0527922b1bb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988066486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3988066486
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2804030616
Short name T1281
Test name
Test status
Simulation time 26608694 ps
CPU time 1.35 seconds
Started Jul 19 04:28:54 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 200836 kb
Host smart-f267a9b1-d399-4d75-829d-8b32a3ff4f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804030616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2804030616
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1556135500
Short name T1289
Test name
Test status
Simulation time 238116329 ps
CPU time 0.92 seconds
Started Jul 19 04:28:55 PM PDT 24
Finished Jul 19 04:28:59 PM PDT 24
Peak memory 199676 kb
Host smart-98b3d625-d3fe-49b8-98fb-8b2a1869ec0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556135500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1556135500
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.350970832
Short name T1231
Test name
Test status
Simulation time 25484852 ps
CPU time 1.11 seconds
Started Jul 19 04:29:00 PM PDT 24
Finished Jul 19 04:29:04 PM PDT 24
Peak memory 200476 kb
Host smart-528b0997-3035-49fb-af7f-32cedfe264bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350970832 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.350970832
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.4024953774
Short name T1260
Test name
Test status
Simulation time 47333880 ps
CPU time 0.54 seconds
Started Jul 19 04:28:55 PM PDT 24
Finished Jul 19 04:28:58 PM PDT 24
Peak memory 196156 kb
Host smart-7a25bc71-cd0c-494d-a184-ea2f5d58f7e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024953774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.4024953774
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.994039903
Short name T1217
Test name
Test status
Simulation time 12269756 ps
CPU time 0.58 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:01 PM PDT 24
Peak memory 195072 kb
Host smart-98700812-82a6-4809-bde5-659280ce0273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994039903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.994039903
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1781807410
Short name T1265
Test name
Test status
Simulation time 19245089 ps
CPU time 0.72 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 196676 kb
Host smart-63895bf2-3198-431e-9edf-3f39f31a53d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781807410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1781807410
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2428243622
Short name T1183
Test name
Test status
Simulation time 457125146 ps
CPU time 2.56 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:04 PM PDT 24
Peak memory 200752 kb
Host smart-90ec2bca-ed86-464c-8cad-bde9c163a55e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428243622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2428243622
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2078612176
Short name T1301
Test name
Test status
Simulation time 179585259 ps
CPU time 0.93 seconds
Started Jul 19 04:28:55 PM PDT 24
Finished Jul 19 04:28:59 PM PDT 24
Peak memory 199816 kb
Host smart-4b4e6c1e-c96f-4998-a843-3a8e13a25c05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078612176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2078612176
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1447024999
Short name T1252
Test name
Test status
Simulation time 23731443 ps
CPU time 0.81 seconds
Started Jul 19 04:29:00 PM PDT 24
Finished Jul 19 04:29:04 PM PDT 24
Peak memory 199428 kb
Host smart-59a7d947-cfe1-49d8-9143-12b70ce5adff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447024999 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1447024999
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2586601812
Short name T1290
Test name
Test status
Simulation time 81100285 ps
CPU time 0.62 seconds
Started Jul 19 04:28:58 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 196472 kb
Host smart-9f2b0b74-2860-4c6f-99c7-d52f8cd6e766
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586601812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2586601812
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1731011771
Short name T1299
Test name
Test status
Simulation time 58887128 ps
CPU time 0.56 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:01 PM PDT 24
Peak memory 195060 kb
Host smart-8953fe05-0e52-41e5-b2e4-056fa805fb14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731011771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1731011771
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1328010947
Short name T1287
Test name
Test status
Simulation time 17352032 ps
CPU time 0.59 seconds
Started Jul 19 04:28:54 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 196316 kb
Host smart-eb832dd3-6b5f-4115-bafc-8b50b832d90a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328010947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1328010947
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.989184856
Short name T1204
Test name
Test status
Simulation time 71472279 ps
CPU time 1.07 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 200876 kb
Host smart-d87ac8cc-20fa-45aa-86a4-1df47d848a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989184856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.989184856
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3189930881
Short name T1226
Test name
Test status
Simulation time 21477874 ps
CPU time 0.85 seconds
Started Jul 19 04:28:54 PM PDT 24
Finished Jul 19 04:28:56 PM PDT 24
Peak memory 200612 kb
Host smart-6c30e58c-fd90-4dae-90e1-b470c1839896
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189930881 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3189930881
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1847361365
Short name T89
Test name
Test status
Simulation time 16965614 ps
CPU time 0.61 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:01 PM PDT 24
Peak memory 196268 kb
Host smart-c9fcd805-f495-49eb-bca0-9d67ecab6bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847361365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1847361365
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.508460560
Short name T1202
Test name
Test status
Simulation time 209052459 ps
CPU time 0.55 seconds
Started Jul 19 04:28:55 PM PDT 24
Finished Jul 19 04:28:58 PM PDT 24
Peak memory 195136 kb
Host smart-26ef94c2-26df-40ad-8061-83bb1b8e57e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508460560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.508460560
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2530013609
Short name T1273
Test name
Test status
Simulation time 54570854 ps
CPU time 0.75 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 198288 kb
Host smart-e69e3ceb-4495-4d3d-801e-811209c1e1fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530013609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2530013609
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3343890190
Short name T1209
Test name
Test status
Simulation time 30722849 ps
CPU time 1.5 seconds
Started Jul 19 04:28:56 PM PDT 24
Finished Jul 19 04:29:01 PM PDT 24
Peak memory 200788 kb
Host smart-8f0a5796-75a7-47ab-b0e2-10a5bd5ff148
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343890190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3343890190
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1303520910
Short name T1288
Test name
Test status
Simulation time 73030788 ps
CPU time 1 seconds
Started Jul 19 04:29:00 PM PDT 24
Finished Jul 19 04:29:04 PM PDT 24
Peak memory 199364 kb
Host smart-726a388a-1bfc-4c53-b6d2-dd3949b0cc38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303520910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1303520910
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.23635752
Short name T1210
Test name
Test status
Simulation time 41947966 ps
CPU time 0.75 seconds
Started Jul 19 04:29:06 PM PDT 24
Finished Jul 19 04:29:10 PM PDT 24
Peak memory 200192 kb
Host smart-7bc6e06a-22d2-4f4e-ab25-bcebeddb5248
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23635752 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.23635752
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2650102980
Short name T88
Test name
Test status
Simulation time 26463340 ps
CPU time 0.57 seconds
Started Jul 19 04:29:06 PM PDT 24
Finished Jul 19 04:29:09 PM PDT 24
Peak memory 196280 kb
Host smart-b2b13bfc-c3e9-4106-9ac1-65f008f517c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650102980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2650102980
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1152333242
Short name T1293
Test name
Test status
Simulation time 36004587 ps
CPU time 0.57 seconds
Started Jul 19 04:29:04 PM PDT 24
Finished Jul 19 04:29:07 PM PDT 24
Peak memory 195124 kb
Host smart-ea9ba4b2-18e7-429a-9bb5-2c3974214bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152333242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1152333242
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.420482640
Short name T1291
Test name
Test status
Simulation time 63432538 ps
CPU time 0.74 seconds
Started Jul 19 04:29:03 PM PDT 24
Finished Jul 19 04:29:06 PM PDT 24
Peak memory 197352 kb
Host smart-02812748-74ef-4054-a0e0-c3321a364ab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420482640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.420482640
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3204363263
Short name T1271
Test name
Test status
Simulation time 561455539 ps
CPU time 1.25 seconds
Started Jul 19 04:29:05 PM PDT 24
Finished Jul 19 04:29:09 PM PDT 24
Peak memory 200752 kb
Host smart-9fe6da28-6c32-4b3b-a85a-bc98ce558b08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204363263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3204363263
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3486915667
Short name T96
Test name
Test status
Simulation time 205921915 ps
CPU time 1.25 seconds
Started Jul 19 04:30:08 PM PDT 24
Finished Jul 19 04:30:19 PM PDT 24
Peak memory 197156 kb
Host smart-4095f9e9-f4cc-4b78-9946-c9ebad5320df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486915667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3486915667
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.302024242
Short name T1276
Test name
Test status
Simulation time 125583071 ps
CPU time 0.86 seconds
Started Jul 19 04:29:12 PM PDT 24
Finished Jul 19 04:29:15 PM PDT 24
Peak memory 200576 kb
Host smart-dfb0d997-b812-4a5d-a3b6-61ff5a70c7cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302024242 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.302024242
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1963237658
Short name T1300
Test name
Test status
Simulation time 39310343 ps
CPU time 0.59 seconds
Started Jul 19 04:29:12 PM PDT 24
Finished Jul 19 04:29:14 PM PDT 24
Peak memory 196172 kb
Host smart-f109c859-dfd4-438d-a30d-2dab1eb62466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963237658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1963237658
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.300616784
Short name T1205
Test name
Test status
Simulation time 24903475 ps
CPU time 0.57 seconds
Started Jul 19 04:29:06 PM PDT 24
Finished Jul 19 04:29:10 PM PDT 24
Peak memory 195196 kb
Host smart-24d7d2f2-6181-4e2a-85fa-c68af1edd328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300616784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.300616784
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3789987544
Short name T86
Test name
Test status
Simulation time 36033643 ps
CPU time 0.64 seconds
Started Jul 19 04:29:09 PM PDT 24
Finished Jul 19 04:29:11 PM PDT 24
Peak memory 197192 kb
Host smart-b992fc2d-6935-4527-938e-f8c6b6effc4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789987544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3789987544
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.230179560
Short name T1245
Test name
Test status
Simulation time 123223242 ps
CPU time 2.07 seconds
Started Jul 19 04:29:04 PM PDT 24
Finished Jul 19 04:29:08 PM PDT 24
Peak memory 200884 kb
Host smart-a19b2a91-c994-4dc4-a9cf-c7975ebe4d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230179560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.230179560
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1696369366
Short name T1256
Test name
Test status
Simulation time 550248383 ps
CPU time 1.3 seconds
Started Jul 19 04:29:09 PM PDT 24
Finished Jul 19 04:29:12 PM PDT 24
Peak memory 200008 kb
Host smart-59e49b3e-9dbe-4c8d-aa15-a752e7710985
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696369366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1696369366
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.927333008
Short name T1313
Test name
Test status
Simulation time 34284049 ps
CPU time 0.99 seconds
Started Jul 19 04:29:12 PM PDT 24
Finished Jul 19 04:29:15 PM PDT 24
Peak memory 200576 kb
Host smart-9174fe0e-3222-42ec-a21a-c00429a79bc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927333008 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.927333008
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.977865115
Short name T66
Test name
Test status
Simulation time 14312224 ps
CPU time 0.58 seconds
Started Jul 19 04:29:06 PM PDT 24
Finished Jul 19 04:29:09 PM PDT 24
Peak memory 196136 kb
Host smart-c63ca3d1-3de7-40c6-a7ce-73cab4564462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977865115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.977865115
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.563256076
Short name T1192
Test name
Test status
Simulation time 22905595 ps
CPU time 0.56 seconds
Started Jul 19 04:29:06 PM PDT 24
Finished Jul 19 04:29:09 PM PDT 24
Peak memory 195112 kb
Host smart-b2ef22a0-7172-4fc1-8a51-776328fbfdb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563256076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.563256076
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3300356239
Short name T1259
Test name
Test status
Simulation time 33135164 ps
CPU time 0.6 seconds
Started Jul 19 04:29:06 PM PDT 24
Finished Jul 19 04:29:09 PM PDT 24
Peak memory 196248 kb
Host smart-148d60a1-1392-427f-a7a9-0fa6a4ee8d75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300356239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3300356239
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.4273203788
Short name T1267
Test name
Test status
Simulation time 104304062 ps
CPU time 1.73 seconds
Started Jul 19 04:29:07 PM PDT 24
Finished Jul 19 04:29:11 PM PDT 24
Peak memory 200756 kb
Host smart-50b7b8f3-58e2-4314-8b84-3535aee08457
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273203788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.4273203788
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3719282209
Short name T1208
Test name
Test status
Simulation time 19047024 ps
CPU time 0.68 seconds
Started Jul 19 04:29:03 PM PDT 24
Finished Jul 19 04:29:06 PM PDT 24
Peak memory 198368 kb
Host smart-0e354747-726c-4627-9c20-8228f7e7585a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719282209 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3719282209
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2785749356
Short name T1236
Test name
Test status
Simulation time 64006301 ps
CPU time 0.56 seconds
Started Jul 19 04:29:03 PM PDT 24
Finished Jul 19 04:29:06 PM PDT 24
Peak memory 196256 kb
Host smart-f7a63843-ada3-42d5-bf93-8707ece530db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785749356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2785749356
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.4030885091
Short name T1242
Test name
Test status
Simulation time 37854373 ps
CPU time 0.54 seconds
Started Jul 19 04:29:05 PM PDT 24
Finished Jul 19 04:29:09 PM PDT 24
Peak memory 195156 kb
Host smart-53556bf3-7f96-472d-8b98-ecfa587e87a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030885091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4030885091
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2888864687
Short name T1278
Test name
Test status
Simulation time 49926923 ps
CPU time 0.74 seconds
Started Jul 19 04:30:08 PM PDT 24
Finished Jul 19 04:30:19 PM PDT 24
Peak memory 194924 kb
Host smart-a95d6409-5862-4ea3-8e35-b4438dcc46dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888864687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2888864687
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.661810530
Short name T1292
Test name
Test status
Simulation time 67057121 ps
CPU time 1.38 seconds
Started Jul 19 04:29:05 PM PDT 24
Finished Jul 19 04:29:09 PM PDT 24
Peak memory 200812 kb
Host smart-2b5433cd-ff56-4c3a-a74c-6802bbf69775
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661810530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.661810530
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1528636001
Short name T1262
Test name
Test status
Simulation time 113732089 ps
CPU time 1 seconds
Started Jul 19 04:29:05 PM PDT 24
Finished Jul 19 04:29:09 PM PDT 24
Peak memory 199836 kb
Host smart-be160fbb-e303-4f20-80db-d0b61b62cc28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528636001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1528636001
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3768660699
Short name T1312
Test name
Test status
Simulation time 17733604 ps
CPU time 0.63 seconds
Started Jul 19 04:29:09 PM PDT 24
Finished Jul 19 04:29:11 PM PDT 24
Peak memory 198008 kb
Host smart-3f5b63e2-6682-43f2-9b87-59c823ea1420
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768660699 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3768660699
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2283298718
Short name T1255
Test name
Test status
Simulation time 33269330 ps
CPU time 0.57 seconds
Started Jul 19 04:29:05 PM PDT 24
Finished Jul 19 04:29:09 PM PDT 24
Peak memory 196224 kb
Host smart-ebacf812-d215-4766-bdf8-681fe544bac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283298718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2283298718
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3188946699
Short name T1223
Test name
Test status
Simulation time 67135955 ps
CPU time 0.58 seconds
Started Jul 19 04:29:05 PM PDT 24
Finished Jul 19 04:29:08 PM PDT 24
Peak memory 195048 kb
Host smart-a17dc59a-1100-4696-a9f8-167e563bb97a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188946699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3188946699
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3796029181
Short name T1302
Test name
Test status
Simulation time 125142300 ps
CPU time 0.63 seconds
Started Jul 19 04:29:12 PM PDT 24
Finished Jul 19 04:29:14 PM PDT 24
Peak memory 196336 kb
Host smart-c7c5e939-3584-4536-86ad-65fa4382bcca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796029181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3796029181
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2453613826
Short name T1310
Test name
Test status
Simulation time 174176252 ps
CPU time 2 seconds
Started Jul 19 04:29:15 PM PDT 24
Finished Jul 19 04:29:18 PM PDT 24
Peak memory 200872 kb
Host smart-f24098cd-7a04-4a3f-a3a3-8ef63c3f0c46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453613826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2453613826
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.271217139
Short name T1307
Test name
Test status
Simulation time 42982223 ps
CPU time 0.94 seconds
Started Jul 19 04:29:04 PM PDT 24
Finished Jul 19 04:29:07 PM PDT 24
Peak memory 199672 kb
Host smart-64340754-e1ad-4112-bfac-ebb55325ed6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271217139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.271217139
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3686502583
Short name T1238
Test name
Test status
Simulation time 16184045 ps
CPU time 0.7 seconds
Started Jul 19 04:30:08 PM PDT 24
Finished Jul 19 04:30:19 PM PDT 24
Peak memory 198180 kb
Host smart-16adf31d-97a5-4eb0-80ee-1da2673c8d60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686502583 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3686502583
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1949400301
Short name T1315
Test name
Test status
Simulation time 15405360 ps
CPU time 0.59 seconds
Started Jul 19 04:29:03 PM PDT 24
Finished Jul 19 04:29:06 PM PDT 24
Peak memory 196192 kb
Host smart-d5e3c016-fae3-4279-ba3b-257ce7ba8593
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949400301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1949400301
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.320931846
Short name T1180
Test name
Test status
Simulation time 42245329 ps
CPU time 0.52 seconds
Started Jul 19 04:29:04 PM PDT 24
Finished Jul 19 04:29:07 PM PDT 24
Peak memory 195072 kb
Host smart-0320bcaa-bea5-4af0-b5a2-233d7e3f27aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320931846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.320931846
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.4269474168
Short name T82
Test name
Test status
Simulation time 104535193 ps
CPU time 0.79 seconds
Started Jul 19 04:29:07 PM PDT 24
Finished Jul 19 04:29:10 PM PDT 24
Peak memory 197980 kb
Host smart-83d64ffe-51b8-4e4e-9bc0-fcde5e17ec66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269474168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.4269474168
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2791498140
Short name T1305
Test name
Test status
Simulation time 99276178 ps
CPU time 1 seconds
Started Jul 19 04:29:09 PM PDT 24
Finished Jul 19 04:29:11 PM PDT 24
Peak memory 200544 kb
Host smart-e9c90a39-a53a-4cf0-b57f-db5ad93531a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791498140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2791498140
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1761304527
Short name T1296
Test name
Test status
Simulation time 47401099 ps
CPU time 0.94 seconds
Started Jul 19 04:29:04 PM PDT 24
Finished Jul 19 04:29:08 PM PDT 24
Peak memory 199684 kb
Host smart-b02a0f3f-792f-4aa0-a88f-4fad5ea753fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761304527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1761304527
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1823608031
Short name T1219
Test name
Test status
Simulation time 27270281 ps
CPU time 0.65 seconds
Started Jul 19 04:28:43 PM PDT 24
Finished Jul 19 04:28:45 PM PDT 24
Peak memory 196164 kb
Host smart-c535d87e-a85a-4616-8819-c0ff2a38125f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823608031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1823608031
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2639406262
Short name T1275
Test name
Test status
Simulation time 253278981 ps
CPU time 2.74 seconds
Started Jul 19 04:28:44 PM PDT 24
Finished Jul 19 04:28:49 PM PDT 24
Peak memory 196880 kb
Host smart-956a74c4-4ed5-4219-ae03-7150b01b360d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639406262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2639406262
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1381777467
Short name T1303
Test name
Test status
Simulation time 22029002 ps
CPU time 0.56 seconds
Started Jul 19 04:28:37 PM PDT 24
Finished Jul 19 04:28:39 PM PDT 24
Peak memory 196140 kb
Host smart-1fa216a9-1960-4aee-9a34-9834314b11d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381777467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1381777467
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3319960297
Short name T1250
Test name
Test status
Simulation time 75017443 ps
CPU time 0.72 seconds
Started Jul 19 04:28:43 PM PDT 24
Finished Jul 19 04:28:46 PM PDT 24
Peak memory 199352 kb
Host smart-1048cd54-3732-4cff-b96f-298942f900f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319960297 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3319960297
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.53160051
Short name T80
Test name
Test status
Simulation time 42932354 ps
CPU time 0.55 seconds
Started Jul 19 04:28:42 PM PDT 24
Finished Jul 19 04:28:45 PM PDT 24
Peak memory 196160 kb
Host smart-8b5c597e-b15b-4432-bfc2-70c79668a11f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53160051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.53160051
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3736734850
Short name T1246
Test name
Test status
Simulation time 38981305 ps
CPU time 0.59 seconds
Started Jul 19 04:28:40 PM PDT 24
Finished Jul 19 04:28:42 PM PDT 24
Peak memory 195148 kb
Host smart-fdaa4911-c8f4-4ec2-828c-980f52c369de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736734850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3736734850
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2111923916
Short name T87
Test name
Test status
Simulation time 117697692 ps
CPU time 0.76 seconds
Started Jul 19 04:28:38 PM PDT 24
Finished Jul 19 04:28:41 PM PDT 24
Peak memory 196640 kb
Host smart-8c604045-3a50-41d5-80c4-e8903a8d7214
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111923916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2111923916
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3930347314
Short name T1218
Test name
Test status
Simulation time 225194928 ps
CPU time 1.32 seconds
Started Jul 19 04:28:38 PM PDT 24
Finished Jul 19 04:28:42 PM PDT 24
Peak memory 200880 kb
Host smart-900ce797-2b9b-43cf-ad46-d42d99ad7f10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930347314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3930347314
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3720729774
Short name T95
Test name
Test status
Simulation time 77313984 ps
CPU time 0.89 seconds
Started Jul 19 04:28:45 PM PDT 24
Finished Jul 19 04:28:47 PM PDT 24
Peak memory 199436 kb
Host smart-7eb4360c-da83-4a94-be14-7beb0684a80a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720729774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3720729774
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1873494634
Short name T1215
Test name
Test status
Simulation time 88954341 ps
CPU time 0.56 seconds
Started Jul 19 04:29:17 PM PDT 24
Finished Jul 19 04:29:20 PM PDT 24
Peak memory 195180 kb
Host smart-fe3e6c20-012d-4e08-ace7-de8f94e3302f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873494634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1873494634
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1677726558
Short name T1197
Test name
Test status
Simulation time 87899507 ps
CPU time 0.55 seconds
Started Jul 19 04:29:18 PM PDT 24
Finished Jul 19 04:29:20 PM PDT 24
Peak memory 195100 kb
Host smart-62aa3426-8424-429d-9f3b-d61cc24f8b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677726558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1677726558
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1339455737
Short name T1269
Test name
Test status
Simulation time 29380192 ps
CPU time 0.6 seconds
Started Jul 19 04:29:17 PM PDT 24
Finished Jul 19 04:29:20 PM PDT 24
Peak memory 195100 kb
Host smart-c70fb029-f8f0-4f29-9e9a-4e59fb9c241a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339455737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1339455737
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2764394243
Short name T1221
Test name
Test status
Simulation time 14942850 ps
CPU time 0.58 seconds
Started Jul 19 04:29:16 PM PDT 24
Finished Jul 19 04:29:18 PM PDT 24
Peak memory 195100 kb
Host smart-020d2594-ad37-4903-9400-561651a55884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764394243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2764394243
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.399100161
Short name T1181
Test name
Test status
Simulation time 39228728 ps
CPU time 0.6 seconds
Started Jul 19 04:29:15 PM PDT 24
Finished Jul 19 04:29:17 PM PDT 24
Peak memory 195252 kb
Host smart-6830132f-f259-4783-8c21-e6e0fb199dee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399100161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.399100161
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1049981072
Short name T1272
Test name
Test status
Simulation time 52214223 ps
CPU time 0.62 seconds
Started Jul 19 04:29:17 PM PDT 24
Finished Jul 19 04:29:20 PM PDT 24
Peak memory 195228 kb
Host smart-398e5cbd-94cc-4f34-85a9-9d6eb30e3ba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049981072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1049981072
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.4044124026
Short name T1248
Test name
Test status
Simulation time 15188519 ps
CPU time 0.59 seconds
Started Jul 19 04:29:16 PM PDT 24
Finished Jul 19 04:29:19 PM PDT 24
Peak memory 195204 kb
Host smart-42e57ef3-ff82-4534-9953-f78410912919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044124026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.4044124026
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3045603419
Short name T1247
Test name
Test status
Simulation time 41735865 ps
CPU time 0.59 seconds
Started Jul 19 04:29:18 PM PDT 24
Finished Jul 19 04:29:21 PM PDT 24
Peak memory 195152 kb
Host smart-7981f41e-3a9b-4306-872a-6b2a8017c430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045603419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3045603419
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.910817785
Short name T1286
Test name
Test status
Simulation time 14913240 ps
CPU time 0.58 seconds
Started Jul 19 04:29:18 PM PDT 24
Finished Jul 19 04:29:21 PM PDT 24
Peak memory 195048 kb
Host smart-385133da-5664-4732-be81-d070664844d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910817785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.910817785
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.252960648
Short name T1212
Test name
Test status
Simulation time 28640691 ps
CPU time 0.56 seconds
Started Jul 19 04:29:20 PM PDT 24
Finished Jul 19 04:29:22 PM PDT 24
Peak memory 195004 kb
Host smart-4c9e1133-67bf-4706-98a7-e75f86d1b9ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252960648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.252960648
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2139930944
Short name T1314
Test name
Test status
Simulation time 29022935 ps
CPU time 0.72 seconds
Started Jul 19 04:28:54 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 197520 kb
Host smart-33076491-182a-4743-8e50-7729918bb6ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139930944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2139930944
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.989007467
Short name T1179
Test name
Test status
Simulation time 336220735 ps
CPU time 2.32 seconds
Started Jul 19 04:28:39 PM PDT 24
Finished Jul 19 04:28:43 PM PDT 24
Peak memory 198612 kb
Host smart-488ff570-ebc7-4b77-a854-2b688f583b45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989007467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.989007467
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.592738925
Short name T61
Test name
Test status
Simulation time 57942740 ps
CPU time 0.57 seconds
Started Jul 19 04:28:41 PM PDT 24
Finished Jul 19 04:28:44 PM PDT 24
Peak memory 196156 kb
Host smart-46c5b393-1873-401a-bee2-981dcf651c96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592738925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.592738925
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3563076180
Short name T1234
Test name
Test status
Simulation time 66533344 ps
CPU time 0.67 seconds
Started Jul 19 04:28:50 PM PDT 24
Finished Jul 19 04:28:53 PM PDT 24
Peak memory 198364 kb
Host smart-0556f262-fb12-4b25-9878-f1cbe59df118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563076180 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3563076180
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.150569095
Short name T1237
Test name
Test status
Simulation time 17195404 ps
CPU time 0.59 seconds
Started Jul 19 04:28:40 PM PDT 24
Finished Jul 19 04:28:42 PM PDT 24
Peak memory 196140 kb
Host smart-61833a67-25fb-4661-a11f-505edfed1696
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150569095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.150569095
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.991261830
Short name T1185
Test name
Test status
Simulation time 16360769 ps
CPU time 0.54 seconds
Started Jul 19 04:28:40 PM PDT 24
Finished Jul 19 04:28:42 PM PDT 24
Peak memory 195084 kb
Host smart-90e2e7d5-f9b3-4495-8e66-2b0d0bd19447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991261830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.991261830
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3638508071
Short name T1261
Test name
Test status
Simulation time 71586526 ps
CPU time 0.61 seconds
Started Jul 19 04:28:48 PM PDT 24
Finished Jul 19 04:28:50 PM PDT 24
Peak memory 197268 kb
Host smart-6c1e2178-44d9-427a-9176-7754352a27bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638508071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3638508071
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3545123331
Short name T1274
Test name
Test status
Simulation time 85276432 ps
CPU time 1.83 seconds
Started Jul 19 04:28:45 PM PDT 24
Finished Jul 19 04:28:48 PM PDT 24
Peak memory 200840 kb
Host smart-1e46c79e-84ff-41fa-be46-79b918c0e2e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545123331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3545123331
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3320964141
Short name T98
Test name
Test status
Simulation time 155721228 ps
CPU time 1.29 seconds
Started Jul 19 04:28:39 PM PDT 24
Finished Jul 19 04:28:42 PM PDT 24
Peak memory 200280 kb
Host smart-5c53c613-56d1-4dc8-941d-cd0ac4a096f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320964141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3320964141
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1297474035
Short name T1200
Test name
Test status
Simulation time 66021142 ps
CPU time 0.56 seconds
Started Jul 19 04:29:17 PM PDT 24
Finished Jul 19 04:29:20 PM PDT 24
Peak memory 195088 kb
Host smart-fc775e02-df1a-44f7-8f8f-a6dca946c5b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297474035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1297474035
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.4286692095
Short name T1188
Test name
Test status
Simulation time 15589379 ps
CPU time 0.55 seconds
Started Jul 19 04:29:18 PM PDT 24
Finished Jul 19 04:29:21 PM PDT 24
Peak memory 195100 kb
Host smart-124647a3-1d69-41a0-a9e5-53ce4026032c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286692095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.4286692095
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4194882240
Short name T1232
Test name
Test status
Simulation time 57158696 ps
CPU time 0.56 seconds
Started Jul 19 04:29:17 PM PDT 24
Finished Jul 19 04:29:19 PM PDT 24
Peak memory 195092 kb
Host smart-7f7ab64c-140c-4b37-8a7e-ae4e3943a63c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194882240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4194882240
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3424410290
Short name T1277
Test name
Test status
Simulation time 33158084 ps
CPU time 0.55 seconds
Started Jul 19 04:29:17 PM PDT 24
Finished Jul 19 04:29:19 PM PDT 24
Peak memory 195180 kb
Host smart-7c788c5f-59a1-4d6e-8089-6a8c0d259b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424410290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3424410290
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.517383092
Short name T1297
Test name
Test status
Simulation time 11747009 ps
CPU time 0.53 seconds
Started Jul 19 04:29:19 PM PDT 24
Finished Jul 19 04:29:22 PM PDT 24
Peak memory 195100 kb
Host smart-5365d65d-cd7e-4008-9698-84530dd66f98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517383092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.517383092
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3486790201
Short name T1195
Test name
Test status
Simulation time 50303287 ps
CPU time 0.55 seconds
Started Jul 19 04:29:19 PM PDT 24
Finished Jul 19 04:29:22 PM PDT 24
Peak memory 195164 kb
Host smart-302fbc2f-f8e4-4d38-9394-da8976272a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486790201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3486790201
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2183792956
Short name T1182
Test name
Test status
Simulation time 71268931 ps
CPU time 0.57 seconds
Started Jul 19 04:29:20 PM PDT 24
Finished Jul 19 04:29:22 PM PDT 24
Peak memory 194988 kb
Host smart-501ec0c8-d9e1-4a45-80d1-7e8a87da5d2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183792956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2183792956
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.889075959
Short name T1186
Test name
Test status
Simulation time 28178858 ps
CPU time 0.58 seconds
Started Jul 19 04:29:16 PM PDT 24
Finished Jul 19 04:29:19 PM PDT 24
Peak memory 195192 kb
Host smart-92ae7718-0a90-446f-8fdb-1291b57e7774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889075959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.889075959
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3158244730
Short name T1196
Test name
Test status
Simulation time 27237673 ps
CPU time 0.58 seconds
Started Jul 19 04:29:16 PM PDT 24
Finished Jul 19 04:29:18 PM PDT 24
Peak memory 195156 kb
Host smart-fd341804-30ac-4d30-a562-24598f0d99c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158244730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3158244730
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.164098428
Short name T1191
Test name
Test status
Simulation time 13910839 ps
CPU time 0.61 seconds
Started Jul 19 04:29:19 PM PDT 24
Finished Jul 19 04:29:22 PM PDT 24
Peak memory 195168 kb
Host smart-f3e358f7-656a-4628-b5e5-12392a237d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164098428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.164098428
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.295875595
Short name T1243
Test name
Test status
Simulation time 94128112 ps
CPU time 0.75 seconds
Started Jul 19 04:28:50 PM PDT 24
Finished Jul 19 04:28:53 PM PDT 24
Peak memory 197360 kb
Host smart-68ecb4c8-6e4a-4167-a14f-6408b419c541
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295875595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.295875595
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2995647019
Short name T62
Test name
Test status
Simulation time 974282364 ps
CPU time 1.51 seconds
Started Jul 19 04:28:48 PM PDT 24
Finished Jul 19 04:28:52 PM PDT 24
Peak memory 198664 kb
Host smart-3421d85b-e767-4a05-8ccd-1311bd78aa54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995647019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2995647019
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.5968685
Short name T1298
Test name
Test status
Simulation time 29558489 ps
CPU time 0.61 seconds
Started Jul 19 04:28:49 PM PDT 24
Finished Jul 19 04:28:52 PM PDT 24
Peak memory 196204 kb
Host smart-0a5d80f3-fb5f-41e0-b363-3cefacb46e1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5968685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.5968685
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1644495547
Short name T1220
Test name
Test status
Simulation time 20810652 ps
CPU time 0.86 seconds
Started Jul 19 04:28:48 PM PDT 24
Finished Jul 19 04:28:51 PM PDT 24
Peak memory 200500 kb
Host smart-66bc056f-e131-4b74-b0ff-955a348ffe7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644495547 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1644495547
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3013243782
Short name T1222
Test name
Test status
Simulation time 34233861 ps
CPU time 0.58 seconds
Started Jul 19 04:28:45 PM PDT 24
Finished Jul 19 04:28:47 PM PDT 24
Peak memory 196200 kb
Host smart-b0efa517-0358-439f-901d-af9f14def313
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013243782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3013243782
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.583092911
Short name T1283
Test name
Test status
Simulation time 37768305 ps
CPU time 0.59 seconds
Started Jul 19 04:28:47 PM PDT 24
Finished Jul 19 04:28:49 PM PDT 24
Peak memory 195208 kb
Host smart-1aa0087d-f04f-48b3-8754-0f887ed39044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583092911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.583092911
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2377517640
Short name T81
Test name
Test status
Simulation time 31231940 ps
CPU time 0.7 seconds
Started Jul 19 04:28:48 PM PDT 24
Finished Jul 19 04:28:50 PM PDT 24
Peak memory 196828 kb
Host smart-cf1b97b5-d52c-4ca3-b24f-6b6677425e80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377517640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2377517640
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.4240309265
Short name T1280
Test name
Test status
Simulation time 163694576 ps
CPU time 1.64 seconds
Started Jul 19 04:28:47 PM PDT 24
Finished Jul 19 04:28:49 PM PDT 24
Peak memory 200808 kb
Host smart-da3bfb96-eecb-4034-8cc7-c587d3e21492
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240309265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.4240309265
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3028114877
Short name T1264
Test name
Test status
Simulation time 49174860 ps
CPU time 0.9 seconds
Started Jul 19 04:28:50 PM PDT 24
Finished Jul 19 04:28:54 PM PDT 24
Peak memory 199724 kb
Host smart-adae3a9d-acb2-40ae-aca0-b1bc24cd9289
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028114877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3028114877
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2804667939
Short name T1190
Test name
Test status
Simulation time 36162807 ps
CPU time 0.58 seconds
Started Jul 19 04:29:16 PM PDT 24
Finished Jul 19 04:29:18 PM PDT 24
Peak memory 195076 kb
Host smart-e6f9f8fa-b6c4-4b5d-854b-e559c4d65bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804667939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2804667939
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.4285596758
Short name T1213
Test name
Test status
Simulation time 16949564 ps
CPU time 0.54 seconds
Started Jul 19 04:29:14 PM PDT 24
Finished Jul 19 04:29:16 PM PDT 24
Peak memory 195116 kb
Host smart-0c56716c-fdad-4700-b5a8-672f5df5fd3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285596758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.4285596758
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4031843043
Short name T1253
Test name
Test status
Simulation time 14983510 ps
CPU time 0.55 seconds
Started Jul 19 04:29:15 PM PDT 24
Finished Jul 19 04:29:16 PM PDT 24
Peak memory 195096 kb
Host smart-87618e8d-6b8b-40af-89e0-f50d56973c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031843043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4031843043
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1947069218
Short name T1306
Test name
Test status
Simulation time 11127524 ps
CPU time 0.58 seconds
Started Jul 19 04:29:17 PM PDT 24
Finished Jul 19 04:29:19 PM PDT 24
Peak memory 195104 kb
Host smart-8c2ed2a2-1560-463d-b87f-af66a6bdc62d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947069218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1947069218
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2716636569
Short name T1224
Test name
Test status
Simulation time 13670038 ps
CPU time 0.55 seconds
Started Jul 19 04:29:18 PM PDT 24
Finished Jul 19 04:29:21 PM PDT 24
Peak memory 195100 kb
Host smart-ac65e7f9-5718-4525-af73-d1a895f4a013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716636569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2716636569
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.4054992071
Short name T1279
Test name
Test status
Simulation time 15125720 ps
CPU time 0.59 seconds
Started Jul 19 04:29:21 PM PDT 24
Finished Jul 19 04:29:23 PM PDT 24
Peak memory 195168 kb
Host smart-46df811a-b572-4ec6-bd64-19cbee0779b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054992071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.4054992071
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2776254374
Short name T1304
Test name
Test status
Simulation time 40781444 ps
CPU time 0.56 seconds
Started Jul 19 04:29:17 PM PDT 24
Finished Jul 19 04:29:20 PM PDT 24
Peak memory 195084 kb
Host smart-b8737986-db94-40c8-849d-58a6a27782ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776254374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2776254374
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.452519493
Short name T1233
Test name
Test status
Simulation time 28180463 ps
CPU time 0.61 seconds
Started Jul 19 04:29:17 PM PDT 24
Finished Jul 19 04:29:19 PM PDT 24
Peak memory 195204 kb
Host smart-7a8c3a35-de47-4feb-b371-65f73b523c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452519493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.452519493
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3933703691
Short name T1241
Test name
Test status
Simulation time 15745558 ps
CPU time 0.6 seconds
Started Jul 19 04:29:19 PM PDT 24
Finished Jul 19 04:29:22 PM PDT 24
Peak memory 195300 kb
Host smart-47a40fc7-8d92-4aba-bfb8-b3d0dbdf77b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933703691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3933703691
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1368780526
Short name T1225
Test name
Test status
Simulation time 46526143 ps
CPU time 0.58 seconds
Started Jul 19 04:29:19 PM PDT 24
Finished Jul 19 04:29:22 PM PDT 24
Peak memory 195120 kb
Host smart-82399237-2faa-40d2-85ef-d48388d4797f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368780526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1368780526
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.261133553
Short name T1285
Test name
Test status
Simulation time 21524126 ps
CPU time 0.94 seconds
Started Jul 19 04:28:52 PM PDT 24
Finished Jul 19 04:28:55 PM PDT 24
Peak memory 200576 kb
Host smart-b0973b6b-84ec-4e08-a6ce-5c93153ff926
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261133553 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.261133553
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2060453802
Short name T1308
Test name
Test status
Simulation time 56629095 ps
CPU time 0.6 seconds
Started Jul 19 04:28:47 PM PDT 24
Finished Jul 19 04:28:49 PM PDT 24
Peak memory 196420 kb
Host smart-97ff500f-7ae5-43f8-92b3-1717dfbd1393
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060453802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2060453802
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.498599973
Short name T1240
Test name
Test status
Simulation time 26382330 ps
CPU time 0.56 seconds
Started Jul 19 04:28:49 PM PDT 24
Finished Jul 19 04:28:52 PM PDT 24
Peak memory 195076 kb
Host smart-52649bf6-1bb5-4d28-bec0-9e49d4fb7b4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498599973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.498599973
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3147296685
Short name T1268
Test name
Test status
Simulation time 17913813 ps
CPU time 0.67 seconds
Started Jul 19 04:28:54 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 196536 kb
Host smart-e3b5ecd5-6f7f-4110-aede-6283421c2ef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147296685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3147296685
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.622577708
Short name T1227
Test name
Test status
Simulation time 47102619 ps
CPU time 1 seconds
Started Jul 19 04:28:48 PM PDT 24
Finished Jul 19 04:28:50 PM PDT 24
Peak memory 200544 kb
Host smart-de686e0c-b77c-4aa0-971c-9668919deaaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622577708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.622577708
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1363183763
Short name T94
Test name
Test status
Simulation time 87119478 ps
CPU time 0.9 seconds
Started Jul 19 04:28:54 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 199656 kb
Host smart-221cace7-0a11-4682-824c-074a67c5621c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363183763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1363183763
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2935046197
Short name T1206
Test name
Test status
Simulation time 21926942 ps
CPU time 0.74 seconds
Started Jul 19 04:28:48 PM PDT 24
Finished Jul 19 04:28:51 PM PDT 24
Peak memory 199444 kb
Host smart-21df41e6-1541-474f-ac45-5adbeb7f658f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935046197 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2935046197
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.4273857878
Short name T1258
Test name
Test status
Simulation time 88302955 ps
CPU time 0.61 seconds
Started Jul 19 04:28:52 PM PDT 24
Finished Jul 19 04:28:55 PM PDT 24
Peak memory 196256 kb
Host smart-050eb7d1-ff97-4888-b04e-655ff9a6864e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273857878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.4273857878
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1521955625
Short name T1201
Test name
Test status
Simulation time 13870611 ps
CPU time 0.53 seconds
Started Jul 19 04:28:50 PM PDT 24
Finished Jul 19 04:28:52 PM PDT 24
Peak memory 195148 kb
Host smart-2d0458e4-9de8-4872-92be-7d1b6118ddd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521955625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1521955625
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1189729463
Short name T85
Test name
Test status
Simulation time 56333247 ps
CPU time 0.58 seconds
Started Jul 19 04:28:48 PM PDT 24
Finished Jul 19 04:28:51 PM PDT 24
Peak memory 196260 kb
Host smart-d1d0fac8-820e-479f-9504-60732c87db60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189729463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1189729463
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3698322294
Short name T1251
Test name
Test status
Simulation time 164048139 ps
CPU time 1.68 seconds
Started Jul 19 04:28:49 PM PDT 24
Finished Jul 19 04:28:52 PM PDT 24
Peak memory 200696 kb
Host smart-60b94e44-8790-47d7-81a0-774d341d2df1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698322294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3698322294
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.522410193
Short name T91
Test name
Test status
Simulation time 83453100 ps
CPU time 0.87 seconds
Started Jul 19 04:28:46 PM PDT 24
Finished Jul 19 04:28:48 PM PDT 24
Peak memory 199692 kb
Host smart-83a2f62a-1df8-48d0-af57-03a76118e41b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522410193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.522410193
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3730341810
Short name T1229
Test name
Test status
Simulation time 21206953 ps
CPU time 0.73 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:01 PM PDT 24
Peak memory 199316 kb
Host smart-554458ef-e297-480a-8ddb-2e1ec6dcff05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730341810 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3730341810
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.4122906131
Short name T1230
Test name
Test status
Simulation time 44707851 ps
CPU time 0.58 seconds
Started Jul 19 04:28:47 PM PDT 24
Finished Jul 19 04:28:49 PM PDT 24
Peak memory 196312 kb
Host smart-252d7ea8-71b7-4586-94f7-6e2863d429d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122906131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4122906131
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.4245505915
Short name T1193
Test name
Test status
Simulation time 14295431 ps
CPU time 0.56 seconds
Started Jul 19 04:28:53 PM PDT 24
Finished Jul 19 04:28:56 PM PDT 24
Peak memory 195084 kb
Host smart-d9938666-c46d-4ca4-808c-4d41ee542f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245505915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.4245505915
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.579785000
Short name T1216
Test name
Test status
Simulation time 118842672 ps
CPU time 0.75 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 198476 kb
Host smart-f52aa1ca-ebbb-4779-a7b1-b990a9bccef2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579785000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.579785000
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.531427365
Short name T1199
Test name
Test status
Simulation time 104602522 ps
CPU time 1.48 seconds
Started Jul 19 04:28:48 PM PDT 24
Finished Jul 19 04:28:51 PM PDT 24
Peak memory 200840 kb
Host smart-3f1e1223-9de6-4642-a7eb-c825027b3d25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531427365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.531427365
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1339273349
Short name T99
Test name
Test status
Simulation time 1000605374 ps
CPU time 1.51 seconds
Started Jul 19 04:28:54 PM PDT 24
Finished Jul 19 04:28:58 PM PDT 24
Peak memory 200140 kb
Host smart-87434018-23d6-43e8-9338-344b93435c0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339273349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1339273349
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1912478183
Short name T1189
Test name
Test status
Simulation time 48593937 ps
CPU time 0.75 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 200540 kb
Host smart-cf78e5ce-3038-4712-9820-bf51cf0b8271
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912478183 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1912478183
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2989522061
Short name T65
Test name
Test status
Simulation time 33316261 ps
CPU time 0.54 seconds
Started Jul 19 04:28:55 PM PDT 24
Finished Jul 19 04:28:59 PM PDT 24
Peak memory 196136 kb
Host smart-a817e5bf-1672-456c-a16b-c846c964d02e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989522061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2989522061
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.964522398
Short name T1309
Test name
Test status
Simulation time 59124852 ps
CPU time 0.55 seconds
Started Jul 19 04:28:54 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 195188 kb
Host smart-0ff14f81-b019-4900-b0da-696371f5ec07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964522398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.964522398
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3374471913
Short name T83
Test name
Test status
Simulation time 135241792 ps
CPU time 0.74 seconds
Started Jul 19 04:28:59 PM PDT 24
Finished Jul 19 04:29:03 PM PDT 24
Peak memory 196820 kb
Host smart-286e1e86-1461-423c-bb54-d6920deffd3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374471913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3374471913
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3063400237
Short name T1235
Test name
Test status
Simulation time 323531009 ps
CPU time 1.83 seconds
Started Jul 19 04:28:55 PM PDT 24
Finished Jul 19 04:29:00 PM PDT 24
Peak memory 200728 kb
Host smart-f42108b5-81f2-4d5b-98d6-cabdc126757c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063400237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3063400237
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3494658682
Short name T1244
Test name
Test status
Simulation time 157699711 ps
CPU time 0.89 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:01 PM PDT 24
Peak memory 199648 kb
Host smart-6cb2d965-188e-4e6b-8745-0bf0aabe9701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494658682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3494658682
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2283269781
Short name T1295
Test name
Test status
Simulation time 30478758 ps
CPU time 0.75 seconds
Started Jul 19 04:28:55 PM PDT 24
Finished Jul 19 04:29:00 PM PDT 24
Peak memory 200556 kb
Host smart-34806ba5-3593-4cba-ba1b-a80b95bfd785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283269781 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2283269781
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.4000442439
Short name T79
Test name
Test status
Simulation time 12521396 ps
CPU time 0.57 seconds
Started Jul 19 04:28:55 PM PDT 24
Finished Jul 19 04:28:58 PM PDT 24
Peak memory 196220 kb
Host smart-3889a8b6-cc89-444c-b7d8-2b0966461a7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000442439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.4000442439
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.261203698
Short name T1207
Test name
Test status
Simulation time 27906738 ps
CPU time 0.53 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 195152 kb
Host smart-bda92c9f-2aa3-4236-98ec-aec9c5b8f72a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261203698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.261203698
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.311182048
Short name T1254
Test name
Test status
Simulation time 31951483 ps
CPU time 0.73 seconds
Started Jul 19 04:28:57 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 196896 kb
Host smart-6a9f13e4-001f-4e49-ba10-652710032c52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311182048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.311182048
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1551499156
Short name T1311
Test name
Test status
Simulation time 33084993 ps
CPU time 0.95 seconds
Started Jul 19 04:28:56 PM PDT 24
Finished Jul 19 04:29:01 PM PDT 24
Peak memory 200624 kb
Host smart-3dcf4da7-9aec-43a5-940d-f0d5c4ac413a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551499156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1551499156
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.700820330
Short name T138
Test name
Test status
Simulation time 211008784 ps
CPU time 0.91 seconds
Started Jul 19 04:28:54 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 199948 kb
Host smart-b7bba404-0d1d-4bcc-99cb-4a6de69f7772
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700820330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.700820330
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2189907678
Short name T855
Test name
Test status
Simulation time 43051793 ps
CPU time 0.55 seconds
Started Jul 19 04:24:56 PM PDT 24
Finished Jul 19 04:25:24 PM PDT 24
Peak memory 195004 kb
Host smart-5d643f3f-c738-436c-82c7-ea193c4e55b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189907678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2189907678
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2546561412
Short name T829
Test name
Test status
Simulation time 72555898279 ps
CPU time 54.07 seconds
Started Jul 19 04:24:49 PM PDT 24
Finished Jul 19 04:26:14 PM PDT 24
Peak memory 199940 kb
Host smart-bda5a406-78c9-47d4-ba34-bcbeece0019a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546561412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2546561412
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.4102499477
Short name T721
Test name
Test status
Simulation time 9665889348 ps
CPU time 13.95 seconds
Started Jul 19 04:24:45 PM PDT 24
Finished Jul 19 04:25:33 PM PDT 24
Peak memory 199860 kb
Host smart-238ac971-e529-47f4-b25c-611051532f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102499477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.4102499477
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2521655888
Short name T1038
Test name
Test status
Simulation time 88341317951 ps
CPU time 229.7 seconds
Started Jul 19 04:24:55 PM PDT 24
Finished Jul 19 04:29:13 PM PDT 24
Peak memory 199824 kb
Host smart-a4b06806-5f30-4f9e-81db-13c2e886f8f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521655888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2521655888
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3475920591
Short name T1135
Test name
Test status
Simulation time 7041075366 ps
CPU time 3.06 seconds
Started Jul 19 04:24:56 PM PDT 24
Finished Jul 19 04:25:26 PM PDT 24
Peak memory 199404 kb
Host smart-c177cc94-9b21-4cd7-8c71-876e73248f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475920591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3475920591
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2217939788
Short name T453
Test name
Test status
Simulation time 31290212492 ps
CPU time 45.37 seconds
Started Jul 19 04:24:52 PM PDT 24
Finished Jul 19 04:26:06 PM PDT 24
Peak memory 198656 kb
Host smart-5eea0ebc-bd28-4471-a869-62417d67aa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217939788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2217939788
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3440972647
Short name T1025
Test name
Test status
Simulation time 15566332458 ps
CPU time 177.42 seconds
Started Jul 19 04:24:55 PM PDT 24
Finished Jul 19 04:28:20 PM PDT 24
Peak memory 199904 kb
Host smart-cd4f6948-713d-466c-a1a4-6f5781e89650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440972647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3440972647
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3731693857
Short name T21
Test name
Test status
Simulation time 1400496694 ps
CPU time 1.1 seconds
Started Jul 19 04:24:45 PM PDT 24
Finished Jul 19 04:25:20 PM PDT 24
Peak memory 195472 kb
Host smart-85e92577-eb26-46a9-b19e-d4c0d325f437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731693857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3731693857
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.451980914
Short name T606
Test name
Test status
Simulation time 70537946125 ps
CPU time 54.06 seconds
Started Jul 19 04:24:50 PM PDT 24
Finished Jul 19 04:26:15 PM PDT 24
Peak memory 199868 kb
Host smart-04372675-4212-4cff-8a7a-5f39f020eb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451980914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.451980914
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.4143014254
Short name T638
Test name
Test status
Simulation time 453928157 ps
CPU time 1.3 seconds
Started Jul 19 04:24:55 PM PDT 24
Finished Jul 19 04:25:24 PM PDT 24
Peak memory 195424 kb
Host smart-e691d6af-3e41-48b2-862c-ca9e7a53ae44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143014254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.4143014254
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3606197027
Short name T102
Test name
Test status
Simulation time 67745626 ps
CPU time 0.75 seconds
Started Jul 19 04:24:53 PM PDT 24
Finished Jul 19 04:25:23 PM PDT 24
Peak memory 218236 kb
Host smart-1c6b45d0-4376-46dc-83a0-a28cdc1913a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606197027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3606197027
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2102439172
Short name T588
Test name
Test status
Simulation time 5537248436 ps
CPU time 6.71 seconds
Started Jul 19 04:24:42 PM PDT 24
Finished Jul 19 04:25:24 PM PDT 24
Peak memory 199732 kb
Host smart-ade37db5-0314-4050-af4c-1f43335d2bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102439172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2102439172
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1108718979
Short name T1082
Test name
Test status
Simulation time 615833373044 ps
CPU time 907.36 seconds
Started Jul 19 04:24:52 PM PDT 24
Finished Jul 19 04:40:28 PM PDT 24
Peak memory 225800 kb
Host smart-80e3c61e-004d-4022-8757-c5a40c1d9404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108718979 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1108718979
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.4229493146
Short name T1003
Test name
Test status
Simulation time 1285985646 ps
CPU time 1.41 seconds
Started Jul 19 04:24:52 PM PDT 24
Finished Jul 19 04:25:23 PM PDT 24
Peak memory 199804 kb
Host smart-b5da0bd9-f6ef-4bd2-88bb-838ff860ec0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229493146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.4229493146
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3939945165
Short name T1106
Test name
Test status
Simulation time 119763764955 ps
CPU time 78.54 seconds
Started Jul 19 04:24:49 PM PDT 24
Finished Jul 19 04:26:39 PM PDT 24
Peak memory 199884 kb
Host smart-82f398ec-a561-4f36-a7c0-521b3aa9fef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939945165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3939945165
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.358873904
Short name T627
Test name
Test status
Simulation time 36013250 ps
CPU time 0.59 seconds
Started Jul 19 04:25:09 PM PDT 24
Finished Jul 19 04:25:32 PM PDT 24
Peak memory 194796 kb
Host smart-3064a5d8-8ae0-4631-a6ee-cfcea37cbb56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358873904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.358873904
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.58312877
Short name T827
Test name
Test status
Simulation time 64420821575 ps
CPU time 16.85 seconds
Started Jul 19 04:25:06 PM PDT 24
Finished Jul 19 04:25:46 PM PDT 24
Peak memory 199892 kb
Host smart-5e33ae89-e2c4-425f-ab47-bd64a1749c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58312877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.58312877
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.408542818
Short name T1010
Test name
Test status
Simulation time 44938076000 ps
CPU time 38.98 seconds
Started Jul 19 04:25:09 PM PDT 24
Finished Jul 19 04:26:10 PM PDT 24
Peak memory 199884 kb
Host smart-70b27406-dc5d-4887-aa45-07efaa9227e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408542818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.408542818
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3400043023
Short name T749
Test name
Test status
Simulation time 96301725268 ps
CPU time 157.63 seconds
Started Jul 19 04:25:09 PM PDT 24
Finished Jul 19 04:28:09 PM PDT 24
Peak memory 199948 kb
Host smart-46e8f88f-a1d0-4ae7-9ef2-13e7246f714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400043023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3400043023
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.740441779
Short name T595
Test name
Test status
Simulation time 59022810984 ps
CPU time 109.23 seconds
Started Jul 19 04:25:12 PM PDT 24
Finished Jul 19 04:27:22 PM PDT 24
Peak memory 199964 kb
Host smart-f1f3aecc-f222-45e6-9312-f7c9ee2c924b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740441779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.740441779
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2475334893
Short name T700
Test name
Test status
Simulation time 161854812269 ps
CPU time 430.37 seconds
Started Jul 19 04:25:05 PM PDT 24
Finished Jul 19 04:32:39 PM PDT 24
Peak memory 199756 kb
Host smart-bdbe6f09-2812-4d3b-86be-c9a09e71894a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2475334893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2475334893
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1720213424
Short name T836
Test name
Test status
Simulation time 940794237 ps
CPU time 0.9 seconds
Started Jul 19 04:25:10 PM PDT 24
Finished Jul 19 04:25:32 PM PDT 24
Peak memory 195620 kb
Host smart-74aa5908-9b55-460b-b324-7dc72eca9fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720213424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1720213424
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2389740973
Short name T524
Test name
Test status
Simulation time 64093742186 ps
CPU time 99.45 seconds
Started Jul 19 04:25:09 PM PDT 24
Finished Jul 19 04:27:11 PM PDT 24
Peak memory 200028 kb
Host smart-fb71a3cc-5e34-4294-9c5e-ad23347ee22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389740973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2389740973
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2683267756
Short name T390
Test name
Test status
Simulation time 8308067483 ps
CPU time 91.09 seconds
Started Jul 19 04:25:09 PM PDT 24
Finished Jul 19 04:27:02 PM PDT 24
Peak memory 199908 kb
Host smart-f51d90e8-7b20-4697-a7c6-7629555537d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683267756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2683267756
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.90252344
Short name T359
Test name
Test status
Simulation time 6533653237 ps
CPU time 28.98 seconds
Started Jul 19 04:25:07 PM PDT 24
Finished Jul 19 04:25:58 PM PDT 24
Peak memory 198100 kb
Host smart-b4711697-bbb4-44fe-8357-b5ce1ac330fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90252344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.90252344
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.4087592387
Short name T454
Test name
Test status
Simulation time 42801867509 ps
CPU time 29.05 seconds
Started Jul 19 04:25:10 PM PDT 24
Finished Jul 19 04:26:01 PM PDT 24
Peak memory 200256 kb
Host smart-2f42dcbd-afef-40f7-b400-3c466557df29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087592387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.4087592387
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3706793912
Short name T512
Test name
Test status
Simulation time 4072489461 ps
CPU time 6.06 seconds
Started Jul 19 04:25:07 PM PDT 24
Finished Jul 19 04:25:36 PM PDT 24
Peak memory 196392 kb
Host smart-1574544c-0db4-4ada-97a4-2ba60694546c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706793912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3706793912
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.4081952963
Short name T725
Test name
Test status
Simulation time 332579870 ps
CPU time 1 seconds
Started Jul 19 04:25:06 PM PDT 24
Finished Jul 19 04:25:30 PM PDT 24
Peak memory 198188 kb
Host smart-d98c5990-e292-4fcf-a8a0-6fa69279c9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081952963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4081952963
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2113288880
Short name T280
Test name
Test status
Simulation time 260050316683 ps
CPU time 85.22 seconds
Started Jul 19 04:25:10 PM PDT 24
Finished Jul 19 04:26:58 PM PDT 24
Peak memory 208216 kb
Host smart-da145ba0-1b9c-47f1-b420-2c256f54ee7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113288880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2113288880
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.4039446587
Short name T987
Test name
Test status
Simulation time 33394506767 ps
CPU time 366.55 seconds
Started Jul 19 04:25:11 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 216580 kb
Host smart-174f2f61-1af8-4649-a517-b10eeb9a598e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039446587 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.4039446587
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3785306193
Short name T444
Test name
Test status
Simulation time 1314593459 ps
CPU time 2.38 seconds
Started Jul 19 04:25:16 PM PDT 24
Finished Jul 19 04:25:38 PM PDT 24
Peak memory 198232 kb
Host smart-f1e7207d-763c-4a38-8ed9-379cbec5867e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785306193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3785306193
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2089593220
Short name T705
Test name
Test status
Simulation time 283831763428 ps
CPU time 126.32 seconds
Started Jul 19 04:25:08 PM PDT 24
Finished Jul 19 04:27:37 PM PDT 24
Peak memory 199860 kb
Host smart-ec71e5a2-7c0f-420b-ae7e-924685f9a055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089593220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2089593220
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1895857836
Short name T860
Test name
Test status
Simulation time 14085709 ps
CPU time 0.6 seconds
Started Jul 19 04:25:38 PM PDT 24
Finished Jul 19 04:25:56 PM PDT 24
Peak memory 195408 kb
Host smart-7e4e7113-885d-46bd-b98c-8706130b299b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895857836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1895857836
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1744437828
Short name T1137
Test name
Test status
Simulation time 66555546149 ps
CPU time 30.42 seconds
Started Jul 19 04:25:38 PM PDT 24
Finished Jul 19 04:26:26 PM PDT 24
Peak memory 199948 kb
Host smart-15f49325-a1ff-4c84-bf10-b257507f32f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744437828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1744437828
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.365531927
Short name T374
Test name
Test status
Simulation time 145318808119 ps
CPU time 222.49 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:29:37 PM PDT 24
Peak memory 199896 kb
Host smart-e835d951-3d04-4174-9be5-6848ec7b3392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365531927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.365531927
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2577117462
Short name T42
Test name
Test status
Simulation time 236371998082 ps
CPU time 62.52 seconds
Started Jul 19 04:25:33 PM PDT 24
Finished Jul 19 04:26:53 PM PDT 24
Peak memory 199960 kb
Host smart-0668e2fd-a661-47e3-a5bd-d23beca02e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577117462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2577117462
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2598796461
Short name T421
Test name
Test status
Simulation time 23022703373 ps
CPU time 34.93 seconds
Started Jul 19 04:25:34 PM PDT 24
Finished Jul 19 04:26:27 PM PDT 24
Peak memory 197552 kb
Host smart-ec42f5bc-9d0e-4dbe-ba65-78eecf43b11e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598796461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2598796461
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.888292592
Short name T295
Test name
Test status
Simulation time 81802547747 ps
CPU time 151.2 seconds
Started Jul 19 04:25:32 PM PDT 24
Finished Jul 19 04:28:20 PM PDT 24
Peak memory 199944 kb
Host smart-8cd87db9-e512-47b8-91d5-b8fb76fb211c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888292592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.888292592
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3413733631
Short name T808
Test name
Test status
Simulation time 780161342 ps
CPU time 0.64 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:25:55 PM PDT 24
Peak memory 195292 kb
Host smart-43a1475c-f522-408d-984e-d236a248b84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413733631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3413733631
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1333073426
Short name T920
Test name
Test status
Simulation time 3033003396 ps
CPU time 4.44 seconds
Started Jul 19 04:25:38 PM PDT 24
Finished Jul 19 04:25:59 PM PDT 24
Peak memory 194548 kb
Host smart-df168cc1-e3f7-4812-b802-ff1bc6aaeae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333073426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1333073426
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3663367943
Short name T1086
Test name
Test status
Simulation time 2318119908 ps
CPU time 134.93 seconds
Started Jul 19 04:25:35 PM PDT 24
Finished Jul 19 04:28:08 PM PDT 24
Peak memory 199968 kb
Host smart-00e709e7-e7d9-4bcb-9a1d-54d051c1e705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663367943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3663367943
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2687204556
Short name T952
Test name
Test status
Simulation time 5091235938 ps
CPU time 10.03 seconds
Started Jul 19 04:25:40 PM PDT 24
Finished Jul 19 04:26:07 PM PDT 24
Peak memory 198032 kb
Host smart-d8626e98-03dd-41be-aa31-6a24f9163067
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2687204556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2687204556
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3904430130
Short name T697
Test name
Test status
Simulation time 11205056786 ps
CPU time 13.15 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:26:12 PM PDT 24
Peak memory 199892 kb
Host smart-179fe626-b2ff-40d4-94ba-b2c982955ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904430130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3904430130
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3654036644
Short name T660
Test name
Test status
Simulation time 41189403590 ps
CPU time 30.13 seconds
Started Jul 19 04:25:34 PM PDT 24
Finished Jul 19 04:26:21 PM PDT 24
Peak memory 196100 kb
Host smart-3a11f146-759d-47f4-947d-1768b83f8e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654036644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3654036644
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3187371177
Short name T981
Test name
Test status
Simulation time 569081006 ps
CPU time 0.97 seconds
Started Jul 19 04:25:34 PM PDT 24
Finished Jul 19 04:25:52 PM PDT 24
Peak memory 198476 kb
Host smart-a34ce5ff-80d0-41f3-a3fd-a06e0e055b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187371177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3187371177
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.815820256
Short name T308
Test name
Test status
Simulation time 330011632226 ps
CPU time 603.42 seconds
Started Jul 19 04:25:33 PM PDT 24
Finished Jul 19 04:35:53 PM PDT 24
Peak memory 200024 kb
Host smart-72f35dd7-c6df-4474-b1d9-d4e9fa457816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815820256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.815820256
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1174249496
Short name T50
Test name
Test status
Simulation time 36270306245 ps
CPU time 349.92 seconds
Started Jul 19 04:25:37 PM PDT 24
Finished Jul 19 04:31:45 PM PDT 24
Peak memory 216628 kb
Host smart-23f91bd9-a01d-4ba1-8878-5303384e6fab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174249496 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1174249496
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2147062029
Short name T1126
Test name
Test status
Simulation time 1260649028 ps
CPU time 3.27 seconds
Started Jul 19 04:25:37 PM PDT 24
Finished Jul 19 04:25:58 PM PDT 24
Peak memory 198504 kb
Host smart-39180d16-4fe3-4cec-9b49-d85aed365e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147062029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2147062029
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2276550052
Short name T665
Test name
Test status
Simulation time 22034345589 ps
CPU time 42.69 seconds
Started Jul 19 04:25:34 PM PDT 24
Finished Jul 19 04:26:34 PM PDT 24
Peak memory 199896 kb
Host smart-fab48ffb-1c0e-4775-960d-62acfd69a1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276550052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2276550052
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3784016037
Short name T217
Test name
Test status
Simulation time 21607667403 ps
CPU time 39.92 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:28:36 PM PDT 24
Peak memory 199884 kb
Host smart-f00b7f90-c6af-4268-9f83-f9682caa9412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784016037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3784016037
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.267497595
Short name T306
Test name
Test status
Simulation time 15522617090 ps
CPU time 19.85 seconds
Started Jul 19 04:27:53 PM PDT 24
Finished Jul 19 04:28:19 PM PDT 24
Peak memory 200000 kb
Host smart-913af0c0-fabe-4053-bcae-820ea74c6f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267497595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.267497595
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.295283925
Short name T1153
Test name
Test status
Simulation time 13678534220 ps
CPU time 20.18 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:28:18 PM PDT 24
Peak memory 199900 kb
Host smart-5d8a3ac8-5c10-4d74-82f6-d13e4a762e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295283925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.295283925
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.139103743
Short name T591
Test name
Test status
Simulation time 7723956364 ps
CPU time 21.01 seconds
Started Jul 19 04:27:47 PM PDT 24
Finished Jul 19 04:28:12 PM PDT 24
Peak memory 200268 kb
Host smart-608b61c4-2ed1-4797-ba09-fb29d9fd3266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139103743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.139103743
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1444349124
Short name T493
Test name
Test status
Simulation time 30462416107 ps
CPU time 34.91 seconds
Started Jul 19 04:27:52 PM PDT 24
Finished Jul 19 04:28:34 PM PDT 24
Peak memory 199992 kb
Host smart-b8c4d4fb-ddfb-43ed-8f52-85dcd955f03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444349124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1444349124
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.745859726
Short name T584
Test name
Test status
Simulation time 114988421511 ps
CPU time 549.29 seconds
Started Jul 19 04:27:46 PM PDT 24
Finished Jul 19 04:37:00 PM PDT 24
Peak memory 199988 kb
Host smart-770a0d4f-b9ee-4a3e-8619-c2e5025342ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745859726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.745859726
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.259712369
Short name T335
Test name
Test status
Simulation time 92186148631 ps
CPU time 89.83 seconds
Started Jul 19 04:27:55 PM PDT 24
Finished Jul 19 04:29:30 PM PDT 24
Peak memory 199908 kb
Host smart-8e069a9a-3742-4591-951d-3b166510a4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259712369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.259712369
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3856247694
Short name T1027
Test name
Test status
Simulation time 61021426690 ps
CPU time 52.99 seconds
Started Jul 19 04:27:47 PM PDT 24
Finished Jul 19 04:28:45 PM PDT 24
Peak memory 199900 kb
Host smart-f91f099a-d641-42cd-901a-429dedfc07db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856247694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3856247694
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1040423041
Short name T178
Test name
Test status
Simulation time 38981979670 ps
CPU time 22.93 seconds
Started Jul 19 04:27:51 PM PDT 24
Finished Jul 19 04:28:21 PM PDT 24
Peak memory 199660 kb
Host smart-ee94cfe0-2f35-49ef-9220-419fb7ecd3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040423041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1040423041
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3293156344
Short name T514
Test name
Test status
Simulation time 52680359834 ps
CPU time 68.45 seconds
Started Jul 19 04:27:49 PM PDT 24
Finished Jul 19 04:29:03 PM PDT 24
Peak memory 199892 kb
Host smart-010f00a1-ac39-49df-99f6-25d62ce48582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293156344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3293156344
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.817917080
Short name T1174
Test name
Test status
Simulation time 18397436 ps
CPU time 0.54 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:26:00 PM PDT 24
Peak memory 194308 kb
Host smart-f869d5e8-679d-4539-9b72-34988de33673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817917080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.817917080
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2140192691
Short name T1154
Test name
Test status
Simulation time 15741812151 ps
CPU time 30.46 seconds
Started Jul 19 04:25:34 PM PDT 24
Finished Jul 19 04:26:22 PM PDT 24
Peak memory 199992 kb
Host smart-19182585-126d-4e32-a3be-f4366b97ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140192691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2140192691
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1643121440
Short name T183
Test name
Test status
Simulation time 85819999475 ps
CPU time 71.95 seconds
Started Jul 19 04:25:37 PM PDT 24
Finished Jul 19 04:27:07 PM PDT 24
Peak memory 199904 kb
Host smart-aff74316-a2b2-4ae7-b949-0ab0e8568cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643121440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1643121440
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3490735299
Short name T310
Test name
Test status
Simulation time 85564268855 ps
CPU time 69.98 seconds
Started Jul 19 04:25:34 PM PDT 24
Finished Jul 19 04:27:01 PM PDT 24
Peak memory 200036 kb
Host smart-c40cd12d-e9e1-42aa-ab34-44ac5688f497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490735299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3490735299
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.994264910
Short name T432
Test name
Test status
Simulation time 38404558269 ps
CPU time 74.86 seconds
Started Jul 19 04:25:33 PM PDT 24
Finished Jul 19 04:27:04 PM PDT 24
Peak memory 199844 kb
Host smart-53e05bab-d7d8-4c08-8458-8acab3bff025
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994264910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.994264910
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1194783238
Short name T679
Test name
Test status
Simulation time 102198180029 ps
CPU time 540.43 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:34:55 PM PDT 24
Peak memory 199916 kb
Host smart-f8c185bf-8d6b-4e20-954b-6a1ca303986f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1194783238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1194783238
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1008446364
Short name T500
Test name
Test status
Simulation time 3532661290 ps
CPU time 2.75 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:25:57 PM PDT 24
Peak memory 199640 kb
Host smart-49912e25-32e4-4f3a-9793-29c2cdc33773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008446364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1008446364
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3522952375
Short name T626
Test name
Test status
Simulation time 115889003082 ps
CPU time 52.28 seconds
Started Jul 19 04:25:32 PM PDT 24
Finished Jul 19 04:26:41 PM PDT 24
Peak memory 200112 kb
Host smart-f7d47cb0-e87d-418c-9ef4-88ade16f93a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522952375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3522952375
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3913048145
Short name T422
Test name
Test status
Simulation time 22943961379 ps
CPU time 532.82 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:34:52 PM PDT 24
Peak memory 199876 kb
Host smart-8a447506-cb8c-4bb5-b588-639575441b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913048145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3913048145
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1252404611
Short name T351
Test name
Test status
Simulation time 4632773696 ps
CPU time 20.54 seconds
Started Jul 19 04:25:34 PM PDT 24
Finished Jul 19 04:26:11 PM PDT 24
Peak memory 198404 kb
Host smart-e8635b38-f175-49af-b9c1-51e84c6ad8e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252404611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1252404611
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2727027234
Short name T450
Test name
Test status
Simulation time 35534398101 ps
CPU time 68.39 seconds
Started Jul 19 04:25:34 PM PDT 24
Finished Jul 19 04:27:00 PM PDT 24
Peak memory 199980 kb
Host smart-b56ab771-c884-46b7-8d3e-1528a70a0038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727027234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2727027234
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3596782024
Short name T398
Test name
Test status
Simulation time 44717096780 ps
CPU time 30 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:26:29 PM PDT 24
Peak memory 195984 kb
Host smart-4baa6528-13f4-4c61-be53-11ee42092212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596782024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3596782024
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1095316923
Short name T870
Test name
Test status
Simulation time 268373280 ps
CPU time 1.73 seconds
Started Jul 19 04:25:35 PM PDT 24
Finished Jul 19 04:25:54 PM PDT 24
Peak memory 199036 kb
Host smart-8ad052c0-1854-4e52-9488-3c3fa75c661f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095316923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1095316923
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2452422656
Short name T299
Test name
Test status
Simulation time 516774290922 ps
CPU time 474.27 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:33:49 PM PDT 24
Peak memory 199920 kb
Host smart-2b63aece-ae2b-418c-84f9-70afeb559a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452422656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2452422656
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2529270507
Short name T731
Test name
Test status
Simulation time 7856397105 ps
CPU time 100.1 seconds
Started Jul 19 04:25:35 PM PDT 24
Finished Jul 19 04:27:33 PM PDT 24
Peak memory 215616 kb
Host smart-5eaf4f14-d7da-45c3-8f8d-602ed2c0ddd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529270507 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2529270507
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2135990300
Short name T364
Test name
Test status
Simulation time 769906290 ps
CPU time 1.42 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:25:56 PM PDT 24
Peak memory 198708 kb
Host smart-27966f13-ab06-4c1b-b1e9-9a620eb7d53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135990300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2135990300
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.909705859
Short name T573
Test name
Test status
Simulation time 34500948046 ps
CPU time 27.67 seconds
Started Jul 19 04:25:32 PM PDT 24
Finished Jul 19 04:26:17 PM PDT 24
Peak memory 200344 kb
Host smart-c01bd6a2-0dca-44f5-ac52-e6cf449f393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909705859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.909705859
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1654330421
Short name T109
Test name
Test status
Simulation time 110976036464 ps
CPU time 46.79 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:28:43 PM PDT 24
Peak memory 199872 kb
Host smart-512c5a34-189e-4ae5-b651-5909cdf9ea0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654330421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1654330421
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.397883992
Short name T401
Test name
Test status
Simulation time 28706547680 ps
CPU time 23.69 seconds
Started Jul 19 04:27:49 PM PDT 24
Finished Jul 19 04:28:18 PM PDT 24
Peak memory 199900 kb
Host smart-ec57e4c7-d8fb-4b4c-88e1-20e30bbce8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397883992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.397883992
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.10083989
Short name T355
Test name
Test status
Simulation time 101819010712 ps
CPU time 18.95 seconds
Started Jul 19 04:27:52 PM PDT 24
Finished Jul 19 04:28:18 PM PDT 24
Peak memory 200012 kb
Host smart-e0d64567-68e4-426f-8925-6ccd298d429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10083989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.10083989
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1197164176
Short name T765
Test name
Test status
Simulation time 27561785547 ps
CPU time 42.76 seconds
Started Jul 19 04:27:53 PM PDT 24
Finished Jul 19 04:28:42 PM PDT 24
Peak memory 200024 kb
Host smart-c20df944-d08e-4fa4-9f3a-ef48a7291958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197164176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1197164176
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1006787286
Short name T139
Test name
Test status
Simulation time 33875597686 ps
CPU time 11.07 seconds
Started Jul 19 04:27:51 PM PDT 24
Finished Jul 19 04:28:09 PM PDT 24
Peak memory 200044 kb
Host smart-1b05f4af-bf30-4462-ba5c-65b64abedd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006787286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1006787286
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3075457741
Short name T1068
Test name
Test status
Simulation time 58555677583 ps
CPU time 33.54 seconds
Started Jul 19 04:27:54 PM PDT 24
Finished Jul 19 04:28:34 PM PDT 24
Peak memory 200000 kb
Host smart-3bedf8a2-5a9a-40fb-bb29-df8b440bbeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075457741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3075457741
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1017991207
Short name T305
Test name
Test status
Simulation time 109216664297 ps
CPU time 172.28 seconds
Started Jul 19 04:27:56 PM PDT 24
Finished Jul 19 04:30:54 PM PDT 24
Peak memory 199960 kb
Host smart-1410fac4-ce93-4e99-95ec-55cb6c24c49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017991207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1017991207
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1630564274
Short name T557
Test name
Test status
Simulation time 42848564 ps
CPU time 0.57 seconds
Started Jul 19 04:25:35 PM PDT 24
Finished Jul 19 04:25:52 PM PDT 24
Peak memory 195344 kb
Host smart-f71d76a6-7654-49a0-8d6e-6a21e2ca3dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630564274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1630564274
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3453327644
Short name T134
Test name
Test status
Simulation time 118974262004 ps
CPU time 31.11 seconds
Started Jul 19 04:25:35 PM PDT 24
Finished Jul 19 04:26:24 PM PDT 24
Peak memory 199980 kb
Host smart-76d5b8d0-9f75-463b-b491-3c8d248d2bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453327644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3453327644
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1142087053
Short name T848
Test name
Test status
Simulation time 32743103855 ps
CPU time 27.06 seconds
Started Jul 19 04:25:34 PM PDT 24
Finished Jul 19 04:26:18 PM PDT 24
Peak memory 199876 kb
Host smart-c84229de-a709-4001-8bca-a6e91727eff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142087053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1142087053
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.808933224
Short name T676
Test name
Test status
Simulation time 119656267935 ps
CPU time 205.39 seconds
Started Jul 19 04:25:35 PM PDT 24
Finished Jul 19 04:29:19 PM PDT 24
Peak memory 199872 kb
Host smart-e8077596-8a50-446d-ac70-2ecb41e9a102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808933224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.808933224
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3074601109
Short name T792
Test name
Test status
Simulation time 4214123198 ps
CPU time 3.8 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:25:58 PM PDT 24
Peak memory 198868 kb
Host smart-2fedae72-e71e-411a-92ec-af38aa8e9421
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074601109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3074601109
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3762827496
Short name T371
Test name
Test status
Simulation time 104680755083 ps
CPU time 678.6 seconds
Started Jul 19 04:25:35 PM PDT 24
Finished Jul 19 04:37:11 PM PDT 24
Peak memory 199944 kb
Host smart-b294da09-4c92-4493-bcab-0fffde2d1a94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3762827496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3762827496
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.788542766
Short name T921
Test name
Test status
Simulation time 10404193551 ps
CPU time 6.63 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:26:01 PM PDT 24
Peak memory 199736 kb
Host smart-ed12a1f5-f12f-442a-a31d-8a6edebb5940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788542766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.788542766
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.4073929456
Short name T1117
Test name
Test status
Simulation time 49444457689 ps
CPU time 89.8 seconds
Started Jul 19 04:25:38 PM PDT 24
Finished Jul 19 04:27:25 PM PDT 24
Peak memory 199968 kb
Host smart-3c95e469-c04d-495b-9d48-a2e83a359717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073929456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.4073929456
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.4145379943
Short name T724
Test name
Test status
Simulation time 13524853673 ps
CPU time 820.11 seconds
Started Jul 19 04:25:33 PM PDT 24
Finished Jul 19 04:39:30 PM PDT 24
Peak memory 199944 kb
Host smart-e7fe900f-184e-41fb-b518-f335becd9fcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145379943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.4145379943
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.631047607
Short name T34
Test name
Test status
Simulation time 2538755784 ps
CPU time 4.57 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:26:04 PM PDT 24
Peak memory 198872 kb
Host smart-6810a7ef-e603-4177-8a96-be210d44c964
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631047607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.631047607
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2306688743
Short name T285
Test name
Test status
Simulation time 106750817997 ps
CPU time 40.98 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:26:35 PM PDT 24
Peak memory 199968 kb
Host smart-451805f0-ed40-4df0-8064-123cc563ff5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306688743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2306688743
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.780868676
Short name T542
Test name
Test status
Simulation time 29433834574 ps
CPU time 40.61 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:26:35 PM PDT 24
Peak memory 196028 kb
Host smart-4025dc13-5089-47f7-b5d3-b20b53814f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780868676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.780868676
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1921867490
Short name T1128
Test name
Test status
Simulation time 455546282 ps
CPU time 1.51 seconds
Started Jul 19 04:25:34 PM PDT 24
Finished Jul 19 04:25:52 PM PDT 24
Peak memory 198856 kb
Host smart-e73413a8-34dd-4af2-88a3-e45ead735804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921867490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1921867490
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3469859734
Short name T769
Test name
Test status
Simulation time 182698990314 ps
CPU time 631.41 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:36:26 PM PDT 24
Peak memory 199912 kb
Host smart-80f6c0a5-3890-4601-a3ec-410c45fe6d8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469859734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3469859734
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1322540374
Short name T56
Test name
Test status
Simulation time 46640619808 ps
CPU time 945.67 seconds
Started Jul 19 04:25:38 PM PDT 24
Finished Jul 19 04:41:41 PM PDT 24
Peak memory 226204 kb
Host smart-491d749a-fc5e-4a9f-8915-4b6e3e01a4b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322540374 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1322540374
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1825282339
Short name T881
Test name
Test status
Simulation time 7383086902 ps
CPU time 8.57 seconds
Started Jul 19 04:25:38 PM PDT 24
Finished Jul 19 04:26:04 PM PDT 24
Peak memory 199964 kb
Host smart-3c8137a0-b481-4255-afc8-928195df930d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825282339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1825282339
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3501986977
Short name T1088
Test name
Test status
Simulation time 23308621027 ps
CPU time 10.49 seconds
Started Jul 19 04:25:33 PM PDT 24
Finished Jul 19 04:26:00 PM PDT 24
Peak memory 197696 kb
Host smart-e1ec2da6-6270-44a0-98e3-c957418ab218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501986977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3501986977
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3516318573
Short name T274
Test name
Test status
Simulation time 15175132094 ps
CPU time 28.14 seconds
Started Jul 19 04:27:57 PM PDT 24
Finished Jul 19 04:28:30 PM PDT 24
Peak memory 200208 kb
Host smart-31cb55b5-61ab-4b27-97b4-abb7a3713549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516318573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3516318573
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3578690669
Short name T1101
Test name
Test status
Simulation time 70200991483 ps
CPU time 113.12 seconds
Started Jul 19 04:27:56 PM PDT 24
Finished Jul 19 04:29:55 PM PDT 24
Peak memory 199952 kb
Host smart-c520ff1c-8789-48a4-a329-da17b474e2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578690669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3578690669
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3331887901
Short name T868
Test name
Test status
Simulation time 13722756712 ps
CPU time 22.4 seconds
Started Jul 19 04:27:57 PM PDT 24
Finished Jul 19 04:28:25 PM PDT 24
Peak memory 199988 kb
Host smart-6e9a266e-609d-4d53-828c-0ec3fdf42e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331887901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3331887901
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2051731615
Short name T628
Test name
Test status
Simulation time 56631938429 ps
CPU time 136.83 seconds
Started Jul 19 04:28:04 PM PDT 24
Finished Jul 19 04:30:23 PM PDT 24
Peak memory 199992 kb
Host smart-afb6a6d3-3cc1-4c49-a30a-8c68f4eb0f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051731615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2051731615
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2243874982
Short name T185
Test name
Test status
Simulation time 25406528434 ps
CPU time 41.18 seconds
Started Jul 19 04:28:07 PM PDT 24
Finished Jul 19 04:28:51 PM PDT 24
Peak memory 199984 kb
Host smart-0d73cbc6-4f7d-4894-a10a-bea61e1d9163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243874982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2243874982
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1162730729
Short name T212
Test name
Test status
Simulation time 85157337472 ps
CPU time 193.54 seconds
Started Jul 19 04:28:11 PM PDT 24
Finished Jul 19 04:31:27 PM PDT 24
Peak memory 199916 kb
Host smart-13ef76db-91ce-40dc-b708-d7ac2f0f9edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162730729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1162730729
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2113738326
Short name T958
Test name
Test status
Simulation time 141707641738 ps
CPU time 196.05 seconds
Started Jul 19 04:27:55 PM PDT 24
Finished Jul 19 04:31:17 PM PDT 24
Peak memory 199976 kb
Host smart-e9309778-cb28-4424-8a4e-32b9b00db2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113738326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2113738326
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1417038001
Short name T1064
Test name
Test status
Simulation time 41891217 ps
CPU time 0.56 seconds
Started Jul 19 04:25:56 PM PDT 24
Finished Jul 19 04:26:12 PM PDT 24
Peak memory 195360 kb
Host smart-18dbe036-e87c-426b-b385-8ec85e8794a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417038001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1417038001
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1136343348
Short name T1164
Test name
Test status
Simulation time 64026351931 ps
CPU time 136.31 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:28:16 PM PDT 24
Peak memory 199956 kb
Host smart-bed61cdd-c178-4c1e-b9ed-f28887217da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136343348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1136343348
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.165682413
Short name T309
Test name
Test status
Simulation time 47080015119 ps
CPU time 67.64 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:27:02 PM PDT 24
Peak memory 199904 kb
Host smart-3b38e414-56ed-4bbd-b789-313e6556e472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165682413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.165682413
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2433250065
Short name T900
Test name
Test status
Simulation time 63511146450 ps
CPU time 141.91 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:28:16 PM PDT 24
Peak memory 199912 kb
Host smart-6338b4a4-326b-420e-8340-a2f3175464bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433250065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2433250065
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.799881619
Short name T651
Test name
Test status
Simulation time 17589524680 ps
CPU time 4.59 seconds
Started Jul 19 04:25:34 PM PDT 24
Finished Jul 19 04:25:56 PM PDT 24
Peak memory 199916 kb
Host smart-bce5ac31-ee52-468e-b1ed-ed7a9365b50d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799881619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.799881619
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2589275377
Short name T608
Test name
Test status
Simulation time 69315069781 ps
CPU time 190.87 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:29:14 PM PDT 24
Peak memory 199924 kb
Host smart-29f75649-ccd3-418f-868b-be0d03fe32b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2589275377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2589275377
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2506695319
Short name T543
Test name
Test status
Simulation time 2960972088 ps
CPU time 11.96 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:26:16 PM PDT 24
Peak memory 198672 kb
Host smart-cf032dd0-3dcc-47f8-a664-e3df4113383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506695319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2506695319
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.140733615
Short name T544
Test name
Test status
Simulation time 123785318517 ps
CPU time 147 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:28:27 PM PDT 24
Peak memory 199964 kb
Host smart-a31fdfec-8335-4d95-90bd-86150edfc19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140733615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.140733615
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1743296508
Short name T914
Test name
Test status
Simulation time 29242303810 ps
CPU time 309.14 seconds
Started Jul 19 04:25:45 PM PDT 24
Finished Jul 19 04:31:10 PM PDT 24
Peak memory 199948 kb
Host smart-bbf14e46-8d2b-41f2-b595-98ede0602faf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743296508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1743296508
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.863484853
Short name T521
Test name
Test status
Simulation time 7145526039 ps
CPU time 15.28 seconds
Started Jul 19 04:25:37 PM PDT 24
Finished Jul 19 04:26:10 PM PDT 24
Peak memory 198500 kb
Host smart-25acd3aa-e6e4-4a2a-b691-e29a4165398a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=863484853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.863484853
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3988659835
Short name T275
Test name
Test status
Simulation time 85763053343 ps
CPU time 147.43 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:28:31 PM PDT 24
Peak memory 199900 kb
Host smart-f95a46f9-1444-4ab6-92c2-93d7573e06cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988659835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3988659835
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1119180611
Short name T489
Test name
Test status
Simulation time 543106473 ps
CPU time 1.47 seconds
Started Jul 19 04:25:43 PM PDT 24
Finished Jul 19 04:26:00 PM PDT 24
Peak memory 195464 kb
Host smart-b65db205-368d-4ad5-a3ae-308bf03daf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119180611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1119180611
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1965562353
Short name T569
Test name
Test status
Simulation time 690572942 ps
CPU time 2.01 seconds
Started Jul 19 04:25:33 PM PDT 24
Finished Jul 19 04:25:52 PM PDT 24
Peak memory 198612 kb
Host smart-b6b8fd05-f797-4681-831a-055621a54baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965562353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1965562353
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.348021045
Short name T530
Test name
Test status
Simulation time 186268002660 ps
CPU time 748.11 seconds
Started Jul 19 04:25:43 PM PDT 24
Finished Jul 19 04:38:27 PM PDT 24
Peak memory 216552 kb
Host smart-d93b9729-0c28-4493-9309-cb15c305948b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348021045 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.348021045
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.804733354
Short name T354
Test name
Test status
Simulation time 600817719 ps
CPU time 1.89 seconds
Started Jul 19 04:25:45 PM PDT 24
Finished Jul 19 04:26:03 PM PDT 24
Peak memory 198368 kb
Host smart-45240f6d-ed6c-4766-982d-44fde0c9c5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804733354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.804733354
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2487910933
Short name T124
Test name
Test status
Simulation time 4931219758 ps
CPU time 7.61 seconds
Started Jul 19 04:25:37 PM PDT 24
Finished Jul 19 04:26:02 PM PDT 24
Peak memory 196708 kb
Host smart-5b875cd6-a2f6-4c6a-be89-3625d22ca220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487910933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2487910933
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1529884558
Short name T1130
Test name
Test status
Simulation time 98691959338 ps
CPU time 135.39 seconds
Started Jul 19 04:28:05 PM PDT 24
Finished Jul 19 04:30:23 PM PDT 24
Peak memory 199920 kb
Host smart-1e9a080e-c060-4cb8-ac72-fb56043269a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529884558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1529884558
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2511942658
Short name T727
Test name
Test status
Simulation time 113401909381 ps
CPU time 121.47 seconds
Started Jul 19 04:27:55 PM PDT 24
Finished Jul 19 04:30:03 PM PDT 24
Peak memory 199984 kb
Host smart-ed83aafc-3bfb-4fb3-bb95-da54bc42ae76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511942658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2511942658
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1111766305
Short name T228
Test name
Test status
Simulation time 50969207342 ps
CPU time 62.18 seconds
Started Jul 19 04:28:05 PM PDT 24
Finished Jul 19 04:29:09 PM PDT 24
Peak memory 199720 kb
Host smart-4ecb570a-0755-4481-b254-5262e22b453a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111766305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1111766305
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.515237230
Short name T553
Test name
Test status
Simulation time 34698260297 ps
CPU time 16.15 seconds
Started Jul 19 04:27:56 PM PDT 24
Finished Jul 19 04:28:18 PM PDT 24
Peak memory 200072 kb
Host smart-45b915c5-dd05-4ca3-9647-907705f79ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515237230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.515237230
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.4233109436
Short name T730
Test name
Test status
Simulation time 13953431996 ps
CPU time 21.26 seconds
Started Jul 19 04:27:55 PM PDT 24
Finished Jul 19 04:28:22 PM PDT 24
Peak memory 199932 kb
Host smart-73dff9f3-8c65-44ad-978e-7374f4bfe08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233109436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.4233109436
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2313132723
Short name T40
Test name
Test status
Simulation time 70153161346 ps
CPU time 29.88 seconds
Started Jul 19 04:28:11 PM PDT 24
Finished Jul 19 04:28:44 PM PDT 24
Peak memory 199940 kb
Host smart-9fd7f569-9947-4fd9-a680-67467976aa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313132723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2313132723
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2374268734
Short name T175
Test name
Test status
Simulation time 161103584935 ps
CPU time 17.59 seconds
Started Jul 19 04:27:55 PM PDT 24
Finished Jul 19 04:28:18 PM PDT 24
Peak memory 199936 kb
Host smart-e42028f6-9e7a-4b8a-a2d5-8e717b3d9e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374268734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2374268734
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.595692285
Short name T824
Test name
Test status
Simulation time 98647446032 ps
CPU time 168.29 seconds
Started Jul 19 04:28:03 PM PDT 24
Finished Jul 19 04:30:53 PM PDT 24
Peak memory 199992 kb
Host smart-f4221b32-880f-43ac-9731-5791ab20778a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595692285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.595692285
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2952179646
Short name T819
Test name
Test status
Simulation time 27596358831 ps
CPU time 15.66 seconds
Started Jul 19 04:28:02 PM PDT 24
Finished Jul 19 04:28:20 PM PDT 24
Peak memory 199992 kb
Host smart-95aecf95-f69d-46b2-926e-208d50f7778b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952179646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2952179646
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1093767286
Short name T930
Test name
Test status
Simulation time 96884600009 ps
CPU time 74.02 seconds
Started Jul 19 04:28:00 PM PDT 24
Finished Jul 19 04:29:17 PM PDT 24
Peak memory 199956 kb
Host smart-8e98aaac-11f0-44bb-83fa-118869588835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093767286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1093767286
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3315662424
Short name T599
Test name
Test status
Simulation time 12918677 ps
CPU time 0.55 seconds
Started Jul 19 04:25:42 PM PDT 24
Finished Jul 19 04:25:59 PM PDT 24
Peak memory 195456 kb
Host smart-898b64e2-8a9b-4570-bd1b-545bc5aacc93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315662424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3315662424
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2568436108
Short name T176
Test name
Test status
Simulation time 134674731316 ps
CPU time 32.62 seconds
Started Jul 19 04:25:55 PM PDT 24
Finished Jul 19 04:26:43 PM PDT 24
Peak memory 199956 kb
Host smart-e51f2eb5-4538-4967-a570-9ac061e41ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568436108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2568436108
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3862555845
Short name T1124
Test name
Test status
Simulation time 163412803147 ps
CPU time 53.09 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:26:53 PM PDT 24
Peak memory 199872 kb
Host smart-0049caa4-a723-4c25-b829-f3a6857fdc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862555845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3862555845
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.680135542
Short name T1098
Test name
Test status
Simulation time 206237809041 ps
CPU time 91.93 seconds
Started Jul 19 04:25:46 PM PDT 24
Finished Jul 19 04:27:35 PM PDT 24
Peak memory 200020 kb
Host smart-adf84a1f-e903-4a39-bc20-6dd981ed4f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680135542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.680135542
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3131391137
Short name T1020
Test name
Test status
Simulation time 59984977915 ps
CPU time 101.04 seconds
Started Jul 19 04:25:48 PM PDT 24
Finished Jul 19 04:27:45 PM PDT 24
Peak memory 199884 kb
Host smart-6bbc36e6-f990-4ec0-aa67-c65ca22a6ced
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131391137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3131391137
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1925303920
Short name T744
Test name
Test status
Simulation time 79741681086 ps
CPU time 546.74 seconds
Started Jul 19 04:25:46 PM PDT 24
Finished Jul 19 04:35:08 PM PDT 24
Peak memory 199908 kb
Host smart-a44dc794-5e27-46e7-92e8-b95cec3cab9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1925303920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1925303920
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3053481167
Short name T539
Test name
Test status
Simulation time 6906650465 ps
CPU time 7.32 seconds
Started Jul 19 04:25:54 PM PDT 24
Finished Jul 19 04:26:17 PM PDT 24
Peak memory 199464 kb
Host smart-e89f59bb-ea50-4616-9979-c80caa9cb367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053481167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3053481167
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.26519045
Short name T257
Test name
Test status
Simulation time 170687094104 ps
CPU time 99.82 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:27:43 PM PDT 24
Peak memory 200028 kb
Host smart-71176f57-b4f2-4a95-968a-819f1d8383a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26519045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.26519045
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.198983119
Short name T582
Test name
Test status
Simulation time 10830819840 ps
CPU time 134.55 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:28:14 PM PDT 24
Peak memory 199968 kb
Host smart-cae746e5-f705-410d-8bd5-5ecaeec4cac8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=198983119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.198983119
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1485567600
Short name T338
Test name
Test status
Simulation time 5646355763 ps
CPU time 10.96 seconds
Started Jul 19 04:25:45 PM PDT 24
Finished Jul 19 04:26:12 PM PDT 24
Peak memory 198136 kb
Host smart-22ad2913-b44e-407f-bf42-0bd6bb913e93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485567600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1485567600
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1579826617
Short name T956
Test name
Test status
Simulation time 125568692303 ps
CPU time 40.65 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:26:40 PM PDT 24
Peak memory 199956 kb
Host smart-a8bfa7c7-8bc4-4fc3-83ba-3e91c3553c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579826617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1579826617
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1342069332
Short name T510
Test name
Test status
Simulation time 45773206798 ps
CPU time 66.74 seconds
Started Jul 19 04:25:45 PM PDT 24
Finished Jul 19 04:27:07 PM PDT 24
Peak memory 195908 kb
Host smart-b34e9ef5-422e-479a-954a-c60a36a87884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342069332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1342069332
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2585326232
Short name T1077
Test name
Test status
Simulation time 298119052 ps
CPU time 1.42 seconds
Started Jul 19 04:25:51 PM PDT 24
Finished Jul 19 04:26:08 PM PDT 24
Peak memory 198824 kb
Host smart-f5f9fdc2-5576-4463-aee6-e8fa4c83c76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585326232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2585326232
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.4132368435
Short name T944
Test name
Test status
Simulation time 25653002421 ps
CPU time 373.83 seconds
Started Jul 19 04:26:03 PM PDT 24
Finished Jul 19 04:32:32 PM PDT 24
Peak memory 216456 kb
Host smart-3f557f6f-2f0d-4661-8639-acc870ba460a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132368435 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.4132368435
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1700327830
Short name T1144
Test name
Test status
Simulation time 1401553300 ps
CPU time 2.05 seconds
Started Jul 19 04:25:56 PM PDT 24
Finished Jul 19 04:26:14 PM PDT 24
Peak memory 199112 kb
Host smart-0eb609f5-2e09-4feb-825d-b06c348d8ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700327830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1700327830
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.314946921
Short name T1058
Test name
Test status
Simulation time 78531538685 ps
CPU time 27.87 seconds
Started Jul 19 04:25:43 PM PDT 24
Finished Jul 19 04:26:27 PM PDT 24
Peak memory 199820 kb
Host smart-7ab54f7a-bb42-41d0-8de3-b53fa1112ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314946921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.314946921
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1919770562
Short name T761
Test name
Test status
Simulation time 79460150474 ps
CPU time 41.68 seconds
Started Jul 19 04:27:57 PM PDT 24
Finished Jul 19 04:28:44 PM PDT 24
Peak memory 199984 kb
Host smart-dff774b5-96f1-4d2b-aa00-a4644a549461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919770562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1919770562
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3875837033
Short name T1113
Test name
Test status
Simulation time 109558214581 ps
CPU time 45.69 seconds
Started Jul 19 04:28:04 PM PDT 24
Finished Jul 19 04:28:52 PM PDT 24
Peak memory 199716 kb
Host smart-479bfaee-32af-43eb-9aef-04a3931efff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875837033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3875837033
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3186616355
Short name T594
Test name
Test status
Simulation time 58253497636 ps
CPU time 30.59 seconds
Started Jul 19 04:28:04 PM PDT 24
Finished Jul 19 04:28:37 PM PDT 24
Peak memory 199948 kb
Host smart-c891c7c1-ac39-48de-b9d8-d1854830010a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186616355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3186616355
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1933507123
Short name T884
Test name
Test status
Simulation time 22702468144 ps
CPU time 12.96 seconds
Started Jul 19 04:27:57 PM PDT 24
Finished Jul 19 04:28:15 PM PDT 24
Peak memory 200020 kb
Host smart-6d4a2aca-74c4-4627-a04b-e2da07c0f5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933507123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1933507123
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1125169593
Short name T163
Test name
Test status
Simulation time 10804398052 ps
CPU time 15.28 seconds
Started Jul 19 04:28:04 PM PDT 24
Finished Jul 19 04:28:21 PM PDT 24
Peak memory 199676 kb
Host smart-4bc91458-8888-45d5-af89-e420cf240b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125169593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1125169593
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2066136985
Short name T522
Test name
Test status
Simulation time 233834120321 ps
CPU time 186.04 seconds
Started Jul 19 04:27:57 PM PDT 24
Finished Jul 19 04:31:08 PM PDT 24
Peak memory 199472 kb
Host smart-8cd9f035-3333-4999-b482-24a24e790dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066136985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2066136985
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2141013427
Short name T777
Test name
Test status
Simulation time 143980825334 ps
CPU time 59.66 seconds
Started Jul 19 04:27:57 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 199476 kb
Host smart-9e1f48b9-bbcf-4870-914e-1a5e583c4319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141013427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2141013427
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.306166107
Short name T192
Test name
Test status
Simulation time 263072130247 ps
CPU time 32.03 seconds
Started Jul 19 04:27:57 PM PDT 24
Finished Jul 19 04:28:34 PM PDT 24
Peak memory 199904 kb
Host smart-e10eb0e5-3a67-4c25-8b05-610a48e0d12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306166107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.306166107
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.85454039
Short name T33
Test name
Test status
Simulation time 63723354405 ps
CPU time 46.23 seconds
Started Jul 19 04:25:46 PM PDT 24
Finished Jul 19 04:26:49 PM PDT 24
Peak memory 199960 kb
Host smart-edd5f118-a40a-4be1-81a8-1cdbea21031c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85454039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.85454039
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1140006968
Short name T3
Test name
Test status
Simulation time 12121416140 ps
CPU time 18.03 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:26:21 PM PDT 24
Peak memory 199924 kb
Host smart-81d45e89-531f-464c-97e3-3ea57c129dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140006968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1140006968
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3951995475
Short name T666
Test name
Test status
Simulation time 40407044256 ps
CPU time 17.89 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:26:21 PM PDT 24
Peak memory 199928 kb
Host smart-100e6680-c737-44d5-8bff-afccf9069254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951995475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3951995475
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2671357408
Short name T999
Test name
Test status
Simulation time 65878697672 ps
CPU time 107.5 seconds
Started Jul 19 04:25:56 PM PDT 24
Finished Jul 19 04:27:58 PM PDT 24
Peak memory 199860 kb
Host smart-d11febb8-86d2-49b4-90ca-45a1616db872
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671357408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2671357408
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1108437313
Short name T611
Test name
Test status
Simulation time 48844819685 ps
CPU time 443.27 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:33:23 PM PDT 24
Peak memory 199916 kb
Host smart-dc1bce62-f0db-410c-afb5-ed10e3ef43d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108437313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1108437313
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3069637978
Short name T74
Test name
Test status
Simulation time 3583590900 ps
CPU time 7.3 seconds
Started Jul 19 04:25:50 PM PDT 24
Finished Jul 19 04:26:14 PM PDT 24
Peak memory 199252 kb
Host smart-f4381b40-471a-4f54-b014-7d2ae8fa4fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069637978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3069637978
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1922329488
Short name T319
Test name
Test status
Simulation time 62311557288 ps
CPU time 86.06 seconds
Started Jul 19 04:26:17 PM PDT 24
Finished Jul 19 04:27:56 PM PDT 24
Peak memory 208260 kb
Host smart-4c9b7afc-8628-4872-90a9-8a95452b26c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922329488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1922329488
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2924968923
Short name T484
Test name
Test status
Simulation time 7605319014 ps
CPU time 164.99 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:28:49 PM PDT 24
Peak memory 199932 kb
Host smart-c3935cae-6e42-4005-9655-3042d22678ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924968923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2924968923
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1464142188
Short name T562
Test name
Test status
Simulation time 2540638055 ps
CPU time 6.62 seconds
Started Jul 19 04:25:45 PM PDT 24
Finished Jul 19 04:26:08 PM PDT 24
Peak memory 198936 kb
Host smart-3a23098b-a508-4e6e-8c88-6e90e9838b77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464142188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1464142188
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.654354173
Short name T26
Test name
Test status
Simulation time 50920033604 ps
CPU time 72.65 seconds
Started Jul 19 04:25:42 PM PDT 24
Finished Jul 19 04:27:11 PM PDT 24
Peak memory 200236 kb
Host smart-b0aa7312-da7c-4974-87a7-166e90daf449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654354173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.654354173
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3622649135
Short name T995
Test name
Test status
Simulation time 6932345567 ps
CPU time 9.75 seconds
Started Jul 19 04:25:46 PM PDT 24
Finished Jul 19 04:26:12 PM PDT 24
Peak memory 196116 kb
Host smart-8e24cee1-0613-4079-a1b2-3ceb78aec1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622649135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3622649135
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3323337621
Short name T1013
Test name
Test status
Simulation time 449307481 ps
CPU time 1.22 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:26:05 PM PDT 24
Peak memory 198328 kb
Host smart-9b8dbc6d-683d-4e44-9b98-c7f166855883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323337621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3323337621
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1779264071
Short name T179
Test name
Test status
Simulation time 154146473464 ps
CPU time 317.28 seconds
Started Jul 19 04:25:53 PM PDT 24
Finished Jul 19 04:31:26 PM PDT 24
Peak memory 216460 kb
Host smart-fa13f318-7535-404a-8302-36380bc27d83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779264071 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1779264071
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3982372220
Short name T75
Test name
Test status
Simulation time 6718137465 ps
CPU time 17.98 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:26:17 PM PDT 24
Peak memory 199372 kb
Host smart-85528be3-1a9d-47c0-8b64-fb93d6b84861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982372220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3982372220
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2894627317
Short name T1095
Test name
Test status
Simulation time 22099802338 ps
CPU time 13.62 seconds
Started Jul 19 04:25:51 PM PDT 24
Finished Jul 19 04:26:21 PM PDT 24
Peak memory 197360 kb
Host smart-fbc8f661-d1bb-4ce4-a2c8-37111f96f092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894627317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2894627317
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.242153936
Short name T561
Test name
Test status
Simulation time 5812105854 ps
CPU time 10.73 seconds
Started Jul 19 04:28:04 PM PDT 24
Finished Jul 19 04:28:17 PM PDT 24
Peak memory 199964 kb
Host smart-746b5262-316c-486e-b2e7-0e7c93c601d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242153936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.242153936
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3935630066
Short name T1107
Test name
Test status
Simulation time 34928721001 ps
CPU time 16.77 seconds
Started Jul 19 04:28:03 PM PDT 24
Finished Jul 19 04:28:22 PM PDT 24
Peak memory 199972 kb
Host smart-3f6e5c80-b043-4e6d-955f-095be25097a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935630066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3935630066
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1159688551
Short name T1097
Test name
Test status
Simulation time 8295629493 ps
CPU time 4.96 seconds
Started Jul 19 04:27:55 PM PDT 24
Finished Jul 19 04:28:06 PM PDT 24
Peak memory 199932 kb
Host smart-9708c1c9-068f-42be-aa6a-1f954496cd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159688551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1159688551
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3518757892
Short name T1006
Test name
Test status
Simulation time 194969947892 ps
CPU time 72.31 seconds
Started Jul 19 04:28:12 PM PDT 24
Finished Jul 19 04:29:26 PM PDT 24
Peak memory 199996 kb
Host smart-ea1e850c-6e53-4cb2-af0f-54e53ee708b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518757892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3518757892
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2172988315
Short name T1120
Test name
Test status
Simulation time 20435525884 ps
CPU time 10.83 seconds
Started Jul 19 04:28:12 PM PDT 24
Finished Jul 19 04:28:25 PM PDT 24
Peak memory 199996 kb
Host smart-9e9a3865-1dae-43b4-a27c-440af4ad1589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172988315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2172988315
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3227457701
Short name T106
Test name
Test status
Simulation time 202458836891 ps
CPU time 366.98 seconds
Started Jul 19 04:28:12 PM PDT 24
Finished Jul 19 04:34:21 PM PDT 24
Peak memory 199940 kb
Host smart-99f5bb71-e227-41f1-90d1-a067975d89fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227457701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3227457701
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1847876875
Short name T1139
Test name
Test status
Simulation time 13104737539 ps
CPU time 22.16 seconds
Started Jul 19 04:27:57 PM PDT 24
Finished Jul 19 04:28:24 PM PDT 24
Peak memory 199916 kb
Host smart-6e58858a-9357-4553-8329-1464a0d406f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847876875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1847876875
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.806112093
Short name T483
Test name
Test status
Simulation time 49451534609 ps
CPU time 20.35 seconds
Started Jul 19 04:28:05 PM PDT 24
Finished Jul 19 04:28:28 PM PDT 24
Peak memory 199676 kb
Host smart-4cc8605f-28f2-4568-9d04-27f5ab7af8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806112093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.806112093
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3624963235
Short name T779
Test name
Test status
Simulation time 21198731549 ps
CPU time 37.49 seconds
Started Jul 19 04:27:57 PM PDT 24
Finished Jul 19 04:28:40 PM PDT 24
Peak memory 199928 kb
Host smart-19ce0b34-5f31-4255-822e-ecc1d8aaa6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624963235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3624963235
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3355785394
Short name T415
Test name
Test status
Simulation time 25568242 ps
CPU time 0.56 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:26:01 PM PDT 24
Peak memory 195348 kb
Host smart-c3adcec5-188b-42bd-951d-d4f9a1545b6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355785394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3355785394
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.393306439
Short name T923
Test name
Test status
Simulation time 55948619950 ps
CPU time 21.45 seconds
Started Jul 19 04:25:46 PM PDT 24
Finished Jul 19 04:26:23 PM PDT 24
Peak memory 199912 kb
Host smart-634aa775-2eec-4c3b-a536-35cc93048b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393306439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.393306439
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3666246635
Short name T949
Test name
Test status
Simulation time 25544685572 ps
CPU time 10.89 seconds
Started Jul 19 04:25:46 PM PDT 24
Finished Jul 19 04:26:14 PM PDT 24
Peak memory 199880 kb
Host smart-78b5a477-c456-4335-b6ac-6abcb1763e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666246635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3666246635
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1392410890
Short name T4
Test name
Test status
Simulation time 94715394189 ps
CPU time 137.42 seconds
Started Jul 19 04:25:50 PM PDT 24
Finished Jul 19 04:28:24 PM PDT 24
Peak memory 199936 kb
Host smart-9860ddcc-70ef-4a5c-8c4d-7ff36a8c9208
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392410890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1392410890
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3461055588
Short name T966
Test name
Test status
Simulation time 31168851619 ps
CPU time 160.99 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:28:44 PM PDT 24
Peak memory 199876 kb
Host smart-6109dd2b-e0c8-41a3-ac3e-7d006ddd712f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461055588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3461055588
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3837288353
Short name T341
Test name
Test status
Simulation time 9999926068 ps
CPU time 20.32 seconds
Started Jul 19 04:25:46 PM PDT 24
Finished Jul 19 04:26:22 PM PDT 24
Peak memory 199960 kb
Host smart-20b0dafd-babf-4404-b5e2-18c3d003eb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837288353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3837288353
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.354405178
Short name T1045
Test name
Test status
Simulation time 96378382013 ps
CPU time 81.28 seconds
Started Jul 19 04:25:45 PM PDT 24
Finished Jul 19 04:27:22 PM PDT 24
Peak memory 200096 kb
Host smart-c7489394-9c60-4de5-8d3c-38872dd592bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354405178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.354405178
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3307481464
Short name T927
Test name
Test status
Simulation time 12569662197 ps
CPU time 780.49 seconds
Started Jul 19 04:25:48 PM PDT 24
Finished Jul 19 04:39:05 PM PDT 24
Peak memory 199964 kb
Host smart-aea4b27c-7390-41aa-bc5b-57ae64eda078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3307481464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3307481464
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3364807105
Short name T1011
Test name
Test status
Simulation time 5982718965 ps
CPU time 10.25 seconds
Started Jul 19 04:25:46 PM PDT 24
Finished Jul 19 04:26:13 PM PDT 24
Peak memory 199340 kb
Host smart-d0209244-ac19-4750-bc04-0c003b99ae9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364807105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3364807105
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2764953793
Short name T1060
Test name
Test status
Simulation time 110320268673 ps
CPU time 199.25 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:29:23 PM PDT 24
Peak memory 199916 kb
Host smart-af77adac-de59-4bc0-a266-b06ccf0daf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764953793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2764953793
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.536347
Short name T303
Test name
Test status
Simulation time 1872197570 ps
CPU time 1.43 seconds
Started Jul 19 04:25:48 PM PDT 24
Finished Jul 19 04:26:06 PM PDT 24
Peak memory 195464 kb
Host smart-55e56692-c34a-42c8-8f68-5acdef1e06e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.536347
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.865319118
Short name T45
Test name
Test status
Simulation time 254193212 ps
CPU time 1.25 seconds
Started Jul 19 04:25:44 PM PDT 24
Finished Jul 19 04:26:01 PM PDT 24
Peak memory 198248 kb
Host smart-cce52196-f3f6-4a32-a7c2-6b2ddab5d17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865319118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.865319118
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1265974863
Short name T478
Test name
Test status
Simulation time 23572786561 ps
CPU time 363.41 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:32:07 PM PDT 24
Peak memory 199860 kb
Host smart-548a3803-dc7c-4a0c-8f7f-b76d14ccc081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265974863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1265974863
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2587553179
Short name T27
Test name
Test status
Simulation time 120080671247 ps
CPU time 694.66 seconds
Started Jul 19 04:25:50 PM PDT 24
Finished Jul 19 04:37:41 PM PDT 24
Peak memory 216384 kb
Host smart-6998e4ef-f3c9-42a8-b3f3-209d81bfe318
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587553179 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2587553179
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2051630453
Short name T974
Test name
Test status
Simulation time 1412309409 ps
CPU time 2.08 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:26:06 PM PDT 24
Peak memory 198368 kb
Host smart-f5d70679-2fca-4192-a53e-5a3363a5d99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051630453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2051630453
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1061560180
Short name T1170
Test name
Test status
Simulation time 38065232182 ps
CPU time 42.88 seconds
Started Jul 19 04:25:43 PM PDT 24
Finished Jul 19 04:26:42 PM PDT 24
Peak memory 199928 kb
Host smart-3584e141-6c7f-4277-b62f-9d168067396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061560180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1061560180
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.4220151010
Short name T203
Test name
Test status
Simulation time 22095106886 ps
CPU time 16.01 seconds
Started Jul 19 04:28:04 PM PDT 24
Finished Jul 19 04:28:22 PM PDT 24
Peak memory 199460 kb
Host smart-a3d10ab8-d829-46cd-b429-040bea46f5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220151010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.4220151010
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.67247751
Short name T200
Test name
Test status
Simulation time 72279008985 ps
CPU time 57.47 seconds
Started Jul 19 04:28:01 PM PDT 24
Finished Jul 19 04:29:01 PM PDT 24
Peak memory 200340 kb
Host smart-658ab0b5-b55c-4c84-bd09-c13df35ef939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67247751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.67247751
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.913636076
Short name T186
Test name
Test status
Simulation time 7588837367 ps
CPU time 12.02 seconds
Started Jul 19 04:28:11 PM PDT 24
Finished Jul 19 04:28:25 PM PDT 24
Peak memory 199268 kb
Host smart-5e1d2b10-8f61-4454-b7e4-e4c0d5a5df4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913636076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.913636076
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3220560446
Short name T985
Test name
Test status
Simulation time 118518375155 ps
CPU time 180.54 seconds
Started Jul 19 04:27:57 PM PDT 24
Finished Jul 19 04:31:03 PM PDT 24
Peak memory 199840 kb
Host smart-d66bb782-74e5-49d0-bf0c-0f94781a81b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220560446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3220560446
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3122746977
Short name T924
Test name
Test status
Simulation time 85572911880 ps
CPU time 112.46 seconds
Started Jul 19 04:28:05 PM PDT 24
Finished Jul 19 04:30:00 PM PDT 24
Peak memory 199580 kb
Host smart-c673a896-0a86-4d26-bd67-14af4b48728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122746977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3122746977
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.683627349
Short name T1085
Test name
Test status
Simulation time 100265690895 ps
CPU time 121.94 seconds
Started Jul 19 04:27:57 PM PDT 24
Finished Jul 19 04:30:04 PM PDT 24
Peak memory 199988 kb
Host smart-d7398c0a-8b57-4405-b991-79865fc929d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683627349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.683627349
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3631687381
Short name T205
Test name
Test status
Simulation time 262187827835 ps
CPU time 32.78 seconds
Started Jul 19 04:27:56 PM PDT 24
Finished Jul 19 04:28:34 PM PDT 24
Peak memory 199976 kb
Host smart-8b1f5080-f039-4e6e-b4e8-ca3d793e6ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631687381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3631687381
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3445436598
Short name T899
Test name
Test status
Simulation time 103882084731 ps
CPU time 99.4 seconds
Started Jul 19 04:27:55 PM PDT 24
Finished Jul 19 04:29:40 PM PDT 24
Peak memory 200204 kb
Host smart-faf81e7e-5450-484a-8a77-d66d88c2a6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445436598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3445436598
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2647055467
Short name T515
Test name
Test status
Simulation time 67602818584 ps
CPU time 48.14 seconds
Started Jul 19 04:28:03 PM PDT 24
Finished Jul 19 04:28:54 PM PDT 24
Peak memory 199992 kb
Host smart-e6752121-1bea-4555-9566-95b45f3e62c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647055467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2647055467
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3614040316
Short name T563
Test name
Test status
Simulation time 39966007 ps
CPU time 0.53 seconds
Started Jul 19 04:25:54 PM PDT 24
Finished Jul 19 04:26:10 PM PDT 24
Peak memory 195004 kb
Host smart-9216bb22-9c25-4ce7-b94a-8a19b01d44df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614040316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3614040316
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.75734427
Short name T184
Test name
Test status
Simulation time 49951225101 ps
CPU time 28.52 seconds
Started Jul 19 04:25:50 PM PDT 24
Finished Jul 19 04:26:34 PM PDT 24
Peak memory 199956 kb
Host smart-eb0ae9ef-1641-4265-91eb-69e83e309783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75734427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.75734427
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1948122102
Short name T592
Test name
Test status
Simulation time 115839603810 ps
CPU time 93.33 seconds
Started Jul 19 04:25:53 PM PDT 24
Finished Jul 19 04:27:42 PM PDT 24
Peak memory 199896 kb
Host smart-c95526f1-d581-47de-b5a8-169347f1939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948122102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1948122102
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2350815490
Short name T253
Test name
Test status
Simulation time 99912262998 ps
CPU time 62.52 seconds
Started Jul 19 04:25:50 PM PDT 24
Finished Jul 19 04:27:08 PM PDT 24
Peak memory 199896 kb
Host smart-98324963-82ea-4bf8-8cde-470639055dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350815490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2350815490
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3153815440
Short name T366
Test name
Test status
Simulation time 18405137405 ps
CPU time 14.56 seconds
Started Jul 19 04:25:47 PM PDT 24
Finished Jul 19 04:26:18 PM PDT 24
Peak memory 197664 kb
Host smart-167805ff-1b05-4cfb-8081-a57782eac54e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153815440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3153815440
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1148100883
Short name T686
Test name
Test status
Simulation time 86659723263 ps
CPU time 187.68 seconds
Started Jul 19 04:26:02 PM PDT 24
Finished Jul 19 04:29:25 PM PDT 24
Peak memory 200232 kb
Host smart-580e2949-4cb2-4d4d-aadd-77b2b4a74ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1148100883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1148100883
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3027427930
Short name T736
Test name
Test status
Simulation time 4852628246 ps
CPU time 6.1 seconds
Started Jul 19 04:25:54 PM PDT 24
Finished Jul 19 04:26:15 PM PDT 24
Peak memory 197772 kb
Host smart-1ea1a04b-3fce-472e-8b0b-366a32a8b106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027427930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3027427930
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.973501973
Short name T501
Test name
Test status
Simulation time 9977287419 ps
CPU time 16.94 seconds
Started Jul 19 04:26:03 PM PDT 24
Finished Jul 19 04:26:35 PM PDT 24
Peak memory 200096 kb
Host smart-9dc95c6c-3a34-4b32-b4e3-5dd69e0acc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973501973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.973501973
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1979856360
Short name T505
Test name
Test status
Simulation time 25506906775 ps
CPU time 220.97 seconds
Started Jul 19 04:26:16 PM PDT 24
Finished Jul 19 04:30:10 PM PDT 24
Peak memory 199876 kb
Host smart-5f149fd8-65ac-422a-9ea8-8783f1d40ebc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1979856360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1979856360
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.4067235505
Short name T372
Test name
Test status
Simulation time 6365140100 ps
CPU time 25.85 seconds
Started Jul 19 04:25:56 PM PDT 24
Finished Jul 19 04:26:37 PM PDT 24
Peak memory 199032 kb
Host smart-ce7f0d3d-97f3-4f2f-b1ae-81def31100b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4067235505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.4067235505
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.440624670
Short name T844
Test name
Test status
Simulation time 11003713296 ps
CPU time 25.18 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:26:40 PM PDT 24
Peak memory 199924 kb
Host smart-f7180f4e-cbd6-4aec-aa25-1deed78deb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440624670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.440624670
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1948155421
Short name T1114
Test name
Test status
Simulation time 4016386835 ps
CPU time 6.36 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:26:20 PM PDT 24
Peak memory 196284 kb
Host smart-1a8b0c62-2421-474c-b07d-15d187cdd97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948155421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1948155421
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.300375838
Short name T750
Test name
Test status
Simulation time 688585297 ps
CPU time 1.44 seconds
Started Jul 19 04:25:45 PM PDT 24
Finished Jul 19 04:26:02 PM PDT 24
Peak memory 198392 kb
Host smart-74bdb1ac-05bb-4c4c-b164-bb35dba8ac7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300375838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.300375838
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1415296643
Short name T695
Test name
Test status
Simulation time 186404155788 ps
CPU time 325.14 seconds
Started Jul 19 04:25:53 PM PDT 24
Finished Jul 19 04:31:34 PM PDT 24
Peak memory 208252 kb
Host smart-e2d5e2a4-3208-4074-bfc5-628f183974be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415296643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1415296643
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2939762604
Short name T298
Test name
Test status
Simulation time 9135413197 ps
CPU time 6.78 seconds
Started Jul 19 04:25:51 PM PDT 24
Finished Jul 19 04:26:14 PM PDT 24
Peak memory 199932 kb
Host smart-1b02f876-5f06-4b5a-9e13-fa6e5204187c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939762604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2939762604
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1783962985
Short name T908
Test name
Test status
Simulation time 153578050843 ps
CPU time 89.36 seconds
Started Jul 19 04:25:50 PM PDT 24
Finished Jul 19 04:27:35 PM PDT 24
Peak memory 199948 kb
Host smart-ab8a17fa-d0b8-43dc-a64d-88e15c5c616c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783962985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1783962985
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3084011960
Short name T487
Test name
Test status
Simulation time 149554582638 ps
CPU time 160.42 seconds
Started Jul 19 04:28:10 PM PDT 24
Finished Jul 19 04:30:54 PM PDT 24
Peak memory 200000 kb
Host smart-43f5d430-7d11-4caf-9b2b-9381d3eba23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084011960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3084011960
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1603379691
Short name T598
Test name
Test status
Simulation time 97189578172 ps
CPU time 217.08 seconds
Started Jul 19 04:28:03 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 199928 kb
Host smart-03410b72-1047-4b10-8e49-1562dfeda8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603379691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1603379691
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3577820963
Short name T140
Test name
Test status
Simulation time 19691935738 ps
CPU time 31.91 seconds
Started Jul 19 04:28:09 PM PDT 24
Finished Jul 19 04:28:44 PM PDT 24
Peak memory 199932 kb
Host smart-6663fd0b-ebd3-445a-8784-a6fac094aa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577820963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3577820963
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3848781912
Short name T246
Test name
Test status
Simulation time 69388838969 ps
CPU time 120.25 seconds
Started Jul 19 04:28:06 PM PDT 24
Finished Jul 19 04:30:09 PM PDT 24
Peak memory 199968 kb
Host smart-4adb20ef-71c6-4981-bfa7-fb4b029be70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848781912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3848781912
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.486605991
Short name T1012
Test name
Test status
Simulation time 97240308743 ps
CPU time 13.27 seconds
Started Jul 19 04:28:08 PM PDT 24
Finished Jul 19 04:28:24 PM PDT 24
Peak memory 199672 kb
Host smart-3b945839-1e76-4f4c-a2ba-860b6b873edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486605991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.486605991
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1867883771
Short name T565
Test name
Test status
Simulation time 97380213259 ps
CPU time 46.96 seconds
Started Jul 19 04:28:08 PM PDT 24
Finished Jul 19 04:28:58 PM PDT 24
Peak memory 199932 kb
Host smart-9593dc2c-7043-407f-a2ff-bde005508bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867883771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1867883771
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.4085014050
Short name T785
Test name
Test status
Simulation time 25071668421 ps
CPU time 10.02 seconds
Started Jul 19 04:28:10 PM PDT 24
Finished Jul 19 04:28:23 PM PDT 24
Peak memory 199884 kb
Host smart-b93c92c0-b8cf-44b5-8508-750e76670f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085014050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.4085014050
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1021685633
Short name T181
Test name
Test status
Simulation time 117713576805 ps
CPU time 13.9 seconds
Started Jul 19 04:28:08 PM PDT 24
Finished Jul 19 04:28:25 PM PDT 24
Peak memory 199648 kb
Host smart-5f603f6c-c852-427d-a413-31c26d6e1030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021685633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1021685633
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.4126394626
Short name T1004
Test name
Test status
Simulation time 16005678 ps
CPU time 0.56 seconds
Started Jul 19 04:26:03 PM PDT 24
Finished Jul 19 04:26:19 PM PDT 24
Peak memory 195348 kb
Host smart-d4d04d7f-3804-4dee-8c77-1a987e3bf0cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126394626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.4126394626
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.143240079
Short name T577
Test name
Test status
Simulation time 125364309571 ps
CPU time 356.64 seconds
Started Jul 19 04:26:11 PM PDT 24
Finished Jul 19 04:32:22 PM PDT 24
Peak memory 199844 kb
Host smart-417739c1-2841-4197-ab0e-23b9cc2bf121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143240079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.143240079
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.946887274
Short name T780
Test name
Test status
Simulation time 85017036867 ps
CPU time 126.81 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:28:22 PM PDT 24
Peak memory 199900 kb
Host smart-c46ba4fa-a5c0-43f5-9585-c8a6600c5e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946887274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.946887274
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1369600434
Short name T1062
Test name
Test status
Simulation time 91121939413 ps
CPU time 21.39 seconds
Started Jul 19 04:25:50 PM PDT 24
Finished Jul 19 04:26:28 PM PDT 24
Peak memory 199860 kb
Host smart-84b93f75-f8c0-410e-a777-181edf48dbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369600434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1369600434
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3785123719
Short name T320
Test name
Test status
Simulation time 20503066503 ps
CPU time 7.23 seconds
Started Jul 19 04:25:56 PM PDT 24
Finished Jul 19 04:26:19 PM PDT 24
Peak memory 196888 kb
Host smart-9e1d92d0-4a87-4272-a6c7-6df0c83a1be9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785123719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3785123719
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2526508519
Short name T873
Test name
Test status
Simulation time 130052964276 ps
CPU time 998.97 seconds
Started Jul 19 04:26:08 PM PDT 24
Finished Jul 19 04:43:01 PM PDT 24
Peak memory 199936 kb
Host smart-eaccc47a-b0d4-4f72-8145-d84f2a80d95e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526508519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2526508519
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2010433154
Short name T20
Test name
Test status
Simulation time 1146054654 ps
CPU time 2.72 seconds
Started Jul 19 04:25:58 PM PDT 24
Finished Jul 19 04:26:16 PM PDT 24
Peak memory 197144 kb
Host smart-33ac7dea-1d10-4f0d-a12d-5a2330ae615f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010433154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2010433154
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2025637658
Short name T794
Test name
Test status
Simulation time 172959642275 ps
CPU time 252.17 seconds
Started Jul 19 04:25:53 PM PDT 24
Finished Jul 19 04:30:21 PM PDT 24
Peak memory 199952 kb
Host smart-8254d9a3-dfb6-4425-8ee9-87534fca9dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025637658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2025637658
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2365113775
Short name T1055
Test name
Test status
Simulation time 8074481019 ps
CPU time 99.26 seconds
Started Jul 19 04:25:56 PM PDT 24
Finished Jul 19 04:27:51 PM PDT 24
Peak memory 199912 kb
Host smart-08241197-6152-466e-b00d-9ee62a9a3da4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2365113775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2365113775
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1368705019
Short name T1017
Test name
Test status
Simulation time 3838352324 ps
CPU time 2.5 seconds
Started Jul 19 04:25:51 PM PDT 24
Finished Jul 19 04:26:10 PM PDT 24
Peak memory 198408 kb
Host smart-8fa6675a-025d-4880-b66a-919b5b9c4fbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1368705019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1368705019
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2045750034
Short name T301
Test name
Test status
Simulation time 5914998231 ps
CPU time 8.8 seconds
Started Jul 19 04:26:09 PM PDT 24
Finished Jul 19 04:26:32 PM PDT 24
Peak memory 199956 kb
Host smart-b7c6feb0-922b-4764-988f-233c8aeee867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045750034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2045750034
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3217564867
Short name T757
Test name
Test status
Simulation time 50304326247 ps
CPU time 57.9 seconds
Started Jul 19 04:25:54 PM PDT 24
Finished Jul 19 04:27:07 PM PDT 24
Peak memory 196144 kb
Host smart-1224b6cc-df6d-43c9-9cd1-64751caae5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217564867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3217564867
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2328775433
Short name T344
Test name
Test status
Simulation time 268889082 ps
CPU time 1.37 seconds
Started Jul 19 04:25:55 PM PDT 24
Finished Jul 19 04:26:12 PM PDT 24
Peak memory 198944 kb
Host smart-825668ed-4e3f-46a8-a3bd-c7c12efe08b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328775433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2328775433
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1092852170
Short name T788
Test name
Test status
Simulation time 39924202444 ps
CPU time 192.18 seconds
Started Jul 19 04:26:06 PM PDT 24
Finished Jul 19 04:29:33 PM PDT 24
Peak memory 216604 kb
Host smart-cd2900d6-4445-416f-b44e-535350fc12f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092852170 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1092852170
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3508725581
Short name T767
Test name
Test status
Simulation time 6026949671 ps
CPU time 14.25 seconds
Started Jul 19 04:25:53 PM PDT 24
Finished Jul 19 04:26:23 PM PDT 24
Peak memory 199808 kb
Host smart-58411e8e-09a4-47b9-b178-26422483daee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508725581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3508725581
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2453689386
Short name T1046
Test name
Test status
Simulation time 106206829777 ps
CPU time 38.68 seconds
Started Jul 19 04:26:05 PM PDT 24
Finished Jul 19 04:26:59 PM PDT 24
Peak memory 200000 kb
Host smart-d03fff99-fe03-42eb-9736-47fe1b2902f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453689386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2453689386
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.920740653
Short name T604
Test name
Test status
Simulation time 19687400272 ps
CPU time 35.46 seconds
Started Jul 19 04:28:06 PM PDT 24
Finished Jul 19 04:28:44 PM PDT 24
Peak memory 199952 kb
Host smart-943b9a65-2829-4b39-92ae-319abbc82b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920740653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.920740653
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.610079490
Short name T1138
Test name
Test status
Simulation time 39882618911 ps
CPU time 82.61 seconds
Started Jul 19 04:28:09 PM PDT 24
Finished Jul 19 04:29:35 PM PDT 24
Peak memory 199928 kb
Host smart-2b454b44-2eeb-432b-aff5-0e7017050652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610079490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.610079490
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2994227291
Short name T323
Test name
Test status
Simulation time 40024611665 ps
CPU time 5.73 seconds
Started Jul 19 04:28:07 PM PDT 24
Finished Jul 19 04:28:16 PM PDT 24
Peak memory 199740 kb
Host smart-f2ad19c9-19ef-408d-b722-db8e1075d4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994227291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2994227291
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3860264099
Short name T614
Test name
Test status
Simulation time 90122841340 ps
CPU time 137.52 seconds
Started Jul 19 04:28:07 PM PDT 24
Finished Jul 19 04:30:27 PM PDT 24
Peak memory 200080 kb
Host smart-78692fbb-4698-414d-a176-da02f2fa0a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860264099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3860264099
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2510088306
Short name T214
Test name
Test status
Simulation time 31184107778 ps
CPU time 28.06 seconds
Started Jul 19 04:28:07 PM PDT 24
Finished Jul 19 04:28:38 PM PDT 24
Peak memory 199988 kb
Host smart-6a088ac2-ddb8-4081-9436-e9a23904dede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510088306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2510088306
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2212578486
Short name T746
Test name
Test status
Simulation time 94045213022 ps
CPU time 123.55 seconds
Started Jul 19 04:28:05 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 199928 kb
Host smart-174489dc-7659-468c-8c46-f7b1b201bac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212578486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2212578486
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.4213919995
Short name T231
Test name
Test status
Simulation time 25826258101 ps
CPU time 51.83 seconds
Started Jul 19 04:28:07 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 199988 kb
Host smart-d2712234-115a-47a5-94b1-11370a63690b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213919995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4213919995
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2607575059
Short name T759
Test name
Test status
Simulation time 10974092735 ps
CPU time 8.34 seconds
Started Jul 19 04:28:06 PM PDT 24
Finished Jul 19 04:28:16 PM PDT 24
Peak memory 199724 kb
Host smart-9bd4849b-577a-4434-96a4-07c31beefb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607575059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2607575059
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3209348710
Short name T734
Test name
Test status
Simulation time 98416247574 ps
CPU time 154.47 seconds
Started Jul 19 04:28:09 PM PDT 24
Finished Jul 19 04:30:46 PM PDT 24
Peak memory 199880 kb
Host smart-985664a8-8b13-4d2a-bfe7-10ce37f3c111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209348710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3209348710
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.968105399
Short name T491
Test name
Test status
Simulation time 38756766 ps
CPU time 0.55 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:26:16 PM PDT 24
Peak memory 194800 kb
Host smart-3e5e0833-da1f-4bac-95c1-c8b527d578e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968105399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.968105399
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.780314575
Short name T706
Test name
Test status
Simulation time 95317308847 ps
CPU time 131.59 seconds
Started Jul 19 04:26:07 PM PDT 24
Finished Jul 19 04:28:34 PM PDT 24
Peak memory 199908 kb
Host smart-cd51dca1-735b-4361-899b-c61a0d9d06b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780314575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.780314575
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2585265702
Short name T659
Test name
Test status
Simulation time 11942407462 ps
CPU time 5.14 seconds
Started Jul 19 04:25:53 PM PDT 24
Finished Jul 19 04:26:14 PM PDT 24
Peak memory 199580 kb
Host smart-daf9f1da-813f-4e14-897e-d83ab32d0a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585265702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2585265702
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2814827346
Short name T1081
Test name
Test status
Simulation time 106930320861 ps
CPU time 169.11 seconds
Started Jul 19 04:25:57 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 199900 kb
Host smart-0dbe9abd-5b16-4774-afdf-91acc9b7409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814827346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2814827346
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3414741539
Short name T126
Test name
Test status
Simulation time 9469850103 ps
CPU time 3.93 seconds
Started Jul 19 04:25:56 PM PDT 24
Finished Jul 19 04:26:16 PM PDT 24
Peak memory 199484 kb
Host smart-ff9521d1-b259-4ada-a57e-7ab55b090b76
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414741539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3414741539
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1482383600
Short name T435
Test name
Test status
Simulation time 196109221459 ps
CPU time 72.51 seconds
Started Jul 19 04:25:55 PM PDT 24
Finished Jul 19 04:27:23 PM PDT 24
Peak memory 199888 kb
Host smart-3b927b76-d611-445e-b910-25f1b4df450c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482383600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1482383600
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2743902773
Short name T951
Test name
Test status
Simulation time 8480056782 ps
CPU time 5.44 seconds
Started Jul 19 04:25:54 PM PDT 24
Finished Jul 19 04:26:14 PM PDT 24
Peak memory 198988 kb
Host smart-8e3a704b-e524-49da-aac8-d5b0513d7d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743902773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2743902773
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.200794199
Short name T639
Test name
Test status
Simulation time 33536900194 ps
CPU time 15.08 seconds
Started Jul 19 04:25:53 PM PDT 24
Finished Jul 19 04:26:24 PM PDT 24
Peak memory 197840 kb
Host smart-3deec429-7845-419c-9992-4ad053d07a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200794199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.200794199
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1468266165
Short name T406
Test name
Test status
Simulation time 10040762819 ps
CPU time 106.07 seconds
Started Jul 19 04:26:10 PM PDT 24
Finished Jul 19 04:28:10 PM PDT 24
Peak memory 199904 kb
Host smart-ffdb75d7-0139-494e-b33d-11830cde0675
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468266165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1468266165
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1342898364
Short name T950
Test name
Test status
Simulation time 4336437827 ps
CPU time 9.35 seconds
Started Jul 19 04:26:13 PM PDT 24
Finished Jul 19 04:26:36 PM PDT 24
Peak memory 199196 kb
Host smart-6d253df4-5299-4558-bac5-007051f2ac23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342898364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1342898364
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2560486838
Short name T1112
Test name
Test status
Simulation time 135922142958 ps
CPU time 313.97 seconds
Started Jul 19 04:26:08 PM PDT 24
Finished Jul 19 04:31:37 PM PDT 24
Peak memory 199936 kb
Host smart-e3d1d210-8b75-44d1-baa9-1f711e3a48fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560486838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2560486838
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1809587927
Short name T446
Test name
Test status
Simulation time 44471299924 ps
CPU time 70.95 seconds
Started Jul 19 04:26:06 PM PDT 24
Finished Jul 19 04:27:32 PM PDT 24
Peak memory 195924 kb
Host smart-e048e6c8-29a8-43a4-a2b4-5f91a3c2d39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809587927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1809587927
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3513664931
Short name T283
Test name
Test status
Simulation time 689517261 ps
CPU time 2.83 seconds
Started Jul 19 04:26:04 PM PDT 24
Finished Jul 19 04:26:22 PM PDT 24
Peak memory 199844 kb
Host smart-2a7ae2c6-d4d4-4d9b-9f56-d339b47185b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513664931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3513664931
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2600648787
Short name T304
Test name
Test status
Simulation time 282471971848 ps
CPU time 534.76 seconds
Started Jul 19 04:26:05 PM PDT 24
Finished Jul 19 04:35:14 PM PDT 24
Peak memory 199924 kb
Host smart-c4230b23-2f77-4160-aa61-1a6cf86836e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600648787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2600648787
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3561097577
Short name T1167
Test name
Test status
Simulation time 502468366153 ps
CPU time 1248.23 seconds
Started Jul 19 04:25:58 PM PDT 24
Finished Jul 19 04:47:02 PM PDT 24
Peak memory 224844 kb
Host smart-62940f4c-0697-46b4-87e4-9c4243446927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561097577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3561097577
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.4261086525
Short name T1014
Test name
Test status
Simulation time 512548155 ps
CPU time 1.94 seconds
Started Jul 19 04:25:56 PM PDT 24
Finished Jul 19 04:26:14 PM PDT 24
Peak memory 198360 kb
Host smart-b071caae-d60f-495f-af93-d1c4c959a840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261086525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.4261086525
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.17733964
Short name T992
Test name
Test status
Simulation time 7801295910 ps
CPU time 11.28 seconds
Started Jul 19 04:25:54 PM PDT 24
Finished Jul 19 04:26:21 PM PDT 24
Peak memory 198968 kb
Host smart-267cf2f3-bf50-4f50-9b1c-2d4b60c7c59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17733964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.17733964
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2720362737
Short name T875
Test name
Test status
Simulation time 138327438940 ps
CPU time 81.32 seconds
Started Jul 19 04:28:07 PM PDT 24
Finished Jul 19 04:29:32 PM PDT 24
Peak memory 200304 kb
Host smart-72a10e1b-5e29-4c1e-a3a6-e04666da0adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720362737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2720362737
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2366059963
Short name T234
Test name
Test status
Simulation time 151999205514 ps
CPU time 95.12 seconds
Started Jul 19 04:28:15 PM PDT 24
Finished Jul 19 04:29:51 PM PDT 24
Peak memory 199988 kb
Host smart-a4cc8bc5-d275-46c6-8172-7d0ba338ea83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366059963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2366059963
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1670105716
Short name T838
Test name
Test status
Simulation time 44964426141 ps
CPU time 20.81 seconds
Started Jul 19 04:28:08 PM PDT 24
Finished Jul 19 04:28:32 PM PDT 24
Peak memory 199668 kb
Host smart-48690428-3336-401d-be17-b0dfe3b0eb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670105716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1670105716
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1071627899
Short name T1037
Test name
Test status
Simulation time 157891911854 ps
CPU time 59.18 seconds
Started Jul 19 04:28:06 PM PDT 24
Finished Jul 19 04:29:07 PM PDT 24
Peak memory 199872 kb
Host smart-bd5bc052-e264-4dcd-9ada-1bbd4664bf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071627899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1071627899
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1434932176
Short name T142
Test name
Test status
Simulation time 12969378043 ps
CPU time 22.11 seconds
Started Jul 19 04:28:07 PM PDT 24
Finished Jul 19 04:28:32 PM PDT 24
Peak memory 199852 kb
Host smart-6ea157ea-6e4e-46d6-bd6f-e3de4450bc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434932176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1434932176
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.805482533
Short name T1089
Test name
Test status
Simulation time 161682682360 ps
CPU time 33.74 seconds
Started Jul 19 04:28:07 PM PDT 24
Finished Jul 19 04:28:44 PM PDT 24
Peak memory 199952 kb
Host smart-8ca9df5c-f952-4f55-b387-6affb9ad9226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805482533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.805482533
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.821408045
Short name T1150
Test name
Test status
Simulation time 42573230443 ps
CPU time 42.53 seconds
Started Jul 19 04:28:09 PM PDT 24
Finished Jul 19 04:28:54 PM PDT 24
Peak memory 199960 kb
Host smart-2f0b2716-4ca1-4b51-a6a3-7261f57d05c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821408045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.821408045
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3194286299
Short name T331
Test name
Test status
Simulation time 24743169843 ps
CPU time 36.67 seconds
Started Jul 19 04:28:06 PM PDT 24
Finished Jul 19 04:28:46 PM PDT 24
Peak memory 199868 kb
Host smart-15b650be-3b55-4202-89e0-64a774a297c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194286299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3194286299
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2404538377
Short name T1049
Test name
Test status
Simulation time 38273691541 ps
CPU time 54.9 seconds
Started Jul 19 04:28:08 PM PDT 24
Finished Jul 19 04:29:07 PM PDT 24
Peak memory 199712 kb
Host smart-bc0c23ba-8947-49a3-858e-ef0f3bf58606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404538377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2404538377
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.4137712701
Short name T833
Test name
Test status
Simulation time 203379734171 ps
CPU time 134.25 seconds
Started Jul 19 04:28:12 PM PDT 24
Finished Jul 19 04:30:28 PM PDT 24
Peak memory 199988 kb
Host smart-371de469-e166-48d7-93e4-6ccf57dfebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137712701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.4137712701
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3842561939
Short name T362
Test name
Test status
Simulation time 12067297 ps
CPU time 0.53 seconds
Started Jul 19 04:25:16 PM PDT 24
Finished Jul 19 04:25:36 PM PDT 24
Peak memory 194740 kb
Host smart-b2bbcc3c-654d-4c09-a3d4-87968599a324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842561939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3842561939
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1712422701
Short name T938
Test name
Test status
Simulation time 83588780597 ps
CPU time 24.01 seconds
Started Jul 19 04:25:09 PM PDT 24
Finished Jul 19 04:25:55 PM PDT 24
Peak memory 199960 kb
Host smart-39e855ae-6fc6-4eb9-be23-c85f7a05dba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712422701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1712422701
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1485533640
Short name T121
Test name
Test status
Simulation time 23286978731 ps
CPU time 37.02 seconds
Started Jul 19 04:25:15 PM PDT 24
Finished Jul 19 04:26:12 PM PDT 24
Peak memory 199944 kb
Host smart-e5b96267-625c-491f-8a52-d49bc805ceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485533640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1485533640
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.4254425881
Short name T330
Test name
Test status
Simulation time 176647807123 ps
CPU time 55.46 seconds
Started Jul 19 04:25:10 PM PDT 24
Finished Jul 19 04:26:28 PM PDT 24
Peak memory 199824 kb
Host smart-f507ab45-0332-4b49-bc26-de48c70dd516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254425881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.4254425881
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3193845920
Short name T786
Test name
Test status
Simulation time 6968124377 ps
CPU time 5.17 seconds
Started Jul 19 04:25:10 PM PDT 24
Finished Jul 19 04:25:37 PM PDT 24
Peak memory 199896 kb
Host smart-3abcf531-90cc-489b-9e1d-983a94a70179
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193845920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3193845920
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3259422130
Short name T754
Test name
Test status
Simulation time 160252654653 ps
CPU time 429.2 seconds
Started Jul 19 04:25:19 PM PDT 24
Finished Jul 19 04:32:48 PM PDT 24
Peak memory 199824 kb
Host smart-cad50e91-4cea-4aa5-89eb-f9e522b52d8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259422130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3259422130
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1181178657
Short name T523
Test name
Test status
Simulation time 1558112751 ps
CPU time 5.78 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:25:43 PM PDT 24
Peak memory 199140 kb
Host smart-5e674b91-0c72-47eb-919a-56ece5a1ba19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181178657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1181178657
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2059325141
Short name T1080
Test name
Test status
Simulation time 163196899818 ps
CPU time 52.8 seconds
Started Jul 19 04:25:11 PM PDT 24
Finished Jul 19 04:26:25 PM PDT 24
Peak memory 215608 kb
Host smart-b50656b8-3e7e-4a4e-aa85-0e3df032fe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059325141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2059325141
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1295416943
Short name T925
Test name
Test status
Simulation time 21389557692 ps
CPU time 511.84 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:34:10 PM PDT 24
Peak memory 199916 kb
Host smart-e8fe8c90-7c02-4fd9-93f5-cecc46b5b020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295416943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1295416943
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3089755503
Short name T465
Test name
Test status
Simulation time 3103494401 ps
CPU time 4.41 seconds
Started Jul 19 04:25:09 PM PDT 24
Finished Jul 19 04:25:35 PM PDT 24
Peak memory 199056 kb
Host smart-49ca5dbf-ab87-4dc7-9f5d-a7ab8f21c730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089755503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3089755503
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1510444182
Short name T1075
Test name
Test status
Simulation time 11879199181 ps
CPU time 19.31 seconds
Started Jul 19 04:25:13 PM PDT 24
Finished Jul 19 04:25:53 PM PDT 24
Peak memory 199088 kb
Host smart-99775169-a02d-4ca1-a70f-27ada9a93bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510444182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1510444182
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.4033769745
Short name T400
Test name
Test status
Simulation time 39803135895 ps
CPU time 30.27 seconds
Started Jul 19 04:25:06 PM PDT 24
Finished Jul 19 04:26:00 PM PDT 24
Peak memory 196248 kb
Host smart-ba276c43-4ca2-42e6-a92d-11036b798762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033769745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.4033769745
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1761618204
Short name T25
Test name
Test status
Simulation time 68897601 ps
CPU time 0.75 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:25:38 PM PDT 24
Peak memory 218172 kb
Host smart-faf27cfd-534a-458e-85c1-b60bce61f436
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761618204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1761618204
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.156740826
Short name T882
Test name
Test status
Simulation time 662306183 ps
CPU time 2.35 seconds
Started Jul 19 04:25:09 PM PDT 24
Finished Jul 19 04:25:34 PM PDT 24
Peak memory 198724 kb
Host smart-93898d62-ea2d-41ba-8f22-19eaa2acfe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156740826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.156740826
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3968474196
Short name T1111
Test name
Test status
Simulation time 32459079366 ps
CPU time 30.69 seconds
Started Jul 19 04:25:19 PM PDT 24
Finished Jul 19 04:26:09 PM PDT 24
Peak memory 200156 kb
Host smart-0be695d0-8047-4ed3-ae89-fee41331ec84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968474196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3968474196
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2728244678
Short name T1057
Test name
Test status
Simulation time 84435380252 ps
CPU time 431.7 seconds
Started Jul 19 04:25:17 PM PDT 24
Finished Jul 19 04:32:48 PM PDT 24
Peak memory 227288 kb
Host smart-b96072f4-60a6-4baf-9d7d-c8939f88b176
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728244678 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2728244678
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.892983107
Short name T428
Test name
Test status
Simulation time 8741452336 ps
CPU time 5.46 seconds
Started Jul 19 04:25:08 PM PDT 24
Finished Jul 19 04:25:36 PM PDT 24
Peak memory 199876 kb
Host smart-5d6c5570-e0a2-4c5f-9d73-99b10f85662a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892983107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.892983107
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3242771313
Short name T690
Test name
Test status
Simulation time 25514842506 ps
CPU time 6.8 seconds
Started Jul 19 04:25:14 PM PDT 24
Finished Jul 19 04:25:41 PM PDT 24
Peak memory 198456 kb
Host smart-957c5499-aad4-4dcb-8193-977b0021981a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242771313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3242771313
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3605700063
Short name T475
Test name
Test status
Simulation time 10108632 ps
CPU time 0.55 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:26:16 PM PDT 24
Peak memory 194324 kb
Host smart-f1391988-e75c-499f-a01d-296f97a2c9c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605700063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3605700063
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.89660909
Short name T774
Test name
Test status
Simulation time 75451818930 ps
CPU time 29.22 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:26:44 PM PDT 24
Peak memory 199920 kb
Host smart-460323cb-ba8b-4030-ad87-6379d70664cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89660909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.89660909
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.731548825
Short name T160
Test name
Test status
Simulation time 16808793660 ps
CPU time 13.15 seconds
Started Jul 19 04:25:58 PM PDT 24
Finished Jul 19 04:26:27 PM PDT 24
Peak memory 199872 kb
Host smart-a3786151-f7e0-4d8a-9342-3fa26a515aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731548825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.731548825
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.101267914
Short name T1051
Test name
Test status
Simulation time 152236861213 ps
CPU time 219.96 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:29:54 PM PDT 24
Peak memory 197492 kb
Host smart-6c68d1a7-c672-4ecb-b8ef-5a2f8f66bd4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101267914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.101267914
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1281954022
Short name T425
Test name
Test status
Simulation time 125130608387 ps
CPU time 1060.35 seconds
Started Jul 19 04:26:07 PM PDT 24
Finished Jul 19 04:44:02 PM PDT 24
Peak memory 199940 kb
Host smart-ec8ac784-d627-4f32-81ea-2510967f58f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1281954022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1281954022
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3738515287
Short name T507
Test name
Test status
Simulation time 4886709593 ps
CPU time 6.33 seconds
Started Jul 19 04:25:58 PM PDT 24
Finished Jul 19 04:26:20 PM PDT 24
Peak memory 199928 kb
Host smart-e57c793a-2bf1-4d67-8d0b-d3b6032046bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738515287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3738515287
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.419942242
Short name T104
Test name
Test status
Simulation time 5779116762 ps
CPU time 7.75 seconds
Started Jul 19 04:26:07 PM PDT 24
Finished Jul 19 04:26:30 PM PDT 24
Peak memory 200140 kb
Host smart-d782416e-8d35-457a-9b4d-3b94fd98fd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419942242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.419942242
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.16845265
Short name T334
Test name
Test status
Simulation time 17452643553 ps
CPU time 568.09 seconds
Started Jul 19 04:26:10 PM PDT 24
Finished Jul 19 04:35:52 PM PDT 24
Peak memory 199880 kb
Host smart-d6263111-4d1a-45bd-bc52-1584898ec13c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16845265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.16845265
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.521886859
Short name T975
Test name
Test status
Simulation time 2020258536 ps
CPU time 6.17 seconds
Started Jul 19 04:25:55 PM PDT 24
Finished Jul 19 04:26:16 PM PDT 24
Peak memory 197852 kb
Host smart-4f2d7a5a-d0e7-4391-ae5f-8b77307ac647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521886859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.521886859
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3381342655
Short name T567
Test name
Test status
Simulation time 90641514028 ps
CPU time 27.73 seconds
Started Jul 19 04:25:57 PM PDT 24
Finished Jul 19 04:26:41 PM PDT 24
Peak memory 199952 kb
Host smart-f3efc711-7d7a-4704-a141-0d08c3d63285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381342655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3381342655
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1244519282
Short name T576
Test name
Test status
Simulation time 33408883003 ps
CPU time 11.7 seconds
Started Jul 19 04:26:05 PM PDT 24
Finished Jul 19 04:26:32 PM PDT 24
Peak memory 196756 kb
Host smart-2ba85d61-3379-407c-b862-1b3134f5dc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244519282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1244519282
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1398836062
Short name T375
Test name
Test status
Simulation time 5305961422 ps
CPU time 15.56 seconds
Started Jul 19 04:26:11 PM PDT 24
Finished Jul 19 04:26:41 PM PDT 24
Peak memory 199784 kb
Host smart-939ebb89-cecb-4e6c-a180-3103be446ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398836062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1398836062
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.2652809761
Short name T1093
Test name
Test status
Simulation time 148051549215 ps
CPU time 91.46 seconds
Started Jul 19 04:26:09 PM PDT 24
Finished Jul 19 04:27:55 PM PDT 24
Peak memory 199948 kb
Host smart-268b14da-4d00-492f-8b17-86c5f8fb8b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652809761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2652809761
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.836115483
Short name T826
Test name
Test status
Simulation time 625830434938 ps
CPU time 391.01 seconds
Started Jul 19 04:26:05 PM PDT 24
Finished Jul 19 04:32:51 PM PDT 24
Peak memory 216576 kb
Host smart-65bc834e-55b3-4c69-937f-0db2a4dc002f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836115483 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.836115483
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2107412163
Short name T717
Test name
Test status
Simulation time 449260454 ps
CPU time 1.51 seconds
Started Jul 19 04:25:54 PM PDT 24
Finished Jul 19 04:26:11 PM PDT 24
Peak memory 198444 kb
Host smart-87db3e88-9965-4e28-9b89-c68593595790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107412163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2107412163
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2824326060
Short name T1084
Test name
Test status
Simulation time 71574350670 ps
CPU time 29.51 seconds
Started Jul 19 04:25:53 PM PDT 24
Finished Jul 19 04:26:38 PM PDT 24
Peak memory 199888 kb
Host smart-7b007f1b-7746-4cb5-accd-fac5ca12b47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824326060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2824326060
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.179937589
Short name T546
Test name
Test status
Simulation time 93339404423 ps
CPU time 66.11 seconds
Started Jul 19 04:28:08 PM PDT 24
Finished Jul 19 04:29:17 PM PDT 24
Peak memory 199900 kb
Host smart-a36e129f-4cf3-4a39-97d7-e272ffbff3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179937589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.179937589
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.456514713
Short name T397
Test name
Test status
Simulation time 14804125794 ps
CPU time 8.88 seconds
Started Jul 19 04:28:08 PM PDT 24
Finished Jul 19 04:28:20 PM PDT 24
Peak memory 199804 kb
Host smart-fab93ca1-8ae1-446f-9348-4d3fc20e129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456514713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.456514713
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.59945531
Short name T671
Test name
Test status
Simulation time 35622864637 ps
CPU time 69.6 seconds
Started Jul 19 04:28:06 PM PDT 24
Finished Jul 19 04:29:17 PM PDT 24
Peak memory 199892 kb
Host smart-4cad79ef-42f0-4159-8b4c-18c79ba8ba19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59945531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.59945531
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1285293987
Short name T771
Test name
Test status
Simulation time 184236532409 ps
CPU time 51.18 seconds
Started Jul 19 04:28:09 PM PDT 24
Finished Jul 19 04:29:03 PM PDT 24
Peak memory 200036 kb
Host smart-12475177-4937-4066-8de7-5d15d673814b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285293987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1285293987
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3500287997
Short name T321
Test name
Test status
Simulation time 218582878724 ps
CPU time 76.7 seconds
Started Jul 19 04:28:08 PM PDT 24
Finished Jul 19 04:29:28 PM PDT 24
Peak memory 200080 kb
Host smart-99cbdc62-9524-47b5-967f-e0dc4c270f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500287997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3500287997
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1307076107
Short name T1176
Test name
Test status
Simulation time 30251130488 ps
CPU time 23.17 seconds
Started Jul 19 04:28:08 PM PDT 24
Finished Jul 19 04:28:34 PM PDT 24
Peak memory 199944 kb
Host smart-bc27c7bc-a733-4ff2-b9ca-567d2baa4a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307076107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1307076107
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1639535049
Short name T942
Test name
Test status
Simulation time 245556366352 ps
CPU time 51.13 seconds
Started Jul 19 04:28:07 PM PDT 24
Finished Jul 19 04:29:01 PM PDT 24
Peak memory 199968 kb
Host smart-cb9edbe9-d543-4254-bf82-beede0e7d660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639535049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1639535049
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3845992152
Short name T804
Test name
Test status
Simulation time 38915544 ps
CPU time 0.54 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:26:15 PM PDT 24
Peak memory 195392 kb
Host smart-7d16ae79-a640-4322-a6f7-a1ad55ab9045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845992152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3845992152
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3192919644
Short name T1056
Test name
Test status
Simulation time 302248525466 ps
CPU time 350.78 seconds
Started Jul 19 04:26:04 PM PDT 24
Finished Jul 19 04:32:10 PM PDT 24
Peak memory 199868 kb
Host smart-5d5370b2-699e-481a-b153-85df17ae0d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192919644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3192919644
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.946274270
Short name T1149
Test name
Test status
Simulation time 34625063661 ps
CPU time 22.72 seconds
Started Jul 19 04:26:03 PM PDT 24
Finished Jul 19 04:26:41 PM PDT 24
Peak memory 199988 kb
Host smart-72d8f480-89a1-45c8-89d7-724321b51790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946274270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.946274270
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3097592027
Short name T941
Test name
Test status
Simulation time 118168177991 ps
CPU time 42.24 seconds
Started Jul 19 04:26:07 PM PDT 24
Finished Jul 19 04:27:04 PM PDT 24
Peak memory 199872 kb
Host smart-4a072acd-12d1-4d52-895a-2dc7081b7e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097592027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3097592027
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3466458684
Short name T805
Test name
Test status
Simulation time 62317479569 ps
CPU time 34.84 seconds
Started Jul 19 04:26:07 PM PDT 24
Finished Jul 19 04:26:57 PM PDT 24
Peak memory 199876 kb
Host smart-c88130d5-ebab-4624-b9d2-f1753a4fb942
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466458684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3466458684
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2014699883
Short name T1053
Test name
Test status
Simulation time 63967735975 ps
CPU time 518.87 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:34:54 PM PDT 24
Peak memory 199944 kb
Host smart-84d06ad4-5eb0-42fa-abaa-719a7c50409c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2014699883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2014699883
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.12447940
Short name T672
Test name
Test status
Simulation time 6638552814 ps
CPU time 6.02 seconds
Started Jul 19 04:25:54 PM PDT 24
Finished Jul 19 04:26:15 PM PDT 24
Peak memory 198748 kb
Host smart-7a036804-9cdf-4c30-b042-78f00a5adf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12447940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.12447940
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.202460373
Short name T1146
Test name
Test status
Simulation time 94513815624 ps
CPU time 225.27 seconds
Started Jul 19 04:26:05 PM PDT 24
Finished Jul 19 04:30:05 PM PDT 24
Peak memory 208276 kb
Host smart-eba2b8d1-902e-4be2-a23c-8656258e6c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202460373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.202460373
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3041719615
Short name T379
Test name
Test status
Simulation time 18239861457 ps
CPU time 489.96 seconds
Started Jul 19 04:25:58 PM PDT 24
Finished Jul 19 04:34:24 PM PDT 24
Peak memory 200008 kb
Host smart-61769554-dc4f-4f83-9aef-f19602bc5a9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3041719615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3041719615
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2968019719
Short name T499
Test name
Test status
Simulation time 4191763433 ps
CPU time 2.09 seconds
Started Jul 19 04:26:10 PM PDT 24
Finished Jul 19 04:26:27 PM PDT 24
Peak memory 198040 kb
Host smart-b2b00877-d578-43ba-8f7b-f0279f6cea94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968019719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2968019719
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3204199938
Short name T782
Test name
Test status
Simulation time 92728310461 ps
CPU time 88.1 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:27:43 PM PDT 24
Peak memory 200004 kb
Host smart-4b6ff4ba-b83c-45e3-a809-22a60c401901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204199938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3204199938
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2103011537
Short name T1002
Test name
Test status
Simulation time 4017874157 ps
CPU time 6.66 seconds
Started Jul 19 04:26:05 PM PDT 24
Finished Jul 19 04:26:26 PM PDT 24
Peak memory 196724 kb
Host smart-14bb35fc-b1d2-43c3-a80f-11c9265821e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103011537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2103011537
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1001941006
Short name T488
Test name
Test status
Simulation time 10541844766 ps
CPU time 9.35 seconds
Started Jul 19 04:25:56 PM PDT 24
Finished Jul 19 04:26:21 PM PDT 24
Peak memory 199556 kb
Host smart-5958ab44-c2cc-4b51-9738-750ee1b76f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001941006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1001941006
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1329934112
Short name T667
Test name
Test status
Simulation time 30677495728 ps
CPU time 17.77 seconds
Started Jul 19 04:25:54 PM PDT 24
Finished Jul 19 04:26:27 PM PDT 24
Peak memory 199972 kb
Host smart-30d39ab5-d053-4e34-8fff-4dc4916aa27c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329934112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1329934112
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2438875860
Short name T564
Test name
Test status
Simulation time 112819593927 ps
CPU time 414.19 seconds
Started Jul 19 04:25:57 PM PDT 24
Finished Jul 19 04:33:07 PM PDT 24
Peak memory 216476 kb
Host smart-dc3510cc-d33a-4d9f-a45a-6ddbd9ef4995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438875860 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2438875860
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2066607911
Short name T316
Test name
Test status
Simulation time 727453356 ps
CPU time 2.69 seconds
Started Jul 19 04:26:23 PM PDT 24
Finished Jul 19 04:26:37 PM PDT 24
Peak memory 199712 kb
Host smart-3e735a24-2d36-46f5-a619-4b50d7e192a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066607911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2066607911
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1951994795
Short name T1087
Test name
Test status
Simulation time 129336605361 ps
CPU time 141.27 seconds
Started Jul 19 04:26:08 PM PDT 24
Finished Jul 19 04:28:44 PM PDT 24
Peak memory 199856 kb
Host smart-9cf361c5-451b-433b-932e-5381a0285b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951994795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1951994795
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1157266541
Short name T977
Test name
Test status
Simulation time 351282348415 ps
CPU time 42.18 seconds
Started Jul 19 04:28:09 PM PDT 24
Finished Jul 19 04:28:54 PM PDT 24
Peak memory 199932 kb
Host smart-a272a45c-efe1-4082-8aa3-141af58426ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157266541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1157266541
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.410913453
Short name T152
Test name
Test status
Simulation time 113448063119 ps
CPU time 380.11 seconds
Started Jul 19 04:28:06 PM PDT 24
Finished Jul 19 04:34:29 PM PDT 24
Peak memory 199960 kb
Host smart-d3fe94fe-ac4b-48f2-84c6-2a50b97ea20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410913453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.410913453
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2829687363
Short name T636
Test name
Test status
Simulation time 163424790009 ps
CPU time 15.53 seconds
Started Jul 19 04:28:06 PM PDT 24
Finished Jul 19 04:28:25 PM PDT 24
Peak memory 199520 kb
Host smart-c85f0d25-9709-4a38-9e84-bf9ed4d7e196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829687363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2829687363
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.29081884
Short name T1142
Test name
Test status
Simulation time 32395260610 ps
CPU time 26.28 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:28:49 PM PDT 24
Peak memory 199976 kb
Host smart-2940a2da-a98e-4b15-bb8d-aa3c98bb842e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29081884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.29081884
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1756412995
Short name T392
Test name
Test status
Simulation time 118081873877 ps
CPU time 54.93 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:29:17 PM PDT 24
Peak memory 199896 kb
Host smart-f092382f-8bf2-494f-a747-a8bf9eb453f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756412995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1756412995
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.833027364
Short name T174
Test name
Test status
Simulation time 90591789026 ps
CPU time 86.01 seconds
Started Jul 19 04:28:21 PM PDT 24
Finished Jul 19 04:29:49 PM PDT 24
Peak memory 199992 kb
Host smart-900e7771-bd5e-4d8a-8a6c-a2327efcc632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833027364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.833027364
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2530850813
Short name T946
Test name
Test status
Simulation time 38596756955 ps
CPU time 26.73 seconds
Started Jul 19 04:28:17 PM PDT 24
Finished Jul 19 04:28:45 PM PDT 24
Peak memory 198876 kb
Host smart-ff749f0a-60a7-4518-8000-0bee32638450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530850813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2530850813
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4193578681
Short name T129
Test name
Test status
Simulation time 121690154422 ps
CPU time 48.1 seconds
Started Jul 19 04:28:22 PM PDT 24
Finished Jul 19 04:29:12 PM PDT 24
Peak memory 199932 kb
Host smart-77197079-1d5b-4eaf-815e-181596b03cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193578681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4193578681
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3150344249
Short name T878
Test name
Test status
Simulation time 93485653562 ps
CPU time 28.87 seconds
Started Jul 19 04:28:19 PM PDT 24
Finished Jul 19 04:28:49 PM PDT 24
Peak memory 199928 kb
Host smart-5c0d40c7-91f8-4d5c-ad38-a6a6a074253b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150344249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3150344249
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2047608720
Short name T452
Test name
Test status
Simulation time 12606913 ps
CPU time 0.58 seconds
Started Jul 19 04:26:03 PM PDT 24
Finished Jul 19 04:26:19 PM PDT 24
Peak memory 195720 kb
Host smart-36ca72ed-6d80-442d-913f-3370cf584e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047608720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2047608720
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3694427365
Short name T1043
Test name
Test status
Simulation time 97792708523 ps
CPU time 153.38 seconds
Started Jul 19 04:26:09 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 199956 kb
Host smart-0dde856a-59b3-44f4-ba16-e51586ced63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694427365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3694427365
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3354928967
Short name T490
Test name
Test status
Simulation time 22466585850 ps
CPU time 17.68 seconds
Started Jul 19 04:25:58 PM PDT 24
Finished Jul 19 04:26:32 PM PDT 24
Peak memory 199868 kb
Host smart-31cc6eaa-8fa5-4adb-98e5-8de3d5c31281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354928967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3354928967
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.616335405
Short name T1016
Test name
Test status
Simulation time 185037878938 ps
CPU time 85.14 seconds
Started Jul 19 04:26:07 PM PDT 24
Finished Jul 19 04:27:47 PM PDT 24
Peak memory 199956 kb
Host smart-c789a9aa-520c-451f-9ffc-914b5be43b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616335405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.616335405
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1359066371
Short name T329
Test name
Test status
Simulation time 56874047772 ps
CPU time 88.59 seconds
Started Jul 19 04:26:10 PM PDT 24
Finished Jul 19 04:27:53 PM PDT 24
Peak memory 200300 kb
Host smart-1d27f6a6-d7ad-4c64-8453-b061a604fa07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359066371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1359066371
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.4062431985
Short name T637
Test name
Test status
Simulation time 112954713087 ps
CPU time 658.17 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:37:13 PM PDT 24
Peak memory 199944 kb
Host smart-b2d1afb3-68bc-41bb-b958-817a410fef1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062431985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.4062431985
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1152798484
Short name T722
Test name
Test status
Simulation time 775082914 ps
CPU time 2.1 seconds
Started Jul 19 04:26:08 PM PDT 24
Finished Jul 19 04:26:25 PM PDT 24
Peak memory 199552 kb
Host smart-315669cd-ad6b-4475-ad12-235f91ed05c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152798484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1152798484
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1912875438
Short name T1121
Test name
Test status
Simulation time 227211459692 ps
CPU time 107.07 seconds
Started Jul 19 04:26:11 PM PDT 24
Finished Jul 19 04:28:13 PM PDT 24
Peak memory 208168 kb
Host smart-3eecae25-3249-4129-b6b2-661b5131def3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912875438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1912875438
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1032973430
Short name T902
Test name
Test status
Simulation time 14148045928 ps
CPU time 197.28 seconds
Started Jul 19 04:26:16 PM PDT 24
Finished Jul 19 04:29:46 PM PDT 24
Peak memory 199912 kb
Host smart-bf3c8484-7f44-4e99-9b3e-3d9899b3f1e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032973430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1032973430
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1671793490
Short name T1100
Test name
Test status
Simulation time 7046580734 ps
CPU time 56.67 seconds
Started Jul 19 04:25:55 PM PDT 24
Finished Jul 19 04:27:07 PM PDT 24
Peak memory 198056 kb
Host smart-778cbe33-eee0-400a-b295-eb8143f82a22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671793490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1671793490
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2200594601
Short name T9
Test name
Test status
Simulation time 130645221191 ps
CPU time 51.55 seconds
Started Jul 19 04:25:58 PM PDT 24
Finished Jul 19 04:27:05 PM PDT 24
Peak memory 199844 kb
Host smart-0fbae354-e208-4be7-b5d9-e210387278a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200594601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2200594601
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.4010746353
Short name T845
Test name
Test status
Simulation time 2800927176 ps
CPU time 1.74 seconds
Started Jul 19 04:26:09 PM PDT 24
Finished Jul 19 04:26:25 PM PDT 24
Peak memory 195808 kb
Host smart-7ff15a9b-4a66-43db-bcfb-a45b150055d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010746353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.4010746353
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1717355054
Short name T276
Test name
Test status
Simulation time 5891307810 ps
CPU time 22.94 seconds
Started Jul 19 04:25:57 PM PDT 24
Finished Jul 19 04:26:36 PM PDT 24
Peak memory 199964 kb
Host smart-011a6ec0-452c-44b2-851f-daf2b03cd446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717355054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1717355054
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.388841866
Short name T60
Test name
Test status
Simulation time 57614204110 ps
CPU time 515.77 seconds
Started Jul 19 04:26:09 PM PDT 24
Finished Jul 19 04:34:59 PM PDT 24
Peak memory 216652 kb
Host smart-64700225-c3d3-4a3f-ad48-66f55a265897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388841866 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.388841866
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.162074768
Short name T469
Test name
Test status
Simulation time 6954310986 ps
CPU time 10.94 seconds
Started Jul 19 04:26:04 PM PDT 24
Finished Jul 19 04:26:30 PM PDT 24
Peak memory 199968 kb
Host smart-a3dd4ad3-904e-45ac-b640-c0594ae04b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162074768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.162074768
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2683251259
Short name T983
Test name
Test status
Simulation time 42948716771 ps
CPU time 31.86 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:26:46 PM PDT 24
Peak memory 199924 kb
Host smart-9705bc2a-e017-4f23-81d3-d4858c00e9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683251259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2683251259
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.816203991
Short name T680
Test name
Test status
Simulation time 122327790342 ps
CPU time 44.24 seconds
Started Jul 19 04:28:19 PM PDT 24
Finished Jul 19 04:29:05 PM PDT 24
Peak memory 199964 kb
Host smart-2aad21d8-9e3a-4384-9bf1-1823cdb14d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816203991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.816203991
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2854505482
Short name T548
Test name
Test status
Simulation time 79708680795 ps
CPU time 20 seconds
Started Jul 19 04:28:17 PM PDT 24
Finished Jul 19 04:28:39 PM PDT 24
Peak memory 199964 kb
Host smart-c0699eaf-a504-4862-8796-7f1efccd71fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854505482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2854505482
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.512065548
Short name T162
Test name
Test status
Simulation time 27699050699 ps
CPU time 50.6 seconds
Started Jul 19 04:28:19 PM PDT 24
Finished Jul 19 04:29:12 PM PDT 24
Peak memory 199868 kb
Host smart-bd152836-bf8d-436d-ba51-830dbee13ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512065548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.512065548
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1094003896
Short name T1140
Test name
Test status
Simulation time 119660659242 ps
CPU time 227.4 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:32:10 PM PDT 24
Peak memory 200004 kb
Host smart-39e85cee-eea7-4052-a04e-865495ec5a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094003896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1094003896
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2858011770
Short name T146
Test name
Test status
Simulation time 30199147780 ps
CPU time 12.85 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:28:36 PM PDT 24
Peak memory 199664 kb
Host smart-b6a5f74a-41d5-4ee5-8fbc-8fa5e974a07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858011770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2858011770
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.238264405
Short name T1008
Test name
Test status
Simulation time 120592331278 ps
CPU time 298.87 seconds
Started Jul 19 04:28:17 PM PDT 24
Finished Jul 19 04:33:18 PM PDT 24
Peak memory 200024 kb
Host smart-64c57915-b284-4b9c-b18f-fa788f157cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238264405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.238264405
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1976650414
Short name T156
Test name
Test status
Simulation time 69468255070 ps
CPU time 52.69 seconds
Started Jul 19 04:28:19 PM PDT 24
Finished Jul 19 04:29:14 PM PDT 24
Peak memory 200008 kb
Host smart-256910df-b37c-456d-8c60-46003a9bc8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976650414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1976650414
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2663844527
Short name T197
Test name
Test status
Simulation time 97146775001 ps
CPU time 251.44 seconds
Started Jul 19 04:28:17 PM PDT 24
Finished Jul 19 04:32:30 PM PDT 24
Peak memory 199936 kb
Host smart-ca2b5cc8-4578-45fb-979b-22344a052ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663844527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2663844527
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3543458469
Short name T1061
Test name
Test status
Simulation time 91314015885 ps
CPU time 157.77 seconds
Started Jul 19 04:28:17 PM PDT 24
Finished Jul 19 04:30:56 PM PDT 24
Peak memory 199960 kb
Host smart-fabc4ed8-ddf9-42cd-8bd4-e5d269d5cd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543458469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3543458469
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2733388334
Short name T22
Test name
Test status
Simulation time 102294514 ps
CPU time 0.52 seconds
Started Jul 19 04:26:08 PM PDT 24
Finished Jul 19 04:26:23 PM PDT 24
Peak memory 194164 kb
Host smart-fff7c1f2-0ba5-4e1a-bc91-554174408c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733388334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2733388334
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.665424827
Short name T961
Test name
Test status
Simulation time 180344256414 ps
CPU time 70.19 seconds
Started Jul 19 04:26:04 PM PDT 24
Finished Jul 19 04:27:29 PM PDT 24
Peak memory 199876 kb
Host smart-9ee98481-b35e-4d6a-883f-b89ce94ff497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665424827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.665424827
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2822510099
Short name T476
Test name
Test status
Simulation time 108471310485 ps
CPU time 196.63 seconds
Started Jul 19 04:26:16 PM PDT 24
Finished Jul 19 04:29:46 PM PDT 24
Peak memory 199952 kb
Host smart-978da378-e87f-49fe-a6f2-d2085e6b2300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822510099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2822510099
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.260865728
Short name T825
Test name
Test status
Simulation time 25042597441 ps
CPU time 36.7 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:26:51 PM PDT 24
Peak memory 199076 kb
Host smart-16f43e39-f559-420c-a5f9-a6b8f89d9658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260865728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.260865728
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.516982110
Short name T424
Test name
Test status
Simulation time 38149185850 ps
CPU time 55.63 seconds
Started Jul 19 04:26:02 PM PDT 24
Finished Jul 19 04:27:13 PM PDT 24
Peak memory 199964 kb
Host smart-72efe21d-1882-4a77-a9da-d79dbbb3c3f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516982110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.516982110
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.4242139256
Short name T791
Test name
Test status
Simulation time 56100810016 ps
CPU time 268.51 seconds
Started Jul 19 04:26:11 PM PDT 24
Finished Jul 19 04:30:54 PM PDT 24
Peak memory 199944 kb
Host smart-dc9f2adc-e8c7-4c6c-9b2d-b85b10c2fc33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4242139256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.4242139256
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1780436064
Short name T653
Test name
Test status
Simulation time 4025131055 ps
CPU time 4.39 seconds
Started Jul 19 04:26:03 PM PDT 24
Finished Jul 19 04:26:22 PM PDT 24
Peak memory 198976 kb
Host smart-0f2345fb-0c04-47d9-ab36-33a29c750127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780436064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1780436064
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3733372622
Short name T612
Test name
Test status
Simulation time 119830874030 ps
CPU time 28.93 seconds
Started Jul 19 04:26:04 PM PDT 24
Finished Jul 19 04:26:48 PM PDT 24
Peak memory 198776 kb
Host smart-1a2a2567-b599-4601-a208-5c34afc1a5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733372622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3733372622
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1028111343
Short name T552
Test name
Test status
Simulation time 13219105508 ps
CPU time 392.46 seconds
Started Jul 19 04:26:21 PM PDT 24
Finished Jul 19 04:33:05 PM PDT 24
Peak memory 199836 kb
Host smart-b03d8314-c541-4f01-88d7-b569d60d0ec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028111343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1028111343
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.186020590
Short name T508
Test name
Test status
Simulation time 6261745771 ps
CPU time 53.12 seconds
Started Jul 19 04:26:04 PM PDT 24
Finished Jul 19 04:27:12 PM PDT 24
Peak memory 199096 kb
Host smart-9c3b8629-9ef5-47ab-a7f0-770f2d75d7e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186020590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.186020590
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2058615016
Short name T649
Test name
Test status
Simulation time 58108403482 ps
CPU time 45.21 seconds
Started Jul 19 04:26:23 PM PDT 24
Finished Jul 19 04:27:19 PM PDT 24
Peak memory 199796 kb
Host smart-6a83c044-ef5e-46f7-be48-a0149b9fadb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058615016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2058615016
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.470297028
Short name T1157
Test name
Test status
Simulation time 2433154692 ps
CPU time 1.62 seconds
Started Jul 19 04:26:15 PM PDT 24
Finished Jul 19 04:26:30 PM PDT 24
Peak memory 196428 kb
Host smart-f858e701-b19e-4ba7-807f-9a525fbc73a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470297028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.470297028
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.113471911
Short name T931
Test name
Test status
Simulation time 284360413 ps
CPU time 1.71 seconds
Started Jul 19 04:25:59 PM PDT 24
Finished Jul 19 04:26:16 PM PDT 24
Peak memory 197864 kb
Host smart-0f650168-1d60-4f9d-8d8c-a77791e3f497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113471911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.113471911
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3757318910
Short name T560
Test name
Test status
Simulation time 363151546451 ps
CPU time 151.17 seconds
Started Jul 19 04:26:11 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 208256 kb
Host smart-49d6b22f-5f46-490b-80c1-18e9da5348eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757318910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3757318910
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2646582380
Short name T1029
Test name
Test status
Simulation time 128025805505 ps
CPU time 1086.36 seconds
Started Jul 19 04:26:05 PM PDT 24
Finished Jul 19 04:44:26 PM PDT 24
Peak memory 224844 kb
Host smart-4a0e73db-cca1-4632-88ab-a357c2d56a2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646582380 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2646582380
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3099252511
Short name T541
Test name
Test status
Simulation time 972210385 ps
CPU time 2.59 seconds
Started Jul 19 04:26:03 PM PDT 24
Finished Jul 19 04:26:20 PM PDT 24
Peak memory 198344 kb
Host smart-3c6ce67d-8b5d-4992-b892-932c7cded865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099252511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3099252511
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3700175551
Short name T513
Test name
Test status
Simulation time 14533198020 ps
CPU time 31.06 seconds
Started Jul 19 04:25:58 PM PDT 24
Finished Jul 19 04:26:45 PM PDT 24
Peak memory 199996 kb
Host smart-6932cf32-3e96-4967-8713-2d7e3864337e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700175551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3700175551
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3173576132
Short name T213
Test name
Test status
Simulation time 23951462260 ps
CPU time 36.71 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:28:59 PM PDT 24
Peak memory 199924 kb
Host smart-33a2ff73-8877-489e-88b9-0ee5975e2e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173576132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3173576132
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1239537639
Short name T127
Test name
Test status
Simulation time 97069894264 ps
CPU time 148.14 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:30:51 PM PDT 24
Peak memory 199932 kb
Host smart-5b1ae9fe-6abc-48dc-b2cf-dd5a3900d95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239537639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1239537639
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.741795304
Short name T230
Test name
Test status
Simulation time 44143654895 ps
CPU time 201.49 seconds
Started Jul 19 04:28:19 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 200032 kb
Host smart-9099a324-681f-4488-b715-2dc21a74d469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741795304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.741795304
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2234151060
Short name T201
Test name
Test status
Simulation time 17382422229 ps
CPU time 30.86 seconds
Started Jul 19 04:28:19 PM PDT 24
Finished Jul 19 04:28:51 PM PDT 24
Peak memory 199988 kb
Host smart-9fd10650-dea5-4ee3-b43d-a7d75098ad12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234151060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2234151060
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3647484802
Short name T781
Test name
Test status
Simulation time 289599475371 ps
CPU time 448.62 seconds
Started Jul 19 04:28:21 PM PDT 24
Finished Jul 19 04:35:52 PM PDT 24
Peak memory 200004 kb
Host smart-0716d9e2-8869-46f5-b893-dab93138858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647484802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3647484802
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1324028930
Short name T720
Test name
Test status
Simulation time 137949249408 ps
CPU time 193.27 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:31:36 PM PDT 24
Peak memory 199944 kb
Host smart-12350169-24b0-4948-ab84-227dafccb3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324028930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1324028930
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1712842424
Short name T698
Test name
Test status
Simulation time 99161267009 ps
CPU time 156.19 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:30:59 PM PDT 24
Peak memory 200076 kb
Host smart-f1373905-2c71-424c-9743-17272e79ba19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712842424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1712842424
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4217172793
Short name T391
Test name
Test status
Simulation time 31454923 ps
CPU time 0.53 seconds
Started Jul 19 04:26:16 PM PDT 24
Finished Jul 19 04:26:29 PM PDT 24
Peak memory 194292 kb
Host smart-8c6c2ba5-811a-4045-a715-4f1c41af89ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217172793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4217172793
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2380597073
Short name T486
Test name
Test status
Simulation time 185235965697 ps
CPU time 84.95 seconds
Started Jul 19 04:26:04 PM PDT 24
Finished Jul 19 04:27:43 PM PDT 24
Peak memory 199888 kb
Host smart-59a9d130-f9e6-4aa5-b3d0-a6963715c1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380597073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2380597073
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.4269972051
Short name T336
Test name
Test status
Simulation time 128752873837 ps
CPU time 224.85 seconds
Started Jul 19 04:26:04 PM PDT 24
Finished Jul 19 04:30:04 PM PDT 24
Peak memory 199936 kb
Host smart-fc55e9da-af69-4590-83f6-7dc4d44affd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269972051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.4269972051
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3003413734
Short name T47
Test name
Test status
Simulation time 34996979912 ps
CPU time 30.09 seconds
Started Jul 19 04:26:12 PM PDT 24
Finished Jul 19 04:26:56 PM PDT 24
Peak memory 199904 kb
Host smart-eb9e8d1b-d30c-492e-afe3-6558033eedc1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003413734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3003413734
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1042995108
Short name T1141
Test name
Test status
Simulation time 244419105209 ps
CPU time 227.29 seconds
Started Jul 19 04:26:28 PM PDT 24
Finished Jul 19 04:30:27 PM PDT 24
Peak memory 199936 kb
Host smart-4a8afb0d-2e38-4ed7-89c0-27b1505d861b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1042995108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1042995108
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.979664736
Short name T776
Test name
Test status
Simulation time 1559811056 ps
CPU time 1.23 seconds
Started Jul 19 04:26:04 PM PDT 24
Finished Jul 19 04:26:20 PM PDT 24
Peak memory 196128 kb
Host smart-4308cb83-0dcc-4a91-970d-4ae22e805e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979664736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.979664736
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.871509141
Short name T293
Test name
Test status
Simulation time 166393071712 ps
CPU time 157.86 seconds
Started Jul 19 04:26:23 PM PDT 24
Finished Jul 19 04:29:12 PM PDT 24
Peak memory 199804 kb
Host smart-4ed3fc64-2f91-449c-9ae9-0806357b6804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871509141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.871509141
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1405162300
Short name T892
Test name
Test status
Simulation time 4862948441 ps
CPU time 272.55 seconds
Started Jul 19 04:26:23 PM PDT 24
Finished Jul 19 04:31:06 PM PDT 24
Peak memory 199892 kb
Host smart-0dbc7fdc-b080-4642-933d-70d47e7eadaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405162300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1405162300
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.956563771
Short name T349
Test name
Test status
Simulation time 4154050920 ps
CPU time 6.27 seconds
Started Jul 19 04:26:01 PM PDT 24
Finished Jul 19 04:26:23 PM PDT 24
Peak memory 198268 kb
Host smart-06449c15-b9d6-425d-8b90-e65d9499d3c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956563771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.956563771
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2258798837
Short name T380
Test name
Test status
Simulation time 51360459890 ps
CPU time 81.67 seconds
Started Jul 19 04:26:07 PM PDT 24
Finished Jul 19 04:27:43 PM PDT 24
Peak memory 199920 kb
Host smart-3b5447c5-48f3-4ed1-a6a5-73ddc84b6e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258798837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2258798837
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2467127475
Short name T370
Test name
Test status
Simulation time 3455039759 ps
CPU time 5.94 seconds
Started Jul 19 04:26:11 PM PDT 24
Finished Jul 19 04:26:31 PM PDT 24
Peak memory 196256 kb
Host smart-b10e9074-5648-4db8-b3e9-ce9a7d890c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467127475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2467127475
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2061076936
Short name T410
Test name
Test status
Simulation time 291064913 ps
CPU time 1.97 seconds
Started Jul 19 04:26:15 PM PDT 24
Finished Jul 19 04:26:30 PM PDT 24
Peak memory 198360 kb
Host smart-9c98c30d-170a-439e-9c3f-0c7aeed0e275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061076936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2061076936
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3789861394
Short name T437
Test name
Test status
Simulation time 168566425202 ps
CPU time 1093.83 seconds
Started Jul 19 04:26:11 PM PDT 24
Finished Jul 19 04:44:40 PM PDT 24
Peak memory 216396 kb
Host smart-bc8125fc-9be2-4e99-9064-64b623f68158
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789861394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3789861394
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2585417914
Short name T449
Test name
Test status
Simulation time 6546166281 ps
CPU time 15.13 seconds
Started Jul 19 04:26:07 PM PDT 24
Finished Jul 19 04:26:37 PM PDT 24
Peak memory 199928 kb
Host smart-01144212-d804-4c8c-b0b1-825aa64f062c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585417914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2585417914
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.757532684
Short name T668
Test name
Test status
Simulation time 70115944088 ps
CPU time 21.02 seconds
Started Jul 19 04:26:25 PM PDT 24
Finished Jul 19 04:26:57 PM PDT 24
Peak memory 199976 kb
Host smart-ab7e4667-3025-473f-9ab8-07aaeadf523b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757532684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.757532684
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.540921564
Short name T442
Test name
Test status
Simulation time 91946805925 ps
CPU time 139.63 seconds
Started Jul 19 04:28:19 PM PDT 24
Finished Jul 19 04:30:40 PM PDT 24
Peak memory 199912 kb
Host smart-79003454-9730-4df3-8b5a-72d3a8d7be92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540921564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.540921564
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3162066544
Short name T333
Test name
Test status
Simulation time 62575641051 ps
CPU time 130.9 seconds
Started Jul 19 04:28:21 PM PDT 24
Finished Jul 19 04:30:35 PM PDT 24
Peak memory 200000 kb
Host smart-4bf64159-cdd7-4a75-9fc2-46e033cf5df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162066544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3162066544
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1821823422
Short name T762
Test name
Test status
Simulation time 185901448442 ps
CPU time 79.01 seconds
Started Jul 19 04:28:18 PM PDT 24
Finished Jul 19 04:29:38 PM PDT 24
Peak memory 199920 kb
Host smart-0e2bfe66-9493-4521-98e5-1b772faf900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821823422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1821823422
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1880082244
Short name T962
Test name
Test status
Simulation time 68002689979 ps
CPU time 29.07 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:28:51 PM PDT 24
Peak memory 199712 kb
Host smart-42a628b3-efcd-4ff3-a482-02044e1fdb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880082244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1880082244
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3767739887
Short name T438
Test name
Test status
Simulation time 34493734023 ps
CPU time 35.36 seconds
Started Jul 19 04:28:19 PM PDT 24
Finished Jul 19 04:28:56 PM PDT 24
Peak memory 199936 kb
Host smart-78a0931f-2882-4526-9185-0b52e13c220e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767739887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3767739887
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.4217789426
Short name T159
Test name
Test status
Simulation time 77023235367 ps
CPU time 56.06 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:29:19 PM PDT 24
Peak memory 199972 kb
Host smart-753ee666-b9e8-4fd3-a31e-a214c3a9505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217789426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.4217789426
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.802197854
Short name T701
Test name
Test status
Simulation time 19791559199 ps
CPU time 26.18 seconds
Started Jul 19 04:28:18 PM PDT 24
Finished Jul 19 04:28:45 PM PDT 24
Peak memory 199840 kb
Host smart-ad46bbb1-e0b4-48c2-8dbd-9eba80c9e5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802197854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.802197854
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2492373007
Short name T575
Test name
Test status
Simulation time 22974911627 ps
CPU time 34.69 seconds
Started Jul 19 04:28:20 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 199988 kb
Host smart-5474edf4-277a-4878-b7c1-acb66a18d032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492373007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2492373007
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1220871890
Short name T1115
Test name
Test status
Simulation time 145421600608 ps
CPU time 98.96 seconds
Started Jul 19 04:28:17 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 199948 kb
Host smart-edfadfeb-0029-4f00-9537-36faccdf9984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220871890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1220871890
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1149003302
Short name T858
Test name
Test status
Simulation time 39081544634 ps
CPU time 152.79 seconds
Started Jul 19 04:28:19 PM PDT 24
Finished Jul 19 04:30:53 PM PDT 24
Peak memory 199984 kb
Host smart-fedd2237-80c6-425c-8772-42b5082f0012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149003302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1149003302
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3868426043
Short name T814
Test name
Test status
Simulation time 39042722 ps
CPU time 0.55 seconds
Started Jul 19 04:26:18 PM PDT 24
Finished Jul 19 04:26:31 PM PDT 24
Peak memory 195356 kb
Host smart-e460e8cc-1d83-41a1-a528-1c629eaed94a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868426043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3868426043
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1006891414
Short name T574
Test name
Test status
Simulation time 68161032281 ps
CPU time 96.15 seconds
Started Jul 19 04:26:03 PM PDT 24
Finished Jul 19 04:27:54 PM PDT 24
Peak memory 199948 kb
Host smart-ffe744b5-b8fe-4625-915b-c4e5f5ee177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006891414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1006891414
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3683797297
Short name T145
Test name
Test status
Simulation time 93793536368 ps
CPU time 36.34 seconds
Started Jul 19 04:26:15 PM PDT 24
Finished Jul 19 04:27:04 PM PDT 24
Peak memory 199928 kb
Host smart-820c7d21-39ea-4d3f-afa7-4de6c082a53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683797297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3683797297
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.552334377
Short name T955
Test name
Test status
Simulation time 65556137932 ps
CPU time 25.56 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:26:58 PM PDT 24
Peak memory 199960 kb
Host smart-e6843859-13e4-488b-84af-4f662dc6c3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552334377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.552334377
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2072316335
Short name T973
Test name
Test status
Simulation time 16159993864 ps
CPU time 11.59 seconds
Started Jul 19 04:26:29 PM PDT 24
Finished Jul 19 04:26:52 PM PDT 24
Peak memory 199908 kb
Host smart-d7d3c3ac-f33d-4021-b866-aaf814f24d4e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072316335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2072316335
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.4195765367
Short name T840
Test name
Test status
Simulation time 88355057856 ps
CPU time 620.62 seconds
Started Jul 19 04:26:18 PM PDT 24
Finished Jul 19 04:36:50 PM PDT 24
Peak memory 199964 kb
Host smart-abda17e4-6a22-4a8c-9035-2faba5c3cb2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4195765367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.4195765367
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1917313585
Short name T1015
Test name
Test status
Simulation time 5722682977 ps
CPU time 10.92 seconds
Started Jul 19 04:26:01 PM PDT 24
Finished Jul 19 04:26:27 PM PDT 24
Peak memory 199972 kb
Host smart-c4692a5e-4080-4b94-8272-6c9921732ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917313585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1917313585
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2407473525
Short name T1033
Test name
Test status
Simulation time 122620235088 ps
CPU time 24.84 seconds
Started Jul 19 04:26:10 PM PDT 24
Finished Jul 19 04:26:50 PM PDT 24
Peak memory 200108 kb
Host smart-9d241781-7d33-448c-9062-c05fb5652901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407473525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2407473525
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.4240878417
Short name T536
Test name
Test status
Simulation time 26636520988 ps
CPU time 799.3 seconds
Started Jul 19 04:26:16 PM PDT 24
Finished Jul 19 04:39:48 PM PDT 24
Peak memory 199884 kb
Host smart-5945e951-6b04-4e41-9506-e82a2a1764e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240878417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.4240878417
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3947456538
Short name T601
Test name
Test status
Simulation time 5248182831 ps
CPU time 42.43 seconds
Started Jul 19 04:26:12 PM PDT 24
Finished Jul 19 04:27:09 PM PDT 24
Peak memory 198284 kb
Host smart-28229699-590a-4533-8316-36c9ec66301f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947456538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3947456538
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2598237693
Short name T150
Test name
Test status
Simulation time 14126538852 ps
CPU time 22.1 seconds
Started Jul 19 04:26:07 PM PDT 24
Finished Jul 19 04:26:44 PM PDT 24
Peak memory 199916 kb
Host smart-eeff09f9-34ba-4b97-962d-d450e5afc3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598237693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2598237693
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1305696806
Short name T458
Test name
Test status
Simulation time 1914685156 ps
CPU time 3.69 seconds
Started Jul 19 04:26:03 PM PDT 24
Finished Jul 19 04:26:22 PM PDT 24
Peak memory 195620 kb
Host smart-16f26382-6342-4a3b-8335-6ebba6152473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305696806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1305696806
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3572557404
Short name T707
Test name
Test status
Simulation time 637315935 ps
CPU time 2.39 seconds
Started Jul 19 04:26:21 PM PDT 24
Finished Jul 19 04:26:34 PM PDT 24
Peak memory 198316 kb
Host smart-37b0c614-53f5-4a58-9fa0-92a8e72b6962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572557404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3572557404
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2183488731
Short name T800
Test name
Test status
Simulation time 213920640549 ps
CPU time 399.77 seconds
Started Jul 19 04:26:12 PM PDT 24
Finished Jul 19 04:33:06 PM PDT 24
Peak memory 199852 kb
Host smart-934fecdd-971b-458b-9e5d-5d4b9cbdb809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183488731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2183488731
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.846083015
Short name T55
Test name
Test status
Simulation time 12372481162 ps
CPU time 147.93 seconds
Started Jul 19 04:26:12 PM PDT 24
Finished Jul 19 04:28:54 PM PDT 24
Peak memory 208292 kb
Host smart-bb2a4781-5195-427e-97b8-2bc84a351388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846083015 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.846083015
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1179113195
Short name T373
Test name
Test status
Simulation time 1403064884 ps
CPU time 4.09 seconds
Started Jul 19 04:26:18 PM PDT 24
Finished Jul 19 04:26:34 PM PDT 24
Peak memory 198384 kb
Host smart-e7ef476e-3d99-420f-97d6-88a26f876362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179113195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1179113195
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2172772202
Short name T278
Test name
Test status
Simulation time 70541721225 ps
CPU time 17.14 seconds
Started Jul 19 04:26:03 PM PDT 24
Finished Jul 19 04:26:35 PM PDT 24
Peak memory 199920 kb
Host smart-56691d37-150d-45b7-b9fd-6f08f4842612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172772202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2172772202
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1674172125
Short name T1099
Test name
Test status
Simulation time 17994162571 ps
CPU time 11.31 seconds
Started Jul 19 04:28:17 PM PDT 24
Finished Jul 19 04:28:30 PM PDT 24
Peak memory 199900 kb
Host smart-3ad7d889-f564-4508-99bc-11676b92cce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674172125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1674172125
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3807292661
Short name T994
Test name
Test status
Simulation time 37184609343 ps
CPU time 13.71 seconds
Started Jul 19 04:28:31 PM PDT 24
Finished Jul 19 04:28:49 PM PDT 24
Peak memory 197524 kb
Host smart-0882f0a2-5bd7-4214-8f88-6c3821793de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807292661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3807292661
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1918810552
Short name T496
Test name
Test status
Simulation time 60192032572 ps
CPU time 23.55 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 199872 kb
Host smart-7de38d18-51a4-4bac-b7f6-744387fa1506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918810552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1918810552
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.389194394
Short name T233
Test name
Test status
Simulation time 50778607451 ps
CPU time 24.42 seconds
Started Jul 19 04:28:28 PM PDT 24
Finished Jul 19 04:28:55 PM PDT 24
Peak memory 199916 kb
Host smart-d4198889-845c-4bd1-9a6e-3f20a410f86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389194394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.389194394
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3203511113
Short name T289
Test name
Test status
Simulation time 69591658897 ps
CPU time 27.46 seconds
Started Jul 19 04:28:28 PM PDT 24
Finished Jul 19 04:28:58 PM PDT 24
Peak memory 199348 kb
Host smart-7c7b9542-8a9c-4854-a7bd-61bd620609d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203511113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3203511113
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1460869469
Short name T1116
Test name
Test status
Simulation time 107015786135 ps
CPU time 142.17 seconds
Started Jul 19 04:28:31 PM PDT 24
Finished Jul 19 04:30:58 PM PDT 24
Peak memory 199928 kb
Host smart-df15312b-2df9-45ff-b607-72bda80e58a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460869469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1460869469
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1312089742
Short name T662
Test name
Test status
Simulation time 111344179864 ps
CPU time 47.17 seconds
Started Jul 19 04:28:30 PM PDT 24
Finished Jul 19 04:29:22 PM PDT 24
Peak memory 199820 kb
Host smart-4969a3b3-cd8e-4d79-8f08-d6785eea3678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312089742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1312089742
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1827180645
Short name T408
Test name
Test status
Simulation time 43314233 ps
CPU time 0.58 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:26:33 PM PDT 24
Peak memory 194972 kb
Host smart-156fd318-6d2f-44c5-bfb4-542e96136fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827180645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1827180645
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.27814469
Short name T537
Test name
Test status
Simulation time 41818001469 ps
CPU time 56.99 seconds
Started Jul 19 04:26:00 PM PDT 24
Finished Jul 19 04:27:12 PM PDT 24
Peak memory 200276 kb
Host smart-3d1b7006-68a5-4e60-9e5f-6995acea4912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27814469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.27814469
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1624834550
Short name T1129
Test name
Test status
Simulation time 85705972130 ps
CPU time 32.3 seconds
Started Jul 19 04:26:08 PM PDT 24
Finished Jul 19 04:26:55 PM PDT 24
Peak memory 199804 kb
Host smart-a3063ec1-b1b8-4d6c-9c59-23e8ce49bf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624834550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1624834550
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.625336727
Short name T748
Test name
Test status
Simulation time 67802337715 ps
CPU time 16.75 seconds
Started Jul 19 04:26:12 PM PDT 24
Finished Jul 19 04:26:43 PM PDT 24
Peak memory 199964 kb
Host smart-fd2beeda-f479-4657-9818-4ac4588eedf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625336727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.625336727
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1630015035
Short name T258
Test name
Test status
Simulation time 7679217247 ps
CPU time 1.81 seconds
Started Jul 19 04:26:15 PM PDT 24
Finished Jul 19 04:26:30 PM PDT 24
Peak memory 199612 kb
Host smart-a5e678a0-4a32-4007-a350-dc961db68bfc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630015035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1630015035
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.668048014
Short name T535
Test name
Test status
Simulation time 92972367728 ps
CPU time 636.4 seconds
Started Jul 19 04:26:09 PM PDT 24
Finished Jul 19 04:37:00 PM PDT 24
Peak memory 199948 kb
Host smart-cea66f24-8529-4bdc-8da8-3948012cb25c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668048014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.668048014
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3034175226
Short name T959
Test name
Test status
Simulation time 6086803276 ps
CPU time 3.67 seconds
Started Jul 19 04:26:21 PM PDT 24
Finished Jul 19 04:26:36 PM PDT 24
Peak memory 197372 kb
Host smart-f9ee7f95-d9e7-49d3-983e-10c64541f1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034175226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3034175226
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.855308112
Short name T1134
Test name
Test status
Simulation time 16249568177 ps
CPU time 12.25 seconds
Started Jul 19 04:26:14 PM PDT 24
Finished Jul 19 04:26:40 PM PDT 24
Peak memory 198040 kb
Host smart-20687dc9-d71a-4e82-a762-a531aa95be55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855308112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.855308112
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.829426542
Short name T272
Test name
Test status
Simulation time 5762050506 ps
CPU time 62.83 seconds
Started Jul 19 04:26:10 PM PDT 24
Finished Jul 19 04:27:28 PM PDT 24
Peak memory 199984 kb
Host smart-efe51777-dedc-4d05-b3a1-702ff869b360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829426542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.829426542
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3100239451
Short name T1094
Test name
Test status
Simulation time 4007978794 ps
CPU time 6.53 seconds
Started Jul 19 04:26:24 PM PDT 24
Finished Jul 19 04:26:41 PM PDT 24
Peak memory 198104 kb
Host smart-a7792f6d-36b2-465e-9649-fe3c14d562a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100239451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3100239451
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3527693464
Short name T772
Test name
Test status
Simulation time 50935874563 ps
CPU time 21.18 seconds
Started Jul 19 04:26:28 PM PDT 24
Finished Jul 19 04:27:01 PM PDT 24
Peak memory 199820 kb
Host smart-3501ef1f-c8c0-4c01-ab3f-35e6a74690fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527693464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3527693464
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.4055369128
Short name T1104
Test name
Test status
Simulation time 573814646 ps
CPU time 1.1 seconds
Started Jul 19 04:26:10 PM PDT 24
Finished Jul 19 04:26:26 PM PDT 24
Peak memory 195648 kb
Host smart-82930bf0-08c2-4337-aa47-959dc91cecc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055369128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.4055369128
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.745179251
Short name T768
Test name
Test status
Simulation time 447666085 ps
CPU time 1.17 seconds
Started Jul 19 04:26:10 PM PDT 24
Finished Jul 19 04:26:26 PM PDT 24
Peak memory 198564 kb
Host smart-f7b51657-9224-4703-b8a8-e5ccafa9b2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745179251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.745179251
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3386688948
Short name T904
Test name
Test status
Simulation time 98449271545 ps
CPU time 1039.57 seconds
Started Jul 19 04:26:11 PM PDT 24
Finished Jul 19 04:43:45 PM PDT 24
Peak memory 228536 kb
Host smart-24ed17c8-0835-4049-afb1-d45a6181dc97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386688948 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3386688948
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3659273370
Short name T616
Test name
Test status
Simulation time 978511759 ps
CPU time 1.25 seconds
Started Jul 19 04:26:15 PM PDT 24
Finished Jul 19 04:26:29 PM PDT 24
Peak memory 198236 kb
Host smart-73e40241-bfa4-45c9-a97a-2e5e5c291f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659273370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3659273370
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1346163607
Short name T525
Test name
Test status
Simulation time 160980192751 ps
CPU time 97.21 seconds
Started Jul 19 04:26:08 PM PDT 24
Finished Jul 19 04:28:00 PM PDT 24
Peak memory 199860 kb
Host smart-77fd505d-2b74-4e66-81fb-c347a05d560f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346163607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1346163607
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1242951790
Short name T399
Test name
Test status
Simulation time 17172823553 ps
CPU time 16.43 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:28:50 PM PDT 24
Peak memory 199844 kb
Host smart-65dbd538-66ba-41e5-aead-c10c53514a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242951790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1242951790
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1113848766
Short name T474
Test name
Test status
Simulation time 16470434317 ps
CPU time 23.77 seconds
Started Jul 19 04:28:30 PM PDT 24
Finished Jul 19 04:28:59 PM PDT 24
Peak memory 200000 kb
Host smart-bb40281b-dd5a-496d-b28f-9baef2686239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113848766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1113848766
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.444329539
Short name T6
Test name
Test status
Simulation time 124849726185 ps
CPU time 55.22 seconds
Started Jul 19 04:28:27 PM PDT 24
Finished Jul 19 04:29:25 PM PDT 24
Peak memory 199960 kb
Host smart-edb5369d-1ac8-4aac-9082-bb1cc5b4a1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444329539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.444329539
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3758218771
Short name T856
Test name
Test status
Simulation time 81756807810 ps
CPU time 145.44 seconds
Started Jul 19 04:28:30 PM PDT 24
Finished Jul 19 04:31:00 PM PDT 24
Peak memory 199932 kb
Host smart-2f5b82b7-699d-4a3e-9ed9-e15fcb6346ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758218771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3758218771
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.979431687
Short name T225
Test name
Test status
Simulation time 14600652631 ps
CPU time 22.24 seconds
Started Jul 19 04:28:30 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 199648 kb
Host smart-b9993df6-7d72-4329-bf4d-e1d41a15ccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979431687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.979431687
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3255236985
Short name T238
Test name
Test status
Simulation time 96860971433 ps
CPU time 39.12 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:29:13 PM PDT 24
Peak memory 199900 kb
Host smart-7b79a7cf-dae9-4da1-9345-537643bfa506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255236985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3255236985
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3056546536
Short name T820
Test name
Test status
Simulation time 102648707502 ps
CPU time 16.46 seconds
Started Jul 19 04:28:28 PM PDT 24
Finished Jul 19 04:28:48 PM PDT 24
Peak memory 199884 kb
Host smart-33b921e1-4db5-43bb-a067-2f9c80b4f0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056546536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3056546536
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3621853501
Short name T685
Test name
Test status
Simulation time 67752038933 ps
CPU time 36.64 seconds
Started Jul 19 04:30:17 PM PDT 24
Finished Jul 19 04:31:00 PM PDT 24
Peak memory 199612 kb
Host smart-467cac31-b8a0-4c55-a809-46105976f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621853501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3621853501
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.720928938
Short name T1159
Test name
Test status
Simulation time 79120639370 ps
CPU time 31.92 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:29:06 PM PDT 24
Peak memory 200068 kb
Host smart-32cb70f5-1628-4a89-95ef-d06700203fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720928938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.720928938
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3845407936
Short name T485
Test name
Test status
Simulation time 12199954 ps
CPU time 0.6 seconds
Started Jul 19 04:28:52 PM PDT 24
Finished Jul 19 04:28:55 PM PDT 24
Peak memory 195356 kb
Host smart-491e1dc0-21b4-4f9c-9468-89a63f4e0ae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845407936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3845407936
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3972174473
Short name T646
Test name
Test status
Simulation time 111510755792 ps
CPU time 250.1 seconds
Started Jul 19 04:26:29 PM PDT 24
Finished Jul 19 04:30:51 PM PDT 24
Peak memory 199980 kb
Host smart-4c22bfe4-0f26-480f-8be6-25f2641fb9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972174473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3972174473
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1070456151
Short name T1147
Test name
Test status
Simulation time 70082994699 ps
CPU time 102.8 seconds
Started Jul 19 04:26:16 PM PDT 24
Finished Jul 19 04:28:12 PM PDT 24
Peak memory 199868 kb
Host smart-a45d3144-6cb9-4be9-88d5-dee74752e907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070456151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1070456151
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_intr.1773544006
Short name T511
Test name
Test status
Simulation time 9371571057 ps
CPU time 14.17 seconds
Started Jul 19 04:26:11 PM PDT 24
Finished Jul 19 04:26:40 PM PDT 24
Peak memory 196560 kb
Host smart-96f0ac68-8be6-460b-9d0b-2a2a1f774365
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773544006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1773544006
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.4182881231
Short name T928
Test name
Test status
Simulation time 102511829768 ps
CPU time 569.93 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:36:03 PM PDT 24
Peak memory 199916 kb
Host smart-52bcd363-163c-4a96-9cfe-91fd59ab3f4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182881231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.4182881231
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.991265437
Short name T1019
Test name
Test status
Simulation time 1205337666 ps
CPU time 1.13 seconds
Started Jul 19 04:26:17 PM PDT 24
Finished Jul 19 04:26:31 PM PDT 24
Peak memory 195688 kb
Host smart-02ef45ba-b74d-48f9-831d-38f0ba25ec26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991265437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.991265437
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1922280344
Short name T287
Test name
Test status
Simulation time 219205263426 ps
CPU time 90.2 seconds
Started Jul 19 04:26:15 PM PDT 24
Finished Jul 19 04:27:59 PM PDT 24
Peak memory 200384 kb
Host smart-c1162dc2-8da7-47b3-87c2-25f4c5c05a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922280344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1922280344
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1630679178
Short name T696
Test name
Test status
Simulation time 10105319496 ps
CPU time 118.07 seconds
Started Jul 19 04:26:12 PM PDT 24
Finished Jul 19 04:28:24 PM PDT 24
Peak memory 200060 kb
Host smart-499fc80a-7364-4baf-b25b-f1d35a719b25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630679178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1630679178
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.4236050960
Short name T998
Test name
Test status
Simulation time 3402881780 ps
CPU time 6.01 seconds
Started Jul 19 04:26:13 PM PDT 24
Finished Jul 19 04:26:33 PM PDT 24
Peak memory 198848 kb
Host smart-84c617aa-9d01-4c19-ab9e-f965fc04452d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236050960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4236050960
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1543251010
Short name T917
Test name
Test status
Simulation time 84567357924 ps
CPU time 34.17 seconds
Started Jul 19 04:26:14 PM PDT 24
Finished Jul 19 04:27:01 PM PDT 24
Peak memory 199988 kb
Host smart-4bd420ef-e73e-4c7e-9f08-4ae72cd1937c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543251010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1543251010
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.4030634577
Short name T828
Test name
Test status
Simulation time 38576099964 ps
CPU time 14.7 seconds
Started Jul 19 04:26:17 PM PDT 24
Finished Jul 19 04:26:44 PM PDT 24
Peak memory 196344 kb
Host smart-b9fb0cf8-e7c3-4205-90eb-896c6b87d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030634577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.4030634577
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1766190734
Short name T462
Test name
Test status
Simulation time 5290684307 ps
CPU time 11.03 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:26:45 PM PDT 24
Peak memory 199800 kb
Host smart-ff72a156-08a1-4caf-8264-1c005e13a472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766190734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1766190734
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2780839672
Short name T540
Test name
Test status
Simulation time 78858462964 ps
CPU time 942 seconds
Started Jul 19 04:26:09 PM PDT 24
Finished Jul 19 04:42:05 PM PDT 24
Peak memory 216652 kb
Host smart-409916c1-a4f3-4178-a4e2-36e9032b36bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780839672 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2780839672
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1987454627
Short name T886
Test name
Test status
Simulation time 3207936860 ps
CPU time 1.88 seconds
Started Jul 19 04:26:10 PM PDT 24
Finished Jul 19 04:26:26 PM PDT 24
Peak memory 198888 kb
Host smart-841e6ce9-7f09-4923-9cf3-1ba349e85b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987454627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1987454627
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2070338513
Short name T420
Test name
Test status
Simulation time 122666816995 ps
CPU time 232.03 seconds
Started Jul 19 04:26:15 PM PDT 24
Finished Jul 19 04:30:21 PM PDT 24
Peak memory 199892 kb
Host smart-4a406bdc-2b7d-440d-8057-002c88a7649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070338513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2070338513
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2758141475
Short name T71
Test name
Test status
Simulation time 6386966996 ps
CPU time 15.01 seconds
Started Jul 19 04:28:28 PM PDT 24
Finished Jul 19 04:28:46 PM PDT 24
Peak memory 199960 kb
Host smart-38a5e88f-c5b1-4264-99c2-c1168aa3fea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758141475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2758141475
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3951211888
Short name T1007
Test name
Test status
Simulation time 44431134627 ps
CPU time 20.75 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:28:53 PM PDT 24
Peak memory 200044 kb
Host smart-f0abaa9c-c2f4-4732-97a8-bd6bf28c5488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951211888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3951211888
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3177166037
Short name T1047
Test name
Test status
Simulation time 20423361867 ps
CPU time 54.23 seconds
Started Jul 19 04:28:27 PM PDT 24
Finished Jul 19 04:29:24 PM PDT 24
Peak memory 199928 kb
Host smart-795c3b58-15d6-4170-a7b3-89e291673c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177166037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3177166037
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1463914882
Short name T259
Test name
Test status
Simulation time 106773818457 ps
CPU time 82.61 seconds
Started Jul 19 04:28:30 PM PDT 24
Finished Jul 19 04:29:57 PM PDT 24
Peak memory 199960 kb
Host smart-01f79b9a-f9b6-48d9-b849-d98b4666d008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463914882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1463914882
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1771644327
Short name T224
Test name
Test status
Simulation time 20210584749 ps
CPU time 31.57 seconds
Started Jul 19 04:28:28 PM PDT 24
Finished Jul 19 04:29:02 PM PDT 24
Peak memory 199984 kb
Host smart-90f4e4d2-f532-49ef-a7ce-9975ac7eab93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771644327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1771644327
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1835104486
Short name T180
Test name
Test status
Simulation time 66992851658 ps
CPU time 52.33 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:29:25 PM PDT 24
Peak memory 199988 kb
Host smart-9404cb43-0487-4dc4-ab74-0699e24cf140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835104486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1835104486
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.692706693
Short name T969
Test name
Test status
Simulation time 21298379451 ps
CPU time 32.35 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:29:06 PM PDT 24
Peak memory 199968 kb
Host smart-c5d88206-a599-4ca3-87bc-c5f3d8b7a1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692706693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.692706693
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1783830256
Short name T326
Test name
Test status
Simulation time 28560489104 ps
CPU time 35.37 seconds
Started Jul 19 04:28:28 PM PDT 24
Finished Jul 19 04:29:07 PM PDT 24
Peak memory 199944 kb
Host smart-5f1641f8-0d38-4356-bbf6-c52137068674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783830256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1783830256
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1024581687
Short name T247
Test name
Test status
Simulation time 22962066565 ps
CPU time 34.26 seconds
Started Jul 19 04:28:28 PM PDT 24
Finished Jul 19 04:29:05 PM PDT 24
Peak memory 199912 kb
Host smart-e28ef138-af5c-4894-9794-91bb5e0adc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024581687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1024581687
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.896142290
Short name T155
Test name
Test status
Simulation time 31715832067 ps
CPU time 22.28 seconds
Started Jul 19 04:28:30 PM PDT 24
Finished Jul 19 04:28:57 PM PDT 24
Peak memory 199928 kb
Host smart-25b03854-cba3-4771-ae2d-73c0b68125c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896142290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.896142290
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2009949171
Short name T883
Test name
Test status
Simulation time 21320628 ps
CPU time 0.56 seconds
Started Jul 19 04:26:27 PM PDT 24
Finished Jul 19 04:26:40 PM PDT 24
Peak memory 195448 kb
Host smart-5ad6b896-1dda-425c-bf12-c8ab3549176e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009949171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2009949171
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.224085584
Short name T1023
Test name
Test status
Simulation time 58254877805 ps
CPU time 25.16 seconds
Started Jul 19 04:26:14 PM PDT 24
Finished Jul 19 04:26:52 PM PDT 24
Peak memory 199968 kb
Host smart-8db2a8b6-d291-4790-bd5f-b637fbad9bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224085584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.224085584
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.489970331
Short name T915
Test name
Test status
Simulation time 122959163249 ps
CPU time 159.74 seconds
Started Jul 19 04:26:15 PM PDT 24
Finished Jul 19 04:29:09 PM PDT 24
Peak memory 199948 kb
Host smart-85e65b1e-69d3-45e9-9d41-746e71d37653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489970331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.489970331
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1136824899
Short name T322
Test name
Test status
Simulation time 265641276038 ps
CPU time 337.8 seconds
Started Jul 19 04:26:20 PM PDT 24
Finished Jul 19 04:32:09 PM PDT 24
Peak memory 197780 kb
Host smart-8d387e8b-7fb1-4136-b4b6-b6962eda19a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136824899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1136824899
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2561442132
Short name T869
Test name
Test status
Simulation time 97748474075 ps
CPU time 885.02 seconds
Started Jul 19 04:26:21 PM PDT 24
Finished Jul 19 04:41:17 PM PDT 24
Peak memory 199916 kb
Host smart-b496b26a-187a-48bb-9489-a71d9fe21043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2561442132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2561442132
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3958809054
Short name T1166
Test name
Test status
Simulation time 1368016102 ps
CPU time 1.07 seconds
Started Jul 19 04:26:26 PM PDT 24
Finished Jul 19 04:26:39 PM PDT 24
Peak memory 195444 kb
Host smart-4f178168-2fce-4376-902d-09add985dcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958809054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3958809054
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.973571613
Short name T531
Test name
Test status
Simulation time 26707787414 ps
CPU time 36.69 seconds
Started Jul 19 04:26:12 PM PDT 24
Finished Jul 19 04:27:03 PM PDT 24
Peak memory 197952 kb
Host smart-c418c0cc-965d-4899-b6c5-e897b41aa882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973571613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.973571613
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.96388748
Short name T360
Test name
Test status
Simulation time 10956713092 ps
CPU time 241.24 seconds
Started Jul 19 04:26:30 PM PDT 24
Finished Jul 19 04:30:43 PM PDT 24
Peak memory 199956 kb
Host smart-680e855b-df50-49d2-93da-36dec641f57c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96388748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.96388748
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.607993816
Short name T572
Test name
Test status
Simulation time 6982487342 ps
CPU time 57.99 seconds
Started Jul 19 04:26:13 PM PDT 24
Finished Jul 19 04:27:25 PM PDT 24
Peak memory 198744 kb
Host smart-8ec3ff86-69d1-4255-b24e-fcc377869973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607993816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.607993816
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3751161734
Short name T495
Test name
Test status
Simulation time 119259423354 ps
CPU time 87.82 seconds
Started Jul 19 04:26:09 PM PDT 24
Finished Jul 19 04:27:51 PM PDT 24
Peak memory 199884 kb
Host smart-f479dd77-332f-4a3d-ac65-013074303a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751161734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3751161734
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3946166423
Short name T632
Test name
Test status
Simulation time 42480635599 ps
CPU time 9.91 seconds
Started Jul 19 04:26:15 PM PDT 24
Finished Jul 19 04:26:38 PM PDT 24
Peak memory 195868 kb
Host smart-28496d0d-c683-4aea-bf51-f88110ca8021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946166423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3946166423
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3962652283
Short name T456
Test name
Test status
Simulation time 484912561 ps
CPU time 1.87 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:26:36 PM PDT 24
Peak memory 198216 kb
Host smart-d56c2bd8-c1d7-4bc7-a543-5004c62b4e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962652283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3962652283
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1826929740
Short name T402
Test name
Test status
Simulation time 1415336949 ps
CPU time 1.56 seconds
Started Jul 19 04:26:20 PM PDT 24
Finished Jul 19 04:26:34 PM PDT 24
Peak memory 198820 kb
Host smart-fcc5660f-30d1-479e-ac69-f4609f47934c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826929740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1826929740
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.304744312
Short name T290
Test name
Test status
Simulation time 41866891752 ps
CPU time 26.97 seconds
Started Jul 19 04:26:14 PM PDT 24
Finished Jul 19 04:26:54 PM PDT 24
Peak memory 199968 kb
Host smart-add4be5c-5f07-4366-9805-70f07e6c9818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304744312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.304744312
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.581132283
Short name T708
Test name
Test status
Simulation time 96979535276 ps
CPU time 40.47 seconds
Started Jul 19 04:30:08 PM PDT 24
Finished Jul 19 04:30:59 PM PDT 24
Peak memory 198192 kb
Host smart-74c4b23a-f139-46fc-b90d-b40e34c7426a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581132283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.581132283
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1564818109
Short name T414
Test name
Test status
Simulation time 21435488220 ps
CPU time 16.87 seconds
Started Jul 19 04:28:27 PM PDT 24
Finished Jul 19 04:28:46 PM PDT 24
Peak memory 199988 kb
Host smart-68a7624a-4df4-4f86-b9a4-6e4fe6cad9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564818109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1564818109
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1030397794
Short name T634
Test name
Test status
Simulation time 13841790355 ps
CPU time 29.56 seconds
Started Jul 19 04:28:31 PM PDT 24
Finished Jul 19 04:29:05 PM PDT 24
Peak memory 200000 kb
Host smart-bf7f5ac8-c6a4-49ef-bb15-7219da0c60d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030397794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1030397794
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.4294268717
Short name T1119
Test name
Test status
Simulation time 21951255524 ps
CPU time 18.36 seconds
Started Jul 19 04:28:30 PM PDT 24
Finished Jul 19 04:28:53 PM PDT 24
Peak memory 199980 kb
Host smart-46563cd6-b9e3-49ec-9142-3eee62758a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294268717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.4294268717
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3190498536
Short name T1071
Test name
Test status
Simulation time 20244031744 ps
CPU time 30.9 seconds
Started Jul 19 04:28:30 PM PDT 24
Finished Jul 19 04:29:06 PM PDT 24
Peak memory 199936 kb
Host smart-e1f9bd65-3e34-4c1b-8982-62c558e472cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190498536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3190498536
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2934286906
Short name T895
Test name
Test status
Simulation time 39734226553 ps
CPU time 17.54 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:28:51 PM PDT 24
Peak memory 199904 kb
Host smart-4f527242-3a65-4144-a1bd-dfa68d657aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934286906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2934286906
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2473691431
Short name T38
Test name
Test status
Simulation time 311286723517 ps
CPU time 71.55 seconds
Started Jul 19 04:28:31 PM PDT 24
Finished Jul 19 04:29:47 PM PDT 24
Peak memory 199904 kb
Host smart-616f7407-841d-48eb-9e23-407044a05dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473691431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2473691431
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.32548947
Short name T623
Test name
Test status
Simulation time 88226052657 ps
CPU time 123.27 seconds
Started Jul 19 04:28:32 PM PDT 24
Finished Jul 19 04:30:39 PM PDT 24
Peak memory 199976 kb
Host smart-f3c705f0-53b7-4f27-98a9-772268646691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32548947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.32548947
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.4278010973
Short name T431
Test name
Test status
Simulation time 30047767781 ps
CPU time 8.99 seconds
Started Jul 19 04:28:30 PM PDT 24
Finished Jul 19 04:28:43 PM PDT 24
Peak memory 199020 kb
Host smart-2e34c8be-c867-4c03-bd20-059721d328ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278010973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.4278010973
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1825474931
Short name T619
Test name
Test status
Simulation time 12212169 ps
CPU time 0.55 seconds
Started Jul 19 04:26:25 PM PDT 24
Finished Jul 19 04:26:37 PM PDT 24
Peak memory 195632 kb
Host smart-009535ce-3154-4a70-94d2-9b345fea592e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825474931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1825474931
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3978106002
Short name T556
Test name
Test status
Simulation time 202548604978 ps
CPU time 96.76 seconds
Started Jul 19 04:26:28 PM PDT 24
Finished Jul 19 04:28:17 PM PDT 24
Peak memory 199984 kb
Host smart-9a52f719-d0c2-4258-98b6-c515d7231ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978106002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3978106002
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1055376181
Short name T1072
Test name
Test status
Simulation time 116371268021 ps
CPU time 121.11 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:28:44 PM PDT 24
Peak memory 199872 kb
Host smart-bd54933b-7f2c-4d43-8ad0-98918145b212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055376181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1055376181
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_intr.2186819952
Short name T1083
Test name
Test status
Simulation time 10622238983 ps
CPU time 18.68 seconds
Started Jul 19 04:26:25 PM PDT 24
Finished Jul 19 04:26:56 PM PDT 24
Peak memory 199960 kb
Host smart-27c2781b-07ad-4583-901c-c1889a08123f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186819952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2186819952
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1947667700
Short name T1169
Test name
Test status
Simulation time 105198114668 ps
CPU time 643.63 seconds
Started Jul 19 04:26:24 PM PDT 24
Finished Jul 19 04:37:19 PM PDT 24
Peak memory 199920 kb
Host smart-da6d5e1e-3a37-491e-9998-a7e8c3e6571d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1947667700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1947667700
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2597541500
Short name T480
Test name
Test status
Simulation time 2484759257 ps
CPU time 1.76 seconds
Started Jul 19 04:26:28 PM PDT 24
Finished Jul 19 04:26:42 PM PDT 24
Peak memory 198812 kb
Host smart-5dd17235-2b9c-4f04-96da-cc3972319ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597541500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2597541500
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.53999672
Short name T851
Test name
Test status
Simulation time 236740852333 ps
CPU time 86.84 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:28:00 PM PDT 24
Peak memory 208260 kb
Host smart-5997eeab-a00f-437d-9f43-f80c77df7896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53999672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.53999672
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.1752219306
Short name T861
Test name
Test status
Simulation time 2466469345 ps
CPU time 80.1 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:27:54 PM PDT 24
Peak memory 199976 kb
Host smart-d81683fb-bfc9-44d4-9ab4-b89bee4fe782
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1752219306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1752219306
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.925404079
Short name T403
Test name
Test status
Simulation time 4231581768 ps
CPU time 17.78 seconds
Started Jul 19 04:26:23 PM PDT 24
Finished Jul 19 04:26:52 PM PDT 24
Peak memory 198996 kb
Host smart-3080d4f8-cc6e-459a-adc7-e0fdf38bbe3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=925404079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.925404079
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3889341570
Short name T989
Test name
Test status
Simulation time 96534771883 ps
CPU time 130.07 seconds
Started Jul 19 04:26:21 PM PDT 24
Finished Jul 19 04:28:42 PM PDT 24
Peak memory 200020 kb
Host smart-caff53ac-78c4-4245-a611-37a34043f96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889341570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3889341570
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1865079277
Short name T529
Test name
Test status
Simulation time 39653136725 ps
CPU time 14.56 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:26:47 PM PDT 24
Peak memory 196120 kb
Host smart-68829fbf-bc68-4713-b3bf-d6473ea316bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865079277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1865079277
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.556510866
Short name T273
Test name
Test status
Simulation time 849767644 ps
CPU time 2.27 seconds
Started Jul 19 04:26:20 PM PDT 24
Finished Jul 19 04:26:34 PM PDT 24
Peak memory 199876 kb
Host smart-8e590091-b82a-4a01-a7e4-fd28c5ebd2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556510866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.556510866
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2281702202
Short name T133
Test name
Test status
Simulation time 518809268950 ps
CPU time 703.12 seconds
Started Jul 19 04:26:29 PM PDT 24
Finished Jul 19 04:38:24 PM PDT 24
Peak memory 199960 kb
Host smart-cd055d83-80b8-4d86-930d-6ccaa2b92e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281702202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2281702202
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1898820770
Short name T114
Test name
Test status
Simulation time 22609662670 ps
CPU time 236.34 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:30:39 PM PDT 24
Peak memory 208308 kb
Host smart-3ca856fa-a573-4490-9cbc-9e131c059b20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898820770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1898820770
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1701056860
Short name T533
Test name
Test status
Simulation time 1061281667 ps
CPU time 2.36 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:26:45 PM PDT 24
Peak memory 198344 kb
Host smart-fe2e76b2-d74e-4604-83d7-15251e76e79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701056860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1701056860
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.189480277
Short name T519
Test name
Test status
Simulation time 10616900377 ps
CPU time 4.99 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:26:48 PM PDT 24
Peak memory 199808 kb
Host smart-a5e2b274-12f2-45ce-9f06-768d63463bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189480277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.189480277
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1188426292
Short name T551
Test name
Test status
Simulation time 85535525587 ps
CPU time 54.32 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:29:26 PM PDT 24
Peak memory 199936 kb
Host smart-90a7efaa-ab93-4b81-8396-68f2d77f5240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188426292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1188426292
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2486434454
Short name T1067
Test name
Test status
Simulation time 171573544183 ps
CPU time 62.42 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:29:36 PM PDT 24
Peak memory 199884 kb
Host smart-e7831571-08d6-426b-8333-9a46fbd9ea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486434454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2486434454
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.454490349
Short name T232
Test name
Test status
Simulation time 59715574857 ps
CPU time 22.3 seconds
Started Jul 19 04:30:16 PM PDT 24
Finished Jul 19 04:30:46 PM PDT 24
Peak memory 199660 kb
Host smart-66ffa00c-92df-43f0-a7e2-6a0a3dd8cb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454490349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.454490349
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.4106645658
Short name T872
Test name
Test status
Simulation time 109216304130 ps
CPU time 257.4 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:32:51 PM PDT 24
Peak memory 200076 kb
Host smart-9a7029de-3efe-43fb-a00f-1c8a12e960f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106645658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.4106645658
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3099911778
Short name T1091
Test name
Test status
Simulation time 101253829783 ps
CPU time 140.5 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:30:55 PM PDT 24
Peak memory 199956 kb
Host smart-07cfb2ba-a182-4368-bcec-c322db0bb1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099911778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3099911778
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.692535895
Short name T413
Test name
Test status
Simulation time 56739578858 ps
CPU time 85.26 seconds
Started Jul 19 04:28:29 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 199960 kb
Host smart-e4bffb17-fa55-41b8-ba04-48a5b9460c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692535895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.692535895
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3361098164
Short name T1109
Test name
Test status
Simulation time 64524524202 ps
CPU time 57.71 seconds
Started Jul 19 04:28:27 PM PDT 24
Finished Jul 19 04:29:26 PM PDT 24
Peak memory 199916 kb
Host smart-842fa2f5-ce3c-4e5f-8232-b7287cfdab6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361098164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3361098164
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.268335797
Short name T471
Test name
Test status
Simulation time 110281532878 ps
CPU time 51.34 seconds
Started Jul 19 04:28:30 PM PDT 24
Finished Jul 19 04:29:26 PM PDT 24
Peak memory 199712 kb
Host smart-06e48a4c-d5dd-4e90-8b2c-132f70553fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268335797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.268335797
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2394884458
Short name T194
Test name
Test status
Simulation time 27185834098 ps
CPU time 10.53 seconds
Started Jul 19 04:28:31 PM PDT 24
Finished Jul 19 04:28:46 PM PDT 24
Peak memory 200000 kb
Host smart-b5bc76d2-cba0-4f14-b4f5-fbc0710aec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394884458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2394884458
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3763679771
Short name T427
Test name
Test status
Simulation time 31618470 ps
CPU time 0.55 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:25:38 PM PDT 24
Peak memory 195376 kb
Host smart-264befe2-b991-4c6f-9cca-83f4521dd92d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763679771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3763679771
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2630268562
Short name T898
Test name
Test status
Simulation time 35070810218 ps
CPU time 15.03 seconds
Started Jul 19 04:25:25 PM PDT 24
Finished Jul 19 04:25:59 PM PDT 24
Peak memory 199924 kb
Host smart-ee6b8822-62b3-45de-961a-b8a16babb099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630268562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2630268562
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.783349170
Short name T609
Test name
Test status
Simulation time 206373214213 ps
CPU time 149.32 seconds
Started Jul 19 04:25:29 PM PDT 24
Finished Jul 19 04:28:16 PM PDT 24
Peak memory 199680 kb
Host smart-210c7fbe-7e24-496f-8e3b-d56dfebffc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783349170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.783349170
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1008390955
Short name T393
Test name
Test status
Simulation time 123803987758 ps
CPU time 33.75 seconds
Started Jul 19 04:25:17 PM PDT 24
Finished Jul 19 04:26:10 PM PDT 24
Peak memory 199888 kb
Host smart-4367c310-7487-4318-9794-84ed44e348cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008390955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1008390955
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3482585121
Short name T534
Test name
Test status
Simulation time 29897117639 ps
CPU time 48.28 seconds
Started Jul 19 04:25:21 PM PDT 24
Finished Jul 19 04:26:29 PM PDT 24
Peak memory 199944 kb
Host smart-94587500-ebe8-4dee-a30d-dbd31643b1a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482585121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3482585121
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2460238714
Short name T498
Test name
Test status
Simulation time 109379808521 ps
CPU time 882.85 seconds
Started Jul 19 04:25:15 PM PDT 24
Finished Jul 19 04:40:18 PM PDT 24
Peak memory 199892 kb
Host smart-cb126de7-666e-4f28-aa09-d87da68ca0c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460238714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2460238714
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.513966202
Short name T342
Test name
Test status
Simulation time 6853563144 ps
CPU time 10.73 seconds
Started Jul 19 04:25:19 PM PDT 24
Finished Jul 19 04:25:49 PM PDT 24
Peak memory 197940 kb
Host smart-ae0d5556-6999-4f52-95ea-aa6a48f5faf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513966202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.513966202
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3720837508
Short name T482
Test name
Test status
Simulation time 56785561629 ps
CPU time 32.2 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:26:10 PM PDT 24
Peak memory 198076 kb
Host smart-e6e5e65b-c241-4800-9a46-0a2add79f929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720837508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3720837508
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2196891523
Short name T526
Test name
Test status
Simulation time 14954636903 ps
CPU time 176.98 seconds
Started Jul 19 04:25:13 PM PDT 24
Finished Jul 19 04:28:30 PM PDT 24
Peak memory 200008 kb
Host smart-854430fd-bacd-4c5a-912a-4a7e6c1ce474
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2196891523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2196891523
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.73083905
Short name T433
Test name
Test status
Simulation time 4392144797 ps
CPU time 2.71 seconds
Started Jul 19 04:25:20 PM PDT 24
Finished Jul 19 04:25:43 PM PDT 24
Peak memory 198688 kb
Host smart-c5b11a67-11b0-411c-ae72-70c31a7e3968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73083905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.73083905
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3867236075
Short name T416
Test name
Test status
Simulation time 291318064041 ps
CPU time 164.58 seconds
Started Jul 19 04:25:20 PM PDT 24
Finished Jul 19 04:28:24 PM PDT 24
Peak memory 199808 kb
Host smart-e01542d9-704a-4046-ad95-58f3583cd2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867236075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3867236075
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1626301196
Short name T770
Test name
Test status
Simulation time 520949352 ps
CPU time 1.64 seconds
Started Jul 19 04:25:17 PM PDT 24
Finished Jul 19 04:25:38 PM PDT 24
Peak memory 195452 kb
Host smart-f8e3060e-03d1-48ac-a624-ba4fec4f6023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626301196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1626301196
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3822869814
Short name T24
Test name
Test status
Simulation time 110781115 ps
CPU time 0.88 seconds
Started Jul 19 04:25:25 PM PDT 24
Finished Jul 19 04:25:45 PM PDT 24
Peak memory 218104 kb
Host smart-808a7162-e0c4-4c1a-93b2-eba05b36f1fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822869814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3822869814
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.366820990
Short name T850
Test name
Test status
Simulation time 571922433 ps
CPU time 1.91 seconds
Started Jul 19 04:25:21 PM PDT 24
Finished Jul 19 04:25:42 PM PDT 24
Peak memory 198800 kb
Host smart-1da8f333-cd45-4602-9f31-0c6961ecc5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366820990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.366820990
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.695862723
Short name T161
Test name
Test status
Simulation time 488332704104 ps
CPU time 222.67 seconds
Started Jul 19 04:25:20 PM PDT 24
Finished Jul 19 04:29:23 PM PDT 24
Peak memory 199572 kb
Host smart-c0a083e7-1ee5-47fe-be26-56525acea09f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695862723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.695862723
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.880231244
Short name T817
Test name
Test status
Simulation time 9356676655 ps
CPU time 2.13 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:25:39 PM PDT 24
Peak memory 199792 kb
Host smart-272fc980-dbf8-49c5-9b9b-15e1086aaa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880231244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.880231244
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1790175796
Short name T311
Test name
Test status
Simulation time 67575209979 ps
CPU time 19.91 seconds
Started Jul 19 04:25:17 PM PDT 24
Finished Jul 19 04:25:57 PM PDT 24
Peak memory 199972 kb
Host smart-debe9cce-c992-4077-8e9b-bfa6e08229e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790175796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1790175796
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3554084134
Short name T596
Test name
Test status
Simulation time 16019817 ps
CPU time 0.56 seconds
Started Jul 19 04:26:25 PM PDT 24
Finished Jul 19 04:26:38 PM PDT 24
Peak memory 195348 kb
Host smart-13ec0ce2-4616-4b38-a134-4469ed206dae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554084134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3554084134
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.651926676
Short name T1073
Test name
Test status
Simulation time 79920487103 ps
CPU time 34.18 seconds
Started Jul 19 04:26:20 PM PDT 24
Finished Jul 19 04:27:06 PM PDT 24
Peak memory 199888 kb
Host smart-73bdcd52-ee5f-4df6-8ffc-4748bee423de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651926676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.651926676
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.907889782
Short name T144
Test name
Test status
Simulation time 21883377400 ps
CPU time 32.24 seconds
Started Jul 19 04:26:25 PM PDT 24
Finished Jul 19 04:27:09 PM PDT 24
Peak memory 199960 kb
Host smart-0b72a2be-3872-4620-a9b0-1b2ddb6cfc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907889782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.907889782
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1121299628
Short name T802
Test name
Test status
Simulation time 117233643345 ps
CPU time 42.73 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:27:15 PM PDT 24
Peak memory 199940 kb
Host smart-12107815-488d-468d-b3e4-f6f437060d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121299628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1121299628
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.4108100300
Short name T773
Test name
Test status
Simulation time 125982001733 ps
CPU time 48.28 seconds
Started Jul 19 04:26:25 PM PDT 24
Finished Jul 19 04:27:25 PM PDT 24
Peak memory 197164 kb
Host smart-dd99e881-875b-4d42-9ce1-d0b6f6ab57e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108100300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4108100300
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3378177170
Short name T78
Test name
Test status
Simulation time 74444462794 ps
CPU time 260.13 seconds
Started Jul 19 04:26:29 PM PDT 24
Finished Jul 19 04:31:01 PM PDT 24
Peak memory 199940 kb
Host smart-594030a6-2e52-4dac-95b0-5667e0403437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3378177170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3378177170
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1651822213
Short name T1152
Test name
Test status
Simulation time 6861762621 ps
CPU time 9.35 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:26:43 PM PDT 24
Peak memory 199700 kb
Host smart-d75aaf6e-68a0-4071-afe2-adec1cef39b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651822213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1651822213
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1314757006
Short name T468
Test name
Test status
Simulation time 239708290139 ps
CPU time 110.91 seconds
Started Jul 19 04:26:26 PM PDT 24
Finished Jul 19 04:28:29 PM PDT 24
Peak memory 208268 kb
Host smart-29773536-6c2d-42bd-8156-9f621049264b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314757006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1314757006
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.670061175
Short name T624
Test name
Test status
Simulation time 21141060732 ps
CPU time 401.17 seconds
Started Jul 19 04:26:26 PM PDT 24
Finished Jul 19 04:33:19 PM PDT 24
Peak memory 199928 kb
Host smart-042eb48f-4386-4609-9b19-e1e3e6bd7751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670061175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.670061175
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.251587854
Short name T455
Test name
Test status
Simulation time 1586456425 ps
CPU time 6.21 seconds
Started Jul 19 04:26:21 PM PDT 24
Finished Jul 19 04:26:39 PM PDT 24
Peak memory 197956 kb
Host smart-312a82e0-9b1d-4b7d-b7d1-ce7ee1a16ebe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251587854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.251587854
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1992290672
Short name T473
Test name
Test status
Simulation time 87161526649 ps
CPU time 42.69 seconds
Started Jul 19 04:26:22 PM PDT 24
Finished Jul 19 04:27:16 PM PDT 24
Peak memory 199932 kb
Host smart-bcc74a1e-cbe2-462f-9482-915e129faa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992290672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1992290672
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.114125274
Short name T568
Test name
Test status
Simulation time 3157638784 ps
CPU time 5.74 seconds
Started Jul 19 04:26:24 PM PDT 24
Finished Jul 19 04:26:42 PM PDT 24
Peak memory 196016 kb
Host smart-9c7b47af-c85c-4ee9-95da-e6ae593255c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114125274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.114125274
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2655958743
Short name T709
Test name
Test status
Simulation time 104369530 ps
CPU time 1.08 seconds
Started Jul 19 04:26:21 PM PDT 24
Finished Jul 19 04:26:34 PM PDT 24
Peak memory 198904 kb
Host smart-cebbc6ad-48e3-46ce-990e-09f237a55d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655958743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2655958743
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1852310222
Short name T477
Test name
Test status
Simulation time 75969848177 ps
CPU time 421.75 seconds
Started Jul 19 04:26:21 PM PDT 24
Finished Jul 19 04:33:34 PM PDT 24
Peak memory 199972 kb
Host smart-4ee24586-9a1f-429f-9eb0-5543bddca9fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852310222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1852310222
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3251841235
Short name T57
Test name
Test status
Simulation time 587143077635 ps
CPU time 925.9 seconds
Started Jul 19 04:26:23 PM PDT 24
Finished Jul 19 04:42:00 PM PDT 24
Peak memory 224856 kb
Host smart-c03fcad0-5a93-4bcb-a3c0-1c55b7e995ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251841235 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3251841235
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3097149791
Short name T1172
Test name
Test status
Simulation time 1781467531 ps
CPU time 2.03 seconds
Started Jul 19 04:26:30 PM PDT 24
Finished Jul 19 04:26:43 PM PDT 24
Peak memory 198868 kb
Host smart-c1768413-4fc1-44a9-82d7-d460af53e499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097149791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3097149791
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2547913539
Short name T264
Test name
Test status
Simulation time 22871478949 ps
CPU time 21.1 seconds
Started Jul 19 04:26:27 PM PDT 24
Finished Jul 19 04:27:01 PM PDT 24
Peak memory 199976 kb
Host smart-aa4eaeb3-54c5-47fa-8a2b-da855630b264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547913539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2547913539
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1797331552
Short name T1161
Test name
Test status
Simulation time 15276984 ps
CPU time 0.6 seconds
Started Jul 19 04:26:37 PM PDT 24
Finished Jul 19 04:26:46 PM PDT 24
Peak memory 195360 kb
Host smart-604b2122-8870-4868-9e97-71109d0c5ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797331552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1797331552
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.4153870126
Short name T597
Test name
Test status
Simulation time 13740105533 ps
CPU time 21.71 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:27:05 PM PDT 24
Peak memory 199984 kb
Host smart-9d11c19f-ef7a-45d8-9efc-d54d8c2e2db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153870126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.4153870126
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2581033634
Short name T821
Test name
Test status
Simulation time 39151245581 ps
CPU time 28.98 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:27:12 PM PDT 24
Peak memory 199920 kb
Host smart-e1fbcb63-9d4b-42de-8bcb-4f27b63b295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581033634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2581033634
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.251050478
Short name T1065
Test name
Test status
Simulation time 6309809629 ps
CPU time 15.25 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:26:58 PM PDT 24
Peak memory 200028 kb
Host smart-8ea64e98-83b4-4020-9631-c456c52efaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251050478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.251050478
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.21619609
Short name T328
Test name
Test status
Simulation time 42553574837 ps
CPU time 71.24 seconds
Started Jul 19 04:26:44 PM PDT 24
Finished Jul 19 04:28:00 PM PDT 24
Peak memory 199868 kb
Host smart-28080c49-1358-46d6-909d-752cb5691a31
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21619609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.21619609
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3374198847
Short name T46
Test name
Test status
Simulation time 128877931758 ps
CPU time 415.41 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:33:39 PM PDT 24
Peak memory 199976 kb
Host smart-7289820b-0bdb-4653-9153-94c02ec36345
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374198847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3374198847
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2902263799
Short name T1076
Test name
Test status
Simulation time 7903833321 ps
CPU time 57.41 seconds
Started Jul 19 04:26:31 PM PDT 24
Finished Jul 19 04:27:39 PM PDT 24
Peak memory 199088 kb
Host smart-2028d47d-a8de-4f6b-8c9f-314009f3a72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902263799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2902263799
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3696006464
Short name T699
Test name
Test status
Simulation time 106787371204 ps
CPU time 49.71 seconds
Started Jul 19 04:26:34 PM PDT 24
Finished Jul 19 04:27:34 PM PDT 24
Peak memory 208272 kb
Host smart-44cffee4-ec24-4e2a-807f-747f4d72862e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696006464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3696006464
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.168996317
Short name T314
Test name
Test status
Simulation time 20147284247 ps
CPU time 583.98 seconds
Started Jul 19 04:26:33 PM PDT 24
Finished Jul 19 04:36:28 PM PDT 24
Peak memory 200340 kb
Host smart-495680f6-ed66-497d-8e76-ae2e99f0938f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=168996317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.168996317
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2887678141
Short name T620
Test name
Test status
Simulation time 7482584777 ps
CPU time 63.67 seconds
Started Jul 19 04:26:37 PM PDT 24
Finished Jul 19 04:27:49 PM PDT 24
Peak memory 198908 kb
Host smart-461ca1e5-fca5-4b34-b72d-859c4818f0e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887678141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2887678141
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.194299392
Short name T907
Test name
Test status
Simulation time 266779248016 ps
CPU time 27.93 seconds
Started Jul 19 04:26:37 PM PDT 24
Finished Jul 19 04:27:14 PM PDT 24
Peak memory 199812 kb
Host smart-abd4c267-ca03-4a33-ba0b-32a97a180561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194299392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.194299392
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1559571098
Short name T538
Test name
Test status
Simulation time 3237909580 ps
CPU time 5.52 seconds
Started Jul 19 04:26:34 PM PDT 24
Finished Jul 19 04:26:50 PM PDT 24
Peak memory 196200 kb
Host smart-0e8c3439-9cea-457a-864f-874e69c5bdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559571098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1559571098
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.414314679
Short name T909
Test name
Test status
Simulation time 533885733 ps
CPU time 2.65 seconds
Started Jul 19 04:26:24 PM PDT 24
Finished Jul 19 04:26:38 PM PDT 24
Peak memory 198908 kb
Host smart-95a0da68-fdc4-4fb3-b941-fd287a6d2b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414314679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.414314679
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.528044082
Short name T113
Test name
Test status
Simulation time 41100494690 ps
CPU time 501.6 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:35:05 PM PDT 24
Peak memory 216464 kb
Host smart-9b179fe1-8d32-432f-bc4d-36be28961c08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528044082 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.528044082
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2886348640
Short name T732
Test name
Test status
Simulation time 6675223173 ps
CPU time 16.71 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:27:00 PM PDT 24
Peak memory 199804 kb
Host smart-d59e44f4-4964-4456-a678-bfe8d7c60c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886348640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2886348640
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2235176514
Short name T1030
Test name
Test status
Simulation time 34818353223 ps
CPU time 13.82 seconds
Started Jul 19 04:26:36 PM PDT 24
Finished Jul 19 04:26:59 PM PDT 24
Peak memory 199260 kb
Host smart-855e761d-adc3-42a0-a3d3-d9ffd128065c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235176514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2235176514
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1799476429
Short name T460
Test name
Test status
Simulation time 25359581 ps
CPU time 0.53 seconds
Started Jul 19 04:26:30 PM PDT 24
Finished Jul 19 04:26:42 PM PDT 24
Peak memory 195348 kb
Host smart-1fd39c8e-bcae-4db6-8c69-3ecd619c5931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799476429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1799476429
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.4177385793
Short name T583
Test name
Test status
Simulation time 39078702769 ps
CPU time 62.45 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:27:46 PM PDT 24
Peak memory 199948 kb
Host smart-8aeec812-0fcd-4bd4-a21a-b2baf8520435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177385793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.4177385793
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2124790412
Short name T110
Test name
Test status
Simulation time 110956306587 ps
CPU time 172.94 seconds
Started Jul 19 04:26:34 PM PDT 24
Finished Jul 19 04:29:37 PM PDT 24
Peak memory 199924 kb
Host smart-c50df879-cd25-4f22-8bc2-db70c26d4681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124790412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2124790412
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3113499274
Short name T1039
Test name
Test status
Simulation time 19794102674 ps
CPU time 15.59 seconds
Started Jul 19 04:26:33 PM PDT 24
Finished Jul 19 04:26:59 PM PDT 24
Peak memory 199888 kb
Host smart-c0ea86c4-4528-4a2f-932d-ec7bdb8be0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113499274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3113499274
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3087622305
Short name T863
Test name
Test status
Simulation time 95215179388 ps
CPU time 65.82 seconds
Started Jul 19 04:26:35 PM PDT 24
Finished Jul 19 04:27:51 PM PDT 24
Peak memory 199872 kb
Host smart-01e2689c-c887-4148-95c9-ec841349da4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087622305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3087622305
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2685006232
Short name T504
Test name
Test status
Simulation time 38509105003 ps
CPU time 175.78 seconds
Started Jul 19 04:26:34 PM PDT 24
Finished Jul 19 04:29:40 PM PDT 24
Peak memory 199960 kb
Host smart-3fce9b85-92c3-484d-b382-dfc7feee87a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685006232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2685006232
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1419575316
Short name T347
Test name
Test status
Simulation time 6680043146 ps
CPU time 10.35 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:26:53 PM PDT 24
Peak memory 198992 kb
Host smart-42a7ab3e-e08f-498a-8cd9-3acbae6fb446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419575316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1419575316
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2373389936
Short name T436
Test name
Test status
Simulation time 106157177184 ps
CPU time 189.9 seconds
Started Jul 19 04:26:38 PM PDT 24
Finished Jul 19 04:29:56 PM PDT 24
Peak memory 200116 kb
Host smart-b26eccb6-970a-4941-b425-4d18977a4a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373389936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2373389936
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2836810743
Short name T687
Test name
Test status
Simulation time 15827333004 ps
CPU time 710 seconds
Started Jul 19 04:26:33 PM PDT 24
Finished Jul 19 04:38:33 PM PDT 24
Peak memory 200088 kb
Host smart-f76f91ff-f055-4cbd-80e3-c5c1e8aeee3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2836810743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2836810743
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.712935517
Short name T1000
Test name
Test status
Simulation time 3604538666 ps
CPU time 6.42 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:26:50 PM PDT 24
Peak memory 198096 kb
Host smart-8e6b7107-3f32-4326-b7ca-0b2fd6b47a8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712935517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.712935517
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.853906126
Short name T889
Test name
Test status
Simulation time 195154342735 ps
CPU time 86.15 seconds
Started Jul 19 04:26:33 PM PDT 24
Finished Jul 19 04:28:10 PM PDT 24
Peak memory 199964 kb
Host smart-7d6beaca-9e82-4aaa-a219-542d559df09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853906126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.853906126
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3254515218
Short name T663
Test name
Test status
Simulation time 62328440992 ps
CPU time 100.58 seconds
Started Jul 19 04:26:33 PM PDT 24
Finished Jul 19 04:28:25 PM PDT 24
Peak memory 196284 kb
Host smart-f5fb3bfe-0d6a-4012-8024-be3fdf4ccf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254515218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3254515218
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.839820920
Short name T1131
Test name
Test status
Simulation time 126813201 ps
CPU time 0.75 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:26:43 PM PDT 24
Peak memory 197240 kb
Host smart-e759f71f-e969-4bc3-b84f-d6ba56c6c89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839820920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.839820920
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2264980406
Short name T170
Test name
Test status
Simulation time 91544957844 ps
CPU time 893.79 seconds
Started Jul 19 04:26:35 PM PDT 24
Finished Jul 19 04:41:39 PM PDT 24
Peak memory 199932 kb
Host smart-b5b30200-0802-4bb2-9be7-d44cc3c3aa52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264980406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2264980406
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.972675377
Short name T726
Test name
Test status
Simulation time 139116981334 ps
CPU time 499.86 seconds
Started Jul 19 04:26:34 PM PDT 24
Finished Jul 19 04:35:04 PM PDT 24
Peak memory 216596 kb
Host smart-93025f8a-5cec-4451-8d6b-498bfd1b2fe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972675377 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.972675377
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1672694694
Short name T867
Test name
Test status
Simulation time 1190484377 ps
CPU time 1.57 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:26:44 PM PDT 24
Peak memory 198636 kb
Host smart-ba63ebb4-d86b-412d-a4e9-e672bd2f478b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672694694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1672694694
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.444608583
Short name T579
Test name
Test status
Simulation time 23000719580 ps
CPU time 16.53 seconds
Started Jul 19 04:26:33 PM PDT 24
Finished Jul 19 04:27:00 PM PDT 24
Peak memory 197500 kb
Host smart-301ff751-78a1-4ffe-a5e8-898ba782d907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444608583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.444608583
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3612071541
Short name T948
Test name
Test status
Simulation time 15630081 ps
CPU time 0.6 seconds
Started Jul 19 04:26:47 PM PDT 24
Finished Jul 19 04:26:51 PM PDT 24
Peak memory 195396 kb
Host smart-bcd38893-50cd-4a78-9e73-568e4cd76613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612071541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3612071541
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2948662709
Short name T32
Test name
Test status
Simulation time 41171869019 ps
CPU time 44.42 seconds
Started Jul 19 04:26:34 PM PDT 24
Finished Jul 19 04:27:28 PM PDT 24
Peak memory 199800 kb
Host smart-4f1ec145-3505-445f-9a7e-e94c21253e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948662709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2948662709
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2084301058
Short name T1175
Test name
Test status
Simulation time 7492003032 ps
CPU time 12.03 seconds
Started Jul 19 04:26:33 PM PDT 24
Finished Jul 19 04:26:55 PM PDT 24
Peak memory 198368 kb
Host smart-de1ae282-12bd-4e8d-91bc-83cf99b06400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084301058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2084301058
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2619891445
Short name T939
Test name
Test status
Simulation time 182786198555 ps
CPU time 15.88 seconds
Started Jul 19 04:26:33 PM PDT 24
Finished Jul 19 04:26:59 PM PDT 24
Peak memory 199940 kb
Host smart-27a6a638-d335-4014-8bfd-0d3e6135c1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619891445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2619891445
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2118332092
Short name T905
Test name
Test status
Simulation time 78823519957 ps
CPU time 58.34 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:27:41 PM PDT 24
Peak memory 199720 kb
Host smart-a6337e43-0db7-4f68-9d6d-7292042bf398
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118332092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2118332092
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.860101006
Short name T965
Test name
Test status
Simulation time 180892110520 ps
CPU time 224.93 seconds
Started Jul 19 04:26:44 PM PDT 24
Finished Jul 19 04:30:34 PM PDT 24
Peak memory 199916 kb
Host smart-481709e8-a827-4659-9101-2ad828f43850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860101006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.860101006
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1789560078
Short name T382
Test name
Test status
Simulation time 352054565 ps
CPU time 0.63 seconds
Started Jul 19 04:26:33 PM PDT 24
Finished Jul 19 04:26:44 PM PDT 24
Peak memory 196072 kb
Host smart-8e0f4168-cf76-450c-a4ab-009925317b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789560078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1789560078
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.4139660625
Short name T879
Test name
Test status
Simulation time 591154281054 ps
CPU time 76.23 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:27:59 PM PDT 24
Peak memory 200020 kb
Host smart-2be44363-88b2-4b66-9a0b-2df1a63173ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139660625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4139660625
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.4209019253
Short name T267
Test name
Test status
Simulation time 24861721416 ps
CPU time 209.33 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:30:12 PM PDT 24
Peak memory 199996 kb
Host smart-cc71f3dd-76cc-4469-b200-48f34e8592b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209019253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.4209019253
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2528087975
Short name T815
Test name
Test status
Simulation time 2981185847 ps
CPU time 3.79 seconds
Started Jul 19 04:26:34 PM PDT 24
Finished Jul 19 04:26:48 PM PDT 24
Peak memory 198208 kb
Host smart-b77434c2-f58c-4fe3-82b9-1a17f9629194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528087975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2528087975
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3154381656
Short name T716
Test name
Test status
Simulation time 129838972567 ps
CPU time 170.57 seconds
Started Jul 19 04:26:33 PM PDT 24
Finished Jul 19 04:29:34 PM PDT 24
Peak memory 199528 kb
Host smart-0984aa19-09e5-4333-a522-7d4b1b738212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154381656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3154381656
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1772697643
Short name T887
Test name
Test status
Simulation time 2893235741 ps
CPU time 4.92 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:26:48 PM PDT 24
Peak memory 195768 kb
Host smart-683a41c5-7985-469e-940d-ed132cea4e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772697643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1772697643
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3825053943
Short name T357
Test name
Test status
Simulation time 453873084 ps
CPU time 1.28 seconds
Started Jul 19 04:26:36 PM PDT 24
Finished Jul 19 04:26:47 PM PDT 24
Peak memory 198680 kb
Host smart-2a193d11-c757-4bf1-a2d3-b3e8df066e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825053943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3825053943
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1808164767
Short name T15
Test name
Test status
Simulation time 664011995 ps
CPU time 7.38 seconds
Started Jul 19 04:26:45 PM PDT 24
Finished Jul 19 04:26:57 PM PDT 24
Peak memory 200004 kb
Host smart-bf33c597-52c0-4eaa-8857-06a372ad2669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808164767 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1808164767
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1666679974
Short name T830
Test name
Test status
Simulation time 7245087931 ps
CPU time 14.66 seconds
Started Jul 19 04:26:32 PM PDT 24
Finished Jul 19 04:26:57 PM PDT 24
Peak memory 199804 kb
Host smart-62749442-0775-4872-9dc7-5b5be2bf2776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666679974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1666679974
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1374325939
Short name T1054
Test name
Test status
Simulation time 14258315960 ps
CPU time 12.13 seconds
Started Jul 19 04:26:33 PM PDT 24
Finished Jul 19 04:26:56 PM PDT 24
Peak memory 199888 kb
Host smart-ebe9d38f-96b3-4e56-a7f1-3b4b07b963f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374325939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1374325939
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2136712192
Short name T1092
Test name
Test status
Simulation time 13701767 ps
CPU time 0.66 seconds
Started Jul 19 04:26:43 PM PDT 24
Finished Jul 19 04:26:50 PM PDT 24
Peak memory 195400 kb
Host smart-e00839e2-abf7-465d-8611-67fc2c141db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136712192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2136712192
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.217076892
Short name T1052
Test name
Test status
Simulation time 17437923304 ps
CPU time 25.59 seconds
Started Jul 19 04:26:43 PM PDT 24
Finished Jul 19 04:27:14 PM PDT 24
Peak memory 199996 kb
Host smart-2ed20369-daa5-4be5-9967-0dd0b912455f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217076892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.217076892
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.380004968
Short name T936
Test name
Test status
Simulation time 73607329083 ps
CPU time 31.03 seconds
Started Jul 19 04:26:46 PM PDT 24
Finished Jul 19 04:27:21 PM PDT 24
Peak memory 199848 kb
Host smart-531b4f26-488a-40c9-aa2a-1ddc4d92bc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380004968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.380004968
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3698399556
Short name T147
Test name
Test status
Simulation time 193677405692 ps
CPU time 563.37 seconds
Started Jul 19 04:26:48 PM PDT 24
Finished Jul 19 04:36:15 PM PDT 24
Peak memory 199948 kb
Host smart-dd087c74-8bf9-4182-9c48-8688b7ef381c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698399556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3698399556
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.4870641
Short name T943
Test name
Test status
Simulation time 26586474525 ps
CPU time 35.94 seconds
Started Jul 19 04:26:47 PM PDT 24
Finished Jul 19 04:27:27 PM PDT 24
Peak memory 199876 kb
Host smart-d12cd278-aedb-4511-b1b1-122beaaed398
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4870641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.4870641
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2103122437
Short name T545
Test name
Test status
Simulation time 70752882024 ps
CPU time 263.57 seconds
Started Jul 19 04:26:47 PM PDT 24
Finished Jul 19 04:31:14 PM PDT 24
Peak memory 199972 kb
Host smart-7ea95bec-b1a6-4317-9005-2d8f5d9d3271
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103122437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2103122437
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.4244092328
Short name T692
Test name
Test status
Simulation time 4144140606 ps
CPU time 5.32 seconds
Started Jul 19 04:26:47 PM PDT 24
Finished Jul 19 04:26:56 PM PDT 24
Peak memory 199928 kb
Host smart-a5b18f32-fa70-4cc2-9d34-f66b42e57120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244092328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.4244092328
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.697541056
Short name T459
Test name
Test status
Simulation time 144631872373 ps
CPU time 264.68 seconds
Started Jul 19 04:26:45 PM PDT 24
Finished Jul 19 04:31:14 PM PDT 24
Peak memory 198784 kb
Host smart-28cfd63a-9765-47ec-9b8e-07a72cc4d544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697541056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.697541056
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3928268981
Short name T509
Test name
Test status
Simulation time 30690198150 ps
CPU time 418.52 seconds
Started Jul 19 04:26:46 PM PDT 24
Finished Jul 19 04:33:49 PM PDT 24
Peak memory 199904 kb
Host smart-7b9176ed-e037-4749-8b35-d06dae1c4126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3928268981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3928268981
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.907954014
Short name T1105
Test name
Test status
Simulation time 6528934736 ps
CPU time 50.43 seconds
Started Jul 19 04:26:44 PM PDT 24
Finished Jul 19 04:27:40 PM PDT 24
Peak memory 198776 kb
Host smart-5c9557e4-9939-441c-bf3d-f42996ddac09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=907954014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.907954014
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2737242042
Short name T506
Test name
Test status
Simulation time 93110350055 ps
CPU time 32.76 seconds
Started Jul 19 04:26:47 PM PDT 24
Finished Jul 19 04:27:24 PM PDT 24
Peak memory 199844 kb
Host smart-af512eb8-c9d9-4865-a83a-ea3c180a96d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737242042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2737242042
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3083890255
Short name T479
Test name
Test status
Simulation time 2603372865 ps
CPU time 2.79 seconds
Started Jul 19 04:26:46 PM PDT 24
Finished Jul 19 04:26:53 PM PDT 24
Peak memory 196460 kb
Host smart-984234d1-eb61-4e96-b0c2-0bf136f8bb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083890255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3083890255
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3974570510
Short name T396
Test name
Test status
Simulation time 6330288400 ps
CPU time 11.93 seconds
Started Jul 19 04:26:47 PM PDT 24
Finished Jul 19 04:27:03 PM PDT 24
Peak memory 199932 kb
Host smart-7128ea49-da0c-4b1c-853d-4ae965b698af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974570510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3974570510
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1044401779
Short name T135
Test name
Test status
Simulation time 100659422609 ps
CPU time 641.67 seconds
Started Jul 19 04:26:47 PM PDT 24
Finished Jul 19 04:37:33 PM PDT 24
Peak memory 199972 kb
Host smart-252b2984-8cc8-4c64-a78c-716542268fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044401779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1044401779
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2499175120
Short name T625
Test name
Test status
Simulation time 885875051 ps
CPU time 1.78 seconds
Started Jul 19 04:26:42 PM PDT 24
Finished Jul 19 04:26:50 PM PDT 24
Peak memory 198592 kb
Host smart-7596acc8-1cb7-4a1c-8585-13249200f8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499175120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2499175120
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.302017107
Short name T934
Test name
Test status
Simulation time 15274178524 ps
CPU time 21.62 seconds
Started Jul 19 04:26:50 PM PDT 24
Finished Jul 19 04:27:15 PM PDT 24
Peak memory 200016 kb
Host smart-41eb4af2-a6e6-4c1c-b7ca-a9e57b1236a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302017107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.302017107
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2344853167
Short name T729
Test name
Test status
Simulation time 15443882 ps
CPU time 0.54 seconds
Started Jul 19 04:26:52 PM PDT 24
Finished Jul 19 04:26:57 PM PDT 24
Peak memory 195364 kb
Host smart-052aa487-107e-46c6-87d0-f7b999587a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344853167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2344853167
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3585994208
Short name T912
Test name
Test status
Simulation time 233732588617 ps
CPU time 49.97 seconds
Started Jul 19 04:26:43 PM PDT 24
Finished Jul 19 04:27:39 PM PDT 24
Peak memory 199960 kb
Host smart-57c4a55a-2f6b-4ac7-9334-2da982c751f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585994208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3585994208
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.4221917907
Short name T1177
Test name
Test status
Simulation time 117221917949 ps
CPU time 73.47 seconds
Started Jul 19 04:26:43 PM PDT 24
Finished Jul 19 04:28:02 PM PDT 24
Peak memory 199884 kb
Host smart-51dc6630-79e3-4cef-a660-fd567ca1f043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221917907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.4221917907
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_intr.1468225108
Short name T447
Test name
Test status
Simulation time 421312876465 ps
CPU time 171.07 seconds
Started Jul 19 04:26:45 PM PDT 24
Finished Jul 19 04:29:41 PM PDT 24
Peak memory 199272 kb
Host smart-83a7755b-78d5-4610-b97a-13a962114a41
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468225108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1468225108
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3237781663
Short name T675
Test name
Test status
Simulation time 78020535098 ps
CPU time 403.38 seconds
Started Jul 19 04:26:49 PM PDT 24
Finished Jul 19 04:33:36 PM PDT 24
Peak memory 200056 kb
Host smart-db03fccc-a2c6-45bc-a0c4-9d60f2d0b152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3237781663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3237781663
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1108301962
Short name T555
Test name
Test status
Simulation time 5137084795 ps
CPU time 3.64 seconds
Started Jul 19 04:26:50 PM PDT 24
Finished Jul 19 04:26:57 PM PDT 24
Peak memory 198688 kb
Host smart-7c46c2de-8a24-4e5c-8b57-20b44d5bc7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108301962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1108301962
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.4045695494
Short name T880
Test name
Test status
Simulation time 51539328185 ps
CPU time 84.63 seconds
Started Jul 19 04:26:50 PM PDT 24
Finished Jul 19 04:28:18 PM PDT 24
Peak memory 199796 kb
Host smart-7a6ab393-f116-47de-bbe3-98b44bc9b43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045695494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.4045695494
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.4128512636
Short name T411
Test name
Test status
Simulation time 31557174758 ps
CPU time 425.91 seconds
Started Jul 19 04:26:46 PM PDT 24
Finished Jul 19 04:33:56 PM PDT 24
Peak memory 199852 kb
Host smart-6f1839f2-f90d-492c-9ffd-03e4ba3b7bad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4128512636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.4128512636
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3064839630
Short name T44
Test name
Test status
Simulation time 1392856407 ps
CPU time 2.03 seconds
Started Jul 19 04:26:43 PM PDT 24
Finished Jul 19 04:26:51 PM PDT 24
Peak memory 197804 kb
Host smart-54ce4b47-803f-42f7-b924-1b8216b15aff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3064839630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3064839630
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.4121368208
Short name T984
Test name
Test status
Simulation time 16848206975 ps
CPU time 9.59 seconds
Started Jul 19 04:26:47 PM PDT 24
Finished Jul 19 04:27:01 PM PDT 24
Peak memory 199916 kb
Host smart-83319cc3-d634-430f-981a-c1ec921f47c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121368208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.4121368208
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1979581574
Short name T1145
Test name
Test status
Simulation time 76027780452 ps
CPU time 118.47 seconds
Started Jul 19 04:26:50 PM PDT 24
Finished Jul 19 04:28:53 PM PDT 24
Peak memory 196144 kb
Host smart-58b8b857-2851-4bf2-beaf-b47abc2c4114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979581574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1979581574
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.4119057835
Short name T600
Test name
Test status
Simulation time 487773409 ps
CPU time 2.14 seconds
Started Jul 19 04:26:46 PM PDT 24
Finished Jul 19 04:26:52 PM PDT 24
Peak memory 198792 kb
Host smart-d807e2be-884f-4620-9d33-51415229b35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119057835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.4119057835
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1362596034
Short name T1041
Test name
Test status
Simulation time 128298055936 ps
CPU time 316.75 seconds
Started Jul 19 04:27:06 PM PDT 24
Finished Jul 19 04:32:28 PM PDT 24
Peak memory 200264 kb
Host smart-97faabae-39e1-4431-9ea1-6a2dcf11b76b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362596034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1362596034
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3639633851
Short name T711
Test name
Test status
Simulation time 22838872076 ps
CPU time 343.71 seconds
Started Jul 19 04:26:46 PM PDT 24
Finished Jul 19 04:32:34 PM PDT 24
Peak memory 216372 kb
Host smart-e58c414f-5cc5-428b-8bfe-9b41a0894eec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639633851 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3639633851
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1822000715
Short name T1069
Test name
Test status
Simulation time 1964656574 ps
CPU time 2.17 seconds
Started Jul 19 04:26:44 PM PDT 24
Finished Jul 19 04:26:51 PM PDT 24
Peak memory 199268 kb
Host smart-93b9d35c-6574-4556-aba7-f4c77dc59122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822000715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1822000715
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3007840933
Short name T558
Test name
Test status
Simulation time 54314541572 ps
CPU time 49.39 seconds
Started Jul 19 04:26:45 PM PDT 24
Finished Jul 19 04:27:39 PM PDT 24
Peak memory 199940 kb
Host smart-65e85621-5456-4a9c-b887-ab8d81234b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007840933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3007840933
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2278470694
Short name T346
Test name
Test status
Simulation time 41962429 ps
CPU time 0.56 seconds
Started Jul 19 04:26:51 PM PDT 24
Finished Jul 19 04:26:55 PM PDT 24
Peak memory 195412 kb
Host smart-53c6a973-9df4-40cb-bb08-20a40b3d3766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278470694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2278470694
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3832872529
Short name T607
Test name
Test status
Simulation time 25761053775 ps
CPU time 10.34 seconds
Started Jul 19 04:26:46 PM PDT 24
Finished Jul 19 04:27:01 PM PDT 24
Peak memory 199960 kb
Host smart-b9c1b118-aa26-46b5-a0bc-96cf7f8f5da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832872529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3832872529
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3593152106
Short name T404
Test name
Test status
Simulation time 53625437870 ps
CPU time 33.02 seconds
Started Jul 19 04:26:44 PM PDT 24
Finished Jul 19 04:27:22 PM PDT 24
Peak memory 199840 kb
Host smart-5ebfab8b-91da-47fd-a396-8a8068257ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593152106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3593152106
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4272741030
Short name T210
Test name
Test status
Simulation time 98007188148 ps
CPU time 73.18 seconds
Started Jul 19 04:26:43 PM PDT 24
Finished Jul 19 04:28:02 PM PDT 24
Peak memory 199924 kb
Host smart-eb6c0079-9750-45d2-a4f8-f1a5d3b652a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272741030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4272741030
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2184180377
Short name T77
Test name
Test status
Simulation time 13686775304 ps
CPU time 10.37 seconds
Started Jul 19 04:26:44 PM PDT 24
Finished Jul 19 04:27:00 PM PDT 24
Peak memory 196984 kb
Host smart-77eda6a3-370d-45d1-9029-24798a8669c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184180377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2184180377
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2275440583
Short name T36
Test name
Test status
Simulation time 179637558770 ps
CPU time 1514.85 seconds
Started Jul 19 04:26:47 PM PDT 24
Finished Jul 19 04:52:07 PM PDT 24
Peak memory 199940 kb
Host smart-2bffacf7-9331-4d07-8913-cfd81add0ca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275440583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2275440583
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.211416835
Short name T787
Test name
Test status
Simulation time 7890980739 ps
CPU time 4.02 seconds
Started Jul 19 04:26:50 PM PDT 24
Finished Jul 19 04:26:57 PM PDT 24
Peak memory 199688 kb
Host smart-f189d7b6-0145-4ad2-848c-8a39aa7604aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211416835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.211416835
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3734440169
Short name T976
Test name
Test status
Simulation time 130908557531 ps
CPU time 54.15 seconds
Started Jul 19 04:26:44 PM PDT 24
Finished Jul 19 04:27:43 PM PDT 24
Peak memory 200068 kb
Host smart-2aee6221-1c9a-4957-80ce-b3c521b59d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734440169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3734440169
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.499558071
Short name T857
Test name
Test status
Simulation time 26098775962 ps
CPU time 144.01 seconds
Started Jul 19 04:26:45 PM PDT 24
Finished Jul 19 04:29:14 PM PDT 24
Peak memory 199892 kb
Host smart-2c0ba731-0e16-4f29-b2d4-fc9f10c263a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499558071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.499558071
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.165936398
Short name T644
Test name
Test status
Simulation time 1270995959 ps
CPU time 5.51 seconds
Started Jul 19 04:26:50 PM PDT 24
Finished Jul 19 04:26:59 PM PDT 24
Peak memory 198036 kb
Host smart-ce4045c5-e715-4314-a6fa-6a8a3a48795f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165936398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.165936398
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.158879523
Short name T503
Test name
Test status
Simulation time 166105954383 ps
CPU time 151.46 seconds
Started Jul 19 04:26:44 PM PDT 24
Finished Jul 19 04:29:21 PM PDT 24
Peak memory 199876 kb
Host smart-4ba5d3d3-e3bf-406e-bd86-896ab0105e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158879523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.158879523
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2002399392
Short name T738
Test name
Test status
Simulation time 5556533121 ps
CPU time 1.73 seconds
Started Jul 19 04:26:46 PM PDT 24
Finished Jul 19 04:26:52 PM PDT 24
Peak memory 196240 kb
Host smart-00ad11a0-5a0d-4528-b720-485cb6477d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002399392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2002399392
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3197223255
Short name T466
Test name
Test status
Simulation time 673008547 ps
CPU time 2.04 seconds
Started Jul 19 04:26:48 PM PDT 24
Finished Jul 19 04:26:54 PM PDT 24
Peak memory 198872 kb
Host smart-c175b1ca-e07f-45a9-81f6-2ac45aa1f259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197223255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3197223255
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1078861647
Short name T177
Test name
Test status
Simulation time 154821375986 ps
CPU time 145.91 seconds
Started Jul 19 04:26:45 PM PDT 24
Finished Jul 19 04:29:16 PM PDT 24
Peak memory 200244 kb
Host smart-1409f82c-867c-47fc-8362-c6f35f99899a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078861647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1078861647
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1874042265
Short name T710
Test name
Test status
Simulation time 165099346019 ps
CPU time 1619.34 seconds
Started Jul 19 04:26:45 PM PDT 24
Finished Jul 19 04:53:49 PM PDT 24
Peak memory 216460 kb
Host smart-4076e943-9ce7-41f4-b0cd-3fb4542dee82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874042265 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1874042265
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1690352166
Short name T993
Test name
Test status
Simulation time 4576269347 ps
CPU time 1.97 seconds
Started Jul 19 04:26:50 PM PDT 24
Finished Jul 19 04:26:56 PM PDT 24
Peak memory 199788 kb
Host smart-e1788bd5-5fab-41f2-959f-89ca649fa4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690352166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1690352166
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.106620149
Short name T1021
Test name
Test status
Simulation time 36762679924 ps
CPU time 6.31 seconds
Started Jul 19 04:26:45 PM PDT 24
Finished Jul 19 04:26:56 PM PDT 24
Peak memory 199912 kb
Host smart-5cfea01a-4a48-453c-bb4e-21e4ff313c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106620149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.106620149
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1426842788
Short name T100
Test name
Test status
Simulation time 15939299 ps
CPU time 0.56 seconds
Started Jul 19 04:26:54 PM PDT 24
Finished Jul 19 04:26:59 PM PDT 24
Peak memory 195348 kb
Host smart-9f98ea98-53e8-4192-9912-cadafdf82e42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426842788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1426842788
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.4163762542
Short name T386
Test name
Test status
Simulation time 243394771635 ps
CPU time 43.6 seconds
Started Jul 19 04:26:58 PM PDT 24
Finished Jul 19 04:27:47 PM PDT 24
Peak memory 199964 kb
Host smart-1db3c343-1867-4c4f-bda2-346c2b704abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163762542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.4163762542
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3633137776
Short name T467
Test name
Test status
Simulation time 22324660573 ps
CPU time 35.28 seconds
Started Jul 19 04:26:57 PM PDT 24
Finished Jul 19 04:27:38 PM PDT 24
Peak memory 199816 kb
Host smart-9a995e72-5c19-44b6-98d1-cacaf0391f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633137776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3633137776
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_intr.646276633
Short name T1123
Test name
Test status
Simulation time 257906855071 ps
CPU time 482.52 seconds
Started Jul 19 04:26:56 PM PDT 24
Finished Jul 19 04:35:04 PM PDT 24
Peak memory 199992 kb
Host smart-558247e4-b000-4403-a1ff-27a5e159c79f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646276633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.646276633
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4051272740
Short name T43
Test name
Test status
Simulation time 112974211902 ps
CPU time 951.08 seconds
Started Jul 19 04:26:54 PM PDT 24
Finished Jul 19 04:42:49 PM PDT 24
Peak memory 199900 kb
Host smart-6d2fb184-93f8-4a76-88d5-8fbba4062486
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4051272740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4051272740
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3605956887
Short name T968
Test name
Test status
Simulation time 12249689613 ps
CPU time 8.4 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:27:09 PM PDT 24
Peak memory 199636 kb
Host smart-ced5c660-b3fe-4777-bf03-6828bdaca862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605956887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3605956887
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3212952922
Short name T1165
Test name
Test status
Simulation time 23853278388 ps
CPU time 23.22 seconds
Started Jul 19 04:26:57 PM PDT 24
Finished Jul 19 04:27:26 PM PDT 24
Peak memory 199056 kb
Host smart-8d9486e7-5c3b-44c8-86d0-8af8776b31d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212952922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3212952922
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.3679474101
Short name T1103
Test name
Test status
Simulation time 13452903125 ps
CPU time 78.09 seconds
Started Jul 19 04:26:57 PM PDT 24
Finished Jul 19 04:28:20 PM PDT 24
Peak memory 199908 kb
Host smart-9baa10da-2c18-41d4-8872-d9592b199898
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3679474101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3679474101
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.116408232
Short name T10
Test name
Test status
Simulation time 5611177869 ps
CPU time 45.52 seconds
Started Jul 19 04:26:56 PM PDT 24
Finished Jul 19 04:27:47 PM PDT 24
Peak memory 199124 kb
Host smart-f0272de8-b0a9-4f86-bcc8-6460ab244297
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116408232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.116408232
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2443171276
Short name T586
Test name
Test status
Simulation time 27873544637 ps
CPU time 13.49 seconds
Started Jul 19 04:26:57 PM PDT 24
Finished Jul 19 04:27:16 PM PDT 24
Peak memory 199928 kb
Host smart-3269b537-162c-481a-977a-5278de56037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443171276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2443171276
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2665945407
Short name T368
Test name
Test status
Simulation time 50060293577 ps
CPU time 8.69 seconds
Started Jul 19 04:26:58 PM PDT 24
Finished Jul 19 04:27:12 PM PDT 24
Peak memory 195828 kb
Host smart-17d2fa48-1d56-4349-8e61-65a17dd768cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665945407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2665945407
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.218342702
Short name T1036
Test name
Test status
Simulation time 6292558710 ps
CPU time 15.96 seconds
Started Jul 19 04:26:45 PM PDT 24
Finished Jul 19 04:27:06 PM PDT 24
Peak memory 199944 kb
Host smart-b2aeecaa-77a6-4f1f-9c36-2c03d3fd91e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218342702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.218342702
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3355583479
Short name T1102
Test name
Test status
Simulation time 315079123448 ps
CPU time 139.42 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:29:19 PM PDT 24
Peak memory 208292 kb
Host smart-447577e4-ac9d-4e42-9d8f-59a304259781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355583479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3355583479
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3126337719
Short name T532
Test name
Test status
Simulation time 23713607012 ps
CPU time 786 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:40:07 PM PDT 24
Peak memory 208276 kb
Host smart-0c44da54-6725-4597-abcc-9d4faec46c72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126337719 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3126337719
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1630053116
Short name T1018
Test name
Test status
Simulation time 529837711 ps
CPU time 1.87 seconds
Started Jul 19 04:26:58 PM PDT 24
Finished Jul 19 04:27:05 PM PDT 24
Peak memory 198652 kb
Host smart-3cce037a-b726-4e99-9578-e6afe34c6153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630053116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1630053116
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.4102303217
Short name T617
Test name
Test status
Simulation time 97543232227 ps
CPU time 106.48 seconds
Started Jul 19 04:26:56 PM PDT 24
Finished Jul 19 04:28:48 PM PDT 24
Peak memory 199964 kb
Host smart-2bc921ed-a0db-4ac6-aac3-351f66bdcc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102303217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.4102303217
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3715247576
Short name T352
Test name
Test status
Simulation time 20502526 ps
CPU time 0.55 seconds
Started Jul 19 04:26:54 PM PDT 24
Finished Jul 19 04:26:59 PM PDT 24
Peak memory 194808 kb
Host smart-f98a0d56-d476-4bbb-a564-6c26402b29fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715247576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3715247576
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3255959971
Short name T472
Test name
Test status
Simulation time 100961018086 ps
CPU time 196.77 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:30:17 PM PDT 24
Peak memory 199892 kb
Host smart-7d3cb92a-1a8d-4548-8fb5-f95f9eda793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255959971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3255959971
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1717199297
Short name T1066
Test name
Test status
Simulation time 112226177707 ps
CPU time 171.18 seconds
Started Jul 19 04:26:58 PM PDT 24
Finished Jul 19 04:29:55 PM PDT 24
Peak memory 199868 kb
Host smart-83b27478-ff9d-455a-a027-d3863094742a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717199297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1717199297
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.311182240
Short name T940
Test name
Test status
Simulation time 59685705978 ps
CPU time 38.9 seconds
Started Jul 19 04:26:57 PM PDT 24
Finished Jul 19 04:27:42 PM PDT 24
Peak memory 199916 kb
Host smart-df679383-4d56-4747-82ca-ec7b1e753574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311182240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.311182240
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3759166287
Short name T108
Test name
Test status
Simulation time 19011062309 ps
CPU time 12.76 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:27:14 PM PDT 24
Peak memory 197752 kb
Host smart-4e963403-e117-4871-9a55-be4c9cf37742
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759166287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3759166287
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2369821089
Short name T888
Test name
Test status
Simulation time 172409100151 ps
CPU time 430.49 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:34:10 PM PDT 24
Peak memory 199948 kb
Host smart-4728068d-e076-4af6-8c1f-90928c7d0137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369821089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2369821089
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3023540368
Short name T970
Test name
Test status
Simulation time 8843254216 ps
CPU time 5.29 seconds
Started Jul 19 04:26:54 PM PDT 24
Finished Jul 19 04:27:04 PM PDT 24
Peak memory 199836 kb
Host smart-e9ea3d5c-9dcc-4751-8ab9-eea9d34b7eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023540368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3023540368
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3912662674
Short name T125
Test name
Test status
Simulation time 60207024695 ps
CPU time 17.04 seconds
Started Jul 19 04:26:56 PM PDT 24
Finished Jul 19 04:27:19 PM PDT 24
Peak memory 200100 kb
Host smart-3c642863-c1ea-4211-ad69-7c887ce4f420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912662674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3912662674
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.510025230
Short name T747
Test name
Test status
Simulation time 20808047658 ps
CPU time 1231.36 seconds
Started Jul 19 04:26:54 PM PDT 24
Finished Jul 19 04:47:30 PM PDT 24
Peak memory 199908 kb
Host smart-c8919c97-2d45-46a9-86a0-d3069c6fb95c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510025230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.510025230
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.452226010
Short name T784
Test name
Test status
Simulation time 4530286054 ps
CPU time 8.45 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:27:09 PM PDT 24
Peak memory 198728 kb
Host smart-e16aced0-e392-4511-8b43-1d2fcda1359d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=452226010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.452226010
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2975393227
Short name T832
Test name
Test status
Simulation time 150096117552 ps
CPU time 158.83 seconds
Started Jul 19 04:26:53 PM PDT 24
Finished Jul 19 04:29:36 PM PDT 24
Peak memory 200000 kb
Host smart-74939ac7-2311-4763-bfb6-95bcf206462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975393227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2975393227
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3914810886
Short name T296
Test name
Test status
Simulation time 32544792196 ps
CPU time 3.6 seconds
Started Jul 19 04:26:58 PM PDT 24
Finished Jul 19 04:27:07 PM PDT 24
Peak memory 195964 kb
Host smart-119c14d9-e9c1-41c4-a7d2-81fd3af7711d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914810886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3914810886
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3117421903
Short name T302
Test name
Test status
Simulation time 6308463905 ps
CPU time 7.14 seconds
Started Jul 19 04:26:54 PM PDT 24
Finished Jul 19 04:27:06 PM PDT 24
Peak memory 199880 kb
Host smart-858f41ad-c82c-4823-9049-b0e6d10477de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117421903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3117421903
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1866263575
Short name T59
Test name
Test status
Simulation time 78340689090 ps
CPU time 1034.01 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:44:15 PM PDT 24
Peak memory 227060 kb
Host smart-2fdd3700-9253-4a5c-9167-36dc8458b5d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866263575 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1866263575
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.553171961
Short name T735
Test name
Test status
Simulation time 6056715269 ps
CPU time 15.22 seconds
Started Jul 19 04:26:56 PM PDT 24
Finished Jul 19 04:27:17 PM PDT 24
Peak memory 199860 kb
Host smart-a801a866-cec6-4137-a815-058d78eafb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553171961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.553171961
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1954816541
Short name T658
Test name
Test status
Simulation time 48260606130 ps
CPU time 33.44 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:27:34 PM PDT 24
Peak memory 199936 kb
Host smart-eb9c4993-2126-4268-a446-44403be41c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954816541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1954816541
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.195262231
Short name T337
Test name
Test status
Simulation time 26072716 ps
CPU time 0.57 seconds
Started Jul 19 04:26:57 PM PDT 24
Finished Jul 19 04:27:03 PM PDT 24
Peak memory 195660 kb
Host smart-17dafdb9-6378-4fe2-876f-ab67bbd5b2c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195262231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.195262231
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2750142312
Short name T621
Test name
Test status
Simulation time 68158267196 ps
CPU time 98.14 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:28:39 PM PDT 24
Peak memory 199940 kb
Host smart-275e2e1f-99f5-4be4-8c2f-1b0f417add50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750142312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2750142312
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.631348154
Short name T834
Test name
Test status
Simulation time 68693302607 ps
CPU time 10.06 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:27:11 PM PDT 24
Peak memory 199848 kb
Host smart-a4e9f480-78f1-4607-9a72-4d4c1781ed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631348154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.631348154
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.514599792
Short name T363
Test name
Test status
Simulation time 157713691293 ps
CPU time 169.21 seconds
Started Jul 19 04:26:54 PM PDT 24
Finished Jul 19 04:29:48 PM PDT 24
Peak memory 200028 kb
Host smart-ab75838c-2d27-4dd7-8642-3aa2450a1cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514599792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.514599792
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1934103061
Short name T130
Test name
Test status
Simulation time 54536805227 ps
CPU time 38.96 seconds
Started Jul 19 04:26:54 PM PDT 24
Finished Jul 19 04:27:38 PM PDT 24
Peak memory 200080 kb
Host smart-9d9e33ef-2b3b-408c-90c2-4b87a21f0785
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934103061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1934103061
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1228501632
Short name T516
Test name
Test status
Simulation time 106575005283 ps
CPU time 560.22 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:36:21 PM PDT 24
Peak memory 199972 kb
Host smart-1fa4f82d-80b4-4287-b0bb-c3e9a181d520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1228501632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1228501632
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3695978705
Short name T517
Test name
Test status
Simulation time 5137306334 ps
CPU time 9.21 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:27:10 PM PDT 24
Peak memory 199048 kb
Host smart-98601c4a-73d4-433a-800f-144f12d46108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695978705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3695978705
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2247247945
Short name T263
Test name
Test status
Simulation time 93051405534 ps
CPU time 183.48 seconds
Started Jul 19 04:26:58 PM PDT 24
Finished Jul 19 04:30:07 PM PDT 24
Peak memory 208192 kb
Host smart-cb35f16b-4214-49b7-8d51-ebb4d7c784d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247247945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2247247945
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3030222841
Short name T766
Test name
Test status
Simulation time 27475639730 ps
CPU time 227.02 seconds
Started Jul 19 04:26:58 PM PDT 24
Finished Jul 19 04:30:51 PM PDT 24
Peak memory 199904 kb
Host smart-7991546b-31a9-428b-a33b-b053bc82458e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030222841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3030222841
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3186742835
Short name T996
Test name
Test status
Simulation time 6164218355 ps
CPU time 11.04 seconds
Started Jul 19 04:26:54 PM PDT 24
Finished Jul 19 04:27:10 PM PDT 24
Peak memory 199468 kb
Host smart-c3c31d36-f96c-47a6-b3ab-b5e33de9f5c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186742835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3186742835
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3313305026
Short name T463
Test name
Test status
Simulation time 66672862468 ps
CPU time 22.09 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:27:22 PM PDT 24
Peak memory 198372 kb
Host smart-d1d7bbed-9b72-4cc1-b3d2-de2cb66971cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313305026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3313305026
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2440999765
Short name T865
Test name
Test status
Simulation time 4096650459 ps
CPU time 2.17 seconds
Started Jul 19 04:26:57 PM PDT 24
Finished Jul 19 04:27:04 PM PDT 24
Peak memory 196288 kb
Host smart-1a02e8b1-e113-4661-a874-a6f20f30c0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440999765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2440999765
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1154221597
Short name T603
Test name
Test status
Simulation time 5365398017 ps
CPU time 13.72 seconds
Started Jul 19 04:26:54 PM PDT 24
Finished Jul 19 04:27:13 PM PDT 24
Peak memory 199904 kb
Host smart-861dc4b5-f25d-40ce-aba6-2b2192ea84b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154221597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1154221597
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2788714620
Short name T664
Test name
Test status
Simulation time 130985450966 ps
CPU time 249.73 seconds
Started Jul 19 04:26:53 PM PDT 24
Finished Jul 19 04:31:08 PM PDT 24
Peak memory 215504 kb
Host smart-424c8f97-76d2-4b58-a0ab-216ec0c4e522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788714620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2788714620
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3330815096
Short name T69
Test name
Test status
Simulation time 45775634119 ps
CPU time 514.98 seconds
Started Jul 19 04:26:54 PM PDT 24
Finished Jul 19 04:35:34 PM PDT 24
Peak memory 216628 kb
Host smart-fae04994-3458-4053-b949-e1b80cce40ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330815096 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3330815096
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.857173224
Short name T1059
Test name
Test status
Simulation time 1790329242 ps
CPU time 2.86 seconds
Started Jul 19 04:26:53 PM PDT 24
Finished Jul 19 04:27:01 PM PDT 24
Peak memory 198320 kb
Host smart-0a896937-27e5-44a0-bc94-998aef199f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857173224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.857173224
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3971479979
Short name T1133
Test name
Test status
Simulation time 10322148689 ps
CPU time 13.65 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:27:14 PM PDT 24
Peak memory 197236 kb
Host smart-735efce0-c936-4eb9-95b6-ddaf77d00cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971479979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3971479979
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3850484042
Short name T629
Test name
Test status
Simulation time 14014456 ps
CPU time 0.56 seconds
Started Jul 19 04:25:21 PM PDT 24
Finished Jul 19 04:25:41 PM PDT 24
Peak memory 195612 kb
Host smart-eab51620-ebc8-48ff-8feb-b572336518c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850484042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3850484042
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.591932813
Short name T1127
Test name
Test status
Simulation time 52709893563 ps
CPU time 83.85 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:27:01 PM PDT 24
Peak memory 200324 kb
Host smart-bef8e8bd-52c6-474d-90a9-165a3a94f2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591932813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.591932813
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.179242102
Short name T417
Test name
Test status
Simulation time 81554640459 ps
CPU time 139.52 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:27:57 PM PDT 24
Peak memory 199888 kb
Host smart-754c63d4-8a95-40be-940f-971291724eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179242102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.179242102
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2113875423
Short name T919
Test name
Test status
Simulation time 114664236483 ps
CPU time 162.86 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:28:20 PM PDT 24
Peak memory 199924 kb
Host smart-d51e0f1b-02df-4218-aa33-02b2b13a5c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113875423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2113875423
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1539950005
Short name T448
Test name
Test status
Simulation time 8497920991 ps
CPU time 3.78 seconds
Started Jul 19 04:25:19 PM PDT 24
Finished Jul 19 04:25:42 PM PDT 24
Peak memory 196484 kb
Host smart-fc9d2330-3028-49f3-b620-01a90e969945
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539950005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1539950005
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.4073003839
Short name T874
Test name
Test status
Simulation time 73532014996 ps
CPU time 393.79 seconds
Started Jul 19 04:25:21 PM PDT 24
Finished Jul 19 04:32:14 PM PDT 24
Peak memory 199884 kb
Host smart-d68ed251-18ba-4a99-82c8-2778a916c64d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073003839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.4073003839
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2445360672
Short name T19
Test name
Test status
Simulation time 1687566404 ps
CPU time 2.18 seconds
Started Jul 19 04:25:30 PM PDT 24
Finished Jul 19 04:25:50 PM PDT 24
Peak memory 198380 kb
Host smart-40cfe66a-3546-46d4-9f4c-9dc435306383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445360672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2445360672
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.423541241
Short name T864
Test name
Test status
Simulation time 90532739086 ps
CPU time 186.24 seconds
Started Jul 19 04:25:16 PM PDT 24
Finished Jul 19 04:28:42 PM PDT 24
Peak memory 200084 kb
Host smart-832f9b9e-2f21-4743-b266-8f7d4dec29d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423541241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.423541241
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1687604965
Short name T107
Test name
Test status
Simulation time 16922260100 ps
CPU time 295.15 seconds
Started Jul 19 04:25:20 PM PDT 24
Finished Jul 19 04:30:35 PM PDT 24
Peak memory 199968 kb
Host smart-03239683-5f8b-4bc2-a721-7fb5f06153af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1687604965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1687604965
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1637939887
Short name T964
Test name
Test status
Simulation time 5596995678 ps
CPU time 45.71 seconds
Started Jul 19 04:25:28 PM PDT 24
Finished Jul 19 04:26:32 PM PDT 24
Peak memory 198196 kb
Host smart-3bf6c70e-bbeb-433a-8d26-941cb91bb753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1637939887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1637939887
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3680589346
Short name T589
Test name
Test status
Simulation time 71281375559 ps
CPU time 243.05 seconds
Started Jul 19 04:25:19 PM PDT 24
Finished Jul 19 04:29:42 PM PDT 24
Peak memory 199996 kb
Host smart-8a56008c-ffae-4ddc-a958-a395020bfee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680589346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3680589346
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1197807350
Short name T719
Test name
Test status
Simulation time 31790472176 ps
CPU time 22.8 seconds
Started Jul 19 04:25:29 PM PDT 24
Finished Jul 19 04:26:10 PM PDT 24
Peak memory 195776 kb
Host smart-1284df3c-eff7-411a-b27d-22596cb4c629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197807350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1197807350
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1660338168
Short name T101
Test name
Test status
Simulation time 56119069 ps
CPU time 0.85 seconds
Started Jul 19 04:25:21 PM PDT 24
Finished Jul 19 04:25:41 PM PDT 24
Peak memory 218152 kb
Host smart-98794a5a-b06d-4f46-b630-ed4a40b99289
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660338168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1660338168
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.276644201
Short name T789
Test name
Test status
Simulation time 458165677 ps
CPU time 2.08 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:25:40 PM PDT 24
Peak memory 199852 kb
Host smart-f46a62a8-9ba8-4886-a529-b00a15c20479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276644201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.276644201
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2408417762
Short name T245
Test name
Test status
Simulation time 126371881765 ps
CPU time 44.31 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:26:22 PM PDT 24
Peak memory 199972 kb
Host smart-a871bcbd-0612-4255-9e4d-adc8a722fbae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408417762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2408417762
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2739703447
Short name T906
Test name
Test status
Simulation time 25648646200 ps
CPU time 311.99 seconds
Started Jul 19 04:25:19 PM PDT 24
Finished Jul 19 04:30:51 PM PDT 24
Peak memory 216360 kb
Host smart-f0ecd799-7a6d-43bd-8fbb-3cd891f792c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739703447 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2739703447
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3545829783
Short name T957
Test name
Test status
Simulation time 7289456586 ps
CPU time 21.12 seconds
Started Jul 19 04:25:17 PM PDT 24
Finished Jul 19 04:25:58 PM PDT 24
Peak memory 199396 kb
Host smart-28b65640-6081-4faa-b26b-5a82aa297426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545829783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3545829783
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1174908256
Short name T294
Test name
Test status
Simulation time 64494323730 ps
CPU time 84.09 seconds
Started Jul 19 04:25:22 PM PDT 24
Finished Jul 19 04:27:06 PM PDT 24
Peak memory 199980 kb
Host smart-02f34ffe-91e9-4b69-b6a9-55c8b8728bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174908256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1174908256
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.5458127
Short name T383
Test name
Test status
Simulation time 11996764 ps
CPU time 0.55 seconds
Started Jul 19 04:27:07 PM PDT 24
Finished Jul 19 04:27:14 PM PDT 24
Peak memory 195360 kb
Host smart-00c8e39c-6fda-495f-a87e-ada51fa85904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5458127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.5458127
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2417160641
Short name T714
Test name
Test status
Simulation time 27622716896 ps
CPU time 44.41 seconds
Started Jul 19 04:26:57 PM PDT 24
Finished Jul 19 04:27:47 PM PDT 24
Peak memory 199896 kb
Host smart-1da130f5-0f52-4aa2-87db-b619fbc21a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417160641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2417160641
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2634395353
Short name T615
Test name
Test status
Simulation time 22048111121 ps
CPU time 23.51 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:27:24 PM PDT 24
Peak memory 199988 kb
Host smart-cb9742e6-dbe4-4cf3-9820-d872797eaeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634395353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2634395353
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.201485663
Short name T332
Test name
Test status
Simulation time 121051593905 ps
CPU time 62.19 seconds
Started Jul 19 04:26:55 PM PDT 24
Finished Jul 19 04:28:03 PM PDT 24
Peak memory 199928 kb
Host smart-cf16a525-e819-4aa7-948b-cbd4d422318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201485663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.201485663
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.689193216
Short name T945
Test name
Test status
Simulation time 38775171993 ps
CPU time 57.02 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:28:12 PM PDT 24
Peak memory 200180 kb
Host smart-64ca71e3-f427-421f-8129-1676cb3833ef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689193216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.689193216
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1656462872
Short name T1173
Test name
Test status
Simulation time 49880097055 ps
CPU time 276.85 seconds
Started Jul 19 04:27:07 PM PDT 24
Finished Jul 19 04:31:50 PM PDT 24
Peak memory 199924 kb
Host smart-f2b6ad48-842b-4202-a10e-acd858dde8b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656462872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1656462872
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2479413043
Short name T703
Test name
Test status
Simulation time 4581782984 ps
CPU time 6.91 seconds
Started Jul 19 04:27:10 PM PDT 24
Finished Jul 19 04:27:23 PM PDT 24
Peak memory 199704 kb
Host smart-7d63b991-e4f5-404b-bbae-4e1675e4eac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479413043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2479413043
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1874557943
Short name T1160
Test name
Test status
Simulation time 37914535021 ps
CPU time 21.52 seconds
Started Jul 19 04:27:04 PM PDT 24
Finished Jul 19 04:27:30 PM PDT 24
Peak memory 194900 kb
Host smart-df64af43-6736-4fbc-8daa-54b30b82e8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874557943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1874557943
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1388467529
Short name T378
Test name
Test status
Simulation time 10563193949 ps
CPU time 470.74 seconds
Started Jul 19 04:27:05 PM PDT 24
Finished Jul 19 04:35:01 PM PDT 24
Peak memory 199880 kb
Host smart-360419d7-7b42-442e-a76d-fc75b8e058ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388467529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1388467529
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.4158227540
Short name T693
Test name
Test status
Simulation time 1298162553 ps
CPU time 1.85 seconds
Started Jul 19 04:27:06 PM PDT 24
Finished Jul 19 04:27:14 PM PDT 24
Peak memory 198076 kb
Host smart-33809d11-dce3-447b-9656-44da88363b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158227540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.4158227540
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1871412779
Short name T677
Test name
Test status
Simulation time 205082124928 ps
CPU time 77.93 seconds
Started Jul 19 04:27:04 PM PDT 24
Finished Jul 19 04:28:26 PM PDT 24
Peak memory 199904 kb
Host smart-c4937edf-cef1-4603-93a7-5be929d282c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871412779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1871412779
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3455353984
Short name T1050
Test name
Test status
Simulation time 3714259577 ps
CPU time 2.28 seconds
Started Jul 19 04:27:06 PM PDT 24
Finished Jul 19 04:27:14 PM PDT 24
Peak memory 195948 kb
Host smart-903ccccb-7470-45da-bfd8-6f2fe3dcf932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455353984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3455353984
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.934883137
Short name T630
Test name
Test status
Simulation time 493311179 ps
CPU time 2.17 seconds
Started Jul 19 04:26:56 PM PDT 24
Finished Jul 19 04:27:03 PM PDT 24
Peak memory 199664 kb
Host smart-c5e0d3ee-1165-4847-aa8f-00ce9a6063d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934883137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.934883137
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1477570456
Short name T605
Test name
Test status
Simulation time 344528922124 ps
CPU time 398.41 seconds
Started Jul 19 04:27:10 PM PDT 24
Finished Jul 19 04:33:54 PM PDT 24
Peak memory 199944 kb
Host smart-0eb892c3-7588-4a98-9a54-d9cfb769482a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477570456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1477570456
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3395321638
Short name T990
Test name
Test status
Simulation time 27291176285 ps
CPU time 245.26 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:31:20 PM PDT 24
Peak memory 210796 kb
Host smart-bb0369a7-96a1-41f7-a0dc-8f85e1ac0b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395321638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3395321638
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1217737234
Short name T361
Test name
Test status
Simulation time 1956037445 ps
CPU time 1.83 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:27:17 PM PDT 24
Peak memory 198940 kb
Host smart-421bd236-46ca-47eb-8188-6d9a4a1ce5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217737234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1217737234
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1555000044
Short name T1031
Test name
Test status
Simulation time 112945569982 ps
CPU time 91.85 seconds
Started Jul 19 04:26:54 PM PDT 24
Finished Jul 19 04:28:31 PM PDT 24
Peak memory 199924 kb
Host smart-8a0343ff-4338-4e0e-afc1-3cee24d76b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555000044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1555000044
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.163572200
Short name T818
Test name
Test status
Simulation time 13735834 ps
CPU time 0.56 seconds
Started Jul 19 04:27:06 PM PDT 24
Finished Jul 19 04:27:12 PM PDT 24
Peak memory 195644 kb
Host smart-237e53bd-8c15-4206-8b02-84f06e7a3c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163572200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.163572200
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3352726439
Short name T796
Test name
Test status
Simulation time 74174679755 ps
CPU time 120.1 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:29:16 PM PDT 24
Peak memory 199072 kb
Host smart-e8961096-c029-4e3c-bd22-00e1a1cf943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352726439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3352726439
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1126191159
Short name T365
Test name
Test status
Simulation time 48979943143 ps
CPU time 40.74 seconds
Started Jul 19 04:27:06 PM PDT 24
Finished Jul 19 04:27:54 PM PDT 24
Peak memory 199928 kb
Host smart-6171a6bd-d2c1-4b58-8436-c1781ccf338d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126191159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1126191159
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.172962311
Short name T239
Test name
Test status
Simulation time 111771346607 ps
CPU time 32.36 seconds
Started Jul 19 04:27:08 PM PDT 24
Finished Jul 19 04:27:47 PM PDT 24
Peak memory 199956 kb
Host smart-d5f5d1b4-cb9c-414b-b2f5-2000676916ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172962311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.172962311
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.4096860756
Short name T702
Test name
Test status
Simulation time 38884660089 ps
CPU time 51.21 seconds
Started Jul 19 04:27:06 PM PDT 24
Finished Jul 19 04:28:03 PM PDT 24
Peak memory 199812 kb
Host smart-41925d01-3514-47d0-a58d-9149eb4c5ab3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096860756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.4096860756
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.4176684146
Short name T1
Test name
Test status
Simulation time 187267337139 ps
CPU time 1419.76 seconds
Started Jul 19 04:27:05 PM PDT 24
Finished Jul 19 04:50:50 PM PDT 24
Peak memory 199900 kb
Host smart-d571a7a7-4630-4450-8187-3d19bb4845ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4176684146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4176684146
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.783870975
Short name T1040
Test name
Test status
Simulation time 4254252757 ps
CPU time 9.74 seconds
Started Jul 19 04:27:08 PM PDT 24
Finished Jul 19 04:27:24 PM PDT 24
Peak memory 199636 kb
Host smart-50817329-440e-409c-b48e-b07d81ae9568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783870975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.783870975
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2267733116
Short name T580
Test name
Test status
Simulation time 213498228548 ps
CPU time 157.85 seconds
Started Jul 19 04:27:10 PM PDT 24
Finished Jul 19 04:29:54 PM PDT 24
Peak memory 208200 kb
Host smart-2fdc1bb0-c65c-4f52-a174-24558ebc5b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267733116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2267733116
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1665649797
Short name T286
Test name
Test status
Simulation time 12047644655 ps
CPU time 137.15 seconds
Started Jul 19 04:27:06 PM PDT 24
Finished Jul 19 04:29:29 PM PDT 24
Peak memory 199928 kb
Host smart-4ca4b9e6-e87e-45b8-8cdc-9fe98d40a768
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1665649797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1665649797
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.883462086
Short name T430
Test name
Test status
Simulation time 3949567573 ps
CPU time 14.26 seconds
Started Jul 19 04:27:04 PM PDT 24
Finished Jul 19 04:27:23 PM PDT 24
Peak memory 197988 kb
Host smart-fb992a3a-fd0b-4847-9f11-b85aaefe1320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883462086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.883462086
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.878376951
Short name T279
Test name
Test status
Simulation time 65708483117 ps
CPU time 72.85 seconds
Started Jul 19 04:27:04 PM PDT 24
Finished Jul 19 04:28:21 PM PDT 24
Peak memory 199896 kb
Host smart-7dc236f4-82c3-4944-8af1-0941548fe95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878376951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.878376951
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1245956308
Short name T1078
Test name
Test status
Simulation time 4501065565 ps
CPU time 3.81 seconds
Started Jul 19 04:27:11 PM PDT 24
Finished Jul 19 04:27:20 PM PDT 24
Peak memory 196240 kb
Host smart-d0b51c35-5619-41cf-b25a-ea227c86e860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245956308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1245956308
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.807312033
Short name T991
Test name
Test status
Simulation time 532771279 ps
CPU time 1.41 seconds
Started Jul 19 04:27:04 PM PDT 24
Finished Jul 19 04:27:10 PM PDT 24
Peak memory 198588 kb
Host smart-cb20579f-1c62-4248-9f04-dd6fd8211068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807312033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.807312033
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.666111780
Short name T168
Test name
Test status
Simulation time 436555019181 ps
CPU time 375.11 seconds
Started Jul 19 04:27:07 PM PDT 24
Finished Jul 19 04:33:28 PM PDT 24
Peak memory 199972 kb
Host smart-c1f66ef3-96db-42b2-ad81-f422f49b7ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666111780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.666111780
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3959791613
Short name T811
Test name
Test status
Simulation time 49451627493 ps
CPU time 301.02 seconds
Started Jul 19 04:27:08 PM PDT 24
Finished Jul 19 04:32:15 PM PDT 24
Peak memory 216644 kb
Host smart-40d88b6c-a151-46ba-b25e-976489d0e37a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959791613 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3959791613
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2641029874
Short name T1143
Test name
Test status
Simulation time 1181238931 ps
CPU time 1.59 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:27:17 PM PDT 24
Peak memory 198548 kb
Host smart-4759a388-a72f-46ec-98d9-af54900b30d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641029874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2641029874
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2168168145
Short name T1162
Test name
Test status
Simulation time 45323425398 ps
CPU time 35.49 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:27:51 PM PDT 24
Peak memory 199980 kb
Host smart-261494cb-484a-4c0d-a3c2-a6e39b879289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168168145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2168168145
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.510709903
Short name T388
Test name
Test status
Simulation time 28153956 ps
CPU time 0.53 seconds
Started Jul 19 04:27:05 PM PDT 24
Finished Jul 19 04:27:10 PM PDT 24
Peak memory 194808 kb
Host smart-d02ec611-8472-446f-8132-5b82e91e9e82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510709903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.510709903
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2578191809
Short name T412
Test name
Test status
Simulation time 61615779611 ps
CPU time 60.64 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:28:17 PM PDT 24
Peak memory 199916 kb
Host smart-f5bc43d2-f191-4372-a6cd-c76a520086a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578191809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2578191809
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.4047673874
Short name T645
Test name
Test status
Simulation time 70355626811 ps
CPU time 26.84 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:27:42 PM PDT 24
Peak memory 199952 kb
Host smart-9b41b0b7-1738-4dee-b083-9a0f80d950ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047673874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.4047673874
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.4187488621
Short name T739
Test name
Test status
Simulation time 52119073094 ps
CPU time 114.43 seconds
Started Jul 19 04:27:04 PM PDT 24
Finished Jul 19 04:29:03 PM PDT 24
Peak memory 199988 kb
Host smart-576d249c-0965-4b58-8b13-a1cf56087ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187488621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.4187488621
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.353191907
Short name T631
Test name
Test status
Simulation time 9481741702 ps
CPU time 3.51 seconds
Started Jul 19 04:27:19 PM PDT 24
Finished Jul 19 04:27:24 PM PDT 24
Peak memory 199516 kb
Host smart-5f0d343c-4d55-49ea-bc1e-4420d7161b98
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353191907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.353191907
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1635910124
Short name T260
Test name
Test status
Simulation time 146311439556 ps
CPU time 1140.77 seconds
Started Jul 19 04:27:06 PM PDT 24
Finished Jul 19 04:46:13 PM PDT 24
Peak memory 199940 kb
Host smart-ab55384d-1695-4736-a1a1-678743521221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635910124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1635910124
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.4062534039
Short name T356
Test name
Test status
Simulation time 4720797743 ps
CPU time 1.75 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:27:17 PM PDT 24
Peak memory 197772 kb
Host smart-6e7ac768-7549-4584-9d8f-a6b6b40ee558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062534039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.4062534039
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1425040355
Short name T434
Test name
Test status
Simulation time 95062734053 ps
CPU time 80.89 seconds
Started Jul 19 04:27:02 PM PDT 24
Finished Jul 19 04:28:27 PM PDT 24
Peak memory 200092 kb
Host smart-77bb2bd2-e3c4-4689-a0f7-16ecbc8e2cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425040355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1425040355
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.136314902
Short name T642
Test name
Test status
Simulation time 9022616105 ps
CPU time 538.16 seconds
Started Jul 19 04:27:08 PM PDT 24
Finished Jul 19 04:36:12 PM PDT 24
Peak memory 199996 kb
Host smart-f45909a3-7bd1-489f-b985-645442478ab2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=136314902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.136314902
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3508278349
Short name T896
Test name
Test status
Simulation time 3670761545 ps
CPU time 3.12 seconds
Started Jul 19 04:27:03 PM PDT 24
Finished Jul 19 04:27:11 PM PDT 24
Peak memory 197816 kb
Host smart-0732c635-beb5-4200-a6f9-b80301663e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508278349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3508278349
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2582394172
Short name T742
Test name
Test status
Simulation time 36873555015 ps
CPU time 16.04 seconds
Started Jul 19 04:27:05 PM PDT 24
Finished Jul 19 04:27:26 PM PDT 24
Peak memory 200076 kb
Host smart-df6d57d0-06bc-4e04-b9c5-6b7561e34323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582394172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2582394172
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3555859207
Short name T1044
Test name
Test status
Simulation time 4240110337 ps
CPU time 2.18 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:27:18 PM PDT 24
Peak memory 195144 kb
Host smart-9d076f6d-c0d0-4e91-a780-111fac9dd874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555859207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3555859207
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.367383921
Short name T528
Test name
Test status
Simulation time 337744915 ps
CPU time 0.9 seconds
Started Jul 19 04:27:08 PM PDT 24
Finished Jul 19 04:27:15 PM PDT 24
Peak memory 198464 kb
Host smart-a4a88833-328e-4d9d-a5a3-2d3ffad82f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367383921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.367383921
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3312231017
Short name T854
Test name
Test status
Simulation time 95614239811 ps
CPU time 479.67 seconds
Started Jul 19 04:27:05 PM PDT 24
Finished Jul 19 04:35:10 PM PDT 24
Peak memory 216480 kb
Host smart-dd84f2c0-54ab-4fc1-9cf5-0d588cb34057
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312231017 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3312231017
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2042251517
Short name T790
Test name
Test status
Simulation time 1567352851 ps
CPU time 2.19 seconds
Started Jul 19 04:27:06 PM PDT 24
Finished Jul 19 04:27:15 PM PDT 24
Peak memory 198748 kb
Host smart-5ff7c130-1f8a-4ade-8a41-230a47423856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042251517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2042251517
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3433505742
Short name T39
Test name
Test status
Simulation time 22983926565 ps
CPU time 35.11 seconds
Started Jul 19 04:27:07 PM PDT 24
Finished Jul 19 04:27:49 PM PDT 24
Peak memory 199992 kb
Host smart-76958b71-b847-44f5-a2fb-fc22a5951e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433505742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3433505742
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1994409527
Short name T763
Test name
Test status
Simulation time 32406696 ps
CPU time 0.56 seconds
Started Jul 19 04:27:07 PM PDT 24
Finished Jul 19 04:27:14 PM PDT 24
Peak memory 195360 kb
Host smart-385755a5-5d27-4fef-a29a-e13a78aa8ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994409527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1994409527
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.631514401
Short name T271
Test name
Test status
Simulation time 27882199656 ps
CPU time 22.94 seconds
Started Jul 19 04:27:08 PM PDT 24
Finished Jul 19 04:27:37 PM PDT 24
Peak memory 199936 kb
Host smart-8c21d924-55b7-4dc8-8f94-f9d6259cdf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631514401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.631514401
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.486260056
Short name T806
Test name
Test status
Simulation time 26368970510 ps
CPU time 14.13 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:27:29 PM PDT 24
Peak memory 199924 kb
Host smart-6339737a-6117-4cfa-b09b-9b5a98c9bb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486260056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.486260056
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3227021891
Short name T195
Test name
Test status
Simulation time 55835918282 ps
CPU time 81.06 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:28:37 PM PDT 24
Peak memory 199988 kb
Host smart-1a968916-c216-41b0-9a79-5f2aea086cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227021891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3227021891
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.4015555400
Short name T891
Test name
Test status
Simulation time 61053748933 ps
CPU time 24.34 seconds
Started Jul 19 04:27:08 PM PDT 24
Finished Jul 19 04:27:38 PM PDT 24
Peak memory 199868 kb
Host smart-17b57ea1-68ce-42fd-bfa6-3f77a223e2a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015555400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.4015555400
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.4067416564
Short name T261
Test name
Test status
Simulation time 107339783661 ps
CPU time 569.41 seconds
Started Jul 19 04:27:08 PM PDT 24
Finished Jul 19 04:36:44 PM PDT 24
Peak memory 199940 kb
Host smart-b63ae8fd-b4c3-4a98-a4f3-e1a8c3f268c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4067416564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4067416564
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1152597957
Short name T345
Test name
Test status
Simulation time 5026007573 ps
CPU time 2.09 seconds
Started Jul 19 04:27:07 PM PDT 24
Finished Jul 19 04:27:15 PM PDT 24
Peak memory 199704 kb
Host smart-56cf5e11-172f-4dc9-8ad1-df6090d10522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152597957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1152597957
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3462858475
Short name T1042
Test name
Test status
Simulation time 146534552071 ps
CPU time 54.04 seconds
Started Jul 19 04:27:08 PM PDT 24
Finished Jul 19 04:28:09 PM PDT 24
Peak memory 199248 kb
Host smart-de5028d3-d7c8-47c6-8fca-c12300723c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462858475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3462858475
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.229742539
Short name T405
Test name
Test status
Simulation time 13639566440 ps
CPU time 208.1 seconds
Started Jul 19 04:27:07 PM PDT 24
Finished Jul 19 04:30:42 PM PDT 24
Peak memory 199892 kb
Host smart-29f11188-a306-4326-b90c-b065c6f91328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229742539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.229742539
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2043251549
Short name T419
Test name
Test status
Simulation time 3494350683 ps
CPU time 29.45 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:27:45 PM PDT 24
Peak memory 199448 kb
Host smart-ca60932e-e86b-4256-a678-6c28777033e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043251549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2043251549
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1451762252
Short name T377
Test name
Test status
Simulation time 23875418300 ps
CPU time 9.61 seconds
Started Jul 19 04:27:08 PM PDT 24
Finished Jul 19 04:27:23 PM PDT 24
Peak memory 200096 kb
Host smart-6b80664c-badd-4a9e-a07e-b6e0b4bc6465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451762252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1451762252
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.492954782
Short name T288
Test name
Test status
Simulation time 2412601105 ps
CPU time 3.89 seconds
Started Jul 19 04:27:07 PM PDT 24
Finished Jul 19 04:27:17 PM PDT 24
Peak memory 196552 kb
Host smart-3f5b5da8-c122-4584-ba23-effaa041ea79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492954782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.492954782
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.626942874
Short name T1155
Test name
Test status
Simulation time 5564101311 ps
CPU time 10.06 seconds
Started Jul 19 04:27:07 PM PDT 24
Finished Jul 19 04:27:23 PM PDT 24
Peak memory 199772 kb
Host smart-64db91a5-4297-4527-8d8b-f2180cdd4aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626942874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.626942874
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1267493692
Short name T1163
Test name
Test status
Simulation time 1528566352672 ps
CPU time 443.66 seconds
Started Jul 19 04:27:08 PM PDT 24
Finished Jul 19 04:34:38 PM PDT 24
Peak memory 199972 kb
Host smart-cb15b505-e1f8-45c4-b74d-9bb29d693529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267493692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1267493692
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.82917779
Short name T947
Test name
Test status
Simulation time 30528146398 ps
CPU time 317.62 seconds
Started Jul 19 04:27:12 PM PDT 24
Finished Jul 19 04:32:34 PM PDT 24
Peak memory 215652 kb
Host smart-dee00880-adae-496e-8647-d1d093cbc74c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82917779 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.82917779
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3570247835
Short name T602
Test name
Test status
Simulation time 7961982419 ps
CPU time 12.74 seconds
Started Jul 19 04:27:09 PM PDT 24
Finished Jul 19 04:27:28 PM PDT 24
Peak memory 199968 kb
Host smart-c3ceb806-8a02-4a45-91df-2790c84d5848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570247835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3570247835
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_alert_test.3091340681
Short name T622
Test name
Test status
Simulation time 43301928 ps
CPU time 0.57 seconds
Started Jul 19 04:27:23 PM PDT 24
Finished Jul 19 04:27:29 PM PDT 24
Peak memory 195076 kb
Host smart-ec17a281-00d5-48f6-838f-b6f928e79073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091340681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3091340681
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3756928454
Short name T841
Test name
Test status
Simulation time 66695650274 ps
CPU time 27.18 seconds
Started Jul 19 04:27:23 PM PDT 24
Finished Jul 19 04:27:56 PM PDT 24
Peak memory 199828 kb
Host smart-25a11f95-cf54-4f4c-95bb-79a78a9a474e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756928454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3756928454
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3385939329
Short name T801
Test name
Test status
Simulation time 34095170252 ps
CPU time 13.65 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:40 PM PDT 24
Peak memory 199372 kb
Host smart-c8c71ebe-4e30-48c4-a87a-b2702f84c069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385939329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3385939329
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2299889233
Short name T441
Test name
Test status
Simulation time 55050059352 ps
CPU time 118.56 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:29:26 PM PDT 24
Peak memory 199928 kb
Host smart-af39b63e-2f88-4e0c-98d7-e797a256efe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299889233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2299889233
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2512166538
Short name T655
Test name
Test status
Simulation time 54356704189 ps
CPU time 44.06 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:28:12 PM PDT 24
Peak memory 200320 kb
Host smart-63c78a6e-76f5-4a41-a7d6-4036b01b4b4a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512166538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2512166538
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2682514756
Short name T988
Test name
Test status
Simulation time 162194415367 ps
CPU time 537.11 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:36:24 PM PDT 24
Peak memory 199972 kb
Host smart-2e6a8591-23a1-497c-8014-da0329fafb98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2682514756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2682514756
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3867209876
Short name T1122
Test name
Test status
Simulation time 2746249119 ps
CPU time 4.22 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:27:32 PM PDT 24
Peak memory 197260 kb
Host smart-bf6df11f-5cb0-4c1a-94cd-76b9c4b84eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867209876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3867209876
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3862546835
Short name T1024
Test name
Test status
Simulation time 33882569951 ps
CPU time 12.58 seconds
Started Jul 19 04:27:20 PM PDT 24
Finished Jul 19 04:27:34 PM PDT 24
Peak memory 195948 kb
Host smart-b3542dc3-9051-4aab-a014-4f840213fd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862546835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3862546835
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.4263258171
Short name T1168
Test name
Test status
Simulation time 1337216984 ps
CPU time 16.71 seconds
Started Jul 19 04:27:19 PM PDT 24
Finished Jul 19 04:27:37 PM PDT 24
Peak memory 199896 kb
Host smart-780dd05b-c7d1-488d-85e8-4bc66d717830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263258171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.4263258171
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3540402145
Short name T343
Test name
Test status
Simulation time 4771005023 ps
CPU time 14.11 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:39 PM PDT 24
Peak memory 199252 kb
Host smart-409e552a-4be7-4fe0-a4de-ac9326b9830a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3540402145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3540402145
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1997231954
Short name T1063
Test name
Test status
Simulation time 102470350304 ps
CPU time 40.64 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:28:06 PM PDT 24
Peak memory 199404 kb
Host smart-13373cef-b735-4d40-b818-efa798e2886e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997231954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1997231954
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.700640653
Short name T48
Test name
Test status
Simulation time 3395207813 ps
CPU time 5.48 seconds
Started Jul 19 04:27:23 PM PDT 24
Finished Jul 19 04:27:34 PM PDT 24
Peak memory 195932 kb
Host smart-b52a6819-d1a1-4b58-96b5-45835ef333a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700640653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.700640653
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1511868702
Short name T816
Test name
Test status
Simulation time 747954604 ps
CPU time 1.47 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:26 PM PDT 24
Peak memory 198744 kb
Host smart-84cdcdfd-7a54-40cf-a7d9-693ac614477b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511868702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1511868702
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.684324662
Short name T893
Test name
Test status
Simulation time 135816761136 ps
CPU time 974.69 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:43:42 PM PDT 24
Peak memory 208388 kb
Host smart-e6687840-4d55-44ca-8b81-026e62e902cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684324662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.684324662
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2422807985
Short name T118
Test name
Test status
Simulation time 111479116940 ps
CPU time 665.65 seconds
Started Jul 19 04:27:20 PM PDT 24
Finished Jul 19 04:38:28 PM PDT 24
Peak memory 216484 kb
Host smart-5a1ffba2-9f77-494e-a088-76cf7a9d1f52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422807985 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2422807985
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.4031174496
Short name T979
Test name
Test status
Simulation time 712611054 ps
CPU time 2.5 seconds
Started Jul 19 04:27:20 PM PDT 24
Finished Jul 19 04:27:26 PM PDT 24
Peak memory 199452 kb
Host smart-555558d3-f7ee-437a-8fb7-2031e842894d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031174496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.4031174496
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.61383047
Short name T566
Test name
Test status
Simulation time 16144166968 ps
CPU time 12.16 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:39 PM PDT 24
Peak memory 198788 kb
Host smart-622d366b-4793-495b-b0f6-7336135d3955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61383047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.61383047
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1870616930
Short name T5
Test name
Test status
Simulation time 16165771 ps
CPU time 0.56 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:27 PM PDT 24
Peak memory 195328 kb
Host smart-67999a29-344a-4339-abfc-2dcabcd64da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870616930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1870616930
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2006915482
Short name T1110
Test name
Test status
Simulation time 28121180058 ps
CPU time 46.99 seconds
Started Jul 19 04:27:19 PM PDT 24
Finished Jul 19 04:28:08 PM PDT 24
Peak memory 199948 kb
Host smart-e09a5619-d693-4c7c-8bc2-571b89cd760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006915482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2006915482
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3009548280
Short name T751
Test name
Test status
Simulation time 124782197042 ps
CPU time 128.6 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:29:34 PM PDT 24
Peak memory 199988 kb
Host smart-bb139ae3-9c31-417b-8ea3-a523539d371d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009548280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3009548280
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3298659096
Short name T196
Test name
Test status
Simulation time 57934623214 ps
CPU time 98.25 seconds
Started Jul 19 04:27:20 PM PDT 24
Finished Jul 19 04:29:00 PM PDT 24
Peak memory 199928 kb
Host smart-02c4134f-e10a-4572-8faa-a7dd68319ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298659096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3298659096
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3179226507
Short name T877
Test name
Test status
Simulation time 10301607347 ps
CPU time 3.41 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:28 PM PDT 24
Peak memory 200012 kb
Host smart-95ee1ab3-1a75-4abc-bfe8-67270df504e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179226507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3179226507
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.4115977662
Short name T387
Test name
Test status
Simulation time 292797104178 ps
CPU time 213.12 seconds
Started Jul 19 04:27:20 PM PDT 24
Finished Jul 19 04:30:54 PM PDT 24
Peak memory 199912 kb
Host smart-15fe3e2a-4570-41cb-818a-8d3345b0bce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115977662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.4115977662
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.4103002343
Short name T1032
Test name
Test status
Simulation time 5020398017 ps
CPU time 11.66 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:38 PM PDT 24
Peak memory 199948 kb
Host smart-ef8aaa4c-fcdd-4f39-b18f-59e979ed5307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103002343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.4103002343
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3145248219
Short name T457
Test name
Test status
Simulation time 83537302961 ps
CPU time 129.22 seconds
Started Jul 19 04:27:23 PM PDT 24
Finished Jul 19 04:29:38 PM PDT 24
Peak memory 199752 kb
Host smart-94caf87d-2ad8-420d-b846-3218be357926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145248219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3145248219
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.117521084
Short name T300
Test name
Test status
Simulation time 5084416920 ps
CPU time 17.76 seconds
Started Jul 19 04:27:20 PM PDT 24
Finished Jul 19 04:27:39 PM PDT 24
Peak memory 200088 kb
Host smart-8b8b134e-99dd-47c6-bd17-8885c8b5e180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117521084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.117521084
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1878050731
Short name T661
Test name
Test status
Simulation time 2755608405 ps
CPU time 5.42 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:27:32 PM PDT 24
Peak memory 198004 kb
Host smart-9cf8522d-5484-4ece-ae6d-ed5057010eba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878050731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1878050731
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3023773313
Short name T986
Test name
Test status
Simulation time 31393204129 ps
CPU time 44.8 seconds
Started Jul 19 04:27:23 PM PDT 24
Finished Jul 19 04:28:13 PM PDT 24
Peak memory 200176 kb
Host smart-24b254a8-8a01-434b-ba2b-8f3f3009509a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023773313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3023773313
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2369040975
Short name T313
Test name
Test status
Simulation time 4199503334 ps
CPU time 6.68 seconds
Started Jul 19 04:27:20 PM PDT 24
Finished Jul 19 04:27:30 PM PDT 24
Peak memory 196072 kb
Host smart-67e9cfea-9cc2-4e6f-b61f-c5ba9fcb2776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369040975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2369040975
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2720436052
Short name T381
Test name
Test status
Simulation time 5983083566 ps
CPU time 25.11 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:27:53 PM PDT 24
Peak memory 199280 kb
Host smart-76b62e40-b1d9-43e3-ae7e-5b04a94a78b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720436052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2720436052
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2796329904
Short name T481
Test name
Test status
Simulation time 44482298338 ps
CPU time 1799.06 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:57:27 PM PDT 24
Peak memory 199888 kb
Host smart-deb7ba6d-4af9-4525-8b1d-2c69a67b05e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796329904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2796329904
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2962082466
Short name T1028
Test name
Test status
Simulation time 110944088838 ps
CPU time 287.68 seconds
Started Jul 19 04:27:23 PM PDT 24
Finished Jul 19 04:32:16 PM PDT 24
Peak memory 216984 kb
Host smart-e33e296e-fdb4-4c81-83e1-4581caa28860
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962082466 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2962082466
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.4251980066
Short name T866
Test name
Test status
Simulation time 968796817 ps
CPU time 3.13 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:28 PM PDT 24
Peak memory 199812 kb
Host smart-a680460b-c1dc-4cb9-98d1-174692ce63c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251980066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.4251980066
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3307514034
Short name T385
Test name
Test status
Simulation time 176047489531 ps
CPU time 39.85 seconds
Started Jul 19 04:27:19 PM PDT 24
Finished Jul 19 04:28:00 PM PDT 24
Peak memory 199984 kb
Host smart-f145c8cf-f5b5-4a06-b97e-1b3b624f1f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307514034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3307514034
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1685835862
Short name T439
Test name
Test status
Simulation time 77601966 ps
CPU time 0.55 seconds
Started Jul 19 04:27:20 PM PDT 24
Finished Jul 19 04:27:23 PM PDT 24
Peak memory 195376 kb
Host smart-2536e631-4bcf-4094-8b8e-855e282a4438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685835862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1685835862
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2832678698
Short name T846
Test name
Test status
Simulation time 47042381461 ps
CPU time 38.75 seconds
Started Jul 19 04:27:20 PM PDT 24
Finished Jul 19 04:28:00 PM PDT 24
Peak memory 199948 kb
Host smart-66280034-c358-473f-b7e1-515deca65a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832678698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2832678698
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3630972435
Short name T853
Test name
Test status
Simulation time 137485821439 ps
CPU time 134.68 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:29:42 PM PDT 24
Peak memory 199920 kb
Host smart-7dcab335-1be7-4131-a128-817fd31f1d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630972435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3630972435
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.871997442
Short name T518
Test name
Test status
Simulation time 32808345431 ps
CPU time 60.46 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:28:27 PM PDT 24
Peak memory 199876 kb
Host smart-8ce067e3-0e65-432a-b049-9078d61effd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871997442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.871997442
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3631297360
Short name T715
Test name
Test status
Simulation time 32076299605 ps
CPU time 43.45 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:28:10 PM PDT 24
Peak memory 199928 kb
Host smart-2baff8ee-9b78-4432-b336-da24c9bc1a9a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631297360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3631297360
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3061711930
Short name T470
Test name
Test status
Simulation time 81704234642 ps
CPU time 386.9 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:33:54 PM PDT 24
Peak memory 199880 kb
Host smart-34159a31-7b07-4950-bf7c-a88370451e89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3061711930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3061711930
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.663325368
Short name T657
Test name
Test status
Simulation time 2303734733 ps
CPU time 1.77 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:28 PM PDT 24
Peak memory 198756 kb
Host smart-16b905c3-47ff-464a-859b-e7dfb8714ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663325368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.663325368
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.807998366
Short name T775
Test name
Test status
Simulation time 49310181783 ps
CPU time 10.65 seconds
Started Jul 19 04:27:24 PM PDT 24
Finished Jul 19 04:27:40 PM PDT 24
Peak memory 198516 kb
Host smart-8db180d5-ad58-4a70-a4a9-8832780ceebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807998366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.807998366
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1924080345
Short name T901
Test name
Test status
Simulation time 15676697826 ps
CPU time 441.35 seconds
Started Jul 19 04:27:23 PM PDT 24
Finished Jul 19 04:34:50 PM PDT 24
Peak memory 199820 kb
Host smart-38126474-7a37-45b8-9670-3d073865d357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924080345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1924080345
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.155776888
Short name T1136
Test name
Test status
Simulation time 6258626656 ps
CPU time 12.2 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:27:39 PM PDT 24
Peak memory 198180 kb
Host smart-bff9e00d-37d5-44df-a442-f67ba055e0fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=155776888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.155776888
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.290053074
Short name T783
Test name
Test status
Simulation time 13904434038 ps
CPU time 12.89 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:38 PM PDT 24
Peak memory 199988 kb
Host smart-5f2b3a59-3074-49c0-8035-c7d424d2d0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290053074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.290053074
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1314524637
Short name T1178
Test name
Test status
Simulation time 4670689041 ps
CPU time 8.17 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:27:36 PM PDT 24
Peak memory 196076 kb
Host smart-03791bcc-96f5-461e-b5e3-41fdf4fe381d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314524637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1314524637
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1856385952
Short name T367
Test name
Test status
Simulation time 690793014 ps
CPU time 3.2 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:29 PM PDT 24
Peak memory 198328 kb
Host smart-3a8c6c6e-050a-43ba-8a96-2fe39860e299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856385952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1856385952
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3309796047
Short name T269
Test name
Test status
Simulation time 342669724526 ps
CPU time 555.56 seconds
Started Jul 19 04:27:26 PM PDT 24
Finished Jul 19 04:36:45 PM PDT 24
Peak memory 200328 kb
Host smart-5e2e915e-dc2b-4fae-ac77-71e41bd205c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309796047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3309796047
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3884819100
Short name T492
Test name
Test status
Simulation time 910890976 ps
CPU time 3.04 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:27 PM PDT 24
Peak memory 198320 kb
Host smart-ab31a5ab-2ff7-47b2-a9fd-1986f6601730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884819100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3884819100
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.729109798
Short name T967
Test name
Test status
Simulation time 36557410295 ps
CPU time 48.74 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:28:13 PM PDT 24
Peak memory 199928 kb
Host smart-53964946-2768-4682-8968-27ee207f3856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729109798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.729109798
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2606843335
Short name T494
Test name
Test status
Simulation time 17170491 ps
CPU time 0.57 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:27:44 PM PDT 24
Peak memory 195316 kb
Host smart-12b242de-beee-4020-8609-9b4f2fa5fd8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606843335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2606843335
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3017583003
Short name T656
Test name
Test status
Simulation time 139106163516 ps
CPU time 201.25 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:30:49 PM PDT 24
Peak memory 200336 kb
Host smart-aa970add-d85f-449c-8cb0-32702ea5f300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017583003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3017583003
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.427657713
Short name T581
Test name
Test status
Simulation time 23881793524 ps
CPU time 8.6 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:27:35 PM PDT 24
Peak memory 198348 kb
Host smart-73d87dd3-2d8b-41f2-8603-7c3f44968f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427657713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.427657713
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.301293127
Short name T73
Test name
Test status
Simulation time 28676292285 ps
CPU time 43.83 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:28:11 PM PDT 24
Peak memory 199948 kb
Host smart-357c1273-ca42-4dfd-bc68-2fbe8291956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301293127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.301293127
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2731091010
Short name T713
Test name
Test status
Simulation time 43451758327 ps
CPU time 26.36 seconds
Started Jul 19 04:27:22 PM PDT 24
Finished Jul 19 04:27:54 PM PDT 24
Peak memory 199972 kb
Host smart-9df86726-1e29-443f-b136-4437f03cf3fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731091010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2731091010
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2523464161
Short name T41
Test name
Test status
Simulation time 111326760855 ps
CPU time 385.68 seconds
Started Jul 19 04:27:24 PM PDT 24
Finished Jul 19 04:33:54 PM PDT 24
Peak memory 199948 kb
Host smart-5dcbb7d2-f44c-41c4-9176-ee0de3987287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523464161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2523464161
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2490490606
Short name T593
Test name
Test status
Simulation time 109053236 ps
CPU time 0.64 seconds
Started Jul 19 04:27:23 PM PDT 24
Finished Jul 19 04:27:29 PM PDT 24
Peak memory 195924 kb
Host smart-67ce49ba-555d-4e66-86e4-9c3f654d181a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490490606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2490490606
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2667975033
Short name T590
Test name
Test status
Simulation time 17692120716 ps
CPU time 8.46 seconds
Started Jul 19 04:27:20 PM PDT 24
Finished Jul 19 04:27:32 PM PDT 24
Peak memory 196156 kb
Host smart-f5b047e4-7f64-4432-b85d-e1fcb446fa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667975033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2667975033
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2020767112
Short name T740
Test name
Test status
Simulation time 20591735492 ps
CPU time 237.3 seconds
Started Jul 19 04:27:21 PM PDT 24
Finished Jul 19 04:31:24 PM PDT 24
Peak memory 200024 kb
Host smart-5935ad0f-5ccb-4d3c-a9db-c3be351f1b13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020767112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2020767112
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2254607197
Short name T613
Test name
Test status
Simulation time 3477597197 ps
CPU time 25.91 seconds
Started Jul 19 04:27:23 PM PDT 24
Finished Jul 19 04:27:54 PM PDT 24
Peak memory 198120 kb
Host smart-d51cb64a-b621-44eb-851c-0941be3de959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254607197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2254607197
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3966376412
Short name T911
Test name
Test status
Simulation time 104775076716 ps
CPU time 137.03 seconds
Started Jul 19 04:27:25 PM PDT 24
Finished Jul 19 04:29:46 PM PDT 24
Peak memory 199852 kb
Host smart-6fc009d1-9015-42a1-a3b7-d7412c17ecb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966376412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3966376412
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.86838568
Short name T123
Test name
Test status
Simulation time 5555844365 ps
CPU time 9.39 seconds
Started Jul 19 04:27:23 PM PDT 24
Finished Jul 19 04:27:38 PM PDT 24
Peak memory 196716 kb
Host smart-3f50400a-ce7b-41bb-9340-6212721ad1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86838568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.86838568
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2319754187
Short name T793
Test name
Test status
Simulation time 269171080 ps
CPU time 1.29 seconds
Started Jul 19 04:27:25 PM PDT 24
Finished Jul 19 04:27:30 PM PDT 24
Peak memory 199260 kb
Host smart-5557b1aa-341a-412d-a919-30f6dc86f956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319754187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2319754187
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2369645232
Short name T718
Test name
Test status
Simulation time 141480771623 ps
CPU time 935.44 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:43:21 PM PDT 24
Peak memory 199956 kb
Host smart-2be5ab14-3453-4813-ba1a-6942d65f55d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369645232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2369645232
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3499863008
Short name T647
Test name
Test status
Simulation time 55674934278 ps
CPU time 792.15 seconds
Started Jul 19 04:27:28 PM PDT 24
Finished Jul 19 04:40:42 PM PDT 24
Peak memory 224796 kb
Host smart-55ad1f33-8d8a-4848-a4b5-66eb634eb4b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499863008 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3499863008
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2259797534
Short name T980
Test name
Test status
Simulation time 1846401336 ps
CPU time 1.89 seconds
Started Jul 19 04:27:24 PM PDT 24
Finished Jul 19 04:27:31 PM PDT 24
Peak memory 198300 kb
Host smart-2d286b20-a50e-4bac-906a-54ca7e69bd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259797534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2259797534
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2739150914
Short name T12
Test name
Test status
Simulation time 6167484429 ps
CPU time 10.53 seconds
Started Jul 19 04:27:24 PM PDT 24
Finished Jul 19 04:27:40 PM PDT 24
Peak memory 199948 kb
Host smart-a4908608-4f19-4e0c-88e2-0c1071fd0985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739150914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2739150914
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.510368691
Short name T885
Test name
Test status
Simulation time 11472697 ps
CPU time 0.55 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:27:43 PM PDT 24
Peak memory 194352 kb
Host smart-909a4ad9-84f4-452d-bfba-59f41ed09c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510368691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.510368691
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3027574421
Short name T960
Test name
Test status
Simulation time 104001572249 ps
CPU time 208.76 seconds
Started Jul 19 04:27:35 PM PDT 24
Finished Jul 19 04:31:07 PM PDT 24
Peak memory 200068 kb
Host smart-68a10fc4-c8a8-4852-bb84-d1857990e1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027574421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3027574421
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.3396071854
Short name T1156
Test name
Test status
Simulation time 181153595656 ps
CPU time 23.55 seconds
Started Jul 19 04:27:35 PM PDT 24
Finished Jul 19 04:28:03 PM PDT 24
Peak memory 199940 kb
Host smart-343afc7e-6fae-4bcb-9930-a4ff8d1c4528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396071854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3396071854
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1368810119
Short name T894
Test name
Test status
Simulation time 36234768596 ps
CPU time 50.56 seconds
Started Jul 19 04:27:34 PM PDT 24
Finished Jul 19 04:28:27 PM PDT 24
Peak memory 200004 kb
Host smart-d9119c8c-2512-44ee-bc55-aa8e15fc8860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368810119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1368810119
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.920434686
Short name T105
Test name
Test status
Simulation time 107621297625 ps
CPU time 75 seconds
Started Jul 19 04:27:33 PM PDT 24
Finished Jul 19 04:28:50 PM PDT 24
Peak memory 196136 kb
Host smart-19ffe63f-8378-452a-87be-faab79853499
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920434686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.920434686
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2245391153
Short name T795
Test name
Test status
Simulation time 277111738390 ps
CPU time 289.57 seconds
Started Jul 19 04:27:35 PM PDT 24
Finished Jul 19 04:32:28 PM PDT 24
Peak memory 200324 kb
Host smart-d9477aa3-73cf-49fb-8bcc-b5317791c165
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2245391153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2245391153
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1459049022
Short name T350
Test name
Test status
Simulation time 5848163266 ps
CPU time 2.27 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:27:48 PM PDT 24
Peak memory 198056 kb
Host smart-d43952b0-420d-4e5c-9f12-54e9255e2281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459049022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1459049022
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1903668469
Short name T277
Test name
Test status
Simulation time 24655041410 ps
CPU time 39.2 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:28:22 PM PDT 24
Peak memory 200132 kb
Host smart-fe5c353f-49da-445c-a120-d998202357d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903668469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1903668469
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2468796453
Short name T554
Test name
Test status
Simulation time 16092771908 ps
CPU time 141.4 seconds
Started Jul 19 04:27:34 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 199928 kb
Host smart-abc9ab69-cbb7-42d2-8171-8b5394e0f366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2468796453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2468796453
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1136640070
Short name T426
Test name
Test status
Simulation time 4016973884 ps
CPU time 3.77 seconds
Started Jul 19 04:27:39 PM PDT 24
Finished Jul 19 04:27:50 PM PDT 24
Peak memory 198356 kb
Host smart-b64231d0-95b7-46b3-a978-27dc72ca3b72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136640070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1136640070
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3234683765
Short name T153
Test name
Test status
Simulation time 60306844793 ps
CPU time 23.47 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:28:06 PM PDT 24
Peak memory 199960 kb
Host smart-a57020d9-4344-47f5-8cb8-ec459f5abd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234683765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3234683765
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.409842024
Short name T461
Test name
Test status
Simulation time 3171372331 ps
CPU time 1.83 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:27:45 PM PDT 24
Peak memory 196640 kb
Host smart-1d417dbe-3447-48ae-b5b4-2e7ae87ef5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409842024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.409842024
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.791250033
Short name T684
Test name
Test status
Simulation time 537122879 ps
CPU time 1.14 seconds
Started Jul 19 04:27:37 PM PDT 24
Finished Jul 19 04:27:45 PM PDT 24
Peak memory 198868 kb
Host smart-d47c41dd-d196-483c-8335-49e4a1922467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791250033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.791250033
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.838933043
Short name T852
Test name
Test status
Simulation time 98073900517 ps
CPU time 210.22 seconds
Started Jul 19 04:27:34 PM PDT 24
Finished Jul 19 04:31:07 PM PDT 24
Peak memory 199944 kb
Host smart-ddcd9286-4206-4d9b-88f1-f5a2227dc792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838933043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.838933043
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.471711924
Short name T932
Test name
Test status
Simulation time 1591911462 ps
CPU time 1.76 seconds
Started Jul 19 04:27:37 PM PDT 24
Finished Jul 19 04:27:46 PM PDT 24
Peak memory 198616 kb
Host smart-6c985704-2bf3-4551-9b1f-39d0f4138de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471711924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.471711924
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1159493275
Short name T111
Test name
Test status
Simulation time 145304678342 ps
CPU time 52.34 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:28:35 PM PDT 24
Peak memory 199884 kb
Host smart-1d5b647d-7a50-4179-9fc2-39c3dc72be89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159493275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1159493275
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1221783329
Short name T2
Test name
Test status
Simulation time 35020695 ps
CPU time 0.62 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:27:46 PM PDT 24
Peak memory 195696 kb
Host smart-261fab25-2fb4-4a02-94b9-e3d86da14c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221783329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1221783329
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.448353479
Short name T803
Test name
Test status
Simulation time 158343306891 ps
CPU time 261.66 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:32:05 PM PDT 24
Peak memory 199952 kb
Host smart-40d2e36b-d2f0-4291-820d-1c315b78bc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448353479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.448353479
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1870693959
Short name T913
Test name
Test status
Simulation time 135096109219 ps
CPU time 44.71 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:28:28 PM PDT 24
Peak memory 199896 kb
Host smart-b39d6807-3d38-41d3-bc1a-53fcec9e9ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870693959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1870693959
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.169409161
Short name T204
Test name
Test status
Simulation time 20501858982 ps
CPU time 30.03 seconds
Started Jul 19 04:27:40 PM PDT 24
Finished Jul 19 04:28:16 PM PDT 24
Peak memory 199992 kb
Host smart-16a6543f-9014-4a78-ba6b-3bd93c020e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169409161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.169409161
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3728302014
Short name T689
Test name
Test status
Simulation time 47247072849 ps
CPU time 20.78 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:28:04 PM PDT 24
Peak memory 199000 kb
Host smart-469e0b4b-f49a-4fd8-8bfb-90733692b0fd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728302014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3728302014
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1769738642
Short name T1108
Test name
Test status
Simulation time 24773055939 ps
CPU time 90.79 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:29:14 PM PDT 24
Peak memory 199868 kb
Host smart-85676c5b-c868-4e11-b521-92dfe743a143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769738642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1769738642
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3233274172
Short name T1070
Test name
Test status
Simulation time 6343820125 ps
CPU time 7.3 seconds
Started Jul 19 04:27:35 PM PDT 24
Finished Jul 19 04:27:47 PM PDT 24
Peak memory 197736 kb
Host smart-48627c4a-1109-412a-b2c7-317f41ed47dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233274172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3233274172
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1232569582
Short name T723
Test name
Test status
Simulation time 48626604772 ps
CPU time 40.6 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:28:25 PM PDT 24
Peak memory 199500 kb
Host smart-17c79388-768e-4585-9f02-a3fa3ac8c027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232569582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1232569582
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2799772717
Short name T669
Test name
Test status
Simulation time 1259179293 ps
CPU time 0.74 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:27:42 PM PDT 24
Peak memory 195732 kb
Host smart-1504f11c-f8f2-41af-9498-9218eaf2ef9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2799772717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2799772717
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3972485084
Short name T1090
Test name
Test status
Simulation time 12622823319 ps
CPU time 19.02 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:28:04 PM PDT 24
Peak memory 199900 kb
Host smart-f18a4f60-086a-4f24-b86a-6df9a38530b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972485084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3972485084
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3837817342
Short name T312
Test name
Test status
Simulation time 51019899979 ps
CPU time 18.89 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:28:04 PM PDT 24
Peak memory 196516 kb
Host smart-9244cca9-2fc1-43aa-9e6a-dc033df25eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837817342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3837817342
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1242199968
Short name T502
Test name
Test status
Simulation time 473903430 ps
CPU time 1.41 seconds
Started Jul 19 04:27:34 PM PDT 24
Finished Jul 19 04:27:39 PM PDT 24
Peak memory 198928 kb
Host smart-057d09a9-21d0-4b6c-8143-906089529ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242199968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1242199968
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1780013946
Short name T670
Test name
Test status
Simulation time 325082159651 ps
CPU time 1356.54 seconds
Started Jul 19 04:27:37 PM PDT 24
Finished Jul 19 04:50:20 PM PDT 24
Peak memory 199960 kb
Host smart-0e7fa975-2e56-4e24-b5b1-3e39ceac33eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780013946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1780013946
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2316688529
Short name T58
Test name
Test status
Simulation time 145954800703 ps
CPU time 961.56 seconds
Started Jul 19 04:27:33 PM PDT 24
Finished Jul 19 04:43:35 PM PDT 24
Peak memory 226652 kb
Host smart-8dab3c44-d16c-4caa-9dfb-27bb16caff8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316688529 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2316688529
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2413674844
Short name T809
Test name
Test status
Simulation time 972563345 ps
CPU time 3.51 seconds
Started Jul 19 04:27:35 PM PDT 24
Finished Jul 19 04:27:42 PM PDT 24
Peak memory 198404 kb
Host smart-d45e5e9f-bedd-4e5c-8878-4cd5c1a0a916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413674844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2413674844
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.852905084
Short name T35
Test name
Test status
Simulation time 90520591215 ps
CPU time 136.57 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:30:00 PM PDT 24
Peak memory 200012 kb
Host smart-a7b2b10c-df28-4fc4-9b54-7ae5c9ddf6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852905084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.852905084
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3834279920
Short name T648
Test name
Test status
Simulation time 12319910 ps
CPU time 0.57 seconds
Started Jul 19 04:25:16 PM PDT 24
Finished Jul 19 04:25:36 PM PDT 24
Peak memory 195636 kb
Host smart-113128a7-4757-402b-af71-732b283a8853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834279920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3834279920
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2932259400
Short name T317
Test name
Test status
Simulation time 68560826989 ps
CPU time 102.64 seconds
Started Jul 19 04:25:19 PM PDT 24
Finished Jul 19 04:27:22 PM PDT 24
Peak memory 199952 kb
Host smart-1c0ab0f3-6eef-4652-80a0-7ff77ecf255e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932259400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2932259400
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.34518265
Short name T812
Test name
Test status
Simulation time 122515101558 ps
CPU time 185.23 seconds
Started Jul 19 04:25:31 PM PDT 24
Finished Jul 19 04:28:54 PM PDT 24
Peak memory 199956 kb
Host smart-c9042886-f3c8-4b36-9ec5-7225bac027f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34518265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.34518265
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1258332913
Short name T394
Test name
Test status
Simulation time 61385180725 ps
CPU time 14.07 seconds
Started Jul 19 04:25:23 PM PDT 24
Finished Jul 19 04:25:56 PM PDT 24
Peak memory 199944 kb
Host smart-c32d7a03-5f78-41b6-917e-9bef9a0f8e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258332913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1258332913
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3674741411
Short name T1035
Test name
Test status
Simulation time 20317901996 ps
CPU time 10.47 seconds
Started Jul 19 04:25:22 PM PDT 24
Finished Jul 19 04:25:52 PM PDT 24
Peak memory 199972 kb
Host smart-0a5bd531-44ab-492b-a538-faf972dbbd92
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674741411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3674741411
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1059435332
Short name T1009
Test name
Test status
Simulation time 112909010900 ps
CPU time 705.25 seconds
Started Jul 19 04:25:17 PM PDT 24
Finished Jul 19 04:37:21 PM PDT 24
Peak memory 199984 kb
Host smart-427766ad-dd34-4712-8a9e-09c3d80b66d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059435332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1059435332
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2233968942
Short name T409
Test name
Test status
Simulation time 1063066029 ps
CPU time 2.4 seconds
Started Jul 19 04:25:19 PM PDT 24
Finished Jul 19 04:25:41 PM PDT 24
Peak memory 196076 kb
Host smart-608fc535-18d8-412f-9ac4-48bec8afbee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233968942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2233968942
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.664260876
Short name T292
Test name
Test status
Simulation time 88094641986 ps
CPU time 143.6 seconds
Started Jul 19 04:25:35 PM PDT 24
Finished Jul 19 04:28:16 PM PDT 24
Peak memory 199508 kb
Host smart-e7c44394-6981-4fc0-abd8-665ffa36b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664260876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.664260876
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1248503666
Short name T318
Test name
Test status
Simulation time 26783547398 ps
CPU time 352.78 seconds
Started Jul 19 04:25:16 PM PDT 24
Finished Jul 19 04:31:29 PM PDT 24
Peak memory 200236 kb
Host smart-debc4d26-87b5-4f51-9793-d40c0ad4b6e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248503666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1248503666
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2815720993
Short name T618
Test name
Test status
Simulation time 5539478700 ps
CPU time 48.6 seconds
Started Jul 19 04:25:21 PM PDT 24
Finished Jul 19 04:26:29 PM PDT 24
Peak memory 198152 kb
Host smart-5189cb81-6943-4b00-b194-3e4197bb095f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815720993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2815720993
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.4291830168
Short name T922
Test name
Test status
Simulation time 20072315308 ps
CPU time 27.95 seconds
Started Jul 19 04:25:19 PM PDT 24
Finished Jul 19 04:26:06 PM PDT 24
Peak memory 199868 kb
Host smart-421b1ad1-4c03-4d15-9dcb-8ea5e767ad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291830168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.4291830168
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1912417320
Short name T395
Test name
Test status
Simulation time 4722382579 ps
CPU time 2.58 seconds
Started Jul 19 04:25:20 PM PDT 24
Finished Jul 19 04:25:42 PM PDT 24
Peak memory 196292 kb
Host smart-3934e5cc-c1df-41c9-8153-3edb4a02225f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912417320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1912417320
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.982852544
Short name T358
Test name
Test status
Simulation time 6200614134 ps
CPU time 15.01 seconds
Started Jul 19 04:25:22 PM PDT 24
Finished Jul 19 04:25:57 PM PDT 24
Peak memory 199772 kb
Host smart-7575563d-be98-48b3-b123-5968e1325055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982852544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.982852544
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2249564787
Short name T1118
Test name
Test status
Simulation time 54515019752 ps
CPU time 219.22 seconds
Started Jul 19 04:25:19 PM PDT 24
Finished Jul 19 04:29:18 PM PDT 24
Peak memory 199944 kb
Host smart-6330bfab-63d8-4173-a981-0348b053ca3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249564787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2249564787
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1570342216
Short name T1096
Test name
Test status
Simulation time 4092774553 ps
CPU time 1.85 seconds
Started Jul 19 04:25:19 PM PDT 24
Finished Jul 19 04:25:40 PM PDT 24
Peak memory 199112 kb
Host smart-676b9dcd-f310-473e-8704-66b70c3b7054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570342216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1570342216
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2016539110
Short name T268
Test name
Test status
Simulation time 28042016650 ps
CPU time 40.09 seconds
Started Jul 19 04:25:20 PM PDT 24
Finished Jul 19 04:26:20 PM PDT 24
Peak memory 199696 kb
Host smart-ec26fce6-80da-4dfb-b3aa-c1c139c8810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016539110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2016539110
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2976314614
Short name T221
Test name
Test status
Simulation time 166816436010 ps
CPU time 67.64 seconds
Started Jul 19 04:27:33 PM PDT 24
Finished Jul 19 04:28:42 PM PDT 24
Peak memory 199956 kb
Host smart-eb929300-6ce1-46c3-8a70-5b5506b29c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976314614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2976314614
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3922968800
Short name T585
Test name
Test status
Simulation time 43792491540 ps
CPU time 249.31 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:31:52 PM PDT 24
Peak memory 208256 kb
Host smart-fd3452d1-3bf9-4808-8aaf-ec79e14019a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922968800 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3922968800
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.752461902
Short name T745
Test name
Test status
Simulation time 28893309537 ps
CPU time 11.84 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:27:54 PM PDT 24
Peak memory 199892 kb
Host smart-d91228b5-eacb-4646-b11f-1de3d95cffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752461902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.752461902
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2244669459
Short name T116
Test name
Test status
Simulation time 154149969701 ps
CPU time 335.03 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:33:16 PM PDT 24
Peak memory 225868 kb
Host smart-726e79c3-5ef4-43c3-9559-fd64a32810f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244669459 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2244669459
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3685307015
Short name T208
Test name
Test status
Simulation time 174713570719 ps
CPU time 46.66 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:28:29 PM PDT 24
Peak memory 200080 kb
Host smart-999ae2da-50fa-4cc2-8e22-62a2b09a4bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685307015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3685307015
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.829100892
Short name T937
Test name
Test status
Simulation time 28305604144 ps
CPU time 615.46 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:37:59 PM PDT 24
Peak memory 216348 kb
Host smart-84b92e56-ebc3-478b-a84e-9883f974c75a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829100892 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.829100892
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3017845391
Short name T1158
Test name
Test status
Simulation time 79337672265 ps
CPU time 123.44 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:29:46 PM PDT 24
Peak memory 199920 kb
Host smart-2152dd7f-7c90-42e1-bc70-2cd65be495e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017845391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3017845391
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3831224790
Short name T1026
Test name
Test status
Simulation time 34195786927 ps
CPU time 327.87 seconds
Started Jul 19 04:27:39 PM PDT 24
Finished Jul 19 04:33:14 PM PDT 24
Peak memory 216508 kb
Host smart-a8393ab9-8a6f-45fd-b77d-7309d6335168
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831224790 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3831224790
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2106405359
Short name T54
Test name
Test status
Simulation time 222985055200 ps
CPU time 1417.88 seconds
Started Jul 19 04:27:39 PM PDT 24
Finished Jul 19 04:51:24 PM PDT 24
Peak memory 232628 kb
Host smart-6d3270c8-c0e3-44aa-8944-f44e3b2db4b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106405359 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2106405359
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.4059559250
Short name T1079
Test name
Test status
Simulation time 69717545834 ps
CPU time 114.01 seconds
Started Jul 19 04:27:37 PM PDT 24
Finished Jul 19 04:29:38 PM PDT 24
Peak memory 199932 kb
Host smart-429c361c-ded4-4b84-8671-18f2b4071156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059559250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.4059559250
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.156631809
Short name T842
Test name
Test status
Simulation time 14281523955 ps
CPU time 126.67 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:29:50 PM PDT 24
Peak memory 216204 kb
Host smart-3d5a377e-2f58-482d-beb3-bf56ec46f70d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156631809 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.156631809
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2472947464
Short name T497
Test name
Test status
Simulation time 74266453815 ps
CPU time 40.78 seconds
Started Jul 19 04:27:35 PM PDT 24
Finished Jul 19 04:28:21 PM PDT 24
Peak memory 199988 kb
Host smart-7c99f97c-0c2e-409d-9d94-ca45a075fe4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472947464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2472947464
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.4079562710
Short name T18
Test name
Test status
Simulation time 84596467588 ps
CPU time 493.08 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:35:58 PM PDT 24
Peak memory 216504 kb
Host smart-5cc24958-0d1c-4234-851c-3f97ada4778d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079562710 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.4079562710
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3366932579
Short name T76
Test name
Test status
Simulation time 129981392624 ps
CPU time 55.58 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:28:41 PM PDT 24
Peak memory 199852 kb
Host smart-70f5a030-37f9-461f-8efe-836c7318cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366932579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3366932579
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1889386545
Short name T1171
Test name
Test status
Simulation time 29627344756 ps
CPU time 123.15 seconds
Started Jul 19 04:27:37 PM PDT 24
Finished Jul 19 04:29:48 PM PDT 24
Peak memory 215588 kb
Host smart-0b6530e6-f0a4-42d3-a1dd-9ff1b6865984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889386545 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1889386545
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2156455962
Short name T650
Test name
Test status
Simulation time 49808053257 ps
CPU time 74.93 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:29:00 PM PDT 24
Peak memory 199804 kb
Host smart-bde42f35-81b0-4a0b-a07b-3f7845d6a1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156455962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2156455962
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1629843837
Short name T752
Test name
Test status
Simulation time 170835887028 ps
CPU time 1151.67 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:46:57 PM PDT 24
Peak memory 224612 kb
Host smart-8a8ac248-b05b-4c4b-a001-f6d46c754d71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629843837 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1629843837
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3602315283
Short name T737
Test name
Test status
Simulation time 108821760 ps
CPU time 0.53 seconds
Started Jul 19 04:25:31 PM PDT 24
Finished Jul 19 04:25:49 PM PDT 24
Peak memory 195320 kb
Host smart-31321b01-03c1-41a0-a727-04adc63835f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602315283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3602315283
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2624417908
Short name T559
Test name
Test status
Simulation time 53355458716 ps
CPU time 16.85 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:25:54 PM PDT 24
Peak memory 199936 kb
Host smart-f2b84a62-9fd7-4339-8379-abc1617b04d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624417908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2624417908
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1725963022
Short name T683
Test name
Test status
Simulation time 109544284912 ps
CPU time 81.29 seconds
Started Jul 19 04:25:21 PM PDT 24
Finished Jul 19 04:27:02 PM PDT 24
Peak memory 199636 kb
Host smart-d650b343-d4af-42fa-bd62-39fc189c79fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725963022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1725963022
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1921353998
Short name T610
Test name
Test status
Simulation time 77568768414 ps
CPU time 74 seconds
Started Jul 19 04:25:19 PM PDT 24
Finished Jul 19 04:26:53 PM PDT 24
Peak memory 200000 kb
Host smart-a8546749-6e80-484f-a0b4-1eb161737afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921353998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1921353998
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3989890263
Short name T712
Test name
Test status
Simulation time 63795378824 ps
CPU time 28.74 seconds
Started Jul 19 04:25:21 PM PDT 24
Finished Jul 19 04:26:09 PM PDT 24
Peak memory 199932 kb
Host smart-9867a9e9-9a70-4be8-a950-c47ebd6fafc7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989890263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3989890263
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2009051246
Short name T440
Test name
Test status
Simulation time 219852139867 ps
CPU time 219.88 seconds
Started Jul 19 04:25:25 PM PDT 24
Finished Jul 19 04:29:24 PM PDT 24
Peak memory 199908 kb
Host smart-0a642a6e-aca7-4cdf-97b7-0d02d44c80cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2009051246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2009051246
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3418303274
Short name T451
Test name
Test status
Simulation time 10573861580 ps
CPU time 14.27 seconds
Started Jul 19 04:25:29 PM PDT 24
Finished Jul 19 04:26:01 PM PDT 24
Peak memory 199888 kb
Host smart-8a79bd16-435d-4510-9180-65122f7ec56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418303274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3418303274
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3913655093
Short name T265
Test name
Test status
Simulation time 62767422356 ps
CPU time 126.98 seconds
Started Jul 19 04:25:30 PM PDT 24
Finished Jul 19 04:27:55 PM PDT 24
Peak memory 200168 kb
Host smart-a015cf86-f6c7-40be-a8de-646db27ad5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913655093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3913655093
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1988385243
Short name T849
Test name
Test status
Simulation time 19113863868 ps
CPU time 557.87 seconds
Started Jul 19 04:25:24 PM PDT 24
Finished Jul 19 04:35:01 PM PDT 24
Peak memory 199908 kb
Host smart-a3bdf6cf-3746-4c6c-a711-c081617ff4d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988385243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1988385243
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2528989877
Short name T353
Test name
Test status
Simulation time 6793407002 ps
CPU time 15.27 seconds
Started Jul 19 04:25:25 PM PDT 24
Finished Jul 19 04:25:59 PM PDT 24
Peak memory 198080 kb
Host smart-8f5f58f2-997f-4843-9dc0-acbc2810c1f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528989877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2528989877
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3612905713
Short name T918
Test name
Test status
Simulation time 151518384204 ps
CPU time 189.17 seconds
Started Jul 19 04:25:31 PM PDT 24
Finished Jul 19 04:28:58 PM PDT 24
Peak memory 199812 kb
Host smart-8ddf5115-ae19-46e1-a151-47cc9fa8360b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612905713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3612905713
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2467554004
Short name T641
Test name
Test status
Simulation time 3255701022 ps
CPU time 2.03 seconds
Started Jul 19 04:25:28 PM PDT 24
Finished Jul 19 04:25:48 PM PDT 24
Peak memory 196248 kb
Host smart-374cc9fe-9b7a-44df-889e-4d71b7ccebcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467554004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2467554004
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.514295717
Short name T753
Test name
Test status
Simulation time 478823200 ps
CPU time 1.99 seconds
Started Jul 19 04:25:21 PM PDT 24
Finished Jul 19 04:25:42 PM PDT 24
Peak memory 198848 kb
Host smart-d2b5310b-9037-4a53-a2d7-6268f480ec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514295717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.514295717
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1592369592
Short name T778
Test name
Test status
Simulation time 880573280363 ps
CPU time 507.02 seconds
Started Jul 19 04:25:31 PM PDT 24
Finished Jul 19 04:34:16 PM PDT 24
Peak memory 228032 kb
Host smart-6d374dcf-56a7-48a5-89eb-4b7848610de2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592369592 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1592369592
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.347223670
Short name T822
Test name
Test status
Simulation time 858329554 ps
CPU time 3.08 seconds
Started Jul 19 04:25:31 PM PDT 24
Finished Jul 19 04:25:52 PM PDT 24
Peak memory 198816 kb
Host smart-ce39122e-21df-4e8f-a3d9-421768bdb368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347223670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.347223670
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1234583004
Short name T916
Test name
Test status
Simulation time 117894525172 ps
CPU time 113.8 seconds
Started Jul 19 04:25:18 PM PDT 24
Finished Jul 19 04:27:31 PM PDT 24
Peak memory 199944 kb
Host smart-279b93e3-08db-4d38-8bc8-755798175678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234583004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1234583004
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.696600564
Short name T1132
Test name
Test status
Simulation time 41874129328 ps
CPU time 58.02 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:28:44 PM PDT 24
Peak memory 199932 kb
Host smart-9c2c7335-e622-428a-9fe1-8881ed33a81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696600564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.696600564
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.526104736
Short name T741
Test name
Test status
Simulation time 276868370372 ps
CPU time 825.48 seconds
Started Jul 19 04:27:39 PM PDT 24
Finished Jul 19 04:41:31 PM PDT 24
Peak memory 224684 kb
Host smart-66c6c7e7-554d-48d8-a24e-4252a8b0c5e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526104736 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.526104736
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1770055151
Short name T550
Test name
Test status
Simulation time 68821750777 ps
CPU time 22.28 seconds
Started Jul 19 04:27:40 PM PDT 24
Finished Jul 19 04:28:09 PM PDT 24
Peak memory 199988 kb
Host smart-51c0111e-27c1-4b25-91c5-db7c607afcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770055151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1770055151
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1800300580
Short name T14
Test name
Test status
Simulation time 66890512806 ps
CPU time 1194.63 seconds
Started Jul 19 04:27:34 PM PDT 24
Finished Jul 19 04:47:31 PM PDT 24
Peak memory 216520 kb
Host smart-d8abc29a-8a3e-4e24-bbe1-13b5505fd4fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800300580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1800300580
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2263351029
Short name T117
Test name
Test status
Simulation time 72457669842 ps
CPU time 556.01 seconds
Started Jul 19 04:27:40 PM PDT 24
Finished Jul 19 04:37:02 PM PDT 24
Peak memory 226036 kb
Host smart-a49b6114-e64f-40a7-890b-efe3093f1e1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263351029 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2263351029
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1942496095
Short name T418
Test name
Test status
Simulation time 62857085315 ps
CPU time 51.3 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:28:37 PM PDT 24
Peak memory 199876 kb
Host smart-28f91518-dca0-4198-b5d9-106fc733bea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942496095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1942496095
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.239706015
Short name T188
Test name
Test status
Simulation time 137853503273 ps
CPU time 1301.79 seconds
Started Jul 19 04:27:39 PM PDT 24
Finished Jul 19 04:49:28 PM PDT 24
Peak memory 224740 kb
Host smart-cc894566-1f18-4037-a599-16522ce6c38b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239706015 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.239706015
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3024024215
Short name T242
Test name
Test status
Simulation time 130310581723 ps
CPU time 102.64 seconds
Started Jul 19 04:27:35 PM PDT 24
Finished Jul 19 04:29:22 PM PDT 24
Peak memory 199884 kb
Host smart-3bb69dc1-04a3-4a23-b08d-1a6dccbc87ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024024215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3024024215
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.767088329
Short name T325
Test name
Test status
Simulation time 47177395823 ps
CPU time 253.86 seconds
Started Jul 19 04:27:36 PM PDT 24
Finished Jul 19 04:31:57 PM PDT 24
Peak memory 214060 kb
Host smart-fdfb00bd-9a95-4375-8320-92dd3bf1716e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767088329 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.767088329
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2639146390
Short name T423
Test name
Test status
Simulation time 166895465962 ps
CPU time 242.82 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:31:48 PM PDT 24
Peak memory 199812 kb
Host smart-f791b52a-defa-45fa-b8c6-efd6ff9d80e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639146390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2639146390
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3192510011
Short name T51
Test name
Test status
Simulation time 69840736850 ps
CPU time 578.08 seconds
Started Jul 19 04:27:39 PM PDT 24
Finished Jul 19 04:37:24 PM PDT 24
Peak memory 226240 kb
Host smart-86ae69cd-7374-4b1f-b9dc-f14e4ffe996d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192510011 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3192510011
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.408398457
Short name T223
Test name
Test status
Simulation time 19057959724 ps
CPU time 10.53 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:27:56 PM PDT 24
Peak memory 199704 kb
Host smart-817c4680-93a4-4de3-a7f7-da962b44a2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408398457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.408398457
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.444803789
Short name T929
Test name
Test status
Simulation time 25559740350 ps
CPU time 151.53 seconds
Started Jul 19 04:27:38 PM PDT 24
Finished Jul 19 04:30:16 PM PDT 24
Peak memory 215556 kb
Host smart-0d8680b7-5439-45b9-a5f2-89c3b9beb376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444803789 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.444803789
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3262346396
Short name T743
Test name
Test status
Simulation time 36614943156 ps
CPU time 28.54 seconds
Started Jul 19 04:27:43 PM PDT 24
Finished Jul 19 04:28:17 PM PDT 24
Peak memory 199932 kb
Host smart-505a7b93-9469-4da4-a174-6b1032bba317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262346396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3262346396
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.4094875793
Short name T691
Test name
Test status
Simulation time 396763593087 ps
CPU time 1181.88 seconds
Started Jul 19 04:27:43 PM PDT 24
Finished Jul 19 04:47:31 PM PDT 24
Peak memory 227188 kb
Host smart-74bda1cb-84ae-426e-a375-51f39163700b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094875793 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.4094875793
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1042706213
Short name T1125
Test name
Test status
Simulation time 87584981440 ps
CPU time 149.96 seconds
Started Jul 19 04:27:37 PM PDT 24
Finished Jul 19 04:30:14 PM PDT 24
Peak memory 199896 kb
Host smart-441adc62-213c-4e48-a4a7-b45d9f90d6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042706213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1042706213
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2455076506
Short name T115
Test name
Test status
Simulation time 30741328602 ps
CPU time 197.89 seconds
Started Jul 19 04:27:43 PM PDT 24
Finished Jul 19 04:31:06 PM PDT 24
Peak memory 211000 kb
Host smart-40e5d129-3be2-4819-b56b-68ff98449453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455076506 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2455076506
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2330414840
Short name T903
Test name
Test status
Simulation time 87259704206 ps
CPU time 57.51 seconds
Started Jul 19 04:27:43 PM PDT 24
Finished Jul 19 04:28:46 PM PDT 24
Peak memory 199868 kb
Host smart-07dc69e8-8b36-48cc-9d32-1fbcadcdfa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330414840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2330414840
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1001563050
Short name T1151
Test name
Test status
Simulation time 34432039724 ps
CPU time 410.34 seconds
Started Jul 19 04:27:42 PM PDT 24
Finished Jul 19 04:34:38 PM PDT 24
Peak memory 215492 kb
Host smart-5ebcc2e5-0727-4e67-8b29-cb9634e4ad78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001563050 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1001563050
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2136759035
Short name T389
Test name
Test status
Simulation time 12296499 ps
CPU time 0.57 seconds
Started Jul 19 04:25:23 PM PDT 24
Finished Jul 19 04:25:43 PM PDT 24
Peak memory 194992 kb
Host smart-8adf4e05-4390-4cdd-8b27-60d61efb6268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136759035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2136759035
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.4172064945
Short name T678
Test name
Test status
Simulation time 96403200265 ps
CPU time 38.63 seconds
Started Jul 19 04:25:55 PM PDT 24
Finished Jul 19 04:26:49 PM PDT 24
Peak memory 200016 kb
Host smart-4c40ae28-0168-486d-8ff9-5ea08529024c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172064945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.4172064945
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2741245565
Short name T847
Test name
Test status
Simulation time 129769328759 ps
CPU time 170.16 seconds
Started Jul 19 04:25:26 PM PDT 24
Finished Jul 19 04:28:35 PM PDT 24
Peak memory 199924 kb
Host smart-58687902-edbd-4cff-bc6f-317e6c640cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741245565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2741245565
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.252832082
Short name T1048
Test name
Test status
Simulation time 35198819712 ps
CPU time 11.59 seconds
Started Jul 19 04:25:25 PM PDT 24
Finished Jul 19 04:25:56 PM PDT 24
Peak memory 199872 kb
Host smart-66af7111-678a-4159-85ad-64bb374f87e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252832082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.252832082
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.290233251
Short name T520
Test name
Test status
Simulation time 39346442060 ps
CPU time 39.08 seconds
Started Jul 19 04:25:26 PM PDT 24
Finished Jul 19 04:26:24 PM PDT 24
Peak memory 199912 kb
Host smart-cb7b3fcc-e2f8-4b80-a506-07e148a31177
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290233251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.290233251
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.135067152
Short name T728
Test name
Test status
Simulation time 126527386941 ps
CPU time 753.58 seconds
Started Jul 19 04:25:30 PM PDT 24
Finished Jul 19 04:38:21 PM PDT 24
Peak memory 199936 kb
Host smart-15fd5bcb-6d1a-41fb-a5b8-eef7104386ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135067152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.135067152
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.219639554
Short name T933
Test name
Test status
Simulation time 3228588478 ps
CPU time 2.49 seconds
Started Jul 19 04:25:31 PM PDT 24
Finished Jul 19 04:25:51 PM PDT 24
Peak memory 197476 kb
Host smart-7ba411d9-930c-4f70-a55f-eead17ad9855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219639554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.219639554
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.4040999639
Short name T843
Test name
Test status
Simulation time 56193712320 ps
CPU time 149.98 seconds
Started Jul 19 04:25:25 PM PDT 24
Finished Jul 19 04:28:14 PM PDT 24
Peak memory 208576 kb
Host smart-567f96b0-86b0-4d98-9efc-5121219c6cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040999639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4040999639
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.541959376
Short name T578
Test name
Test status
Simulation time 19440131250 ps
CPU time 71.53 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:27:06 PM PDT 24
Peak memory 199856 kb
Host smart-dee17ee6-fa4c-49b0-a802-0e862130053b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541959376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.541959376
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1097909894
Short name T926
Test name
Test status
Simulation time 3517769508 ps
CPU time 24.24 seconds
Started Jul 19 04:25:25 PM PDT 24
Finished Jul 19 04:26:08 PM PDT 24
Peak memory 198288 kb
Host smart-5d9886d7-ed83-4fef-bbf1-139fc00399b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1097909894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1097909894
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.60911965
Short name T859
Test name
Test status
Simulation time 24443955249 ps
CPU time 38.63 seconds
Started Jul 19 04:25:27 PM PDT 24
Finished Jul 19 04:26:24 PM PDT 24
Peak memory 199824 kb
Host smart-f6a51e3e-90a4-42d5-9305-bb322472504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60911965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.60911965
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.600122312
Short name T587
Test name
Test status
Simulation time 3905011691 ps
CPU time 6.24 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:26:01 PM PDT 24
Peak memory 196272 kb
Host smart-1c2cd37c-4fa9-452b-bca8-1ddd8ee522a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600122312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.600122312
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1991336582
Short name T831
Test name
Test status
Simulation time 532207416 ps
CPU time 1.43 seconds
Started Jul 19 04:25:25 PM PDT 24
Finished Jul 19 04:25:45 PM PDT 24
Peak memory 198352 kb
Host smart-f3839c06-f350-4742-abde-0af65705f5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991336582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1991336582
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3025741467
Short name T570
Test name
Test status
Simulation time 1149870219592 ps
CPU time 132.56 seconds
Started Jul 19 04:25:27 PM PDT 24
Finished Jul 19 04:27:58 PM PDT 24
Peak memory 216300 kb
Host smart-0c047d97-b378-47a0-bc2b-5bca407fa773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025741467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3025741467
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3924731293
Short name T53
Test name
Test status
Simulation time 124430566382 ps
CPU time 915.4 seconds
Started Jul 19 04:25:26 PM PDT 24
Finished Jul 19 04:41:00 PM PDT 24
Peak memory 230672 kb
Host smart-49697ae2-7321-4a0f-b636-e3bb54bdea18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924731293 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3924731293
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1662399906
Short name T571
Test name
Test status
Simulation time 1638916265 ps
CPU time 2.05 seconds
Started Jul 19 04:25:31 PM PDT 24
Finished Jul 19 04:25:51 PM PDT 24
Peak memory 198868 kb
Host smart-bb5d725e-5e90-4302-9d31-20d31e7f849a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662399906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1662399906
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1919087172
Short name T954
Test name
Test status
Simulation time 70561025905 ps
CPU time 104.39 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:27:39 PM PDT 24
Peak memory 199644 kb
Host smart-c6fac92f-5b50-437c-b4f2-45252ccedc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919087172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1919087172
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1693230116
Short name T244
Test name
Test status
Simulation time 136039427014 ps
CPU time 176.13 seconds
Started Jul 19 04:27:43 PM PDT 24
Finished Jul 19 04:30:45 PM PDT 24
Peak memory 199808 kb
Host smart-d93853e6-afb1-45ba-ae9f-42fcb32aafda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693230116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1693230116
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.642688339
Short name T445
Test name
Test status
Simulation time 220581050643 ps
CPU time 433.22 seconds
Started Jul 19 04:27:53 PM PDT 24
Finished Jul 19 04:35:13 PM PDT 24
Peak memory 224876 kb
Host smart-3b4f9736-bd64-4b31-be1a-5dc5c90180a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642688339 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.642688339
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2237134499
Short name T897
Test name
Test status
Simulation time 59161900686 ps
CPU time 635.27 seconds
Started Jul 19 04:27:47 PM PDT 24
Finished Jul 19 04:38:27 PM PDT 24
Peak memory 216584 kb
Host smart-1e2268a4-4f91-4c91-9592-e4f761026d7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237134499 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2237134499
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2217887631
Short name T193
Test name
Test status
Simulation time 18998193580 ps
CPU time 37.36 seconds
Started Jul 19 04:27:49 PM PDT 24
Finished Jul 19 04:28:33 PM PDT 24
Peak memory 199980 kb
Host smart-acb001ca-da9f-4844-8f8e-d9499ffa0f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217887631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2217887631
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.287409033
Short name T189
Test name
Test status
Simulation time 27590852625 ps
CPU time 29.75 seconds
Started Jul 19 04:27:48 PM PDT 24
Finished Jul 19 04:28:22 PM PDT 24
Peak memory 199944 kb
Host smart-6dd166fc-b6ca-4b26-84b2-3a70c510d586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287409033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.287409033
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3010522169
Short name T154
Test name
Test status
Simulation time 86802319779 ps
CPU time 114.49 seconds
Started Jul 19 04:27:47 PM PDT 24
Finished Jul 19 04:29:47 PM PDT 24
Peak memory 199984 kb
Host smart-fdb4467e-b97d-40da-832e-432cad7a69aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010522169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3010522169
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1273692916
Short name T673
Test name
Test status
Simulation time 169078508994 ps
CPU time 799.84 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:41:16 PM PDT 24
Peak memory 213124 kb
Host smart-04e38c81-5a17-4ed9-a12b-360516af426d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273692916 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1273692916
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.849969881
Short name T837
Test name
Test status
Simulation time 79729743287 ps
CPU time 121.02 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:29:58 PM PDT 24
Peak memory 199976 kb
Host smart-7bc7b1b0-a4a0-4484-9c03-841392dc03d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849969881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.849969881
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3059821814
Short name T1001
Test name
Test status
Simulation time 128434401223 ps
CPU time 597.03 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:37:54 PM PDT 24
Peak memory 212072 kb
Host smart-78377402-ff71-454f-9a77-7f05e7f07e6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059821814 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3059821814
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2374147617
Short name T549
Test name
Test status
Simulation time 69019200436 ps
CPU time 21.48 seconds
Started Jul 19 04:27:48 PM PDT 24
Finished Jul 19 04:28:14 PM PDT 24
Peak memory 200024 kb
Host smart-562f8397-79d8-4862-b1a0-ef5bff76f626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374147617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2374147617
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1638207321
Short name T682
Test name
Test status
Simulation time 26329769145 ps
CPU time 250.91 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:32:08 PM PDT 24
Peak memory 215996 kb
Host smart-812d6c70-c9ab-44c9-a776-d63ec401f147
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638207321 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1638207321
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.4275961098
Short name T215
Test name
Test status
Simulation time 43833540981 ps
CPU time 31.52 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:28:29 PM PDT 24
Peak memory 199956 kb
Host smart-f18aa88b-f295-4182-ad8a-856d9e4e8fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275961098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.4275961098
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1256274596
Short name T270
Test name
Test status
Simulation time 36786275380 ps
CPU time 519.6 seconds
Started Jul 19 04:27:49 PM PDT 24
Finished Jul 19 04:36:35 PM PDT 24
Peak memory 208292 kb
Host smart-35ddd67b-164b-4738-a819-097ac62fa654
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256274596 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1256274596
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2270174696
Short name T248
Test name
Test status
Simulation time 107380478371 ps
CPU time 16.78 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:28:13 PM PDT 24
Peak memory 200072 kb
Host smart-90672085-69dc-4751-8331-b4282a6b36ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270174696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2270174696
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1349311362
Short name T31
Test name
Test status
Simulation time 21547656937 ps
CPU time 227.26 seconds
Started Jul 19 04:27:49 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 208236 kb
Host smart-8d58a588-f636-47a0-a1c9-f7433e10ef68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349311362 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1349311362
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2247765084
Short name T755
Test name
Test status
Simulation time 27480118966 ps
CPU time 32.44 seconds
Started Jul 19 04:27:51 PM PDT 24
Finished Jul 19 04:28:31 PM PDT 24
Peak memory 199928 kb
Host smart-024107de-5947-40c5-bc49-f66e728b36f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247765084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2247765084
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.78561593
Short name T982
Test name
Test status
Simulation time 408755695869 ps
CPU time 758.67 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:40:35 PM PDT 24
Peak memory 216508 kb
Host smart-939e8c34-9283-4f4f-8ca2-c5a70e3ec19a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78561593 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.78561593
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.736862205
Short name T876
Test name
Test status
Simulation time 28583307 ps
CPU time 0.52 seconds
Started Jul 19 04:25:24 PM PDT 24
Finished Jul 19 04:25:44 PM PDT 24
Peak memory 194808 kb
Host smart-e6c9ec33-012f-4c34-be29-5c0daff69b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736862205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.736862205
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.740161396
Short name T674
Test name
Test status
Simulation time 27315474298 ps
CPU time 43.38 seconds
Started Jul 19 04:25:24 PM PDT 24
Finished Jul 19 04:26:27 PM PDT 24
Peak memory 199936 kb
Host smart-f26585b1-b7cf-4017-a6f8-fcd900e6fc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740161396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.740161396
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3826314804
Short name T813
Test name
Test status
Simulation time 74141241190 ps
CPU time 33.11 seconds
Started Jul 19 04:25:28 PM PDT 24
Finished Jul 19 04:26:19 PM PDT 24
Peak memory 199512 kb
Host smart-28f40b73-e8c6-4d9f-ab87-a256313d1ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826314804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3826314804
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3581340751
Short name T1074
Test name
Test status
Simulation time 109820092531 ps
CPU time 206.19 seconds
Started Jul 19 04:25:28 PM PDT 24
Finished Jul 19 04:29:12 PM PDT 24
Peak memory 199980 kb
Host smart-73cdb536-80d6-4d95-b53c-7da1b9a7ccf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581340751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3581340751
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.319568837
Short name T764
Test name
Test status
Simulation time 49839459652 ps
CPU time 44.59 seconds
Started Jul 19 04:25:25 PM PDT 24
Finished Jul 19 04:26:29 PM PDT 24
Peak memory 200000 kb
Host smart-0673ca39-cfc4-4a65-8931-ea0367686f6f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319568837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.319568837
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1433998844
Short name T978
Test name
Test status
Simulation time 115236786941 ps
CPU time 267.61 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:30:22 PM PDT 24
Peak memory 199928 kb
Host smart-34ce5041-2bc0-4e56-9dff-f37dbe92d7b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433998844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1433998844
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3427851156
Short name T694
Test name
Test status
Simulation time 3837552254 ps
CPU time 5.56 seconds
Started Jul 19 04:25:33 PM PDT 24
Finished Jul 19 04:25:56 PM PDT 24
Peak memory 198880 kb
Host smart-ce7a3623-594b-4de9-be0f-bdc5e0f0b568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427851156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3427851156
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3432199563
Short name T704
Test name
Test status
Simulation time 2085090483 ps
CPU time 1.32 seconds
Started Jul 19 04:25:26 PM PDT 24
Finished Jul 19 04:25:46 PM PDT 24
Peak memory 194520 kb
Host smart-73ffc908-cfef-4134-8f0a-97fc18df9548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432199563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3432199563
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1911309664
Short name T37
Test name
Test status
Simulation time 10626700193 ps
CPU time 131.91 seconds
Started Jul 19 04:25:23 PM PDT 24
Finished Jul 19 04:27:55 PM PDT 24
Peak memory 199996 kb
Host smart-d9bc2907-554a-4df2-a763-1dbe47f8399a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911309664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1911309664
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.435319401
Short name T339
Test name
Test status
Simulation time 3375084448 ps
CPU time 11.12 seconds
Started Jul 19 04:25:23 PM PDT 24
Finished Jul 19 04:25:54 PM PDT 24
Peak memory 199048 kb
Host smart-b69ba897-0a59-4869-a3ed-fa0e96ef2196
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=435319401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.435319401
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2944991258
Short name T807
Test name
Test status
Simulation time 86526361787 ps
CPU time 57.05 seconds
Started Jul 19 04:25:26 PM PDT 24
Finished Jul 19 04:26:41 PM PDT 24
Peak memory 199924 kb
Host smart-dcf2a964-a7ea-48bb-b014-34f8a0a54c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944991258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2944991258
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1669714141
Short name T376
Test name
Test status
Simulation time 1715593444 ps
CPU time 2.66 seconds
Started Jul 19 04:25:29 PM PDT 24
Finished Jul 19 04:25:49 PM PDT 24
Peak memory 195428 kb
Host smart-a93f1781-7692-40fd-90c5-4461f89c588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669714141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1669714141
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1103039204
Short name T972
Test name
Test status
Simulation time 5655933099 ps
CPU time 5.2 seconds
Started Jul 19 04:25:27 PM PDT 24
Finished Jul 19 04:25:50 PM PDT 24
Peak memory 199808 kb
Host smart-be2c8439-14bf-465f-8e34-eaf58e1481b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103039204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1103039204
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2870037356
Short name T839
Test name
Test status
Simulation time 588834617009 ps
CPU time 512.45 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:34:27 PM PDT 24
Peak memory 199728 kb
Host smart-dcd6d690-b0f4-4823-a86f-19a50fc79c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870037356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2870037356
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1321339473
Short name T255
Test name
Test status
Simulation time 109100503930 ps
CPU time 1087.49 seconds
Started Jul 19 04:25:33 PM PDT 24
Finished Jul 19 04:43:58 PM PDT 24
Peak memory 224664 kb
Host smart-851a7bc0-0ec0-4fbf-8000-c596b727b676
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321339473 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1321339473
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3973460510
Short name T823
Test name
Test status
Simulation time 1818675236 ps
CPU time 2.32 seconds
Started Jul 19 04:25:27 PM PDT 24
Finished Jul 19 04:25:48 PM PDT 24
Peak memory 198932 kb
Host smart-ab23634a-64f9-4d16-a0a4-1ebb1931366c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973460510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3973460510
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3359867604
Short name T307
Test name
Test status
Simulation time 46971441992 ps
CPU time 19.11 seconds
Started Jul 19 04:25:28 PM PDT 24
Finished Jul 19 04:26:05 PM PDT 24
Peak memory 199832 kb
Host smart-222f2840-ae52-4319-adec-1724cf8d8814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359867604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3359867604
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2178434465
Short name T143
Test name
Test status
Simulation time 98835392300 ps
CPU time 127.91 seconds
Started Jul 19 04:27:51 PM PDT 24
Finished Jul 19 04:30:06 PM PDT 24
Peak memory 199956 kb
Host smart-556e3c39-bd1d-4d60-aacb-f902dd0d0b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178434465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2178434465
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3637014205
Short name T28
Test name
Test status
Simulation time 34015373675 ps
CPU time 653.39 seconds
Started Jul 19 04:27:53 PM PDT 24
Finished Jul 19 04:38:53 PM PDT 24
Peak memory 216620 kb
Host smart-3469d39c-a9c0-457c-9657-21370ee09cff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637014205 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3637014205
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1636685403
Short name T810
Test name
Test status
Simulation time 105390173506 ps
CPU time 70.06 seconds
Started Jul 19 04:27:53 PM PDT 24
Finished Jul 19 04:29:09 PM PDT 24
Peak memory 199928 kb
Host smart-aef9ac3e-b74d-4fd1-9f42-4c1f22be65a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636685403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1636685403
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2673354067
Short name T758
Test name
Test status
Simulation time 104260101015 ps
CPU time 192.36 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:31:09 PM PDT 24
Peak memory 216480 kb
Host smart-f005c506-bc93-484a-adb4-0a100037be89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673354067 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2673354067
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1819776020
Short name T1005
Test name
Test status
Simulation time 87350324803 ps
CPU time 17.12 seconds
Started Jul 19 04:27:48 PM PDT 24
Finished Jul 19 04:28:10 PM PDT 24
Peak memory 199744 kb
Host smart-1edf0341-ff3c-4177-bafe-1a8137b0fc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819776020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1819776020
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.630762033
Short name T953
Test name
Test status
Simulation time 351412887761 ps
CPU time 697.06 seconds
Started Jul 19 04:27:53 PM PDT 24
Finished Jul 19 04:39:37 PM PDT 24
Peak memory 224816 kb
Host smart-00882b01-306a-4ea7-8fff-004ad035d7e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630762033 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.630762033
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1873213173
Short name T733
Test name
Test status
Simulation time 12758681483 ps
CPU time 17.61 seconds
Started Jul 19 04:27:49 PM PDT 24
Finished Jul 19 04:28:13 PM PDT 24
Peak memory 199792 kb
Host smart-a807109a-6d10-4757-bbcc-c17dbace53e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873213173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1873213173
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1421347601
Short name T171
Test name
Test status
Simulation time 64542066366 ps
CPU time 523.15 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:36:40 PM PDT 24
Peak memory 216460 kb
Host smart-021abdaa-65c8-4b44-a963-20dffa821d2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421347601 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1421347601
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3487023372
Short name T935
Test name
Test status
Simulation time 99719191040 ps
CPU time 133.86 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:30:11 PM PDT 24
Peak memory 199820 kb
Host smart-a9bbb10e-1522-481c-8655-d11fa050c873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487023372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3487023372
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2207901488
Short name T760
Test name
Test status
Simulation time 32592618480 ps
CPU time 674.83 seconds
Started Jul 19 04:27:55 PM PDT 24
Finished Jul 19 04:39:16 PM PDT 24
Peak memory 211160 kb
Host smart-f6df32ba-ead5-4a75-a361-829c4382e36e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207901488 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2207901488
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3403866912
Short name T756
Test name
Test status
Simulation time 29981221671 ps
CPU time 43.34 seconds
Started Jul 19 04:27:51 PM PDT 24
Finished Jul 19 04:28:41 PM PDT 24
Peak memory 200028 kb
Host smart-c081dd32-b82b-49a1-bc72-860cec8b7a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403866912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3403866912
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2441445107
Short name T871
Test name
Test status
Simulation time 53823516359 ps
CPU time 325.24 seconds
Started Jul 19 04:27:49 PM PDT 24
Finished Jul 19 04:33:20 PM PDT 24
Peak memory 208340 kb
Host smart-2a99b9fe-9a03-410e-a03c-cf504615f712
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441445107 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2441445107
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.4264292399
Short name T1148
Test name
Test status
Simulation time 118289930901 ps
CPU time 236.11 seconds
Started Jul 19 04:27:49 PM PDT 24
Finished Jul 19 04:31:52 PM PDT 24
Peak memory 199944 kb
Host smart-acb389fa-7300-4d3f-b40b-6b195fcc41e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264292399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.4264292399
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.854851077
Short name T165
Test name
Test status
Simulation time 67727959071 ps
CPU time 1168.7 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:47:25 PM PDT 24
Peak memory 216584 kb
Host smart-16a79248-f296-47d5-ae7e-9375545584e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854851077 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.854851077
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.430862886
Short name T209
Test name
Test status
Simulation time 19034188670 ps
CPU time 20.03 seconds
Started Jul 19 04:27:55 PM PDT 24
Finished Jul 19 04:28:21 PM PDT 24
Peak memory 199964 kb
Host smart-50d71cde-989b-4d82-bd9e-f1f5a34978d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430862886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.430862886
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.4185850484
Short name T443
Test name
Test status
Simulation time 91215248188 ps
CPU time 996.69 seconds
Started Jul 19 04:27:49 PM PDT 24
Finished Jul 19 04:44:31 PM PDT 24
Peak memory 224824 kb
Host smart-64830fbe-9521-4c99-b62d-905cd27c8e17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185850484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.4185850484
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.288018118
Short name T862
Test name
Test status
Simulation time 166562056924 ps
CPU time 55.26 seconds
Started Jul 19 04:27:47 PM PDT 24
Finished Jul 19 04:28:47 PM PDT 24
Peak memory 200296 kb
Host smart-466b6458-75db-4973-931f-7a22ce82d357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288018118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.288018118
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2463330524
Short name T971
Test name
Test status
Simulation time 14839712502 ps
CPU time 174.81 seconds
Started Jul 19 04:27:54 PM PDT 24
Finished Jul 19 04:30:55 PM PDT 24
Peak memory 207180 kb
Host smart-8717fbfa-a625-4a89-b295-85b0fe0a2ce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463330524 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2463330524
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1299925029
Short name T256
Test name
Test status
Simulation time 13413495644 ps
CPU time 12.51 seconds
Started Jul 19 04:27:48 PM PDT 24
Finished Jul 19 04:28:06 PM PDT 24
Peak memory 199908 kb
Host smart-80357995-8e50-471d-9fe9-45e6670f4135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299925029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1299925029
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2459006671
Short name T429
Test name
Test status
Simulation time 17262211 ps
CPU time 0.62 seconds
Started Jul 19 04:25:31 PM PDT 24
Finished Jul 19 04:25:49 PM PDT 24
Peak memory 195336 kb
Host smart-0bd35828-6d33-47a1-96a2-e6afb8e4a6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459006671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2459006671
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2551374229
Short name T547
Test name
Test status
Simulation time 24410170189 ps
CPU time 40.61 seconds
Started Jul 19 04:25:33 PM PDT 24
Finished Jul 19 04:26:30 PM PDT 24
Peak memory 199992 kb
Host smart-2a116015-ce3a-40cc-bcf9-92b83fb78f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551374229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2551374229
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2729756686
Short name T798
Test name
Test status
Simulation time 140927532866 ps
CPU time 168.27 seconds
Started Jul 19 04:25:26 PM PDT 24
Finished Jul 19 04:28:33 PM PDT 24
Peak memory 199932 kb
Host smart-712143ab-b0cd-4976-ace4-41d21fc80e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729756686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2729756686
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1965132292
Short name T198
Test name
Test status
Simulation time 191085062660 ps
CPU time 62.65 seconds
Started Jul 19 04:25:28 PM PDT 24
Finished Jul 19 04:26:49 PM PDT 24
Peak memory 199964 kb
Host smart-520f1f76-a090-4ae5-baa3-6ba94e1379ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965132292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1965132292
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2878898123
Short name T997
Test name
Test status
Simulation time 12491670405 ps
CPU time 14.44 seconds
Started Jul 19 04:25:27 PM PDT 24
Finished Jul 19 04:26:00 PM PDT 24
Peak memory 200024 kb
Host smart-7de95eca-f86a-40d9-9f81-c48746a57ae7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878898123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2878898123
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1363292157
Short name T835
Test name
Test status
Simulation time 129714745165 ps
CPU time 184.71 seconds
Started Jul 19 04:25:37 PM PDT 24
Finished Jul 19 04:28:59 PM PDT 24
Peak memory 199880 kb
Host smart-390edf75-f9c3-4741-961c-c874942ca82e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1363292157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1363292157
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.947756429
Short name T340
Test name
Test status
Simulation time 143924849 ps
CPU time 0.86 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:25:55 PM PDT 24
Peak memory 196704 kb
Host smart-648f1c75-4e0a-4aa3-aa9b-bcc759e86bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947756429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.947756429
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2040061868
Short name T910
Test name
Test status
Simulation time 156448947686 ps
CPU time 77.34 seconds
Started Jul 19 04:25:38 PM PDT 24
Finished Jul 19 04:27:12 PM PDT 24
Peak memory 208288 kb
Host smart-4f8cada2-26a4-46a9-bcde-76f0bc8c24e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040061868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2040061868
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.793708499
Short name T464
Test name
Test status
Simulation time 25706564813 ps
CPU time 241.94 seconds
Started Jul 19 04:25:35 PM PDT 24
Finished Jul 19 04:29:54 PM PDT 24
Peak memory 199896 kb
Host smart-a0b7d03c-5357-45bd-956c-3142146c3ef5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793708499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.793708499
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1924740235
Short name T527
Test name
Test status
Simulation time 5388810388 ps
CPU time 12.38 seconds
Started Jul 19 04:25:26 PM PDT 24
Finished Jul 19 04:25:57 PM PDT 24
Peak memory 198876 kb
Host smart-140d7fa7-7b08-469b-bb63-59a9f07d84c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924740235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1924740235
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1887541809
Short name T688
Test name
Test status
Simulation time 90522665044 ps
CPU time 56.57 seconds
Started Jul 19 04:25:38 PM PDT 24
Finished Jul 19 04:26:52 PM PDT 24
Peak memory 195716 kb
Host smart-eab5b757-4b8b-4536-a8e3-e6582867dcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887541809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1887541809
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.4041224616
Short name T297
Test name
Test status
Simulation time 912705722 ps
CPU time 2.16 seconds
Started Jul 19 04:25:25 PM PDT 24
Finished Jul 19 04:25:46 PM PDT 24
Peak memory 198608 kb
Host smart-bc33a001-574b-4194-bbe2-2af9c6168c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041224616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.4041224616
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.4015958796
Short name T158
Test name
Test status
Simulation time 194896351049 ps
CPU time 68.47 seconds
Started Jul 19 04:25:32 PM PDT 24
Finished Jul 19 04:26:58 PM PDT 24
Peak memory 216032 kb
Host smart-4e1d3531-db2a-48b3-b916-6044cd758ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015958796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4015958796
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.509421099
Short name T681
Test name
Test status
Simulation time 81422107168 ps
CPU time 125.64 seconds
Started Jul 19 04:25:36 PM PDT 24
Finished Jul 19 04:28:00 PM PDT 24
Peak memory 216084 kb
Host smart-06a226e8-01a8-408d-92d1-ed98a8de9fd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509421099 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.509421099
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1949449646
Short name T369
Test name
Test status
Simulation time 1089931497 ps
CPU time 2.11 seconds
Started Jul 19 04:25:32 PM PDT 24
Finished Jul 19 04:25:51 PM PDT 24
Peak memory 198468 kb
Host smart-cd2b6b36-4cc6-494a-a567-39feb3e7d010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949449646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1949449646
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2848506644
Short name T640
Test name
Test status
Simulation time 7145521696 ps
CPU time 5.18 seconds
Started Jul 19 04:25:25 PM PDT 24
Finished Jul 19 04:25:50 PM PDT 24
Peak memory 197496 kb
Host smart-acdafe60-adf8-425c-a6cc-33a85fc4e0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848506644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2848506644
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1537644339
Short name T7
Test name
Test status
Simulation time 112014311365 ps
CPU time 185.25 seconds
Started Jul 19 04:27:44 PM PDT 24
Finished Jul 19 04:30:55 PM PDT 24
Peak memory 199984 kb
Host smart-b498c59a-dab4-4ae8-8bcd-ae5a338ba7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537644339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1537644339
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1372072549
Short name T119
Test name
Test status
Simulation time 56131350622 ps
CPU time 237.77 seconds
Started Jul 19 04:27:47 PM PDT 24
Finished Jul 19 04:31:50 PM PDT 24
Peak memory 216032 kb
Host smart-3c656ad2-9048-407e-beef-a6f2f442cd0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372072549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1372072549
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3917638122
Short name T227
Test name
Test status
Simulation time 89360238345 ps
CPU time 17.7 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:28:14 PM PDT 24
Peak memory 199896 kb
Host smart-18de2562-88b1-4455-8b64-1306b1e89b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917638122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3917638122
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2631472111
Short name T166
Test name
Test status
Simulation time 46052825431 ps
CPU time 264.14 seconds
Started Jul 19 04:27:53 PM PDT 24
Finished Jul 19 04:32:24 PM PDT 24
Peak memory 216600 kb
Host smart-3d113583-1b14-497b-b052-87fc14d76b38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631472111 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2631472111
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2204479550
Short name T324
Test name
Test status
Simulation time 76952709203 ps
CPU time 519.01 seconds
Started Jul 19 04:27:49 PM PDT 24
Finished Jul 19 04:36:35 PM PDT 24
Peak memory 216584 kb
Host smart-2f5ca7d1-6ce6-4f29-9c64-f34695807a9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204479550 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2204479550
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.889441497
Short name T797
Test name
Test status
Simulation time 83946699794 ps
CPU time 69.46 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:29:07 PM PDT 24
Peak memory 200176 kb
Host smart-b9556f90-597a-49f6-8837-e0c407fa47f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889441497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.889441497
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.499874447
Short name T1022
Test name
Test status
Simulation time 30229167141 ps
CPU time 202.89 seconds
Started Jul 19 04:27:51 PM PDT 24
Finished Jul 19 04:31:21 PM PDT 24
Peak memory 216676 kb
Host smart-0033d15a-6549-42ab-84e0-b867f1f78b0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499874447 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.499874447
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.4057864183
Short name T635
Test name
Test status
Simulation time 218278523738 ps
CPU time 403.61 seconds
Started Jul 19 04:27:48 PM PDT 24
Finished Jul 19 04:34:37 PM PDT 24
Peak memory 199896 kb
Host smart-324e11fd-6b84-4f91-b3e4-e9da05b81986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057864183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.4057864183
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2685008
Short name T407
Test name
Test status
Simulation time 57522740423 ps
CPU time 832.51 seconds
Started Jul 19 04:27:49 PM PDT 24
Finished Jul 19 04:41:47 PM PDT 24
Peak memory 216820 kb
Host smart-f771cdf0-de5a-4509-9b79-dea00b3114a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685008 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2685008
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1443115608
Short name T652
Test name
Test status
Simulation time 22494930851 ps
CPU time 54.51 seconds
Started Jul 19 04:27:51 PM PDT 24
Finished Jul 19 04:28:53 PM PDT 24
Peak memory 199856 kb
Host smart-d384c04f-4cd5-4922-b5e7-9bf25351b2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443115608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1443115608
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3128602002
Short name T327
Test name
Test status
Simulation time 153024191877 ps
CPU time 680.52 seconds
Started Jul 19 04:27:55 PM PDT 24
Finished Jul 19 04:39:21 PM PDT 24
Peak memory 216784 kb
Host smart-29797e10-61bd-48cf-97d5-5b21e632ee0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128602002 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3128602002
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2742229254
Short name T633
Test name
Test status
Simulation time 28688171835 ps
CPU time 18.47 seconds
Started Jul 19 04:27:46 PM PDT 24
Finished Jul 19 04:28:09 PM PDT 24
Peak memory 199948 kb
Host smart-e113a171-e03e-4b97-8a35-5e805ac0b1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742229254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2742229254
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2068809379
Short name T1034
Test name
Test status
Simulation time 214678836751 ps
CPU time 513.22 seconds
Started Jul 19 04:27:52 PM PDT 24
Finished Jul 19 04:36:32 PM PDT 24
Peak memory 224800 kb
Host smart-fa793902-595b-4967-956b-b58d8cba03a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068809379 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2068809379
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3272030354
Short name T890
Test name
Test status
Simulation time 20606424931 ps
CPU time 18.24 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:28:15 PM PDT 24
Peak memory 199824 kb
Host smart-82f68a35-159c-4096-8a55-e8cfe9fbe399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272030354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3272030354
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3795376050
Short name T67
Test name
Test status
Simulation time 78340155895 ps
CPU time 969.89 seconds
Started Jul 19 04:27:56 PM PDT 24
Finished Jul 19 04:44:11 PM PDT 24
Peak memory 224744 kb
Host smart-4779c62c-09ce-4baa-aa7a-b7303ff416a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795376050 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3795376050
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2943277357
Short name T963
Test name
Test status
Simulation time 106084300547 ps
CPU time 241.91 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:31:58 PM PDT 24
Peak memory 200080 kb
Host smart-d41459ed-aeb0-4803-bbfa-2a5e0dd8579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943277357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2943277357
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1546306285
Short name T68
Test name
Test status
Simulation time 63359024197 ps
CPU time 346.59 seconds
Started Jul 19 04:27:56 PM PDT 24
Finished Jul 19 04:33:48 PM PDT 24
Peak memory 215656 kb
Host smart-3700601c-533a-4e50-93f6-95253791bd97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546306285 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1546306285
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2584070792
Short name T799
Test name
Test status
Simulation time 97869549792 ps
CPU time 242.04 seconds
Started Jul 19 04:27:50 PM PDT 24
Finished Jul 19 04:31:58 PM PDT 24
Peak memory 199940 kb
Host smart-81956267-d8cf-4f22-a057-097fc80627d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584070792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2584070792
Directory /workspace/99.uart_fifo_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%