Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	103711	1			T1	26		T2	35		T3	5
all_values[1]	103711	1			T1	26		T2	35		T3	5
all_values[2]	103711	1			T1	26		T2	35		T3	5
all_values[3]	103711	1			T1	26		T2	35		T3	5
all_values[4]	103711	1			T1	26		T2	35		T3	5
all_values[5]	103711	1			T1	26		T2	35		T3	5
all_values[6]	103711	1			T1	26		T2	35		T3	5
all_values[7]	103711	1			T1	26		T2	35		T3	5
all_values[8]	103711	1			T1	26		T2	35		T3	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

473019

1

T1

108

T2

174

T3

25

auto[1]

460380

1

T1

126

T2

141

T3

20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

845764

1

T1

201

T2

264

T3

38

auto[1]

87635

1

T1

33

T2

51

T3

7

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	32287	1			T1	10		T2	12		T5	15
all_values[0]	auto[0]	auto[1]	21672	1			T2	16		T3	2		T4	2
all_values[0]	auto[1]	auto[0]	28212	1			T3	2		T6	97		T12	6
all_values[0]	auto[1]	auto[1]	21540	1			T1	16		T2	7		T3	1
all_values[1]	auto[0]	auto[0]	52383	1			T1	5		T2	10		T3	5
all_values[1]	auto[0]	auto[1]	1791	1			T6	1		T7	5		T13	25
all_values[1]	auto[1]	auto[0]	47964	1			T1	11		T2	25		T5	10
all_values[1]	auto[1]	auto[1]	1573	1			T1	10		T6	12		T13	10
all_values[2]	auto[0]	auto[0]	47769	1			T1	21		T2	18		T3	1
all_values[2]	auto[0]	auto[1]	2732	1			T2	2		T3	1		T4	1
all_values[2]	auto[1]	auto[0]	50854	1			T1	3		T2	12		T3	3
all_values[2]	auto[1]	auto[1]	2356	1			T1	2		T2	3		T5	1
all_values[3]	auto[0]	auto[0]	53554	1			T1	10		T2	33		T3	5
all_values[3]	auto[0]	auto[1]	333	1			T6	3		T13	3		T16	3
all_values[3]	auto[1]	auto[0]	49507	1			T1	16		T2	2		T5	17
all_values[3]	auto[1]	auto[1]	317	1			T16	1		T14	2		T112	2
all_values[4]	auto[0]	auto[0]	48807	1			T1	5		T2	20		T3	3
all_values[4]	auto[0]	auto[1]	411	1			T6	1		T13	11		T16	2
all_values[4]	auto[1]	auto[0]	54007	1			T1	21		T2	15		T3	2
all_values[4]	auto[1]	auto[1]	486	1			T6	2		T13	10		T16	1
all_values[5]	auto[0]	auto[0]	50582	1			T1	15		T2	16		T3	3
all_values[5]	auto[0]	auto[1]	171	1			T6	1		T16	1		T30	5
all_values[5]	auto[1]	auto[0]	52771	1			T1	11		T2	19		T3	2
all_values[5]	auto[1]	auto[1]	187	1			T6	1		T14	5		T28	1
all_values[6]	auto[0]	auto[0]	54883	1			T1	26		T2	1		T4	2
all_values[6]	auto[0]	auto[1]	184	1			T6	3		T16	2		T14	3
all_values[6]	auto[1]	auto[0]	48438	1			T2	34		T3	5		T5	11
all_values[6]	auto[1]	auto[1]	206	1			T6	1		T28	2		T116	3
all_values[7]	auto[0]	auto[0]	53049	1			T2	20		T4	2		T5	18
all_values[7]	auto[0]	auto[1]	383	1			T6	2		T16	2		T14	3
all_values[7]	auto[1]	auto[0]	49859	1			T1	26		T2	15		T3	5
all_values[7]	auto[1]	auto[1]	420	1			T6	3		T13	8		T14	4
all_values[8]	auto[0]	auto[0]	34224	1			T1	11		T2	12		T3	2
all_values[8]	auto[0]	auto[1]	17804	1			T1	5		T2	14		T3	3
all_values[8]	auto[1]	auto[0]	36614	1			T1	10		T6	105		T8	12
all_values[8]	auto[1]	auto[1]	15069	1			T2	9		T5	1		T6	14