Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
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Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv



Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 13 0 13 100.00
Crosses 22 0 22 100.00


Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dir 2 0 2 100.00 100 1 1 0
cp_rst_pos 11 0 11 100.00 100 1 1 0


Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
uart_reset_cg_cc 22 0 22 100.00 100 1 1 0


Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UartTx] 2553 1 T1 1 T2 1 T3 1
auto[UartRx] 2553 1 T1 1 T2 1 T3 1



Summary for Variable cp_rst_pos

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 0 11 100.00


User Defined Bins for cp_rst_pos

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4543 1 T1 2 T2 2 T3 2
values[1] 39 1 T16 1 T26 1 T27 1
values[2] 43 1 T6 1 T16 1 T30 1
values[3] 58 1 T14 1 T26 1 T28 3
values[4] 62 1 T6 1 T16 2 T26 2
values[5] 58 1 T16 1 T14 1 T26 4
values[6] 58 1 T26 1 T27 1 T29 3
values[7] 54 1 T16 1 T30 1 T32 1
values[8] 56 1 T14 2 T27 2 T30 1
values[9] 57 1 T16 1 T14 1 T26 1
values[10] 49 1 T16 4 T14 2 T26 2



Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 22 0 22 100.00


Automatically Generated Cross Bins for uart_reset_cg_cc

Bins
cp_dircp_rst_posCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UartTx] values[0] 2346 1 T1 1 T2 1 T3 1
auto[UartTx] values[1] 15 1 T16 1 T26 1 T117 1
auto[UartTx] values[2] 14 1 T6 1 T16 1 T46 1
auto[UartTx] values[3] 28 1 T14 1 T28 2 T29 1
auto[UartTx] values[4] 24 1 T16 1 T28 1 T29 1
auto[UartTx] values[5] 19 1 T26 1 T29 1 T32 1
auto[UartTx] values[6] 25 1 T26 1 T29 1 T30 1
auto[UartTx] values[7] 19 1 T16 1 T30 1 T32 1
auto[UartTx] values[8] 22 1 T14 1 T27 2 T30 1
auto[UartTx] values[9] 21 1 T26 1 T28 1 T30 1
auto[UartTx] values[10] 12 1 T14 1 T50 1 T323 1
auto[UartRx] values[0] 2197 1 T1 1 T2 1 T3 1
auto[UartRx] values[1] 24 1 T27 1 T28 2 T29 1
auto[UartRx] values[2] 29 1 T30 1 T31 1 T69 1
auto[UartRx] values[3] 30 1 T26 1 T28 1 T30 1
auto[UartRx] values[4] 38 1 T6 1 T16 1 T26 2
auto[UartRx] values[5] 39 1 T16 1 T14 1 T26 3
auto[UartRx] values[6] 33 1 T27 1 T29 2 T32 1
auto[UartRx] values[7] 35 1 T118 1 T141 1 T323 2
auto[UartRx] values[8] 34 1 T14 1 T117 1 T314 1
auto[UartRx] values[9] 36 1 T16 1 T14 1 T28 1
auto[UartRx] values[10] 37 1 T16 4 T14 1 T26 2

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