Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2310	1			T2	4		T6	8		T8	12
auto[BaudRate115200]	1931	1			T1	2		T2	1		T3	1
auto[BaudRate230400]	1922	1			T1	2		T2	1		T4	1
auto[BaudRate128Kbps]	2000	1			T1	1		T2	2		T3	2
auto[BaudRate256Kbps]	2166	1			T1	1		T2	2		T3	1
auto[BaudRate1Mbps]	1763	1			T3	1		T5	2		T6	8
auto[BaudRate1p5Mbps]	1177	1			T3	1		T5	2		T7	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1426	1			T42	9		T296	2		T129	9
freqs[25]	1477	1			T3	6		T5	5		T12	5
freqs[48]	492	1			T10	18		T36	7		T18	27
freqs[50]	502	1			T111	7		T29	84		T276	1
freqs[100]	1286	1			T1	6		T43	6		T245	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	225	1			T42	3		T129	1		T121	2
auto[BaudRate9600]	freqs[25]	227	1			T12	2		T41	1		T44	1
auto[BaudRate9600]	freqs[48]	88	1			T10	18		T18	6		T324	3
auto[BaudRate9600]	freqs[50]	80	1			T111	2		T29	7		T276	1
auto[BaudRate9600]	freqs[100]	239	1			T38	1		T249	3		T246	3
auto[BaudRate115200]	freqs[24]	214	1			T42	1		T129	3		T15	1
auto[BaudRate115200]	freqs[25]	206	1			T3	1		T40	1		T41	1
auto[BaudRate115200]	freqs[48]	87	1			T18	6		T30	30		T270	3
auto[BaudRate115200]	freqs[50]	56	1			T111	1		T29	6		T255	3
auto[BaudRate115200]	freqs[100]	167	1			T1	2		T43	1		T245	1
auto[BaudRate230400]	freqs[24]	196	1			T296	1		T15	2		T121	2
auto[BaudRate230400]	freqs[25]	242	1			T12	1		T40	2		T41	1
auto[BaudRate230400]	freqs[48]	59	1			T18	6		T30	13		T144	2
auto[BaudRate230400]	freqs[50]	54	1			T111	1		T29	10		T259	2
auto[BaudRate230400]	freqs[100]	166	1			T1	2		T43	1		T245	1
auto[BaudRate128Kbps]	freqs[24]	224	1			T42	4		T296	1		T129	1
auto[BaudRate128Kbps]	freqs[25]	238	1			T3	2		T12	1		T40	1
auto[BaudRate128Kbps]	freqs[48]	57	1			T30	24		T284	2		T270	1
auto[BaudRate128Kbps]	freqs[50]	63	1			T111	2		T29	13		T325	2
auto[BaudRate128Kbps]	freqs[100]	173	1			T1	1		T43	3		T245	2
auto[BaudRate256Kbps]	freqs[24]	207	1			T42	1		T129	2		T133	2
auto[BaudRate256Kbps]	freqs[25]	236	1			T3	1		T5	1		T40	1
auto[BaudRate256Kbps]	freqs[48]	93	1			T36	3		T18	6		T30	19
auto[BaudRate256Kbps]	freqs[50]	80	1			T29	21		T259	2		T255	1
auto[BaudRate256Kbps]	freqs[100]	166	1			T1	1		T245	1		T38	2
auto[BaudRate1Mbps]	freqs[24]	229	1			T129	2		T121	1		T133	1
auto[BaudRate1Mbps]	freqs[25]	218	1			T3	1		T5	2		T12	1
auto[BaudRate1Mbps]	freqs[48]	47	1			T36	3		T30	11		T284	2
auto[BaudRate1Mbps]	freqs[50]	83	1			T29	12		T259	1		T255	3
auto[BaudRate1Mbps]	freqs[100]	209	1			T43	1		T38	1		T249	1
auto[BaudRate1p5Mbps]	freqs[25]	110	1			T3	1		T5	2		T14	3
auto[BaudRate1p5Mbps]	freqs[48]	61	1			T36	1		T18	3		T30	13
auto[BaudRate1p5Mbps]	freqs[50]	86	1			T111	1		T29	15		T278	1
auto[BaudRate1p5Mbps]	freqs[100]	166	1			T38	1		T249	2		T246	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded