Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	30362929	1			T1	31		T2	40		T3	15
all_levels[1]	187746	1			T1	7		T5	1326		T6	50
all_levels[2]	2439	1			T1	3		T5	11		T6	3
all_levels[3]	1030	1			T1	1		T33	1		T35	8
all_levels[4]	730	1			T1	4		T6	3		T7	2
all_levels[5]	548	1			T1	1		T33	1		T35	2
all_levels[6]	416	1			T6	1		T7	1		T33	1
all_levels[7]	340	1			T1	1		T120	1		T16	1
all_levels[8]	303	1			T1	2		T33	3		T16	1
all_levels[9]	238	1			T1	2		T7	1		T33	1
all_levels[10]	198	1			T1	2		T35	2		T16	1
all_levels[11]	174	1			T2	1		T35	2		T16	4
all_levels[12]	187	1			T6	1		T35	1		T16	3
all_levels[13]	180	1			T1	5		T120	1		T16	1
all_levels[14]	127	1			T1	1		T16	2		T43	2
all_levels[15]	116	1			T1	1		T33	1		T35	1
all_levels[16]	117	1			T1	2		T16	1		T121	1
all_levels[17]	105	1			T1	1		T43	1		T122	1
all_levels[18]	97	1			T1	1		T123	1		T27	1
all_levels[19]	82	1			T35	1		T14	1		T38	1
all_levels[20]	68	1			T43	1		T124	1		T125	2
all_levels[21]	99	1			T124	1		T125	2		T126	2
all_levels[22]	70	1			T35	1		T127	1		T128	1
all_levels[23]	73	1			T40	1		T14	1		T129	1
all_levels[24]	59	1			T43	1		T124	2		T28	1
all_levels[25]	50	1			T16	1		T27	1		T130	1
all_levels[26]	46	1			T14	3		T129	1		T28	1
all_levels[27]	40	1			T35	1		T129	1		T122	1
all_levels[28]	43	1			T35	1		T40	1		T131	2
all_levels[29]	35	1			T42	1		T132	1		T133	1
all_levels[30]	49	1			T129	1		T128	1		T134	1
all_levels[31]	34	1			T38	1		T28	1		T135	1
all_levels[32]	27	1			T132	1		T136	1		T110	1
all_levels[33]	24	1			T6	1		T137	2		T134	3
all_levels[34]	22	1			T35	1		T132	1		T136	1
all_levels[35]	30	1			T125	3		T127	1		T138	1
all_levels[36]	24	1			T14	1		T132	1		T135	1
all_levels[37]	22	1			T139	1		T140	1		T141	1
all_levels[38]	20	1			T130	1		T142	1		T143	1
all_levels[39]	13	1			T35	1		T136	1		T144	2
all_levels[40]	26	1			T38	1		T28	1		T134	1
all_levels[41]	19	1			T40	1		T145	1		T146	1
all_levels[42]	18	1			T147	1		T148	1		T149	1
all_levels[43]	16	1			T148	1		T150	1		T151	1
all_levels[44]	19	1			T127	1		T152	2		T153	5
all_levels[45]	9	1			T154	1		T130	1		T155	1
all_levels[46]	15	1			T38	1		T139	1		T156	4
all_levels[47]	19	1			T129	1		T134	1		T64	1
all_levels[48]	14	1			T122	1		T148	1		T64	1
all_levels[49]	10	1			T42	1		T29	1		T157	1
all_levels[50]	12	1			T64	1		T158	1		T159	1
all_levels[51]	11	1			T160	1		T143	1		T161	1
all_levels[52]	13	1			T147	1		T160	1		T150	1
all_levels[53]	14	1			T43	1		T150	1		T162	1
all_levels[54]	19	1			T42	1		T163	4		T164	1
all_levels[55]	5	1			T165	2		T166	2		T167	1
all_levels[56]	7	1			T168	2		T52	1		T169	1
all_levels[57]	12	1			T14	1		T127	1		T29	1
all_levels[58]	6	1			T170	3		T171	1		T172	1
all_levels[59]	11	1			T28	1		T127	1		T154	1
all_levels[60]	2	1			T173	1		T61	1		-	-
all_levels[61]	4	1			T127	1		T174	1		T175	1
all_levels[62]	10	1			T176	1		T177	1		T178	1
all_levels[63]	6	1			T71	1		T179	1		T180	1
all_levels[64]	111	1			T123	2		T27	1		T181	4

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30554590

1

T1

63

T2

32

T3

10

auto[1]

4768

1

T1

2

T2

9

T3

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[32]]	[auto[1]]	0	1	1
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[48] , all_levels[49]]	[auto[1]]	--	--	2
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[59] , all_levels[60] , all_levels[61]]	[auto[1]]	--	--	3
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	30358630	1			T1	30		T2	31		T3	10
all_levels[0]	auto[1]	4299	1			T1	1		T2	9		T3	5
all_levels[1]	auto[0]	187661	1			T1	7		T5	1326		T6	50
all_levels[1]	auto[1]	85	1			T35	2		T129	1		T125	1
all_levels[2]	auto[0]	2398	1			T1	3		T5	11		T6	3
all_levels[2]	auto[1]	41	1			T182	1		T124	1		T183	1
all_levels[3]	auto[0]	1008	1			T1	1		T33	1		T35	8
all_levels[3]	auto[1]	22	1			T183	1		T184	1		T185	2
all_levels[4]	auto[0]	721	1			T1	4		T6	3		T7	1
all_levels[4]	auto[1]	9	1			T7	1		T42	1		T144	1
all_levels[5]	auto[0]	533	1			T1	1		T33	1		T35	2
all_levels[5]	auto[1]	15	1			T125	1		T186	2		T169	1
all_levels[6]	auto[0]	408	1			T6	1		T7	1		T33	1
all_levels[6]	auto[1]	8	1			T124	2		T187	1		T188	1
all_levels[7]	auto[0]	333	1			T1	1		T120	1		T16	1
all_levels[7]	auto[1]	7	1			T121	1		T125	1		T189	1
all_levels[8]	auto[0]	291	1			T1	2		T33	3		T16	1
all_levels[8]	auto[1]	12	1			T190	1		T191	1		T192	1
all_levels[9]	auto[0]	222	1			T1	2		T7	1		T33	1
all_levels[9]	auto[1]	16	1			T29	2		T46	1		T193	1
all_levels[10]	auto[0]	190	1			T1	2		T35	2		T16	1
all_levels[10]	auto[1]	8	1			T194	2		T134	2		T195	1
all_levels[11]	auto[0]	166	1			T2	1		T35	1		T16	4
all_levels[11]	auto[1]	8	1			T35	1		T196	1		T197	1
all_levels[12]	auto[0]	170	1			T6	1		T35	1		T16	3
all_levels[12]	auto[1]	17	1			T111	1		T138	3		T198	1
all_levels[13]	auto[0]	162	1			T1	4		T120	1		T16	1
all_levels[13]	auto[1]	18	1			T1	1		T46	1		T199	1
all_levels[14]	auto[0]	113	1			T1	1		T16	2		T43	2
all_levels[14]	auto[1]	14	1			T111	1		T176	1		T200	1
all_levels[15]	auto[0]	107	1			T1	1		T33	1		T35	1
all_levels[15]	auto[1]	9	1			T155	2		T108	2		T201	1
all_levels[16]	auto[0]	106	1			T1	2		T16	1		T121	1
all_levels[16]	auto[1]	11	1			T47	1		T202	1		T203	1
all_levels[17]	auto[0]	93	1			T1	1		T43	1		T122	1
all_levels[17]	auto[1]	12	1			T121	1		T204	2		T179	1
all_levels[18]	auto[0]	95	1			T1	1		T123	1		T27	1
all_levels[18]	auto[1]	2	1			T205	2		-	-		-	-
all_levels[19]	auto[0]	73	1			T35	1		T14	1		T38	1
all_levels[19]	auto[1]	9	1			T206	1		T207	3		T208	1
all_levels[20]	auto[0]	61	1			T43	1		T124	1		T125	2
all_levels[20]	auto[1]	7	1			T209	1		T210	1		T211	2
all_levels[21]	auto[0]	86	1			T124	1		T125	1		T126	1
all_levels[21]	auto[1]	13	1			T125	1		T126	1		T143	3
all_levels[22]	auto[0]	67	1			T35	1		T127	1		T128	1
all_levels[22]	auto[1]	3	1			T161	1		T212	1		T213	1
all_levels[23]	auto[0]	62	1			T40	1		T14	1		T129	1
all_levels[23]	auto[1]	11	1			T184	2		T134	2		T214	1
all_levels[24]	auto[0]	50	1			T43	1		T124	1		T28	1
all_levels[24]	auto[1]	9	1			T124	1		T133	1		T215	5
all_levels[25]	auto[0]	48	1			T16	1		T27	1		T130	1
all_levels[25]	auto[1]	2	1			T216	1		T217	1		-	-
all_levels[26]	auto[0]	42	1			T14	1		T129	1		T28	1
all_levels[26]	auto[1]	4	1			T14	2		T218	1		T219	1
all_levels[27]	auto[0]	39	1			T35	1		T129	1		T122	1
all_levels[27]	auto[1]	1	1			T220	1		-	-		-	-
all_levels[28]	auto[0]	38	1			T35	1		T40	1		T131	1
all_levels[28]	auto[1]	5	1			T131	1		T46	1		T221	1
all_levels[29]	auto[0]	34	1			T42	1		T132	1		T133	1
all_levels[29]	auto[1]	1	1			T222	1		-	-		-	-
all_levels[30]	auto[0]	39	1			T129	1		T128	1		T134	1
all_levels[30]	auto[1]	10	1			T223	1		T171	2		T224	2
all_levels[31]	auto[0]	32	1			T38	1		T28	1		T135	1
all_levels[31]	auto[1]	2	1			T225	1		T226	1		-	-
all_levels[32]	auto[0]	27	1			T132	1		T136	1		T110	1
all_levels[33]	auto[0]	18	1			T6	1		T137	1		T134	1
all_levels[33]	auto[1]	6	1			T137	1		T134	2		T227	1
all_levels[34]	auto[0]	21	1			T35	1		T132	1		T136	1
all_levels[34]	auto[1]	1	1			T217	1		-	-		-	-
all_levels[35]	auto[0]	24	1			T125	1		T127	1		T138	1
all_levels[35]	auto[1]	6	1			T125	2		T149	1		T228	1
all_levels[36]	auto[0]	22	1			T14	1		T132	1		T135	1
all_levels[36]	auto[1]	2	1			T158	2		-	-		-	-
all_levels[37]	auto[0]	20	1			T139	1		T140	1		T141	1
all_levels[37]	auto[1]	2	1			T229	1		T230	1		-	-
all_levels[38]	auto[0]	19	1			T130	1		T142	1		T143	1
all_levels[38]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[39]	auto[0]	12	1			T35	1		T136	1		T144	1
all_levels[39]	auto[1]	1	1			T144	1		-	-		-	-
all_levels[40]	auto[0]	24	1			T38	1		T28	1		T134	1
all_levels[40]	auto[1]	2	1			T232	2		-	-		-	-
all_levels[41]	auto[0]	19	1			T40	1		T145	1		T146	1
all_levels[42]	auto[0]	17	1			T147	1		T148	1		T149	1
all_levels[42]	auto[1]	1	1			T233	1		-	-		-	-
all_levels[43]	auto[0]	13	1			T148	1		T150	1		T151	1
all_levels[43]	auto[1]	3	1			T234	3		-	-		-	-
all_levels[44]	auto[0]	12	1			T127	1		T152	1		T153	1
all_levels[44]	auto[1]	7	1			T152	1		T153	4		T235	1
all_levels[45]	auto[0]	8	1			T154	1		T130	1		T155	1
all_levels[45]	auto[1]	1	1			T225	1		-	-		-	-
all_levels[46]	auto[0]	10	1			T38	1		T139	1		T156	1
all_levels[46]	auto[1]	5	1			T156	3		T236	2		-	-
all_levels[47]	auto[0]	16	1			T129	1		T134	1		T64	1
all_levels[47]	auto[1]	3	1			T200	2		T237	1		-	-
all_levels[48]	auto[0]	14	1			T122	1		T148	1		T64	1
all_levels[49]	auto[0]	10	1			T42	1		T29	1		T157	1
all_levels[50]	auto[0]	11	1			T64	1		T158	1		T159	1
all_levels[50]	auto[1]	1	1			T238	1		-	-		-	-
all_levels[51]	auto[0]	11	1			T160	1		T143	1		T161	1
all_levels[52]	auto[0]	11	1			T147	1		T160	1		T150	1
all_levels[52]	auto[1]	2	1			T239	2		-	-		-	-
all_levels[53]	auto[0]	11	1			T43	1		T150	1		T162	1
all_levels[53]	auto[1]	3	1			T240	3		-	-		-	-
all_levels[54]	auto[0]	14	1			T42	1		T163	1		T164	1
all_levels[54]	auto[1]	5	1			T163	3		T172	1		T241	1
all_levels[55]	auto[0]	3	1			T165	1		T166	1		T167	1
all_levels[55]	auto[1]	2	1			T165	1		T166	1		-	-
all_levels[56]	auto[0]	6	1			T168	1		T52	1		T169	1
all_levels[56]	auto[1]	1	1			T168	1		-	-		-	-
all_levels[57]	auto[0]	11	1			T14	1		T127	1		T29	1
all_levels[57]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[58]	auto[0]	4	1			T170	1		T171	1		T172	1
all_levels[58]	auto[1]	2	1			T170	2		-	-		-	-
all_levels[59]	auto[0]	11	1			T28	1		T127	1		T154	1
all_levels[60]	auto[0]	2	1			T173	1		T61	1		-	-
all_levels[61]	auto[0]	4	1			T127	1		T174	1		T175	1
all_levels[62]	auto[0]	9	1			T176	1		T177	1		T178	1
all_levels[62]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[63]	auto[0]	6	1			T71	1		T179	1		T180	1
all_levels[64]	auto[0]	92	1			T123	2		T27	1		T181	1
all_levels[64]	auto[1]	19	1			T181	3		T145	1		T71	1