Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	103711	1			T1	26		T2	35		T3	5
all_pins[1]	103711	1			T1	26		T2	35		T3	5
all_pins[2]	103711	1			T1	26		T2	35		T3	5
all_pins[3]	103711	1			T1	26		T2	35		T3	5
all_pins[4]	103711	1			T1	26		T2	35		T3	5
all_pins[5]	103711	1			T1	26		T2	35		T3	5
all_pins[6]	103711	1			T1	26		T2	35		T3	5
all_pins[7]	103711	1			T1	26		T2	35		T3	5
all_pins[8]	103711	1			T1	26		T2	35		T3	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	890284	1			T1	206		T2	296		T3	43
values[0x1]	43115	1			T1	28		T2	19		T3	2
transitions[0x0=>0x1]	35376	1			T1	28		T2	13		T3	2
transitions[0x1=>0x0]	35140	1			T1	27		T2	12		T3	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	82103	1			T1	10		T2	28		T3	4
all_pins[0]	values[0x1]	21608	1			T1	16		T2	7		T3	1
all_pins[0]	transitions[0x0=>0x1]	21095	1			T1	16		T2	7		T3	1
all_pins[0]	transitions[0x1=>0x0]	1059	1			T1	10		T6	12		T13	10
all_pins[1]	values[0x0]	102139	1			T1	16		T2	35		T3	5
all_pins[1]	values[0x1]	1572	1			T1	10		T6	12		T13	10
all_pins[1]	transitions[0x0=>0x1]	1474	1			T1	10		T6	12		T13	10
all_pins[1]	transitions[0x1=>0x0]	2324	1			T1	2		T2	3		T5	1
all_pins[2]	values[0x0]	101289	1			T1	24		T2	32		T3	5
all_pins[2]	values[0x1]	2422	1			T1	2		T2	3		T5	1
all_pins[2]	transitions[0x0=>0x1]	2356	1			T1	2		T2	3		T5	1
all_pins[2]	transitions[0x1=>0x0]	251	1			T16	1		T14	1		T112	2
all_pins[3]	values[0x0]	103394	1			T1	26		T2	35		T3	5
all_pins[3]	values[0x1]	317	1			T16	1		T14	2		T112	2
all_pins[3]	transitions[0x0=>0x1]	267	1			T14	2		T112	2		T29	1
all_pins[3]	transitions[0x1=>0x0]	436	1			T6	2		T13	10		T14	5
all_pins[4]	values[0x0]	103225	1			T1	26		T2	35		T3	5
all_pins[4]	values[0x1]	486	1			T6	2		T13	10		T16	1
all_pins[4]	transitions[0x0=>0x1]	396	1			T6	1		T13	10		T16	1
all_pins[4]	transitions[0x1=>0x0]	147	1			T14	3		T112	1		T28	1
all_pins[5]	values[0x0]	103474	1			T1	26		T2	35		T3	5
all_pins[5]	values[0x1]	237	1			T6	1		T14	5		T17	3
all_pins[5]	transitions[0x0=>0x1]	171	1			T6	1		T14	5		T17	3
all_pins[5]	transitions[0x1=>0x0]	840	1			T3	1		T6	1		T120	2
all_pins[6]	values[0x0]	102805	1			T1	26		T2	35		T3	4
all_pins[6]	values[0x1]	906	1			T3	1		T6	1		T120	2
all_pins[6]	transitions[0x0=>0x1]	834	1			T3	1		T120	2		T40	2
all_pins[6]	transitions[0x1=>0x0]	348	1			T6	2		T13	8		T14	4
all_pins[7]	values[0x0]	103291	1			T1	26		T2	35		T3	5
all_pins[7]	values[0x1]	420	1			T6	3		T13	8		T14	4
all_pins[7]	transitions[0x0=>0x1]	270	1			T6	1		T14	4		T123	2
all_pins[7]	transitions[0x1=>0x0]	14997	1			T2	9		T5	1		T6	12
all_pins[8]	values[0x0]	88564	1			T1	26		T2	26		T3	5
all_pins[8]	values[0x1]	15147	1			T2	9		T5	1		T6	14
all_pins[8]	transitions[0x0=>0x1]	8513	1			T2	3		T5	1		T6	7
all_pins[8]	transitions[0x1=>0x0]	14738	1			T1	15		T3	1		T5	1