Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7804829	1			T1	9		T2	29		T3	15
all_levels[1]	1853118	1			T1	25		T5	26		T6	223
all_levels[2]	359079	1			T1	3		T3	1		T5	31
all_levels[3]	202516	1			T5	31		T6	121		T12	1
all_levels[4]	403734	1			T1	2		T2	5		T5	28
all_levels[5]	196884	1			T1	2		T2	3		T5	31
all_levels[6]	333225	1			T5	29		T6	125		T12	4
all_levels[7]	397738	1			T1	27		T2	2		T5	29
all_levels[8]	254656	1			T2	2		T5	32		T6	99
all_levels[9]	269926	1			T5	26		T6	193		T12	6
all_levels[10]	276340	1			T5	31		T6	210		T12	3
all_levels[11]	343278	1			T5	34		T6	214		T12	39
all_levels[12]	516377	1			T5	27		T6	221		T8	70
all_levels[13]	301105	1			T5	31		T6	218		T8	1
all_levels[14]	182641	1			T5	27		T6	153		T8	1
all_levels[15]	464666	1			T5	33		T6	146		T12	4
all_levels[16]	219604	1			T5	25		T6	188		T7	5
all_levels[17]	165208	1			T5	29		T6	220		T8	18
all_levels[18]	169022	1			T5	29		T6	199		T7	1
all_levels[19]	178061	1			T5	34		T6	285		T120	1
all_levels[20]	227018	1			T5	30		T6	297		T33	9
all_levels[21]	186664	1			T5	26		T6	264		T12	1
all_levels[22]	172271	1			T5	33		T6	179		T35	3
all_levels[23]	178224	1			T2	1		T5	28		T6	181
all_levels[24]	194563	1			T5	25		T6	254		T12	3
all_levels[25]	180134	1			T5	29		T6	305		T120	1
all_levels[26]	166668	1			T5	33		T6	291		T36	55
all_levels[27]	486658	1			T5	31		T6	263		T120	1
all_levels[28]	219023	1			T5	29		T6	304		T33	1
all_levels[29]	291935	1			T5	22		T6	330		T36	48
all_levels[30]	216394	1			T5	31		T6	203		T36	55
all_levels[31]	537021	1			T5	628		T6	288		T36	1062
all_levels[32]	12610467	1			T5	14504		T6	2543		T12	4

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30554590

1

T1

63

T2

32

T3

10

auto[1]

4457

1

T1

5

T2

10

T3

6

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7802287	1			T1	7		T2	24		T3	9
all_levels[0]	auto[1]	2542	1			T1	2		T2	5		T3	6
all_levels[1]	auto[0]	1852785	1			T1	23		T5	26		T6	223
all_levels[1]	auto[1]	333	1			T1	2		T13	11		T35	2
all_levels[2]	auto[0]	359046	1			T1	3		T3	1		T5	31
all_levels[2]	auto[1]	33	1			T38	1		T126	1		T131	1
all_levels[3]	auto[0]	202322	1			T5	31		T6	121		T12	1
all_levels[3]	auto[1]	194	1			T13	8		T15	18		T183	1
all_levels[4]	auto[0]	403703	1			T1	2		T2	2		T5	28
all_levels[4]	auto[1]	31	1			T2	3		T45	4		T186	2
all_levels[5]	auto[0]	196856	1			T1	2		T2	2		T5	31
all_levels[5]	auto[1]	28	1			T2	1		T129	2		T32	1
all_levels[6]	auto[0]	333193	1			T5	29		T6	125		T12	4
all_levels[6]	auto[1]	32	1			T29	1		T32	1		T145	1
all_levels[7]	auto[0]	397655	1			T1	26		T2	1		T5	29
all_levels[7]	auto[1]	83	1			T1	1		T2	1		T182	2
all_levels[8]	auto[0]	254634	1			T2	2		T5	32		T6	99
all_levels[8]	auto[1]	22	1			T129	1		T135	2		T258	1
all_levels[9]	auto[0]	269897	1			T5	26		T6	193		T12	6
all_levels[9]	auto[1]	29	1			T255	1		T150	2		T327	1
all_levels[10]	auto[0]	276325	1			T5	31		T6	210		T12	3
all_levels[10]	auto[1]	15	1			T133	2		T223	1		T328	1
all_levels[11]	auto[0]	343250	1			T5	34		T6	214		T12	38
all_levels[11]	auto[1]	28	1			T12	1		T223	1		T290	1
all_levels[12]	auto[0]	516348	1			T5	27		T6	221		T8	70
all_levels[12]	auto[1]	29	1			T42	1		T283	1		T130	2
all_levels[13]	auto[0]	301077	1			T5	31		T6	218		T8	1
all_levels[13]	auto[1]	28	1			T41	1		T137	2		T246	1
all_levels[14]	auto[0]	182619	1			T5	27		T6	153		T8	1
all_levels[14]	auto[1]	22	1			T205	2		T329	1		T330	1
all_levels[15]	auto[0]	464557	1			T5	33		T6	146		T12	4
all_levels[15]	auto[1]	109	1			T120	1		T14	9		T38	1
all_levels[16]	auto[0]	219558	1			T5	25		T6	188		T7	2
all_levels[16]	auto[1]	46	1			T7	3		T125	1		T244	2
all_levels[17]	auto[0]	165193	1			T5	29		T6	220		T8	18
all_levels[17]	auto[1]	15	1			T133	2		T251	1		T108	2
all_levels[18]	auto[0]	168998	1			T5	29		T6	199		T7	1
all_levels[18]	auto[1]	24	1			T38	2		T129	2		T260	1
all_levels[19]	auto[0]	178034	1			T5	34		T6	285		T120	1
all_levels[19]	auto[1]	27	1			T125	1		T128	2		T265	1
all_levels[20]	auto[0]	226992	1			T5	30		T6	297		T33	9
all_levels[20]	auto[1]	26	1			T260	1		T143	1		T225	2
all_levels[21]	auto[0]	186624	1			T5	26		T6	264		T12	1
all_levels[21]	auto[1]	40	1			T129	1		T260	4		T132	1
all_levels[22]	auto[0]	172254	1			T5	33		T6	179		T35	3
all_levels[22]	auto[1]	17	1			T42	1		T327	2		T331	2
all_levels[23]	auto[0]	178204	1			T2	1		T5	28		T6	181
all_levels[23]	auto[1]	20	1			T111	2		T139	1		T156	3
all_levels[24]	auto[0]	194544	1			T5	25		T6	254		T12	3
all_levels[24]	auto[1]	19	1			T42	1		T47	4		T161	1
all_levels[25]	auto[0]	180125	1			T5	29		T6	305		T120	1
all_levels[25]	auto[1]	9	1			T133	1		T138	1		T200	1
all_levels[26]	auto[0]	166646	1			T5	33		T6	291		T36	55
all_levels[26]	auto[1]	22	1			T264	1		T67	3		T200	3
all_levels[27]	auto[0]	486641	1			T5	31		T6	263		T120	1
all_levels[27]	auto[1]	17	1			T29	1		T155	1		T161	1
all_levels[28]	auto[0]	219006	1			T5	29		T6	304		T33	1
all_levels[28]	auto[1]	17	1			T117	1		T332	1		T333	3
all_levels[29]	auto[0]	291915	1			T5	22		T6	330		T36	48
all_levels[29]	auto[1]	20	1			T223	1		T334	1		T335	1
all_levels[30]	auto[0]	216379	1			T5	31		T6	203		T36	55
all_levels[30]	auto[1]	15	1			T38	1		T32	1		T50	1
all_levels[31]	auto[0]	537001	1			T5	628		T6	288		T36	1062
all_levels[31]	auto[1]	20	1			T290	2		T143	1		T171	1
all_levels[32]	auto[0]	12609922	1			T5	14503		T6	2543		T12	4
all_levels[32]	auto[1]	545	1			T5	1		T33	1		T16	1