Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	832	1			T6	7		T16	4		T14	11
all_values[1]	832	1			T6	7		T16	4		T14	11
all_values[2]	832	1			T6	7		T16	4		T14	11
all_values[3]	832	1			T6	7		T16	4		T14	11
all_values[4]	832	1			T6	7		T16	4		T14	11
all_values[5]	832	1			T6	7		T16	4		T14	11
all_values[6]	832	1			T6	7		T16	4		T14	11
all_values[7]	832	1			T6	7		T16	4		T14	11
all_values[8]	832	1			T6	7		T16	4		T14	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3999

1

T6

40

T16

13

T14

49

auto[1]

3489

1

T6

23

T16

23

T14

50

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2427

1

T6

20

T16

11

T14

28

auto[1]

5061

1

T6

43

T16

25

T14

71

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4417

1

T6

37

T16

23

T14

48

auto[1]

3071

1

T6

26

T16

13

T14

51

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	250	1			T6	3		T14	2		T116	1
all_values[0]	auto[0]	auto[1]	auto[1]	243	1			T6	2		T16	3		T14	3
all_values[0]	auto[1]	auto[0]	auto[1]	174	1			T6	2		T14	3		T30	2
all_values[0]	auto[1]	auto[1]	auto[1]	165	1			T16	1		T14	3		T28	1
all_values[1]	auto[0]	auto[0]	auto[0]	258	1			T6	4		T14	1		T28	2
all_values[1]	auto[0]	auto[1]	auto[0]	221	1			T6	1		T16	1		T14	3
all_values[1]	auto[1]	auto[0]	auto[1]	196	1			T6	1		T16	2		T14	6
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T6	1		T16	1		T14	1
all_values[2]	auto[0]	auto[0]	auto[0]	198	1			T6	2		T16	1		T14	1
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T6	1		T117	1		T46	2
all_values[2]	auto[0]	auto[1]	auto[0]	122	1			T6	1		T16	1		T14	2
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T6	1		T16	1		T14	1
all_values[2]	auto[1]	auto[0]	auto[1]	203	1			T6	1		T16	1		T14	2
all_values[2]	auto[1]	auto[1]	auto[1]	148	1			T6	1		T14	5		T28	1
all_values[3]	auto[0]	auto[0]	auto[0]	178	1			T14	1		T28	1		T116	3
all_values[3]	auto[0]	auto[0]	auto[1]	90	1			T6	1		T16	1		T14	4
all_values[3]	auto[0]	auto[1]	auto[0]	137	1			T6	2		T28	2		T116	1
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T16	1		T30	1		T31	4
all_values[3]	auto[1]	auto[0]	auto[1]	180	1			T6	1		T16	1		T14	6
all_values[3]	auto[1]	auto[1]	auto[1]	161	1			T6	3		T16	1		T28	1
all_values[4]	auto[0]	auto[0]	auto[0]	176	1			T6	2		T14	1		T28	1
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T16	1		T30	1		T118	2
all_values[4]	auto[0]	auto[1]	auto[0]	158	1			T6	1		T16	1		T14	2
all_values[4]	auto[0]	auto[1]	auto[1]	84	1			T6	1		T16	1		T14	1
all_values[4]	auto[1]	auto[0]	auto[1]	157	1			T6	2		T14	1		T116	2
all_values[4]	auto[1]	auto[1]	auto[1]	170	1			T6	1		T16	1		T14	6
all_values[5]	auto[0]	auto[0]	auto[0]	185	1			T6	2		T14	2		T28	2
all_values[5]	auto[0]	auto[0]	auto[1]	75	1			T30	3		T118	1		T117	1
all_values[5]	auto[0]	auto[1]	auto[0]	165	1			T6	3		T16	3		T14	3
all_values[5]	auto[0]	auto[1]	auto[1]	82	1			T14	1		T116	2		T46	3
all_values[5]	auto[1]	auto[0]	auto[1]	177	1			T6	1		T16	1		T14	1
all_values[5]	auto[1]	auto[1]	auto[1]	148	1			T6	1		T14	4		T28	1
all_values[6]	auto[0]	auto[0]	auto[0]	170	1			T6	2		T16	1		T14	4
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T6	2		T16	1		T14	1
all_values[6]	auto[0]	auto[1]	auto[0]	156	1			T16	1		T14	3		T28	1
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T28	1		T116	1		T118	2
all_values[6]	auto[1]	auto[0]	auto[1]	178	1			T6	3		T14	1		T28	1
all_values[6]	auto[1]	auto[1]	auto[1]	163	1			T16	1		T14	2		T116	1
all_values[7]	auto[0]	auto[0]	auto[0]	171	1			T14	3		T28	1		T30	2
all_values[7]	auto[0]	auto[0]	auto[1]	84	1			T16	1		T14	1		T30	1
all_values[7]	auto[0]	auto[1]	auto[0]	132	1			T16	2		T14	2		T28	1
all_values[7]	auto[0]	auto[1]	auto[1]	93	1			T6	2		T116	1		T31	2
all_values[7]	auto[1]	auto[0]	auto[1]	219	1			T6	4		T14	4		T28	2
all_values[7]	auto[1]	auto[1]	auto[1]	133	1			T6	1		T16	1		T14	1
all_values[8]	auto[0]	auto[0]	auto[1]	239	1			T6	3		T16	1		T14	2
all_values[8]	auto[0]	auto[1]	auto[1]	251	1			T6	1		T16	1		T14	4
all_values[8]	auto[1]	auto[0]	auto[1]	191	1			T6	3		T16	1		T14	2
all_values[8]	auto[1]	auto[1]	auto[1]	151	1			T16	1		T14	3		T30	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal