Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total test records in report: 1312
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T1255 /workspace/coverage/cover_reg_top/11.uart_csr_rw.403252029 Jul 20 05:45:39 PM PDT 24 Jul 20 05:45:40 PM PDT 24 28895510 ps
T1256 /workspace/coverage/cover_reg_top/4.uart_intr_test.1905051039 Jul 20 05:45:36 PM PDT 24 Jul 20 05:45:38 PM PDT 24 18044031 ps
T1257 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1855688227 Jul 20 05:45:40 PM PDT 24 Jul 20 05:45:42 PM PDT 24 90412334 ps
T1258 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3188221228 Jul 20 05:45:44 PM PDT 24 Jul 20 05:45:45 PM PDT 24 17025926 ps
T1259 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3563347311 Jul 20 05:45:52 PM PDT 24 Jul 20 05:45:57 PM PDT 24 316334812 ps
T1260 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2337802897 Jul 20 05:46:00 PM PDT 24 Jul 20 05:46:05 PM PDT 24 28922667 ps
T90 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3308869535 Jul 20 05:45:28 PM PDT 24 Jul 20 05:45:29 PM PDT 24 93767254 ps
T1261 /workspace/coverage/cover_reg_top/44.uart_intr_test.2209517905 Jul 20 05:45:58 PM PDT 24 Jul 20 05:46:01 PM PDT 24 27192353 ps
T1262 /workspace/coverage/cover_reg_top/22.uart_intr_test.1130592550 Jul 20 05:45:57 PM PDT 24 Jul 20 05:46:00 PM PDT 24 13073222 ps
T1263 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2188863073 Jul 20 05:45:37 PM PDT 24 Jul 20 05:45:38 PM PDT 24 63212372 ps
T1264 /workspace/coverage/cover_reg_top/16.uart_intr_test.746343226 Jul 20 05:45:49 PM PDT 24 Jul 20 05:45:54 PM PDT 24 55894020 ps
T1265 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.712338600 Jul 20 05:45:53 PM PDT 24 Jul 20 05:45:58 PM PDT 24 93015722 ps
T1266 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2400221958 Jul 20 05:46:02 PM PDT 24 Jul 20 05:46:10 PM PDT 24 35413888 ps
T1267 /workspace/coverage/cover_reg_top/25.uart_intr_test.3452940764 Jul 20 05:45:57 PM PDT 24 Jul 20 05:46:00 PM PDT 24 12115806 ps
T1268 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2959972064 Jul 20 05:45:47 PM PDT 24 Jul 20 05:45:51 PM PDT 24 25297897 ps
T1269 /workspace/coverage/cover_reg_top/3.uart_tl_errors.910600106 Jul 20 05:45:33 PM PDT 24 Jul 20 05:45:35 PM PDT 24 420651873 ps
T1270 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2439607057 Jul 20 05:45:31 PM PDT 24 Jul 20 05:45:33 PM PDT 24 44882158 ps
T1271 /workspace/coverage/cover_reg_top/32.uart_intr_test.607203797 Jul 20 05:45:54 PM PDT 24 Jul 20 05:45:58 PM PDT 24 37398077 ps
T1272 /workspace/coverage/cover_reg_top/49.uart_intr_test.3820546542 Jul 20 05:45:52 PM PDT 24 Jul 20 05:46:00 PM PDT 24 20508230 ps
T1273 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1067078317 Jul 20 05:45:58 PM PDT 24 Jul 20 05:46:01 PM PDT 24 22071168 ps
T1274 /workspace/coverage/cover_reg_top/19.uart_intr_test.4073362239 Jul 20 05:46:00 PM PDT 24 Jul 20 05:46:06 PM PDT 24 47039589 ps
T1275 /workspace/coverage/cover_reg_top/10.uart_tl_errors.877655757 Jul 20 05:45:46 PM PDT 24 Jul 20 05:45:51 PM PDT 24 1931055079 ps
T1276 /workspace/coverage/cover_reg_top/3.uart_intr_test.1693051842 Jul 20 05:45:42 PM PDT 24 Jul 20 05:45:44 PM PDT 24 29368812 ps
T1277 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3655995319 Jul 20 05:45:56 PM PDT 24 Jul 20 05:46:00 PM PDT 24 51413706 ps
T1278 /workspace/coverage/cover_reg_top/12.uart_intr_test.768385760 Jul 20 05:45:55 PM PDT 24 Jul 20 05:45:59 PM PDT 24 33548889 ps
T1279 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3818221078 Jul 20 05:45:48 PM PDT 24 Jul 20 05:45:53 PM PDT 24 342740401 ps
T1280 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2109380181 Jul 20 05:46:01 PM PDT 24 Jul 20 05:46:09 PM PDT 24 105665681 ps
T1281 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3656736838 Jul 20 05:45:49 PM PDT 24 Jul 20 05:45:54 PM PDT 24 72245216 ps
T1282 /workspace/coverage/cover_reg_top/11.uart_intr_test.4197133735 Jul 20 05:45:51 PM PDT 24 Jul 20 05:45:55 PM PDT 24 17604538 ps
T1283 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4057489438 Jul 20 05:45:49 PM PDT 24 Jul 20 05:45:59 PM PDT 24 23727212 ps
T1284 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3874551415 Jul 20 05:45:54 PM PDT 24 Jul 20 05:45:58 PM PDT 24 17422092 ps
T1285 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2948053904 Jul 20 05:45:48 PM PDT 24 Jul 20 05:45:53 PM PDT 24 44389340 ps
T1286 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.519287581 Jul 20 05:45:35 PM PDT 24 Jul 20 05:45:37 PM PDT 24 24212424 ps
T1287 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4126904734 Jul 20 05:45:35 PM PDT 24 Jul 20 05:45:37 PM PDT 24 23353530 ps
T1288 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.937482458 Jul 20 05:46:01 PM PDT 24 Jul 20 05:46:09 PM PDT 24 31900933 ps
T1289 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2130255031 Jul 20 05:45:47 PM PDT 24 Jul 20 05:45:51 PM PDT 24 132206260 ps
T1290 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3149071217 Jul 20 05:45:53 PM PDT 24 Jul 20 05:45:59 PM PDT 24 968082071 ps
T1291 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1341384312 Jul 20 05:46:02 PM PDT 24 Jul 20 05:46:11 PM PDT 24 424221252 ps
T1292 /workspace/coverage/cover_reg_top/18.uart_intr_test.4251459194 Jul 20 05:45:51 PM PDT 24 Jul 20 05:45:56 PM PDT 24 106850091 ps
T1293 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2605245976 Jul 20 05:45:34 PM PDT 24 Jul 20 05:45:35 PM PDT 24 230406186 ps
T58 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.728780325 Jul 20 05:45:36 PM PDT 24 Jul 20 05:45:38 PM PDT 24 38032193 ps
T1294 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1639073337 Jul 20 05:45:44 PM PDT 24 Jul 20 05:45:46 PM PDT 24 14933857 ps
T59 /workspace/coverage/cover_reg_top/2.uart_csr_rw.41175116 Jul 20 05:45:33 PM PDT 24 Jul 20 05:45:34 PM PDT 24 15030349 ps
T1295 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3890679727 Jul 20 05:45:34 PM PDT 24 Jul 20 05:45:36 PM PDT 24 24440989 ps
T1296 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3112154543 Jul 20 05:46:00 PM PDT 24 Jul 20 05:46:06 PM PDT 24 35263392 ps
T1297 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2828655049 Jul 20 05:45:47 PM PDT 24 Jul 20 05:45:50 PM PDT 24 15262659 ps
T1298 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2846781761 Jul 20 05:45:31 PM PDT 24 Jul 20 05:45:33 PM PDT 24 41255957 ps
T1299 /workspace/coverage/cover_reg_top/42.uart_intr_test.3322933239 Jul 20 05:46:01 PM PDT 24 Jul 20 05:46:09 PM PDT 24 14053844 ps
T1300 /workspace/coverage/cover_reg_top/43.uart_intr_test.2623678846 Jul 20 05:46:01 PM PDT 24 Jul 20 05:46:07 PM PDT 24 29652638 ps
T1301 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4275507836 Jul 20 05:45:48 PM PDT 24 Jul 20 05:45:52 PM PDT 24 71342199 ps
T60 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1986044685 Jul 20 05:45:38 PM PDT 24 Jul 20 05:45:38 PM PDT 24 17231414 ps
T1302 /workspace/coverage/cover_reg_top/6.uart_intr_test.3289334504 Jul 20 05:45:57 PM PDT 24 Jul 20 05:46:00 PM PDT 24 24505712 ps
T1303 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2846953035 Jul 20 05:46:01 PM PDT 24 Jul 20 05:46:09 PM PDT 24 46174939 ps
T1304 /workspace/coverage/cover_reg_top/20.uart_intr_test.1201716159 Jul 20 05:45:49 PM PDT 24 Jul 20 05:45:54 PM PDT 24 44172639 ps
T1305 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1026258973 Jul 20 05:45:46 PM PDT 24 Jul 20 05:45:50 PM PDT 24 50861151 ps
T1306 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3660823269 Jul 20 05:45:31 PM PDT 24 Jul 20 05:45:32 PM PDT 24 67887017 ps
T1307 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3944193707 Jul 20 05:45:34 PM PDT 24 Jul 20 05:45:35 PM PDT 24 50091218 ps
T1308 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3316865078 Jul 20 05:45:42 PM PDT 24 Jul 20 05:45:43 PM PDT 24 68653833 ps
T1309 /workspace/coverage/cover_reg_top/21.uart_intr_test.585060920 Jul 20 05:45:50 PM PDT 24 Jul 20 05:45:55 PM PDT 24 34750443 ps
T1310 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3400145658 Jul 20 05:45:47 PM PDT 24 Jul 20 05:45:50 PM PDT 24 197981147 ps
T1311 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.722008755 Jul 20 05:45:47 PM PDT 24 Jul 20 05:45:50 PM PDT 24 48058705 ps
T1312 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.922455335 Jul 20 05:45:41 PM PDT 24 Jul 20 05:45:43 PM PDT 24 181402519 ps

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.532225722
Short name T6
Test name
Test status
Simulation time 79530359772 ps
CPU time 156.09 seconds
Started Jul 20 06:08:26 PM PDT 24
Finished Jul 20 06:11:03 PM PDT 24
Peak memory 216636 kb
Host smart-0ae05c6e-b54d-45f9-9bbd-2f78f8c7376a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532225722 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.532225722
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.868900913
Short name T46
Test name
Test status
Simulation time 613702156998 ps
CPU time 1794.61 seconds
Started Jul 20 06:08:26 PM PDT 24
Finished Jul 20 06:38:22 PM PDT 24
Peak memory 216860 kb
Host smart-734a6c49-25e8-49d8-a9cf-98aa4b56c8e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868900913 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.868900913
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1152445263
Short name T16
Test name
Test status
Simulation time 90845856389 ps
CPU time 774.38 seconds
Started Jul 20 06:08:20 PM PDT 24
Finished Jul 20 06:21:15 PM PDT 24
Peak memory 224972 kb
Host smart-149f7ccd-bb6c-47de-8563-8d9f247b1455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152445263 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1152445263
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1191983087
Short name T3
Test name
Test status
Simulation time 35276936951 ps
CPU time 19.19 seconds
Started Jul 20 06:08:40 PM PDT 24
Finished Jul 20 06:09:00 PM PDT 24
Peak memory 200168 kb
Host smart-17b177cc-3569-4ede-a825-3dbafacf304f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191983087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1191983087
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3676506629
Short name T29
Test name
Test status
Simulation time 171143190670 ps
CPU time 919.33 seconds
Started Jul 20 06:08:08 PM PDT 24
Finished Jul 20 06:23:28 PM PDT 24
Peak memory 230508 kb
Host smart-8bf150cf-227e-4dd1-b784-2df6ee17a9aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676506629 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3676506629
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3179073366
Short name T14
Test name
Test status
Simulation time 221687873870 ps
CPU time 708.55 seconds
Started Jul 20 06:08:28 PM PDT 24
Finished Jul 20 06:20:17 PM PDT 24
Peak memory 216808 kb
Host smart-37ade010-70ad-4e7e-a30e-4e0216a8f49f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179073366 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3179073366
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.928570085
Short name T48
Test name
Test status
Simulation time 84220948954 ps
CPU time 1186.04 seconds
Started Jul 20 06:08:34 PM PDT 24
Finished Jul 20 06:28:20 PM PDT 24
Peak memory 231432 kb
Host smart-5e0da870-b59d-44fd-a626-b21b0ebed55b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928570085 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.928570085
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1505731416
Short name T275
Test name
Test status
Simulation time 249690470605 ps
CPU time 145.23 seconds
Started Jul 20 06:07:16 PM PDT 24
Finished Jul 20 06:09:42 PM PDT 24
Peak memory 200136 kb
Host smart-ecd50dea-176d-40df-a9ab-e1a28eb907dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505731416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1505731416
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2869134049
Short name T27
Test name
Test status
Simulation time 130866447534 ps
CPU time 396.03 seconds
Started Jul 20 06:07:11 PM PDT 24
Finished Jul 20 06:13:48 PM PDT 24
Peak memory 226056 kb
Host smart-eab3aca9-aa29-4416-940c-d861386e51bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869134049 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2869134049
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3286894649
Short name T87
Test name
Test status
Simulation time 103488436 ps
CPU time 0.99 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:06 PM PDT 24
Peak memory 199736 kb
Host smart-9df14f04-0db7-43a1-8842-3c816ff33709
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286894649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3286894649
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.4234006140
Short name T28
Test name
Test status
Simulation time 83448848050 ps
CPU time 519.37 seconds
Started Jul 20 06:07:44 PM PDT 24
Finished Jul 20 06:16:24 PM PDT 24
Peak memory 225004 kb
Host smart-d15a708f-ed90-4cf3-84ba-6200586f6ebc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234006140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.4234006140
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_alert_test.3475967684
Short name T354
Test name
Test status
Simulation time 15606053 ps
CPU time 0.57 seconds
Started Jul 20 06:02:10 PM PDT 24
Finished Jul 20 06:02:11 PM PDT 24
Peak memory 195704 kb
Host smart-2f1631c4-bc83-42a2-a8cf-655ea92ed171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475967684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3475967684
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.473909941
Short name T35
Test name
Test status
Simulation time 186627285281 ps
CPU time 226.83 seconds
Started Jul 20 06:08:28 PM PDT 24
Finished Jul 20 06:12:15 PM PDT 24
Peak memory 200180 kb
Host smart-097a353e-7dc1-4ff3-92d8-592f66385b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473909941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.473909941
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1416753417
Short name T136
Test name
Test status
Simulation time 93158616539 ps
CPU time 11.57 seconds
Started Jul 20 06:07:44 PM PDT 24
Finished Jul 20 06:07:55 PM PDT 24
Peak memory 200072 kb
Host smart-3a2b5867-dad9-426c-a6b8-3014952a207d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416753417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1416753417
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.639666737
Short name T2
Test name
Test status
Simulation time 416342242346 ps
CPU time 82.87 seconds
Started Jul 20 06:08:52 PM PDT 24
Finished Jul 20 06:10:16 PM PDT 24
Peak memory 200132 kb
Host smart-9ebc78d3-3d6d-4771-9212-08b3b725eb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639666737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.639666737
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2099369023
Short name T32
Test name
Test status
Simulation time 180062073052 ps
CPU time 506.41 seconds
Started Jul 20 06:04:17 PM PDT 24
Finished Jul 20 06:12:44 PM PDT 24
Peak memory 225028 kb
Host smart-7e743ea4-d7eb-443c-8611-63ce12469cb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099369023 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2099369023
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2050854336
Short name T94
Test name
Test status
Simulation time 1131289888 ps
CPU time 0.82 seconds
Started Jul 20 06:02:04 PM PDT 24
Finished Jul 20 06:02:06 PM PDT 24
Peak memory 218392 kb
Host smart-c1be3730-47dd-4daf-8d12-11786c7bbc1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050854336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2050854336
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/23.uart_stress_all.1673004975
Short name T143
Test name
Test status
Simulation time 118416106932 ps
CPU time 52.4 seconds
Started Jul 20 06:05:17 PM PDT 24
Finished Jul 20 06:06:10 PM PDT 24
Peak memory 200120 kb
Host smart-59a4b892-5658-435b-8a6a-c61e38698af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673004975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1673004975
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3078578638
Short name T57
Test name
Test status
Simulation time 13681003 ps
CPU time 0.64 seconds
Started Jul 20 05:45:34 PM PDT 24
Finished Jul 20 05:45:35 PM PDT 24
Peak memory 196412 kb
Host smart-2afac873-2809-4544-b155-64f6201748bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078578638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3078578638
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1062385778
Short name T171
Test name
Test status
Simulation time 190754850483 ps
CPU time 84.79 seconds
Started Jul 20 06:02:03 PM PDT 24
Finished Jul 20 06:03:28 PM PDT 24
Peak memory 200200 kb
Host smart-d2fbac40-1319-44ad-9eeb-be4cf2937fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062385778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1062385778
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3414528326
Short name T111
Test name
Test status
Simulation time 85859235034 ps
CPU time 69.77 seconds
Started Jul 20 06:09:00 PM PDT 24
Finished Jul 20 06:10:10 PM PDT 24
Peak memory 200196 kb
Host smart-774956bf-4a17-4720-917f-ce17c59ad32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414528326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3414528326
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1827179955
Short name T270
Test name
Test status
Simulation time 132638336481 ps
CPU time 126.56 seconds
Started Jul 20 06:05:30 PM PDT 24
Finished Jul 20 06:07:37 PM PDT 24
Peak memory 200180 kb
Host smart-24f402bb-0630-4bfc-b787-951fbc793e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827179955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1827179955
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.4192546856
Short name T38
Test name
Test status
Simulation time 67518768348 ps
CPU time 164.53 seconds
Started Jul 20 06:03:30 PM PDT 24
Finished Jul 20 06:06:15 PM PDT 24
Peak memory 200096 kb
Host smart-dd43daf5-32ba-4abc-965d-e2f751cd3c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192546856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.4192546856
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2674434123
Short name T262
Test name
Test status
Simulation time 263491718954 ps
CPU time 212.19 seconds
Started Jul 20 06:07:14 PM PDT 24
Finished Jul 20 06:10:47 PM PDT 24
Peak memory 200448 kb
Host smart-9717e381-add7-4657-a52f-4a13632592c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674434123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2674434123
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1718030089
Short name T69
Test name
Test status
Simulation time 64461474954 ps
CPU time 304.97 seconds
Started Jul 20 06:06:45 PM PDT 24
Finished Jul 20 06:11:51 PM PDT 24
Peak memory 216572 kb
Host smart-b511911c-f40f-4d2b-b572-3c07acad57c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718030089 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1718030089
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3262563256
Short name T140
Test name
Test status
Simulation time 171523662772 ps
CPU time 152.78 seconds
Started Jul 20 06:05:10 PM PDT 24
Finished Jul 20 06:07:44 PM PDT 24
Peak memory 200132 kb
Host smart-9b2f19f7-8dc0-4c31-8d60-cff6263a1664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262563256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3262563256
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1234653462
Short name T168
Test name
Test status
Simulation time 141391251664 ps
CPU time 102.67 seconds
Started Jul 20 06:08:36 PM PDT 24
Finished Jul 20 06:10:20 PM PDT 24
Peak memory 200144 kb
Host smart-35d8ea1c-0d31-417a-8bad-b798347049d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234653462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1234653462
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.4157023502
Short name T125
Test name
Test status
Simulation time 24465116729 ps
CPU time 37.98 seconds
Started Jul 20 06:09:38 PM PDT 24
Finished Jul 20 06:10:17 PM PDT 24
Peak memory 200152 kb
Host smart-60d09fa2-f5c5-4338-8ebb-106802a03a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157023502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.4157023502
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all.183928232
Short name T116
Test name
Test status
Simulation time 180332487387 ps
CPU time 1278.41 seconds
Started Jul 20 06:03:18 PM PDT 24
Finished Jul 20 06:24:37 PM PDT 24
Peak memory 208604 kb
Host smart-7cf021ce-8a85-4689-a61c-803e0eec3d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183928232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.183928232
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1502747614
Short name T316
Test name
Test status
Simulation time 122977326413 ps
CPU time 479.9 seconds
Started Jul 20 06:05:18 PM PDT 24
Finished Jul 20 06:13:19 PM PDT 24
Peak memory 200068 kb
Host smart-821633e4-d91c-4315-adcd-3ec0936dff8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502747614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1502747614
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3263616691
Short name T150
Test name
Test status
Simulation time 74380856339 ps
CPU time 29.84 seconds
Started Jul 20 06:09:39 PM PDT 24
Finished Jul 20 06:10:09 PM PDT 24
Peak memory 200196 kb
Host smart-45bc3e82-4abd-4a29-9636-7a86adfd65fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263616691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3263616691
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.4109695979
Short name T42
Test name
Test status
Simulation time 91115477879 ps
CPU time 33.66 seconds
Started Jul 20 06:07:16 PM PDT 24
Finished Jul 20 06:07:50 PM PDT 24
Peak memory 200036 kb
Host smart-347727d1-8828-4d33-862b-920bc0f11293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109695979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.4109695979
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1205014656
Short name T519
Test name
Test status
Simulation time 200935484043 ps
CPU time 665.27 seconds
Started Jul 20 06:03:20 PM PDT 24
Finished Jul 20 06:14:26 PM PDT 24
Peak memory 216648 kb
Host smart-cbaf09ea-9dd0-4ead-ab22-c7bbe828c2ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205014656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1205014656
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.361296341
Short name T85
Test name
Test status
Simulation time 95240109 ps
CPU time 1.34 seconds
Started Jul 20 05:45:42 PM PDT 24
Finished Jul 20 05:45:45 PM PDT 24
Peak memory 200252 kb
Host smart-b17f9435-ba9b-4fef-ad9e-98ef9c00bff6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361296341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.361296341
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3886226368
Short name T155
Test name
Test status
Simulation time 64529801712 ps
CPU time 26.83 seconds
Started Jul 20 06:04:17 PM PDT 24
Finished Jul 20 06:04:45 PM PDT 24
Peak memory 200200 kb
Host smart-59c6d858-6a91-4280-944e-1289fb921106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886226368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3886226368
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.229107337
Short name T145
Test name
Test status
Simulation time 38000368541 ps
CPU time 52.42 seconds
Started Jul 20 06:09:31 PM PDT 24
Finished Jul 20 06:10:24 PM PDT 24
Peak memory 200168 kb
Host smart-699b7260-2a16-43c9-88ca-8d5905621b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229107337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.229107337
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3785986612
Short name T174
Test name
Test status
Simulation time 480117528702 ps
CPU time 98.4 seconds
Started Jul 20 06:06:16 PM PDT 24
Finished Jul 20 06:07:54 PM PDT 24
Peak memory 200120 kb
Host smart-1acc345f-1616-4e59-bcfc-4ec89d81bf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785986612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3785986612
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.535966238
Short name T502
Test name
Test status
Simulation time 71062982836 ps
CPU time 44.47 seconds
Started Jul 20 06:08:09 PM PDT 24
Finished Jul 20 06:08:54 PM PDT 24
Peak memory 200128 kb
Host smart-d0724606-1832-46b4-9725-39c9f8056c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535966238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.535966238
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.4006939066
Short name T133
Test name
Test status
Simulation time 72380344035 ps
CPU time 37.89 seconds
Started Jul 20 06:09:31 PM PDT 24
Finished Jul 20 06:10:09 PM PDT 24
Peak memory 200124 kb
Host smart-3c93e385-0b6d-4d7e-accb-ade5bf3c8f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006939066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.4006939066
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all.2562307113
Short name T204
Test name
Test status
Simulation time 210496399887 ps
CPU time 336.06 seconds
Started Jul 20 06:04:52 PM PDT 24
Finished Jul 20 06:10:30 PM PDT 24
Peak memory 200180 kb
Host smart-fbc134ef-ed8c-4325-88e8-45db3b3de850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562307113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2562307113
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1475905805
Short name T806
Test name
Test status
Simulation time 123509086561 ps
CPU time 100.77 seconds
Started Jul 20 06:07:51 PM PDT 24
Finished Jul 20 06:09:32 PM PDT 24
Peak memory 200156 kb
Host smart-b5c629d3-e2f7-437f-837a-f0256c6362d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475905805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1475905805
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1977338977
Short name T180
Test name
Test status
Simulation time 172575097277 ps
CPU time 1735.09 seconds
Started Jul 20 06:08:18 PM PDT 24
Finished Jul 20 06:37:13 PM PDT 24
Peak memory 224896 kb
Host smart-0046d44d-96b2-48cb-b81a-6c1835a04861
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977338977 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1977338977
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3074123341
Short name T173
Test name
Test status
Simulation time 38848108937 ps
CPU time 20.72 seconds
Started Jul 20 06:03:51 PM PDT 24
Finished Jul 20 06:04:12 PM PDT 24
Peak memory 200132 kb
Host smart-0310dc81-4915-467d-b6d7-43663f7ce9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074123341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3074123341
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2314518696
Short name T226
Test name
Test status
Simulation time 162843450414 ps
CPU time 278.53 seconds
Started Jul 20 06:08:50 PM PDT 24
Finished Jul 20 06:13:30 PM PDT 24
Peak memory 200124 kb
Host smart-c80a2789-4623-4475-adf7-c24efad469de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314518696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2314518696
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3651048025
Short name T308
Test name
Test status
Simulation time 67160569360 ps
CPU time 115.34 seconds
Started Jul 20 06:04:33 PM PDT 24
Finished Jul 20 06:06:29 PM PDT 24
Peak memory 200188 kb
Host smart-da3681ac-e463-4962-ae52-deb689ad43c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651048025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3651048025
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/18.uart_stress_all.4116728899
Short name T251
Test name
Test status
Simulation time 278894650978 ps
CPU time 107.82 seconds
Started Jul 20 06:04:43 PM PDT 24
Finished Jul 20 06:06:31 PM PDT 24
Peak memory 200188 kb
Host smart-c091c5d8-3aa0-4cf7-8804-c913504777a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116728899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.4116728899
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2002068343
Short name T165
Test name
Test status
Simulation time 20965990077 ps
CPU time 4.86 seconds
Started Jul 20 06:09:33 PM PDT 24
Finished Jul 20 06:09:38 PM PDT 24
Peak memory 199988 kb
Host smart-d574c9bc-76e5-42d3-827d-88c99e38ddc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002068343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2002068343
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.470172115
Short name T134
Test name
Test status
Simulation time 26057756216 ps
CPU time 24.31 seconds
Started Jul 20 06:07:25 PM PDT 24
Finished Jul 20 06:07:51 PM PDT 24
Peak memory 200132 kb
Host smart-f6d705ca-05da-40b9-82ea-6c346d619597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470172115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.470172115
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3914637934
Short name T188
Test name
Test status
Simulation time 27846675942 ps
CPU time 43.64 seconds
Started Jul 20 06:09:00 PM PDT 24
Finished Jul 20 06:09:44 PM PDT 24
Peak memory 200188 kb
Host smart-c0f9e8c8-674b-444f-a5d1-05db0603354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914637934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3914637934
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1703603757
Short name T200
Test name
Test status
Simulation time 15298461343 ps
CPU time 23.21 seconds
Started Jul 20 06:09:01 PM PDT 24
Finished Jul 20 06:09:25 PM PDT 24
Peak memory 200196 kb
Host smart-4078c9b3-db5e-4f67-a688-13049be85c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703603757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1703603757
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3998153685
Short name T210
Test name
Test status
Simulation time 26135295051 ps
CPU time 43.24 seconds
Started Jul 20 06:09:07 PM PDT 24
Finished Jul 20 06:09:51 PM PDT 24
Peak memory 200136 kb
Host smart-14e711b3-a334-4f74-a50e-511a580906ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998153685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3998153685
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.246714083
Short name T217
Test name
Test status
Simulation time 26253047846 ps
CPU time 16.77 seconds
Started Jul 20 06:09:49 PM PDT 24
Finished Jul 20 06:10:07 PM PDT 24
Peak memory 200192 kb
Host smart-06c19c95-dc45-4a44-84cc-0283b49473dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246714083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.246714083
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2405195022
Short name T243
Test name
Test status
Simulation time 82565262303 ps
CPU time 98.97 seconds
Started Jul 20 06:07:58 PM PDT 24
Finished Jul 20 06:09:38 PM PDT 24
Peak memory 200112 kb
Host smart-95774345-276f-4ec7-97c3-371011236dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405195022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2405195022
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1602256467
Short name T12
Test name
Test status
Simulation time 120694346822 ps
CPU time 70 seconds
Started Jul 20 06:03:19 PM PDT 24
Finished Jul 20 06:04:29 PM PDT 24
Peak memory 200128 kb
Host smart-ea85d099-387a-4b84-b1eb-5a607d59272e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602256467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1602256467
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3468112294
Short name T323
Test name
Test status
Simulation time 257415665588 ps
CPU time 899.34 seconds
Started Jul 20 06:03:28 PM PDT 24
Finished Jul 20 06:18:28 PM PDT 24
Peak memory 225084 kb
Host smart-ead680e7-f9f5-4d4b-9b07-bed9480aaa11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468112294 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3468112294
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1491074510
Short name T203
Test name
Test status
Simulation time 16440628242 ps
CPU time 29.89 seconds
Started Jul 20 06:08:38 PM PDT 24
Finished Jul 20 06:09:08 PM PDT 24
Peak memory 200012 kb
Host smart-068ddb49-37d2-4dcc-9f86-129dfca3a142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491074510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1491074510
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3073508185
Short name T163
Test name
Test status
Simulation time 64986820802 ps
CPU time 24.36 seconds
Started Jul 20 06:08:40 PM PDT 24
Finished Jul 20 06:09:06 PM PDT 24
Peak memory 200104 kb
Host smart-59fe42b2-342e-494b-bc56-86eb0410b7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073508185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3073508185
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.84907093
Short name T980
Test name
Test status
Simulation time 119355704418 ps
CPU time 190.31 seconds
Started Jul 20 06:08:36 PM PDT 24
Finished Jul 20 06:11:46 PM PDT 24
Peak memory 200132 kb
Host smart-ca9ac406-ca80-4035-85a1-f2f47cfdda96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84907093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.84907093
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.844827589
Short name T158
Test name
Test status
Simulation time 147392793379 ps
CPU time 53.81 seconds
Started Jul 20 06:08:43 PM PDT 24
Finished Jul 20 06:09:38 PM PDT 24
Peak memory 200112 kb
Host smart-ab143bca-f99a-4a5c-9177-b3b083a0e46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844827589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.844827589
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2276534356
Short name T212
Test name
Test status
Simulation time 72118957967 ps
CPU time 126.54 seconds
Started Jul 20 06:08:46 PM PDT 24
Finished Jul 20 06:10:53 PM PDT 24
Peak memory 200076 kb
Host smart-ffdc4ad7-175d-4892-a1c7-a5367112b3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276534356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2276534356
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3615691613
Short name T225
Test name
Test status
Simulation time 148438773085 ps
CPU time 34.62 seconds
Started Jul 20 06:04:07 PM PDT 24
Finished Jul 20 06:04:43 PM PDT 24
Peak memory 200120 kb
Host smart-395e1760-09f7-4281-b035-31462dd58525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615691613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3615691613
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3890792088
Short name T205
Test name
Test status
Simulation time 32126010957 ps
CPU time 16.18 seconds
Started Jul 20 06:08:54 PM PDT 24
Finished Jul 20 06:09:10 PM PDT 24
Peak memory 200120 kb
Host smart-d2a35b01-c7b5-4a07-8e77-b5b5cc159521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890792088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3890792088
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.684649299
Short name T994
Test name
Test status
Simulation time 85808570726 ps
CPU time 138.78 seconds
Started Jul 20 06:08:52 PM PDT 24
Finished Jul 20 06:11:11 PM PDT 24
Peak memory 200200 kb
Host smart-4c91547f-1957-42da-a063-3ec5e0259ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684649299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.684649299
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1573114287
Short name T240
Test name
Test status
Simulation time 51022414639 ps
CPU time 19.24 seconds
Started Jul 20 06:08:57 PM PDT 24
Finished Jul 20 06:09:16 PM PDT 24
Peak memory 200088 kb
Host smart-14b62a88-3cc9-4968-989b-33274551d468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573114287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1573114287
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3533936448
Short name T156
Test name
Test status
Simulation time 30631472272 ps
CPU time 44.69 seconds
Started Jul 20 06:09:03 PM PDT 24
Finished Jul 20 06:09:48 PM PDT 24
Peak memory 200040 kb
Host smart-c358d6de-a534-4ecf-85a3-f2cf03b6a84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533936448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3533936448
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1762172938
Short name T231
Test name
Test status
Simulation time 37256637593 ps
CPU time 26.27 seconds
Started Jul 20 06:09:05 PM PDT 24
Finished Jul 20 06:09:32 PM PDT 24
Peak memory 200096 kb
Host smart-7b024df5-20ec-4e1a-8db5-ae721df97486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762172938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1762172938
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.4164376016
Short name T229
Test name
Test status
Simulation time 31160635015 ps
CPU time 62.36 seconds
Started Jul 20 06:09:22 PM PDT 24
Finished Jul 20 06:10:25 PM PDT 24
Peak memory 200132 kb
Host smart-1e333c3c-3f3f-4dac-a2e3-35641d290ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164376016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.4164376016
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1961764276
Short name T222
Test name
Test status
Simulation time 44825327183 ps
CPU time 17.58 seconds
Started Jul 20 06:09:37 PM PDT 24
Finished Jul 20 06:09:55 PM PDT 24
Peak memory 200076 kb
Host smart-3629ebb8-4934-438e-9cd6-e8b5825e393d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961764276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1961764276
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.653017501
Short name T220
Test name
Test status
Simulation time 21971541662 ps
CPU time 32.31 seconds
Started Jul 20 06:05:44 PM PDT 24
Finished Jul 20 06:06:16 PM PDT 24
Peak memory 200112 kb
Host smart-2a99a1ea-dd5d-443c-8716-1365fbcc058a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653017501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.653017501
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1543895584
Short name T239
Test name
Test status
Simulation time 117852114331 ps
CPU time 107.36 seconds
Started Jul 20 06:09:44 PM PDT 24
Finished Jul 20 06:11:32 PM PDT 24
Peak memory 200124 kb
Host smart-c9f31e41-aace-4d74-aa06-49854e96ea74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543895584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1543895584
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1575663200
Short name T233
Test name
Test status
Simulation time 18482974820 ps
CPU time 34.15 seconds
Started Jul 20 06:09:49 PM PDT 24
Finished Jul 20 06:10:24 PM PDT 24
Peak memory 200196 kb
Host smart-b31fbb0a-1cff-4127-b5ca-6b99546a7bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575663200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1575663200
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2102452814
Short name T232
Test name
Test status
Simulation time 75488512410 ps
CPU time 72.63 seconds
Started Jul 20 06:09:51 PM PDT 24
Finished Jul 20 06:11:04 PM PDT 24
Peak memory 200200 kb
Host smart-27be00ff-bedd-4c8b-b2cd-584817d5774a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102452814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2102452814
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1877398966
Short name T144
Test name
Test status
Simulation time 31235426864 ps
CPU time 25.92 seconds
Started Jul 20 06:06:05 PM PDT 24
Finished Jul 20 06:06:31 PM PDT 24
Peak memory 200104 kb
Host smart-ad36e455-b940-41ca-8b1d-fafdbbd48ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877398966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1877398966
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3122279171
Short name T238
Test name
Test status
Simulation time 62209052792 ps
CPU time 242.13 seconds
Started Jul 20 06:06:08 PM PDT 24
Finished Jul 20 06:10:10 PM PDT 24
Peak memory 213780 kb
Host smart-9ccb27ef-0b02-486e-8fcc-cd76ca863b53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122279171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3122279171
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.19659792
Short name T234
Test name
Test status
Simulation time 22207349691 ps
CPU time 34.04 seconds
Started Jul 20 06:08:10 PM PDT 24
Finished Jul 20 06:08:45 PM PDT 24
Peak memory 199900 kb
Host smart-e446ed31-58e5-4f80-af70-02274796cd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19659792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.19659792
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.4034649578
Short name T170
Test name
Test status
Simulation time 70444788449 ps
CPU time 43.05 seconds
Started Jul 20 06:08:11 PM PDT 24
Finished Jul 20 06:08:55 PM PDT 24
Peak memory 200112 kb
Host smart-f8eceaef-ef27-4148-889f-3def89c402b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034649578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.4034649578
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.4197712773
Short name T242
Test name
Test status
Simulation time 341837959869 ps
CPU time 31.98 seconds
Started Jul 20 06:08:26 PM PDT 24
Finished Jul 20 06:08:58 PM PDT 24
Peak memory 200180 kb
Host smart-3faaf7b3-0ff0-4fd7-a90f-910ac735d97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197712773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.4197712773
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3616437756
Short name T1224
Test name
Test status
Simulation time 59431465 ps
CPU time 0.67 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:47 PM PDT 24
Peak memory 196344 kb
Host smart-a0b03ee0-0510-4622-92c4-38b36f698f64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616437756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3616437756
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1790556099
Short name T1208
Test name
Test status
Simulation time 1878751640 ps
CPU time 1.57 seconds
Started Jul 20 05:45:39 PM PDT 24
Finished Jul 20 05:45:42 PM PDT 24
Peak memory 198852 kb
Host smart-8de7087d-70f5-4c86-8ba0-aa156de54683
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790556099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1790556099
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1639073337
Short name T1294
Test name
Test status
Simulation time 14933857 ps
CPU time 0.57 seconds
Started Jul 20 05:45:44 PM PDT 24
Finished Jul 20 05:45:46 PM PDT 24
Peak memory 196312 kb
Host smart-b7d449db-0b18-4071-ae8b-6ed7b2999c80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639073337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1639073337
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3890679727
Short name T1295
Test name
Test status
Simulation time 24440989 ps
CPU time 1.08 seconds
Started Jul 20 05:45:34 PM PDT 24
Finished Jul 20 05:45:36 PM PDT 24
Peak memory 200988 kb
Host smart-c99485ee-3967-4232-8e84-b2bd15a260af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890679727 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3890679727
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.4199387920
Short name T75
Test name
Test status
Simulation time 91957911 ps
CPU time 0.62 seconds
Started Jul 20 05:45:31 PM PDT 24
Finished Jul 20 05:45:32 PM PDT 24
Peak memory 196380 kb
Host smart-1dafa2b3-c9e7-4204-94fc-96cc339c96e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199387920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.4199387920
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1698815637
Short name T1235
Test name
Test status
Simulation time 33080165 ps
CPU time 0.58 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:49 PM PDT 24
Peak memory 195320 kb
Host smart-cc97b6cb-e5be-4970-ad73-df0873614c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698815637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1698815637
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2846781761
Short name T1298
Test name
Test status
Simulation time 41255957 ps
CPU time 0.61 seconds
Started Jul 20 05:45:31 PM PDT 24
Finished Jul 20 05:45:33 PM PDT 24
Peak memory 196336 kb
Host smart-76cd7948-11ac-4f6a-955f-09e6ce77f4b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846781761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2846781761
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.12508802
Short name T1199
Test name
Test status
Simulation time 100780761 ps
CPU time 1.26 seconds
Started Jul 20 05:45:20 PM PDT 24
Finished Jul 20 05:45:22 PM PDT 24
Peak memory 200976 kb
Host smart-f55d8822-75c6-4abb-86ea-f85cb20e0930
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12508802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.12508802
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1855688227
Short name T1257
Test name
Test status
Simulation time 90412334 ps
CPU time 0.88 seconds
Started Jul 20 05:45:40 PM PDT 24
Finished Jul 20 05:45:42 PM PDT 24
Peak memory 199544 kb
Host smart-53614b46-3f4d-4024-b5f5-acafae30b8fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855688227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1855688227
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2755710704
Short name T1177
Test name
Test status
Simulation time 13050327 ps
CPU time 0.62 seconds
Started Jul 20 05:45:43 PM PDT 24
Finished Jul 20 05:45:45 PM PDT 24
Peak memory 195684 kb
Host smart-8f37087a-800c-4175-b2d2-2de7c57c0491
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755710704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2755710704
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.472752387
Short name T1209
Test name
Test status
Simulation time 228541721 ps
CPU time 2.56 seconds
Started Jul 20 05:45:35 PM PDT 24
Finished Jul 20 05:45:38 PM PDT 24
Peak memory 198660 kb
Host smart-ac1a17fa-809d-474b-b968-439202d80421
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472752387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.472752387
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3944193707
Short name T1307
Test name
Test status
Simulation time 50091218 ps
CPU time 0.61 seconds
Started Jul 20 05:45:34 PM PDT 24
Finished Jul 20 05:45:35 PM PDT 24
Peak memory 196316 kb
Host smart-731b9e52-a177-440c-b2ae-601f61f7dfd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944193707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3944193707
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2188863073
Short name T1263
Test name
Test status
Simulation time 63212372 ps
CPU time 0.69 seconds
Started Jul 20 05:45:37 PM PDT 24
Finished Jul 20 05:45:38 PM PDT 24
Peak memory 198788 kb
Host smart-3a38a0d2-499f-49b8-9e42-3cc1afb37aed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188863073 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2188863073
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.746763580
Short name T83
Test name
Test status
Simulation time 15970255 ps
CPU time 0.62 seconds
Started Jul 20 05:45:35 PM PDT 24
Finished Jul 20 05:45:37 PM PDT 24
Peak memory 196376 kb
Host smart-4d6a09ae-dbbc-4f50-8a3e-59e8e10b81b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746763580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.746763580
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.488939315
Short name T1229
Test name
Test status
Simulation time 31834948 ps
CPU time 0.57 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:52 PM PDT 24
Peak memory 195284 kb
Host smart-009688ad-f997-4bf2-96c4-f8b540639ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488939315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.488939315
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3660823269
Short name T1306
Test name
Test status
Simulation time 67887017 ps
CPU time 0.7 seconds
Started Jul 20 05:45:31 PM PDT 24
Finished Jul 20 05:45:32 PM PDT 24
Peak memory 197932 kb
Host smart-1f5f94c8-9265-480a-81d0-236bdf863700
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660823269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3660823269
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3284762203
Short name T1200
Test name
Test status
Simulation time 230074797 ps
CPU time 2.06 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:49 PM PDT 24
Peak memory 200968 kb
Host smart-959389fc-5a31-4a1f-8ef9-7555c3865fce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284762203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3284762203
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3308869535
Short name T90
Test name
Test status
Simulation time 93767254 ps
CPU time 1.01 seconds
Started Jul 20 05:45:28 PM PDT 24
Finished Jul 20 05:45:29 PM PDT 24
Peak memory 199792 kb
Host smart-58e88b3d-037f-435a-9226-5ae62d48b3e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308869535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3308869535
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4145741221
Short name T1175
Test name
Test status
Simulation time 83061068 ps
CPU time 0.71 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 199480 kb
Host smart-0c8093f1-d975-484f-b0d7-a9f98f2e2ec8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145741221 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.4145741221
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2828655049
Short name T1297
Test name
Test status
Simulation time 15262659 ps
CPU time 0.59 seconds
Started Jul 20 05:45:47 PM PDT 24
Finished Jul 20 05:45:50 PM PDT 24
Peak memory 196388 kb
Host smart-e3de589f-0414-4527-b5de-5ed7b22fc349
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828655049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2828655049
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.510643257
Short name T1243
Test name
Test status
Simulation time 12930694 ps
CPU time 0.57 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:48 PM PDT 24
Peak memory 195304 kb
Host smart-b0ed9043-9d93-4e88-9c7b-56214147bed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510643257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.510643257
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1040516485
Short name T1205
Test name
Test status
Simulation time 22455919 ps
CPU time 0.63 seconds
Started Jul 20 05:45:44 PM PDT 24
Finished Jul 20 05:45:46 PM PDT 24
Peak memory 195496 kb
Host smart-84093fbb-6e2d-49cc-9cc6-f14a880505d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040516485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1040516485
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.877655757
Short name T1275
Test name
Test status
Simulation time 1931055079 ps
CPU time 2.03 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:51 PM PDT 24
Peak memory 200868 kb
Host smart-2320861b-c3cf-4523-91ad-fd151d27769a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877655757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.877655757
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.187690830
Short name T88
Test name
Test status
Simulation time 399529919 ps
CPU time 1.31 seconds
Started Jul 20 05:45:51 PM PDT 24
Finished Jul 20 05:45:56 PM PDT 24
Peak memory 200172 kb
Host smart-072e3867-88a0-471c-835b-2efeb4dfe8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187690830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.187690830
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1477563699
Short name T1213
Test name
Test status
Simulation time 25529655 ps
CPU time 1.09 seconds
Started Jul 20 05:45:52 PM PDT 24
Finished Jul 20 05:45:57 PM PDT 24
Peak memory 201052 kb
Host smart-eaa4a8ec-0247-4037-b2c1-812619ff036f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477563699 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1477563699
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.403252029
Short name T1255
Test name
Test status
Simulation time 28895510 ps
CPU time 0.63 seconds
Started Jul 20 05:45:39 PM PDT 24
Finished Jul 20 05:45:40 PM PDT 24
Peak memory 196288 kb
Host smart-f021251b-3a27-4e0f-b2c3-94a99bc5c94f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403252029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.403252029
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.4197133735
Short name T1282
Test name
Test status
Simulation time 17604538 ps
CPU time 0.6 seconds
Started Jul 20 05:45:51 PM PDT 24
Finished Jul 20 05:45:55 PM PDT 24
Peak memory 195296 kb
Host smart-7b5d64ac-b467-4a3d-a814-7574fc8a07e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197133735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4197133735
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.755114773
Short name T1233
Test name
Test status
Simulation time 52248427 ps
CPU time 0.71 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:49 PM PDT 24
Peak memory 197948 kb
Host smart-f5bbc4c2-1751-49d0-86c8-0c000e294d91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755114773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.755114773
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2664145588
Short name T1222
Test name
Test status
Simulation time 501796753 ps
CPU time 1.89 seconds
Started Jul 20 05:45:55 PM PDT 24
Finished Jul 20 05:46:00 PM PDT 24
Peak memory 200892 kb
Host smart-bb6e427a-6e8b-4fb5-961c-a092124a3739
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664145588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2664145588
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.405847911
Short name T89
Test name
Test status
Simulation time 44779112 ps
CPU time 0.97 seconds
Started Jul 20 05:45:50 PM PDT 24
Finished Jul 20 05:45:56 PM PDT 24
Peak memory 199548 kb
Host smart-00128b8a-4efc-4ff9-b4f9-a39f52b27302
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405847911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.405847911
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3563347311
Short name T1259
Test name
Test status
Simulation time 316334812 ps
CPU time 0.82 seconds
Started Jul 20 05:45:52 PM PDT 24
Finished Jul 20 05:45:57 PM PDT 24
Peak memory 200540 kb
Host smart-772be784-7962-4397-ae5b-2f28e2f957d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563347311 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3563347311
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1125019842
Short name T82
Test name
Test status
Simulation time 16757418 ps
CPU time 0.66 seconds
Started Jul 20 05:45:50 PM PDT 24
Finished Jul 20 05:45:55 PM PDT 24
Peak memory 196316 kb
Host smart-7fde1f88-11f5-4306-ad4f-ca4ff84afea5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125019842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1125019842
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.768385760
Short name T1278
Test name
Test status
Simulation time 33548889 ps
CPU time 0.57 seconds
Started Jul 20 05:45:55 PM PDT 24
Finished Jul 20 05:45:59 PM PDT 24
Peak memory 195208 kb
Host smart-510771b1-63fb-4de3-b848-970f51581a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768385760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.768385760
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3212146950
Short name T81
Test name
Test status
Simulation time 21343200 ps
CPU time 0.64 seconds
Started Jul 20 05:45:41 PM PDT 24
Finished Jul 20 05:45:42 PM PDT 24
Peak memory 196380 kb
Host smart-0936bca6-fb31-41b7-bce6-250c0fc1370c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212146950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3212146950
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.4162711145
Short name T1237
Test name
Test status
Simulation time 44174651 ps
CPU time 0.96 seconds
Started Jul 20 05:45:43 PM PDT 24
Finished Jul 20 05:45:45 PM PDT 24
Peak memory 200532 kb
Host smart-200284ab-ebe7-42c9-943e-a1f1fd11eeca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162711145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.4162711145
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.722008755
Short name T1311
Test name
Test status
Simulation time 48058705 ps
CPU time 0.95 seconds
Started Jul 20 05:45:47 PM PDT 24
Finished Jul 20 05:45:50 PM PDT 24
Peak memory 199936 kb
Host smart-15a05463-bb41-4b66-a0b6-36a4c5f92b29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722008755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.722008755
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2846953035
Short name T1303
Test name
Test status
Simulation time 46174939 ps
CPU time 1.23 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 200920 kb
Host smart-f787e96a-f254-4899-b937-745417e43cfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846953035 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2846953035
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1994511831
Short name T78
Test name
Test status
Simulation time 31226035 ps
CPU time 0.6 seconds
Started Jul 20 05:45:54 PM PDT 24
Finished Jul 20 05:46:03 PM PDT 24
Peak memory 196308 kb
Host smart-b26d11f7-666d-481e-976e-2054ca0c1f34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994511831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1994511831
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1903179745
Short name T1172
Test name
Test status
Simulation time 72197098 ps
CPU time 0.57 seconds
Started Jul 20 05:45:41 PM PDT 24
Finished Jul 20 05:45:43 PM PDT 24
Peak memory 195136 kb
Host smart-4da15501-1c7b-403c-8dc1-e6b9b4cef799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903179745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1903179745
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.96038174
Short name T1223
Test name
Test status
Simulation time 20552744 ps
CPU time 0.65 seconds
Started Jul 20 05:45:43 PM PDT 24
Finished Jul 20 05:45:45 PM PDT 24
Peak memory 197464 kb
Host smart-8dbc487d-1164-441f-bfd7-b172f88492df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96038174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_
outstanding.96038174
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3489438170
Short name T1183
Test name
Test status
Simulation time 69915430 ps
CPU time 1.33 seconds
Started Jul 20 05:45:57 PM PDT 24
Finished Jul 20 05:46:00 PM PDT 24
Peak memory 200856 kb
Host smart-4f4eecb9-11f2-4991-9f82-4bb1f8c70d22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489438170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3489438170
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3194022693
Short name T119
Test name
Test status
Simulation time 51453516 ps
CPU time 0.9 seconds
Started Jul 20 05:45:45 PM PDT 24
Finished Jul 20 05:45:47 PM PDT 24
Peak memory 199708 kb
Host smart-4d31914c-d1fa-4b7d-aee2-cf5f595e979a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194022693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3194022693
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3465012423
Short name T1196
Test name
Test status
Simulation time 39225341 ps
CPU time 0.78 seconds
Started Jul 20 05:45:34 PM PDT 24
Finished Jul 20 05:45:35 PM PDT 24
Peak memory 200536 kb
Host smart-f830c2a7-dbbf-44f6-a22b-6fac0bfc9b0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465012423 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3465012423
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2782373130
Short name T80
Test name
Test status
Simulation time 33527157 ps
CPU time 0.6 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:04 PM PDT 24
Peak memory 196240 kb
Host smart-efd12ad3-700e-4c95-8f37-090ac85312ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782373130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2782373130
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1860433552
Short name T1204
Test name
Test status
Simulation time 13060244 ps
CPU time 0.56 seconds
Started Jul 20 05:45:57 PM PDT 24
Finished Jul 20 05:46:00 PM PDT 24
Peak memory 195288 kb
Host smart-bb1f48aa-ea1b-46d2-a677-3e827c9ed887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860433552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1860433552
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1685850456
Short name T1216
Test name
Test status
Simulation time 66638978 ps
CPU time 0.64 seconds
Started Jul 20 05:45:51 PM PDT 24
Finished Jul 20 05:45:56 PM PDT 24
Peak memory 197544 kb
Host smart-96bae258-1e11-4fc4-8f49-696fe331fd6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685850456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1685850456
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2809792610
Short name T1187
Test name
Test status
Simulation time 49019969 ps
CPU time 1.65 seconds
Started Jul 20 05:45:59 PM PDT 24
Finished Jul 20 05:46:04 PM PDT 24
Peak memory 200936 kb
Host smart-6882b5f6-6267-467b-b0ca-83560b7a6b6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809792610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2809792610
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.922455335
Short name T1312
Test name
Test status
Simulation time 181402519 ps
CPU time 1.28 seconds
Started Jul 20 05:45:41 PM PDT 24
Finished Jul 20 05:45:43 PM PDT 24
Peak memory 200356 kb
Host smart-8a5d2895-83bd-4e05-a6c2-b589ef045faa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922455335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.922455335
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1787604376
Short name T1185
Test name
Test status
Simulation time 117457956 ps
CPU time 0.83 seconds
Started Jul 20 05:45:59 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 200656 kb
Host smart-996f1f9e-7f68-471b-9244-d2a739d95178
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787604376 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1787604376
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1076437448
Short name T1236
Test name
Test status
Simulation time 16877955 ps
CPU time 0.61 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 196332 kb
Host smart-10c3aae5-6987-4b18-b747-06f00cbe0538
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076437448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1076437448
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.4163143744
Short name T1173
Test name
Test status
Simulation time 72575757 ps
CPU time 0.57 seconds
Started Jul 20 05:45:52 PM PDT 24
Finished Jul 20 05:45:56 PM PDT 24
Peak memory 195284 kb
Host smart-9b4d9d79-3e0f-4dbb-be27-fd60c5494ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163143744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.4163143744
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2943812322
Short name T1214
Test name
Test status
Simulation time 16692332 ps
CPU time 0.64 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:52 PM PDT 24
Peak memory 196576 kb
Host smart-d9200971-f467-4488-a3a8-3c16786c4f91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943812322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2943812322
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3433004007
Short name T1176
Test name
Test status
Simulation time 374620140 ps
CPU time 2.07 seconds
Started Jul 20 05:45:44 PM PDT 24
Finished Jul 20 05:45:47 PM PDT 24
Peak memory 200960 kb
Host smart-e1a23a29-c4a2-47c4-9cab-9195ac45d8c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433004007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3433004007
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1345382268
Short name T91
Test name
Test status
Simulation time 187319775 ps
CPU time 0.92 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:48 PM PDT 24
Peak memory 199684 kb
Host smart-752d56a6-1e4b-4e7f-825d-e32db162edc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345382268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1345382268
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3512224952
Short name T1181
Test name
Test status
Simulation time 22386081 ps
CPU time 0.96 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:49 PM PDT 24
Peak memory 200696 kb
Host smart-b0f57ccd-ccc3-4956-9378-09feadb9fab5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512224952 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3512224952
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3188221228
Short name T1258
Test name
Test status
Simulation time 17025926 ps
CPU time 0.59 seconds
Started Jul 20 05:45:44 PM PDT 24
Finished Jul 20 05:45:45 PM PDT 24
Peak memory 196308 kb
Host smart-d511e94b-e810-4ece-92a9-4d51a755c29f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188221228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3188221228
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.746343226
Short name T1264
Test name
Test status
Simulation time 55894020 ps
CPU time 0.54 seconds
Started Jul 20 05:45:49 PM PDT 24
Finished Jul 20 05:45:54 PM PDT 24
Peak memory 195256 kb
Host smart-67c44690-eb23-4db6-ba6c-45244bd5becf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746343226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.746343226
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2539348282
Short name T77
Test name
Test status
Simulation time 16229918 ps
CPU time 0.69 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:04 PM PDT 24
Peak memory 197880 kb
Host smart-d6111764-09bf-45fa-9fcd-f73db1490517
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539348282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2539348282
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.4228148537
Short name T1202
Test name
Test status
Simulation time 67251431 ps
CPU time 1.31 seconds
Started Jul 20 05:45:49 PM PDT 24
Finished Jul 20 05:45:55 PM PDT 24
Peak memory 200976 kb
Host smart-4e5ae829-b2fd-459b-a13c-0a1c1239e507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228148537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.4228148537
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1245927664
Short name T92
Test name
Test status
Simulation time 106036608 ps
CPU time 1.32 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:54 PM PDT 24
Peak memory 200284 kb
Host smart-7493e060-f48b-4327-9e42-4e8999ac21e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245927664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1245927664
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.937482458
Short name T1288
Test name
Test status
Simulation time 31900933 ps
CPU time 0.78 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 200648 kb
Host smart-8376961e-c4ad-4c46-9174-4d3d1558074f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937482458 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.937482458
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.129591998
Short name T1253
Test name
Test status
Simulation time 17353133 ps
CPU time 0.61 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 196408 kb
Host smart-c503f43d-f71a-4398-9ca9-87d8b5fb41ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129591998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.129591998
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2665635762
Short name T1246
Test name
Test status
Simulation time 43232706 ps
CPU time 0.56 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:52 PM PDT 24
Peak memory 195432 kb
Host smart-4f6bf505-5c2f-4fe0-a4a7-5bad26610762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665635762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2665635762
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4275507836
Short name T1301
Test name
Test status
Simulation time 71342199 ps
CPU time 0.67 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:52 PM PDT 24
Peak memory 196632 kb
Host smart-0fc043d6-0be0-4589-8ae0-cba6bb9fe3c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275507836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.4275507836
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.384502168
Short name T1227
Test name
Test status
Simulation time 471158148 ps
CPU time 0.98 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 200684 kb
Host smart-db743a58-4288-4e8a-af56-7cd78b035db1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384502168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.384502168
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1067078317
Short name T1273
Test name
Test status
Simulation time 22071168 ps
CPU time 0.72 seconds
Started Jul 20 05:45:58 PM PDT 24
Finished Jul 20 05:46:01 PM PDT 24
Peak memory 198536 kb
Host smart-ec435286-fe84-4fd5-93ae-46e64ebb3b83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067078317 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1067078317
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.866747987
Short name T79
Test name
Test status
Simulation time 13527241 ps
CPU time 0.64 seconds
Started Jul 20 05:45:50 PM PDT 24
Finished Jul 20 05:45:55 PM PDT 24
Peak memory 196392 kb
Host smart-11989ba3-3eb0-41c6-8581-213da73ab019
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866747987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.866747987
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.4251459194
Short name T1292
Test name
Test status
Simulation time 106850091 ps
CPU time 0.55 seconds
Started Jul 20 05:45:51 PM PDT 24
Finished Jul 20 05:45:56 PM PDT 24
Peak memory 195200 kb
Host smart-59203f8f-067b-4cd8-b298-8b8b2270fd72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251459194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.4251459194
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3112154543
Short name T1296
Test name
Test status
Simulation time 35263392 ps
CPU time 0.76 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:06 PM PDT 24
Peak memory 197812 kb
Host smart-ace03002-c9c1-4211-a8d2-4325e8c288db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112154543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3112154543
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.18100413
Short name T1206
Test name
Test status
Simulation time 108118359 ps
CPU time 1.2 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:10 PM PDT 24
Peak memory 200924 kb
Host smart-d3e5f5c0-d7a7-4950-9819-f911df66d1da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18100413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.18100413
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.712338600
Short name T1265
Test name
Test status
Simulation time 93015722 ps
CPU time 1.34 seconds
Started Jul 20 05:45:53 PM PDT 24
Finished Jul 20 05:45:58 PM PDT 24
Peak memory 200328 kb
Host smart-43850022-f649-49f5-85a9-e9861c7e5db8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712338600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.712338600
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4057489438
Short name T1283
Test name
Test status
Simulation time 23727212 ps
CPU time 1.05 seconds
Started Jul 20 05:45:49 PM PDT 24
Finished Jul 20 05:45:59 PM PDT 24
Peak memory 200724 kb
Host smart-2ab8127a-4bc3-4ca6-b966-e6f2182866da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057489438 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.4057489438
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2393451600
Short name T1219
Test name
Test status
Simulation time 34662585 ps
CPU time 0.58 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 196272 kb
Host smart-ad8162d0-9ccf-4aed-9e45-9c77a824cf6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393451600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2393451600
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.4073362239
Short name T1274
Test name
Test status
Simulation time 47039589 ps
CPU time 0.55 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:06 PM PDT 24
Peak memory 195244 kb
Host smart-bc1987a9-23bd-4516-93a0-3bb4ecfde273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073362239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.4073362239
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2959972064
Short name T1268
Test name
Test status
Simulation time 25297897 ps
CPU time 0.66 seconds
Started Jul 20 05:45:47 PM PDT 24
Finished Jul 20 05:45:51 PM PDT 24
Peak memory 197480 kb
Host smart-19dc6908-92d2-4a55-baf2-bf1ff447b8c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959972064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2959972064
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1690740990
Short name T1179
Test name
Test status
Simulation time 59189792 ps
CPU time 1.63 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 200964 kb
Host smart-bb97a43d-7034-49fd-aa1e-30f178f22b64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690740990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1690740990
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1720326868
Short name T86
Test name
Test status
Simulation time 52083478 ps
CPU time 0.95 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:06 PM PDT 24
Peak memory 199940 kb
Host smart-abb39c4a-5749-41e1-a722-27b0113d9c73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720326868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1720326868
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.633451966
Short name T56
Test name
Test status
Simulation time 74883792 ps
CPU time 0.7 seconds
Started Jul 20 05:45:35 PM PDT 24
Finished Jul 20 05:45:36 PM PDT 24
Peak memory 195768 kb
Host smart-a9ec39b3-14d1-433e-9ba5-1c5e02aecac0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633451966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.633451966
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1800807242
Short name T1254
Test name
Test status
Simulation time 367712170 ps
CPU time 2.28 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:55 PM PDT 24
Peak memory 198468 kb
Host smart-6c8dcf06-0fc6-41d5-a763-56afa6c851b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800807242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1800807242
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2428701899
Short name T1195
Test name
Test status
Simulation time 51763304 ps
CPU time 0.58 seconds
Started Jul 20 05:45:53 PM PDT 24
Finished Jul 20 05:45:57 PM PDT 24
Peak memory 196308 kb
Host smart-ae5298aa-51af-4929-b9e9-54326621b316
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428701899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2428701899
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3400145658
Short name T1310
Test name
Test status
Simulation time 197981147 ps
CPU time 0.75 seconds
Started Jul 20 05:45:47 PM PDT 24
Finished Jul 20 05:45:50 PM PDT 24
Peak memory 199888 kb
Host smart-0a5580c1-3520-4783-a921-a07a7fa2fa83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400145658 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3400145658
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.41175116
Short name T59
Test name
Test status
Simulation time 15030349 ps
CPU time 0.62 seconds
Started Jul 20 05:45:33 PM PDT 24
Finished Jul 20 05:45:34 PM PDT 24
Peak memory 196416 kb
Host smart-dbd3af62-7179-4ba2-99e7-0bb8a5d95b20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41175116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.41175116
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3769324584
Short name T1210
Test name
Test status
Simulation time 13333361 ps
CPU time 0.56 seconds
Started Jul 20 05:45:35 PM PDT 24
Finished Jul 20 05:45:36 PM PDT 24
Peak memory 195312 kb
Host smart-8eb348e5-9ea6-4030-8bfa-048faf22b6f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769324584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3769324584
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.425729928
Short name T1230
Test name
Test status
Simulation time 31276274 ps
CPU time 0.75 seconds
Started Jul 20 05:45:35 PM PDT 24
Finished Jul 20 05:45:37 PM PDT 24
Peak memory 196488 kb
Host smart-1d625690-18ff-4eda-9763-283efd95f06b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425729928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.425729928
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2439607057
Short name T1270
Test name
Test status
Simulation time 44882158 ps
CPU time 1.31 seconds
Started Jul 20 05:45:31 PM PDT 24
Finished Jul 20 05:45:33 PM PDT 24
Peak memory 200960 kb
Host smart-a0e916cd-688b-4f9b-8570-b5917ab980a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439607057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2439607057
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2605245976
Short name T1293
Test name
Test status
Simulation time 230406186 ps
CPU time 1.02 seconds
Started Jul 20 05:45:34 PM PDT 24
Finished Jul 20 05:45:35 PM PDT 24
Peak memory 199924 kb
Host smart-00c76fd2-cc12-4a5d-beda-d469a8a90579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605245976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2605245976
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1201716159
Short name T1304
Test name
Test status
Simulation time 44172639 ps
CPU time 0.58 seconds
Started Jul 20 05:45:49 PM PDT 24
Finished Jul 20 05:45:54 PM PDT 24
Peak memory 195348 kb
Host smart-cbede06e-2757-41bc-96fe-7124957df5a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201716159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1201716159
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.585060920
Short name T1309
Test name
Test status
Simulation time 34750443 ps
CPU time 0.6 seconds
Started Jul 20 05:45:50 PM PDT 24
Finished Jul 20 05:45:55 PM PDT 24
Peak memory 195440 kb
Host smart-9f28d21c-17f1-45e1-bd57-4dd694ab9c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585060920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.585060920
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1130592550
Short name T1262
Test name
Test status
Simulation time 13073222 ps
CPU time 0.57 seconds
Started Jul 20 05:45:57 PM PDT 24
Finished Jul 20 05:46:00 PM PDT 24
Peak memory 195220 kb
Host smart-52688736-36ef-47f6-be50-7f6c29cc1581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130592550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1130592550
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1286776269
Short name T1240
Test name
Test status
Simulation time 13428703 ps
CPU time 0.55 seconds
Started Jul 20 05:45:55 PM PDT 24
Finished Jul 20 05:45:59 PM PDT 24
Peak memory 195228 kb
Host smart-25d11dbe-b6be-4cc2-a177-2b02effc4c89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286776269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1286776269
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2290406116
Short name T1184
Test name
Test status
Simulation time 15244539 ps
CPU time 0.58 seconds
Started Jul 20 05:45:52 PM PDT 24
Finished Jul 20 05:45:56 PM PDT 24
Peak memory 195320 kb
Host smart-c5ccfab0-b983-41fe-bc0e-271e3910d704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290406116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2290406116
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3452940764
Short name T1267
Test name
Test status
Simulation time 12115806 ps
CPU time 0.56 seconds
Started Jul 20 05:45:57 PM PDT 24
Finished Jul 20 05:46:00 PM PDT 24
Peak memory 195220 kb
Host smart-2e96525d-541f-4330-ae4d-0378b6ee23fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452940764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3452940764
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.989271718
Short name T1251
Test name
Test status
Simulation time 45045450 ps
CPU time 0.58 seconds
Started Jul 20 05:45:50 PM PDT 24
Finished Jul 20 05:45:55 PM PDT 24
Peak memory 195304 kb
Host smart-4559e272-3a74-43d4-9f68-c00ee4467031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989271718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.989271718
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3883733782
Short name T1211
Test name
Test status
Simulation time 37430774 ps
CPU time 0.53 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 195288 kb
Host smart-03895bd9-8c98-42bb-b533-31fe5be4b794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883733782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3883733782
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3216978200
Short name T1197
Test name
Test status
Simulation time 86359834 ps
CPU time 0.54 seconds
Started Jul 20 05:45:55 PM PDT 24
Finished Jul 20 05:45:59 PM PDT 24
Peak memory 195220 kb
Host smart-d170fb1a-c84b-4a9c-819f-7fa3ec90e606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216978200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3216978200
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.744410381
Short name T1245
Test name
Test status
Simulation time 23036527 ps
CPU time 0.57 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 195296 kb
Host smart-84fac408-e9ea-421c-a204-d79f33898e87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744410381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.744410381
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1460224864
Short name T1198
Test name
Test status
Simulation time 20372066 ps
CPU time 0.68 seconds
Started Jul 20 05:45:42 PM PDT 24
Finished Jul 20 05:45:44 PM PDT 24
Peak memory 195692 kb
Host smart-48a69e91-52eb-4b9e-89df-5c532523f637
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460224864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1460224864
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.728780325
Short name T58
Test name
Test status
Simulation time 38032193 ps
CPU time 1.49 seconds
Started Jul 20 05:45:36 PM PDT 24
Finished Jul 20 05:45:38 PM PDT 24
Peak memory 198980 kb
Host smart-88a26019-aee4-41ac-b166-f7969c8e7f11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728780325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.728780325
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2786738656
Short name T1228
Test name
Test status
Simulation time 89935183 ps
CPU time 0.59 seconds
Started Jul 20 05:45:34 PM PDT 24
Finished Jul 20 05:45:36 PM PDT 24
Peak memory 196304 kb
Host smart-670fc919-c451-4532-b3bf-ecc363cba678
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786738656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2786738656
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4126904734
Short name T1287
Test name
Test status
Simulation time 23353530 ps
CPU time 0.8 seconds
Started Jul 20 05:45:35 PM PDT 24
Finished Jul 20 05:45:37 PM PDT 24
Peak memory 200296 kb
Host smart-3d28ba3a-980d-4fdb-a6d8-dc9fe19969fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126904734 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.4126904734
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1693051842
Short name T1276
Test name
Test status
Simulation time 29368812 ps
CPU time 0.6 seconds
Started Jul 20 05:45:42 PM PDT 24
Finished Jul 20 05:45:44 PM PDT 24
Peak memory 195296 kb
Host smart-f63a7790-926f-4a05-bfc4-05bea397f535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693051842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1693051842
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.519287581
Short name T1286
Test name
Test status
Simulation time 24212424 ps
CPU time 0.66 seconds
Started Jul 20 05:45:35 PM PDT 24
Finished Jul 20 05:45:37 PM PDT 24
Peak memory 196860 kb
Host smart-b5c87b47-88f7-4cf7-b95d-c5644231f37b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519287581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.519287581
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.910600106
Short name T1269
Test name
Test status
Simulation time 420651873 ps
CPU time 2.45 seconds
Started Jul 20 05:45:33 PM PDT 24
Finished Jul 20 05:45:35 PM PDT 24
Peak memory 201004 kb
Host smart-309d8043-2ad2-4dfb-aea3-9ccc99e78312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910600106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.910600106
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1477320025
Short name T1248
Test name
Test status
Simulation time 91219895 ps
CPU time 1.33 seconds
Started Jul 20 05:45:47 PM PDT 24
Finished Jul 20 05:45:51 PM PDT 24
Peak memory 200284 kb
Host smart-a495d94b-d990-4f2a-8116-1e52052d48b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477320025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1477320025
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3454890609
Short name T1241
Test name
Test status
Simulation time 37469166 ps
CPU time 0.58 seconds
Started Jul 20 05:45:53 PM PDT 24
Finished Jul 20 05:45:57 PM PDT 24
Peak memory 195324 kb
Host smart-697fd1f7-3fde-492f-ab02-d12513b635eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454890609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3454890609
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3545733852
Short name T1182
Test name
Test status
Simulation time 52780536 ps
CPU time 0.56 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:05 PM PDT 24
Peak memory 195304 kb
Host smart-d533e59c-7865-4f53-9904-c61cc0c99c48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545733852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3545733852
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.607203797
Short name T1271
Test name
Test status
Simulation time 37398077 ps
CPU time 0.57 seconds
Started Jul 20 05:45:54 PM PDT 24
Finished Jul 20 05:45:58 PM PDT 24
Peak memory 195296 kb
Host smart-879dd4d5-279a-413f-8ee0-491f087a06ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607203797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.607203797
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2831798801
Short name T1201
Test name
Test status
Simulation time 27589723 ps
CPU time 0.59 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 195224 kb
Host smart-3f6696eb-566d-4a94-9276-f81b14331da1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831798801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2831798801
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2846488781
Short name T1174
Test name
Test status
Simulation time 25775191 ps
CPU time 0.58 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:52 PM PDT 24
Peak memory 195280 kb
Host smart-33ec1a8f-2bbc-4efa-9d81-130875a9d7a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846488781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2846488781
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.203095012
Short name T1232
Test name
Test status
Simulation time 23123786 ps
CPU time 0.56 seconds
Started Jul 20 05:45:49 PM PDT 24
Finished Jul 20 05:45:54 PM PDT 24
Peak memory 195332 kb
Host smart-b37a074e-8750-45e8-8213-6479a5add907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203095012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.203095012
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3245514596
Short name T1250
Test name
Test status
Simulation time 160356623 ps
CPU time 0.53 seconds
Started Jul 20 05:45:51 PM PDT 24
Finished Jul 20 05:45:56 PM PDT 24
Peak memory 195224 kb
Host smart-e9fd8c2f-4280-4ed9-b31d-9b3d28712bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245514596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3245514596
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.463070601
Short name T1218
Test name
Test status
Simulation time 39949281 ps
CPU time 0.58 seconds
Started Jul 20 05:45:45 PM PDT 24
Finished Jul 20 05:45:46 PM PDT 24
Peak memory 195348 kb
Host smart-6bd149fe-a3dc-442b-be3c-0dc7152f92f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463070601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.463070601
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2127396641
Short name T1215
Test name
Test status
Simulation time 51226182 ps
CPU time 0.56 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:06 PM PDT 24
Peak memory 195260 kb
Host smart-a71072d6-6f07-4e4f-95de-431522d02559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127396641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2127396641
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2289790275
Short name T1186
Test name
Test status
Simulation time 15798177 ps
CPU time 0.56 seconds
Started Jul 20 05:45:47 PM PDT 24
Finished Jul 20 05:45:50 PM PDT 24
Peak memory 195248 kb
Host smart-1d0bfa10-ab1a-45a5-aeda-5d6f6abab26c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289790275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2289790275
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.718970855
Short name T1221
Test name
Test status
Simulation time 77285546 ps
CPU time 0.67 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:08 PM PDT 24
Peak memory 195804 kb
Host smart-47ffcb05-4be3-4b51-9131-385257b93ace
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718970855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.718970855
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.841799784
Short name T1193
Test name
Test status
Simulation time 387441471 ps
CPU time 2.2 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:50 PM PDT 24
Peak memory 198632 kb
Host smart-4fddbbeb-0558-4216-9cf8-d8b00307b787
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841799784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.841799784
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1986044685
Short name T60
Test name
Test status
Simulation time 17231414 ps
CPU time 0.59 seconds
Started Jul 20 05:45:38 PM PDT 24
Finished Jul 20 05:45:38 PM PDT 24
Peak memory 196444 kb
Host smart-d9a67466-769e-4455-9a9b-fd0ab19f2945
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986044685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1986044685
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3154227696
Short name T1226
Test name
Test status
Simulation time 27529497 ps
CPU time 1.38 seconds
Started Jul 20 05:45:42 PM PDT 24
Finished Jul 20 05:45:44 PM PDT 24
Peak memory 201000 kb
Host smart-090e39da-833b-46d8-aabb-d3a41e5fe972
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154227696 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3154227696
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.4225826503
Short name T76
Test name
Test status
Simulation time 20918845 ps
CPU time 0.58 seconds
Started Jul 20 05:45:35 PM PDT 24
Finished Jul 20 05:45:37 PM PDT 24
Peak memory 196332 kb
Host smart-6da68158-ec4f-4677-b407-d71334d21a4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225826503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.4225826503
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1905051039
Short name T1256
Test name
Test status
Simulation time 18044031 ps
CPU time 0.58 seconds
Started Jul 20 05:45:36 PM PDT 24
Finished Jul 20 05:45:38 PM PDT 24
Peak memory 195284 kb
Host smart-48c4981d-b699-4cd2-92f3-7f701efa77ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905051039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1905051039
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2130255031
Short name T1289
Test name
Test status
Simulation time 132206260 ps
CPU time 0.73 seconds
Started Jul 20 05:45:47 PM PDT 24
Finished Jul 20 05:45:51 PM PDT 24
Peak memory 197792 kb
Host smart-8a830203-0097-4d87-ac3e-a6671ccf7688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130255031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2130255031
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.427989374
Short name T1180
Test name
Test status
Simulation time 48999335 ps
CPU time 1.31 seconds
Started Jul 20 05:45:32 PM PDT 24
Finished Jul 20 05:45:34 PM PDT 24
Peak memory 200984 kb
Host smart-84d02f8a-449b-4864-a7eb-272bfa93b2bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427989374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.427989374
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.417821569
Short name T1191
Test name
Test status
Simulation time 299417772 ps
CPU time 1.34 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:53 PM PDT 24
Peak memory 200112 kb
Host smart-c226b73b-133e-44db-bea7-48202f35a231
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417821569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.417821569
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3282785322
Short name T1225
Test name
Test status
Simulation time 12776881 ps
CPU time 0.56 seconds
Started Jul 20 05:45:50 PM PDT 24
Finished Jul 20 05:45:55 PM PDT 24
Peak memory 195264 kb
Host smart-39cab8f9-85e2-43fe-93b7-3bfb0fd100a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282785322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3282785322
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.147632364
Short name T1239
Test name
Test status
Simulation time 12002587 ps
CPU time 0.57 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:52 PM PDT 24
Peak memory 195184 kb
Host smart-244cb1a0-6b92-4fb3-a0ef-40ece9a10428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147632364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.147632364
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3322933239
Short name T1299
Test name
Test status
Simulation time 14053844 ps
CPU time 0.56 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 195244 kb
Host smart-b9f5ab43-a937-44bf-bceb-06f9a4e8aae6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322933239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3322933239
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2623678846
Short name T1300
Test name
Test status
Simulation time 29652638 ps
CPU time 0.59 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:07 PM PDT 24
Peak memory 195304 kb
Host smart-9c038193-d542-4169-bef8-36b144a14aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623678846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2623678846
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2209517905
Short name T1261
Test name
Test status
Simulation time 27192353 ps
CPU time 0.59 seconds
Started Jul 20 05:45:58 PM PDT 24
Finished Jul 20 05:46:01 PM PDT 24
Peak memory 195288 kb
Host smart-1389c16d-163f-4ad3-a78d-1754481e9b37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209517905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2209517905
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.159273590
Short name T1190
Test name
Test status
Simulation time 44571856 ps
CPU time 0.56 seconds
Started Jul 20 05:45:42 PM PDT 24
Finished Jul 20 05:45:44 PM PDT 24
Peak memory 195324 kb
Host smart-5698d1be-46de-47e0-b92b-494a76533598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159273590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.159273590
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2480360397
Short name T1249
Test name
Test status
Simulation time 58356417 ps
CPU time 0.57 seconds
Started Jul 20 05:45:58 PM PDT 24
Finished Jul 20 05:46:01 PM PDT 24
Peak memory 195316 kb
Host smart-3248fd93-d082-4b17-af77-fee81af296b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480360397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2480360397
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2993479492
Short name T1189
Test name
Test status
Simulation time 17017018 ps
CPU time 0.58 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 195308 kb
Host smart-adec85fb-0bc8-47df-b485-05a953f56eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993479492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2993479492
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1879204796
Short name T1244
Test name
Test status
Simulation time 14173087 ps
CPU time 0.56 seconds
Started Jul 20 05:45:56 PM PDT 24
Finished Jul 20 05:45:59 PM PDT 24
Peak memory 195228 kb
Host smart-5c56c71b-a92c-4736-9ab1-f308387277d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879204796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1879204796
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3820546542
Short name T1272
Test name
Test status
Simulation time 20508230 ps
CPU time 0.55 seconds
Started Jul 20 05:45:52 PM PDT 24
Finished Jul 20 05:46:00 PM PDT 24
Peak memory 195184 kb
Host smart-5237abed-dc8d-40e9-9cd6-52df1443bd90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820546542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3820546542
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2266830719
Short name T1220
Test name
Test status
Simulation time 69291504 ps
CPU time 0.8 seconds
Started Jul 20 05:45:49 PM PDT 24
Finished Jul 20 05:45:54 PM PDT 24
Peak memory 200744 kb
Host smart-bd642947-43b7-4fac-9682-0b3fb97a7e62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266830719 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2266830719
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2337802897
Short name T1260
Test name
Test status
Simulation time 28922667 ps
CPU time 0.59 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:05 PM PDT 24
Peak memory 196416 kb
Host smart-de5202cc-2ad3-4711-9d59-68037b97dd70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337802897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2337802897
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3918400746
Short name T1188
Test name
Test status
Simulation time 22664740 ps
CPU time 0.55 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:06 PM PDT 24
Peak memory 195308 kb
Host smart-820f5b2e-bfce-4f14-b6ba-3716a378b301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918400746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3918400746
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.11793515
Short name T1247
Test name
Test status
Simulation time 39536754 ps
CPU time 0.81 seconds
Started Jul 20 05:45:42 PM PDT 24
Finished Jul 20 05:45:44 PM PDT 24
Peak memory 197900 kb
Host smart-e3460c05-df81-4679-b4da-6b323aa29b62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11793515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_o
utstanding.11793515
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1341384312
Short name T1291
Test name
Test status
Simulation time 424221252 ps
CPU time 2.1 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 200904 kb
Host smart-01cac6f0-48da-4394-880a-35c18fbfe3db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341384312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1341384312
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2887302893
Short name T84
Test name
Test status
Simulation time 41068590 ps
CPU time 0.92 seconds
Started Jul 20 05:45:50 PM PDT 24
Finished Jul 20 05:45:55 PM PDT 24
Peak memory 199776 kb
Host smart-021da464-f12d-4ad7-99c5-0bd4272db6da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887302893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2887302893
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2409738957
Short name T1217
Test name
Test status
Simulation time 32141156 ps
CPU time 0.85 seconds
Started Jul 20 05:45:51 PM PDT 24
Finished Jul 20 05:45:56 PM PDT 24
Peak memory 200724 kb
Host smart-038d27bf-c03e-4f7e-a7fd-30900b997149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409738957 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2409738957
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2948053904
Short name T1285
Test name
Test status
Simulation time 44389340 ps
CPU time 0.62 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:53 PM PDT 24
Peak memory 196308 kb
Host smart-23ae020a-abb9-40c3-9436-16c53d6f06cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948053904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2948053904
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3289334504
Short name T1302
Test name
Test status
Simulation time 24505712 ps
CPU time 0.58 seconds
Started Jul 20 05:45:57 PM PDT 24
Finished Jul 20 05:46:00 PM PDT 24
Peak memory 195296 kb
Host smart-0980cd7c-bd52-4bc0-9346-1223cf2e3cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289334504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3289334504
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.852796263
Short name T1242
Test name
Test status
Simulation time 15206810 ps
CPU time 0.64 seconds
Started Jul 20 05:45:50 PM PDT 24
Finished Jul 20 05:45:55 PM PDT 24
Peak memory 196540 kb
Host smart-bb3787a3-16d6-47a0-889d-d114f3c998f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852796263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.852796263
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3371436523
Short name T1192
Test name
Test status
Simulation time 95101082 ps
CPU time 1.96 seconds
Started Jul 20 05:45:57 PM PDT 24
Finished Jul 20 05:46:02 PM PDT 24
Peak memory 200896 kb
Host smart-72c137ed-bb76-4784-aade-f533de0b6dba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371436523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3371436523
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3656736838
Short name T1281
Test name
Test status
Simulation time 72245216 ps
CPU time 0.96 seconds
Started Jul 20 05:45:49 PM PDT 24
Finished Jul 20 05:45:54 PM PDT 24
Peak memory 199916 kb
Host smart-3eeaea37-a322-4865-bda5-c6dcf1c74a71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656736838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3656736838
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3655995319
Short name T1277
Test name
Test status
Simulation time 51413706 ps
CPU time 1.01 seconds
Started Jul 20 05:45:56 PM PDT 24
Finished Jul 20 05:46:00 PM PDT 24
Peak memory 200676 kb
Host smart-d066481f-5bee-4485-9eb6-96639c0c10c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655995319 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3655995319
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2111400493
Short name T1238
Test name
Test status
Simulation time 52215272 ps
CPU time 0.65 seconds
Started Jul 20 05:45:37 PM PDT 24
Finished Jul 20 05:45:38 PM PDT 24
Peak memory 196352 kb
Host smart-8a28d3de-4d4d-46e2-8dca-1bc47ab8741b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111400493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2111400493
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3595858627
Short name T1252
Test name
Test status
Simulation time 46295130 ps
CPU time 0.56 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:48 PM PDT 24
Peak memory 195324 kb
Host smart-83b9da3c-97d5-4cec-bca1-151731bf00ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595858627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3595858627
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3874551415
Short name T1284
Test name
Test status
Simulation time 17422092 ps
CPU time 0.73 seconds
Started Jul 20 05:45:54 PM PDT 24
Finished Jul 20 05:45:58 PM PDT 24
Peak memory 198396 kb
Host smart-a4c37b82-1027-43b5-b0a3-a2e7a89a4ea9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874551415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3874551415
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2233672257
Short name T1212
Test name
Test status
Simulation time 78683211 ps
CPU time 1.01 seconds
Started Jul 20 05:45:58 PM PDT 24
Finished Jul 20 05:46:01 PM PDT 24
Peak memory 200776 kb
Host smart-68b342c3-78f1-4fd8-a612-2ba1a79fa3ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233672257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2233672257
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2013667021
Short name T1207
Test name
Test status
Simulation time 24430450 ps
CPU time 0.84 seconds
Started Jul 20 05:45:47 PM PDT 24
Finished Jul 20 05:45:51 PM PDT 24
Peak memory 200720 kb
Host smart-d06c8324-0735-4d4f-8ef3-b9898416f8af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013667021 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2013667021
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.617400306
Short name T1231
Test name
Test status
Simulation time 41941208 ps
CPU time 0.6 seconds
Started Jul 20 05:45:47 PM PDT 24
Finished Jul 20 05:45:50 PM PDT 24
Peak memory 196336 kb
Host smart-f967ab99-5aae-48f3-8647-1ed5d035a6fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617400306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.617400306
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1446735955
Short name T1178
Test name
Test status
Simulation time 11040466 ps
CPU time 0.54 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:48 PM PDT 24
Peak memory 195220 kb
Host smart-c4b2672c-2ce7-449c-bb79-b7667f9f7d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446735955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1446735955
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3316865078
Short name T1308
Test name
Test status
Simulation time 68653833 ps
CPU time 0.62 seconds
Started Jul 20 05:45:42 PM PDT 24
Finished Jul 20 05:45:43 PM PDT 24
Peak memory 196380 kb
Host smart-a7ad7adc-fa26-4d75-adf9-1a619764fa70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316865078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3316865078
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3341404117
Short name T1194
Test name
Test status
Simulation time 488129601 ps
CPU time 2.13 seconds
Started Jul 20 05:45:50 PM PDT 24
Finished Jul 20 05:45:56 PM PDT 24
Peak memory 200980 kb
Host smart-5cd554a0-a564-4336-a8fa-b3cd10e5fca4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341404117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3341404117
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1026258973
Short name T1305
Test name
Test status
Simulation time 50861151 ps
CPU time 0.96 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:50 PM PDT 24
Peak memory 199764 kb
Host smart-dd69e91c-8e99-4b5a-818b-ba3c737a9367
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026258973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1026258973
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3818221078
Short name T1279
Test name
Test status
Simulation time 342740401 ps
CPU time 0.96 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:53 PM PDT 24
Peak memory 200752 kb
Host smart-5da4af54-6b17-4ceb-b470-b2f7b64bf0f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818221078 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3818221078
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1171123809
Short name T1203
Test name
Test status
Simulation time 15654550 ps
CPU time 0.63 seconds
Started Jul 20 05:45:45 PM PDT 24
Finished Jul 20 05:45:47 PM PDT 24
Peak memory 196672 kb
Host smart-4004a167-c47d-42dd-92cf-cc60338323f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171123809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1171123809
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2148808761
Short name T1234
Test name
Test status
Simulation time 19074217 ps
CPU time 0.59 seconds
Started Jul 20 05:45:52 PM PDT 24
Finished Jul 20 05:45:57 PM PDT 24
Peak memory 195216 kb
Host smart-60664510-622b-4536-92bf-9790613d414f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148808761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2148808761
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2400221958
Short name T1266
Test name
Test status
Simulation time 35413888 ps
CPU time 0.66 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:10 PM PDT 24
Peak memory 196676 kb
Host smart-b6e9506b-03c6-4eba-a3cc-9be4c757e402
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400221958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2400221958
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3149071217
Short name T1290
Test name
Test status
Simulation time 968082071 ps
CPU time 2.36 seconds
Started Jul 20 05:45:53 PM PDT 24
Finished Jul 20 05:45:59 PM PDT 24
Peak memory 200980 kb
Host smart-0c5a79bc-bb99-48a4-8667-dbe62f429855
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149071217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3149071217
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2109380181
Short name T1280
Test name
Test status
Simulation time 105665681 ps
CPU time 1.3 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 200212 kb
Host smart-06ec9771-4162-4d50-9bb4-f20ef7adf46d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109380181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2109380181
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1391857791
Short name T856
Test name
Test status
Simulation time 35311150 ps
CPU time 0.55 seconds
Started Jul 20 06:02:05 PM PDT 24
Finished Jul 20 06:02:06 PM PDT 24
Peak memory 195556 kb
Host smart-85868ee9-2347-44b1-8702-6d96e1483080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391857791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1391857791
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3535742516
Short name T708
Test name
Test status
Simulation time 98386685865 ps
CPU time 40.99 seconds
Started Jul 20 06:01:56 PM PDT 24
Finished Jul 20 06:02:37 PM PDT 24
Peak memory 200184 kb
Host smart-efef6fe1-a819-4297-9cdd-62c2c489f49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535742516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3535742516
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1729084680
Short name T721
Test name
Test status
Simulation time 31641402034 ps
CPU time 26.83 seconds
Started Jul 20 06:01:54 PM PDT 24
Finished Jul 20 06:02:21 PM PDT 24
Peak memory 200112 kb
Host smart-bc4301d3-7d7a-4a8a-93ae-b07681f961a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729084680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1729084680
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1903979805
Short name T818
Test name
Test status
Simulation time 166158539423 ps
CPU time 59.72 seconds
Started Jul 20 06:01:55 PM PDT 24
Finished Jul 20 06:02:55 PM PDT 24
Peak memory 200156 kb
Host smart-2d464bd6-38ad-4929-a440-4dc5afd0a5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903979805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1903979805
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2183576567
Short name T346
Test name
Test status
Simulation time 25346665381 ps
CPU time 15.62 seconds
Started Jul 20 06:01:56 PM PDT 24
Finished Jul 20 06:02:12 PM PDT 24
Peak memory 200052 kb
Host smart-6242bcea-9bbd-41be-8aea-6c9ee32adeaf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183576567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2183576567
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1159753695
Short name T398
Test name
Test status
Simulation time 96808253882 ps
CPU time 230.17 seconds
Started Jul 20 06:02:05 PM PDT 24
Finished Jul 20 06:05:56 PM PDT 24
Peak memory 200172 kb
Host smart-682a010c-96f1-46d7-839b-c2eb9b97b832
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1159753695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1159753695
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.475189509
Short name T680
Test name
Test status
Simulation time 2044690633 ps
CPU time 3.18 seconds
Started Jul 20 06:02:02 PM PDT 24
Finished Jul 20 06:02:06 PM PDT 24
Peak memory 199516 kb
Host smart-6087166e-eda1-4b0e-8f65-11059efbda88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475189509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.475189509
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2483734719
Short name T740
Test name
Test status
Simulation time 557231427440 ps
CPU time 65.13 seconds
Started Jul 20 06:01:59 PM PDT 24
Finished Jul 20 06:03:04 PM PDT 24
Peak memory 208348 kb
Host smart-f107f8a0-1e4f-47de-95ac-544be2cc4ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483734719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2483734719
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.4087016490
Short name T1101
Test name
Test status
Simulation time 9780407435 ps
CPU time 379.17 seconds
Started Jul 20 06:02:04 PM PDT 24
Finished Jul 20 06:08:24 PM PDT 24
Peak memory 200168 kb
Host smart-b4282e49-5d8f-446a-a7ab-c21801635fb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087016490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.4087016490
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1159023267
Short name T553
Test name
Test status
Simulation time 5617702431 ps
CPU time 11.85 seconds
Started Jul 20 06:01:56 PM PDT 24
Finished Jul 20 06:02:08 PM PDT 24
Peak memory 199436 kb
Host smart-d4c7bcbe-645c-48d6-88d0-80645bde3f2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1159023267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1159023267
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.211647851
Short name T146
Test name
Test status
Simulation time 217815974461 ps
CPU time 187.56 seconds
Started Jul 20 06:02:00 PM PDT 24
Finished Jul 20 06:05:08 PM PDT 24
Peak memory 200116 kb
Host smart-0c5e46f8-0fa1-4605-8b70-85ba2fd0d5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211647851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.211647851
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3973885878
Short name T389
Test name
Test status
Simulation time 1830408844 ps
CPU time 3.31 seconds
Started Jul 20 06:01:53 PM PDT 24
Finished Jul 20 06:01:57 PM PDT 24
Peak memory 195640 kb
Host smart-f1c749c1-98e8-4f36-8548-c120ae46a05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973885878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3973885878
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.420057332
Short name T923
Test name
Test status
Simulation time 676442330 ps
CPU time 2.03 seconds
Started Jul 20 06:01:57 PM PDT 24
Finished Jul 20 06:02:00 PM PDT 24
Peak memory 198484 kb
Host smart-8edec182-1348-4d59-8607-56caa49d94de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420057332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.420057332
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3307423095
Short name T1130
Test name
Test status
Simulation time 65835759680 ps
CPU time 105.33 seconds
Started Jul 20 06:02:04 PM PDT 24
Finished Jul 20 06:03:50 PM PDT 24
Peak memory 200232 kb
Host smart-dc9d9bd8-79c8-4e61-978e-5a912ee1c91b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307423095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3307423095
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.968911884
Short name T694
Test name
Test status
Simulation time 26797063107 ps
CPU time 76.88 seconds
Started Jul 20 06:02:07 PM PDT 24
Finished Jul 20 06:03:24 PM PDT 24
Peak memory 216008 kb
Host smart-3d394188-596e-4b84-9250-8bdf1a392d05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968911884 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.968911884
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1583676700
Short name T4
Test name
Test status
Simulation time 9278735769 ps
CPU time 1.75 seconds
Started Jul 20 06:01:55 PM PDT 24
Finished Jul 20 06:01:57 PM PDT 24
Peak memory 200072 kb
Host smart-83b5426a-db14-41b3-922d-ff2de22511ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583676700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1583676700
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3566191923
Short name T303
Test name
Test status
Simulation time 86399295412 ps
CPU time 88.27 seconds
Started Jul 20 06:01:59 PM PDT 24
Finished Jul 20 06:03:28 PM PDT 24
Peak memory 200180 kb
Host smart-4b690992-c913-471d-81c3-ff66c7751690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566191923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3566191923
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2872567025
Short name T1150
Test name
Test status
Simulation time 181166585073 ps
CPU time 73.49 seconds
Started Jul 20 06:02:03 PM PDT 24
Finished Jul 20 06:03:17 PM PDT 24
Peak memory 200144 kb
Host smart-a6fdcdc9-24fd-4271-8e12-c3345982d8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872567025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2872567025
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3430598359
Short name T511
Test name
Test status
Simulation time 26090273339 ps
CPU time 45.99 seconds
Started Jul 20 06:02:03 PM PDT 24
Finished Jul 20 06:02:50 PM PDT 24
Peak memory 200072 kb
Host smart-8d4c662c-0cee-4558-b86a-6a612db742cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430598359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3430598359
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.843545171
Short name T942
Test name
Test status
Simulation time 54072830102 ps
CPU time 80.37 seconds
Started Jul 20 06:02:09 PM PDT 24
Finished Jul 20 06:03:30 PM PDT 24
Peak memory 199532 kb
Host smart-70f6f9f5-bf63-4782-9015-5708fdf066da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843545171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.843545171
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3517083394
Short name T480
Test name
Test status
Simulation time 48913426382 ps
CPU time 275.03 seconds
Started Jul 20 06:02:14 PM PDT 24
Finished Jul 20 06:06:49 PM PDT 24
Peak memory 200172 kb
Host smart-64d5a6c0-4430-47e2-bd4b-a2c17bcf3e22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3517083394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3517083394
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1973377318
Short name T793
Test name
Test status
Simulation time 8604759470 ps
CPU time 15.66 seconds
Started Jul 20 06:02:15 PM PDT 24
Finished Jul 20 06:02:31 PM PDT 24
Peak memory 200088 kb
Host smart-273844b0-765e-4075-9d8f-70e5fa2b32f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973377318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1973377318
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2119356199
Short name T976
Test name
Test status
Simulation time 20367083797 ps
CPU time 21.9 seconds
Started Jul 20 06:02:12 PM PDT 24
Finished Jul 20 06:02:34 PM PDT 24
Peak memory 198128 kb
Host smart-725c66cc-66c6-4df8-bca6-e58594c6b4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119356199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2119356199
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3293090398
Short name T438
Test name
Test status
Simulation time 7450358100 ps
CPU time 107.74 seconds
Started Jul 20 06:02:12 PM PDT 24
Finished Jul 20 06:04:00 PM PDT 24
Peak memory 200200 kb
Host smart-96c5c0d7-7c27-4cdd-a8ac-cf462b66ad7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3293090398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3293090398
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3531705114
Short name T44
Test name
Test status
Simulation time 1398073947 ps
CPU time 1.82 seconds
Started Jul 20 06:02:04 PM PDT 24
Finished Jul 20 06:02:07 PM PDT 24
Peak memory 198332 kb
Host smart-4b35da1f-8dad-4a32-a319-9bf9f4592f12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531705114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3531705114
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3918155414
Short name T593
Test name
Test status
Simulation time 164432369622 ps
CPU time 18.11 seconds
Started Jul 20 06:02:12 PM PDT 24
Finished Jul 20 06:02:30 PM PDT 24
Peak memory 200140 kb
Host smart-bb0f95fc-f4b5-4e9f-aefd-06d47c34b351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918155414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3918155414
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1593600341
Short name T604
Test name
Test status
Simulation time 4134338974 ps
CPU time 7.29 seconds
Started Jul 20 06:02:13 PM PDT 24
Finished Jul 20 06:02:21 PM PDT 24
Peak memory 196748 kb
Host smart-12bb300f-0fba-4b26-a3e4-20b3f11d2b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593600341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1593600341
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2847164110
Short name T93
Test name
Test status
Simulation time 248490900 ps
CPU time 0.85 seconds
Started Jul 20 06:02:15 PM PDT 24
Finished Jul 20 06:02:16 PM PDT 24
Peak memory 218380 kb
Host smart-165a6675-6dbb-4fbc-bfce-725d357993ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847164110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2847164110
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3918811634
Short name T845
Test name
Test status
Simulation time 993608285 ps
CPU time 1.56 seconds
Started Jul 20 06:02:02 PM PDT 24
Finished Jul 20 06:02:04 PM PDT 24
Peak memory 199756 kb
Host smart-90018bcc-6e11-4ec2-936a-ff87f0e421ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918811634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3918811634
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1828390175
Short name T899
Test name
Test status
Simulation time 486672743915 ps
CPU time 399.03 seconds
Started Jul 20 06:02:10 PM PDT 24
Finished Jul 20 06:08:50 PM PDT 24
Peak memory 200124 kb
Host smart-ff8d8be0-58f9-4b23-a24c-bfb35d82dd5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828390175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1828390175
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.624949751
Short name T934
Test name
Test status
Simulation time 103768970229 ps
CPU time 316.8 seconds
Started Jul 20 06:02:11 PM PDT 24
Finished Jul 20 06:07:28 PM PDT 24
Peak memory 216668 kb
Host smart-ed7947ed-7ead-4ac6-a579-4dc6fb50114e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624949751 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.624949751
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1340139357
Short name T620
Test name
Test status
Simulation time 8444947189 ps
CPU time 9.23 seconds
Started Jul 20 06:02:12 PM PDT 24
Finished Jul 20 06:02:21 PM PDT 24
Peak memory 200152 kb
Host smart-09e9a27e-1278-4152-9390-55425d2e0200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340139357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1340139357
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.4101697021
Short name T246
Test name
Test status
Simulation time 57705827039 ps
CPU time 145.97 seconds
Started Jul 20 06:02:02 PM PDT 24
Finished Jul 20 06:04:29 PM PDT 24
Peak memory 200120 kb
Host smart-ca700ff5-caa3-4493-8506-475a937ee0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101697021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.4101697021
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.649944828
Short name T1115
Test name
Test status
Simulation time 36578540 ps
CPU time 0.53 seconds
Started Jul 20 06:03:37 PM PDT 24
Finished Jul 20 06:03:38 PM PDT 24
Peak memory 195484 kb
Host smart-c02d7a4b-ce21-428b-af28-192c9c82a26b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649944828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.649944828
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3813047714
Short name T521
Test name
Test status
Simulation time 71292414004 ps
CPU time 117.44 seconds
Started Jul 20 06:03:39 PM PDT 24
Finished Jul 20 06:05:37 PM PDT 24
Peak memory 200192 kb
Host smart-917589d0-cfc9-436f-8dc0-ae2db39cfd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813047714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3813047714
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2393578698
Short name T1119
Test name
Test status
Simulation time 111972063655 ps
CPU time 178.14 seconds
Started Jul 20 06:03:37 PM PDT 24
Finished Jul 20 06:06:36 PM PDT 24
Peak memory 200128 kb
Host smart-b0df58d4-e403-4db9-9436-7a1d6093778b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393578698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2393578698
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.31831464
Short name T441
Test name
Test status
Simulation time 62393036712 ps
CPU time 58.54 seconds
Started Jul 20 06:03:46 PM PDT 24
Finished Jul 20 06:04:45 PM PDT 24
Peak memory 200068 kb
Host smart-69e05706-3dc0-493e-89de-5970465d671a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31831464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.31831464
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.4013013845
Short name T627
Test name
Test status
Simulation time 148438486446 ps
CPU time 51.5 seconds
Started Jul 20 06:03:35 PM PDT 24
Finished Jul 20 06:04:27 PM PDT 24
Peak memory 200192 kb
Host smart-da2e726f-e8ba-4f86-af86-a17b69b3e792
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013013845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.4013013845
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.861304619
Short name T759
Test name
Test status
Simulation time 128697319469 ps
CPU time 621.03 seconds
Started Jul 20 06:03:47 PM PDT 24
Finished Jul 20 06:14:09 PM PDT 24
Peak memory 200056 kb
Host smart-c9456bfa-eea4-4e79-a90a-93c85b89b8b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=861304619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.861304619
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2549440643
Short name T379
Test name
Test status
Simulation time 3392590933 ps
CPU time 5.24 seconds
Started Jul 20 06:03:37 PM PDT 24
Finished Jul 20 06:03:43 PM PDT 24
Peak memory 199036 kb
Host smart-addd9c1e-b863-4063-a085-c957437aced4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549440643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2549440643
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3226376759
Short name T532
Test name
Test status
Simulation time 61299763206 ps
CPU time 99.38 seconds
Started Jul 20 06:03:39 PM PDT 24
Finished Jul 20 06:05:19 PM PDT 24
Peak memory 200300 kb
Host smart-02319aed-97bf-4cef-b9be-407f46a33702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226376759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3226376759
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.1448703903
Short name T1159
Test name
Test status
Simulation time 7520141256 ps
CPU time 426.91 seconds
Started Jul 20 06:03:37 PM PDT 24
Finished Jul 20 06:10:44 PM PDT 24
Peak memory 200152 kb
Host smart-8733c9d5-6d90-444b-a8e1-ec3ae75c2c47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448703903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1448703903
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2615701270
Short name T340
Test name
Test status
Simulation time 5431855671 ps
CPU time 52.03 seconds
Started Jul 20 06:03:48 PM PDT 24
Finished Jul 20 06:04:41 PM PDT 24
Peak memory 197912 kb
Host smart-e40ddaa8-1350-45a3-a408-14639cce6602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2615701270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2615701270
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.4132266699
Short name T641
Test name
Test status
Simulation time 151923908823 ps
CPU time 64.61 seconds
Started Jul 20 06:03:47 PM PDT 24
Finished Jul 20 06:04:52 PM PDT 24
Peak memory 199904 kb
Host smart-aa8618ae-78c2-4f6e-bb82-ea7832babf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132266699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.4132266699
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1265180351
Short name T646
Test name
Test status
Simulation time 44966372052 ps
CPU time 32.76 seconds
Started Jul 20 06:03:36 PM PDT 24
Finished Jul 20 06:04:09 PM PDT 24
Peak memory 196204 kb
Host smart-5c9ca4de-33ec-4f1f-9b54-711b38ec843c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265180351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1265180351
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.4122203137
Short name T282
Test name
Test status
Simulation time 11051766000 ps
CPU time 17.62 seconds
Started Jul 20 06:03:37 PM PDT 24
Finished Jul 20 06:03:55 PM PDT 24
Peak memory 200016 kb
Host smart-bbd5e65c-d9ec-481f-ad58-20c626b8c7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122203137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4122203137
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2000828653
Short name T386
Test name
Test status
Simulation time 454850077673 ps
CPU time 1412.02 seconds
Started Jul 20 06:03:37 PM PDT 24
Finished Jul 20 06:27:10 PM PDT 24
Peak memory 200168 kb
Host smart-9a2e095e-5461-426f-af5a-0e592357290e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000828653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2000828653
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3629264467
Short name T107
Test name
Test status
Simulation time 15687425947 ps
CPU time 93.62 seconds
Started Jul 20 06:03:39 PM PDT 24
Finished Jul 20 06:05:14 PM PDT 24
Peak memory 216588 kb
Host smart-9d19fa45-0eb3-4938-979f-c678536b90fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629264467 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3629264467
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.767809792
Short name T744
Test name
Test status
Simulation time 17157683469 ps
CPU time 9.47 seconds
Started Jul 20 06:03:39 PM PDT 24
Finished Jul 20 06:03:49 PM PDT 24
Peak memory 199648 kb
Host smart-456ccddf-1df6-4c01-aff6-b99b0c4af30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767809792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.767809792
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3770816415
Short name T825
Test name
Test status
Simulation time 44001770252 ps
CPU time 24.12 seconds
Started Jul 20 06:03:36 PM PDT 24
Finished Jul 20 06:04:01 PM PDT 24
Peak memory 200092 kb
Host smart-ef4a6293-4ecb-4bea-af80-435e7da4760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770816415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3770816415
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1275591574
Short name T411
Test name
Test status
Simulation time 56204358332 ps
CPU time 20.39 seconds
Started Jul 20 06:08:36 PM PDT 24
Finished Jul 20 06:08:56 PM PDT 24
Peak memory 200160 kb
Host smart-533274ff-1492-4b20-9bd1-64e7b694ce39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275591574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1275591574
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2888443967
Short name T126
Test name
Test status
Simulation time 152226768010 ps
CPU time 30.48 seconds
Started Jul 20 06:08:42 PM PDT 24
Finished Jul 20 06:09:13 PM PDT 24
Peak memory 200180 kb
Host smart-725c2915-409e-413b-9a64-b3d171f23f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888443967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2888443967
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.719679625
Short name T914
Test name
Test status
Simulation time 136068051421 ps
CPU time 57.4 seconds
Started Jul 20 06:08:44 PM PDT 24
Finished Jul 20 06:09:42 PM PDT 24
Peak memory 200136 kb
Host smart-a5901578-7d8e-43af-b984-89da4789d2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719679625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.719679625
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1899643945
Short name T135
Test name
Test status
Simulation time 32206727281 ps
CPU time 27.64 seconds
Started Jul 20 06:08:40 PM PDT 24
Finished Jul 20 06:09:08 PM PDT 24
Peak memory 200188 kb
Host smart-8bb5ba0a-5b07-4cae-9dd1-7a20fa01a1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899643945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1899643945
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2714585364
Short name T855
Test name
Test status
Simulation time 124043138689 ps
CPU time 50.44 seconds
Started Jul 20 06:08:36 PM PDT 24
Finished Jul 20 06:09:27 PM PDT 24
Peak memory 200144 kb
Host smart-3facb6b9-806a-41f8-8c3a-3cb16dd61a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714585364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2714585364
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1287116072
Short name T652
Test name
Test status
Simulation time 146982981242 ps
CPU time 75.01 seconds
Started Jul 20 06:08:41 PM PDT 24
Finished Jul 20 06:09:56 PM PDT 24
Peak memory 200076 kb
Host smart-f4536914-1158-4b6d-9c9c-0cfd83b55cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287116072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1287116072
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1820605347
Short name T1163
Test name
Test status
Simulation time 38378635329 ps
CPU time 57.77 seconds
Started Jul 20 06:08:33 PM PDT 24
Finished Jul 20 06:09:32 PM PDT 24
Peak memory 200304 kb
Host smart-fbead350-2600-42f9-aa72-6a78d5967143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820605347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1820605347
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.499420513
Short name T1050
Test name
Test status
Simulation time 68530274431 ps
CPU time 169.76 seconds
Started Jul 20 06:08:37 PM PDT 24
Finished Jul 20 06:11:27 PM PDT 24
Peak memory 200192 kb
Host smart-4bd86bc8-baf5-4a4f-a09b-d9f2debc57d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499420513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.499420513
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2769311496
Short name T927
Test name
Test status
Simulation time 38383302 ps
CPU time 0.57 seconds
Started Jul 20 06:03:49 PM PDT 24
Finished Jul 20 06:03:50 PM PDT 24
Peak memory 195572 kb
Host smart-d0583c4c-ea61-485e-a788-1d020bfd1aad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769311496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2769311496
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.30169719
Short name T151
Test name
Test status
Simulation time 27012492328 ps
CPU time 14.22 seconds
Started Jul 20 06:03:37 PM PDT 24
Finished Jul 20 06:03:52 PM PDT 24
Peak memory 200128 kb
Host smart-4d705f9a-66a2-4ee5-9c7b-acede7bfe96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30169719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.30169719
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.218958313
Short name T1073
Test name
Test status
Simulation time 108519952950 ps
CPU time 23.73 seconds
Started Jul 20 06:03:48 PM PDT 24
Finished Jul 20 06:04:12 PM PDT 24
Peak memory 200136 kb
Host smart-624799e1-449d-4f48-bf14-82a578089a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218958313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.218958313
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.4015395351
Short name T112
Test name
Test status
Simulation time 38703483730 ps
CPU time 6.81 seconds
Started Jul 20 06:03:55 PM PDT 24
Finished Jul 20 06:04:02 PM PDT 24
Peak memory 200064 kb
Host smart-5207a485-2b0e-43a2-af0e-4fa79a839a76
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015395351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.4015395351
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2215063805
Short name T494
Test name
Test status
Simulation time 109637465074 ps
CPU time 229.68 seconds
Started Jul 20 06:03:49 PM PDT 24
Finished Jul 20 06:07:40 PM PDT 24
Peak memory 200096 kb
Host smart-0755b1dc-96a4-4a4d-9c31-cecfabd21d6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215063805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2215063805
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.4094092951
Short name T736
Test name
Test status
Simulation time 3857974945 ps
CPU time 2.29 seconds
Started Jul 20 06:03:49 PM PDT 24
Finished Jul 20 06:03:52 PM PDT 24
Peak memory 199196 kb
Host smart-1cebfb35-4cd9-4e7a-99f7-e30beebd1279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094092951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.4094092951
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3754109785
Short name T626
Test name
Test status
Simulation time 75296185756 ps
CPU time 41.31 seconds
Started Jul 20 06:03:50 PM PDT 24
Finished Jul 20 06:04:31 PM PDT 24
Peak memory 200296 kb
Host smart-f4169cd8-bfd6-468f-bad8-aaea13db5e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754109785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3754109785
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1879534742
Short name T887
Test name
Test status
Simulation time 17639281827 ps
CPU time 1030.21 seconds
Started Jul 20 06:03:51 PM PDT 24
Finished Jul 20 06:21:02 PM PDT 24
Peak memory 200172 kb
Host smart-7305bac4-127e-4207-ab79-ff8fe1f3b68d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879534742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1879534742
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2532949346
Short name T574
Test name
Test status
Simulation time 6950186252 ps
CPU time 40.29 seconds
Started Jul 20 06:03:48 PM PDT 24
Finished Jul 20 06:04:28 PM PDT 24
Peak memory 199204 kb
Host smart-0550e5b8-c70d-456a-ad63-3c117a6aa2a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532949346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2532949346
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1325436007
Short name T763
Test name
Test status
Simulation time 145650900683 ps
CPU time 15.95 seconds
Started Jul 20 06:03:50 PM PDT 24
Finished Jul 20 06:04:07 PM PDT 24
Peak memory 200156 kb
Host smart-ec018a5b-1799-4124-9bcc-9ee2529d07c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325436007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1325436007
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2719281594
Short name T296
Test name
Test status
Simulation time 4034116191 ps
CPU time 2.01 seconds
Started Jul 20 06:03:52 PM PDT 24
Finished Jul 20 06:03:54 PM PDT 24
Peak memory 196316 kb
Host smart-0c3964dc-576b-4dea-b9fb-f78f3f312154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719281594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2719281594
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3362417901
Short name T858
Test name
Test status
Simulation time 11585965051 ps
CPU time 15.31 seconds
Started Jul 20 06:03:37 PM PDT 24
Finished Jul 20 06:03:53 PM PDT 24
Peak memory 199980 kb
Host smart-50439a6e-5440-4944-92ee-2f447cddae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362417901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3362417901
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.669158207
Short name T588
Test name
Test status
Simulation time 244250959113 ps
CPU time 277.58 seconds
Started Jul 20 06:03:53 PM PDT 24
Finished Jul 20 06:08:31 PM PDT 24
Peak memory 208496 kb
Host smart-fb02ea04-9db2-4344-a675-8ec85ed3620b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669158207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.669158207
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2532607005
Short name T61
Test name
Test status
Simulation time 456631041001 ps
CPU time 1528.06 seconds
Started Jul 20 06:03:49 PM PDT 24
Finished Jul 20 06:29:18 PM PDT 24
Peak memory 216808 kb
Host smart-2017bbdd-1a00-40fb-8019-fde501b67b2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532607005 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2532607005
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.4083387930
Short name T837
Test name
Test status
Simulation time 1097259004 ps
CPU time 1.29 seconds
Started Jul 20 06:03:49 PM PDT 24
Finished Jul 20 06:03:51 PM PDT 24
Peak memory 198804 kb
Host smart-9eb091a9-9500-4f47-bcc1-caf8e1186635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083387930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.4083387930
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1954522419
Short name T1071
Test name
Test status
Simulation time 103241082091 ps
CPU time 101.12 seconds
Started Jul 20 06:03:40 PM PDT 24
Finished Jul 20 06:05:21 PM PDT 24
Peak memory 200148 kb
Host smart-39132241-8e24-4dcf-b665-df49b8d069bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954522419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1954522419
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1073561147
Short name T833
Test name
Test status
Simulation time 191130350616 ps
CPU time 81.54 seconds
Started Jul 20 06:08:37 PM PDT 24
Finished Jul 20 06:09:59 PM PDT 24
Peak memory 200188 kb
Host smart-a4ed3a51-5a8a-4437-bca2-434a56d1b1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073561147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1073561147
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3950790091
Short name T216
Test name
Test status
Simulation time 40508571870 ps
CPU time 28.6 seconds
Started Jul 20 06:08:34 PM PDT 24
Finished Jul 20 06:09:04 PM PDT 24
Peak memory 200164 kb
Host smart-a2be1e0c-c8a6-417d-a6d5-23416e6b592b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950790091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3950790091
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2452501100
Short name T1041
Test name
Test status
Simulation time 26466754263 ps
CPU time 61.05 seconds
Started Jul 20 06:08:34 PM PDT 24
Finished Jul 20 06:09:36 PM PDT 24
Peak memory 200232 kb
Host smart-65629ee8-8a82-4ec1-8b22-b4b36288d378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452501100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2452501100
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.199769165
Short name T157
Test name
Test status
Simulation time 24150401998 ps
CPU time 18.52 seconds
Started Jul 20 06:08:34 PM PDT 24
Finished Jul 20 06:08:53 PM PDT 24
Peak memory 200088 kb
Host smart-c6332f42-a82c-468f-af07-e971b2765b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199769165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.199769165
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2835488173
Short name T1114
Test name
Test status
Simulation time 30189100792 ps
CPU time 45.96 seconds
Started Jul 20 06:08:40 PM PDT 24
Finished Jul 20 06:09:27 PM PDT 24
Peak memory 200128 kb
Host smart-eddac6bc-729b-4f41-8c2f-bc397ef58025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835488173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2835488173
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.535701140
Short name T330
Test name
Test status
Simulation time 39533621756 ps
CPU time 16.36 seconds
Started Jul 20 06:08:40 PM PDT 24
Finished Jul 20 06:08:56 PM PDT 24
Peak memory 200316 kb
Host smart-4eccc471-180d-4f16-8a3b-d8c4019bb045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535701140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.535701140
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2279179183
Short name T1106
Test name
Test status
Simulation time 30273469642 ps
CPU time 29.93 seconds
Started Jul 20 06:08:43 PM PDT 24
Finished Jul 20 06:09:13 PM PDT 24
Peak memory 200168 kb
Host smart-7dbf0363-9383-439e-bce6-fdbf8b6a2649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279179183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2279179183
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2240822051
Short name T1003
Test name
Test status
Simulation time 13347213 ps
CPU time 0.55 seconds
Started Jul 20 06:03:58 PM PDT 24
Finished Jul 20 06:03:59 PM PDT 24
Peak memory 195020 kb
Host smart-c77d6ce6-54bc-4b27-8b6c-87e9e138f98d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240822051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2240822051
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.637318743
Short name T440
Test name
Test status
Simulation time 100582221975 ps
CPU time 24.51 seconds
Started Jul 20 06:03:47 PM PDT 24
Finished Jul 20 06:04:12 PM PDT 24
Peak memory 200184 kb
Host smart-6977366a-0600-429f-ad2d-f0c766f2ed44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637318743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.637318743
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.790449808
Short name T758
Test name
Test status
Simulation time 259420878679 ps
CPU time 83.82 seconds
Started Jul 20 06:03:59 PM PDT 24
Finished Jul 20 06:05:24 PM PDT 24
Peak memory 200192 kb
Host smart-cea44128-90d6-47e9-aff7-8811a7c3e7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790449808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.790449808
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2353348594
Short name T687
Test name
Test status
Simulation time 120603359404 ps
CPU time 287.53 seconds
Started Jul 20 06:03:56 PM PDT 24
Finished Jul 20 06:08:44 PM PDT 24
Peak memory 200184 kb
Host smart-6b74798e-2a25-4b11-91cb-a4cd172ff943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353348594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2353348594
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1593981922
Short name T410
Test name
Test status
Simulation time 15812083500 ps
CPU time 21.33 seconds
Started Jul 20 06:03:59 PM PDT 24
Finished Jul 20 06:04:21 PM PDT 24
Peak memory 197216 kb
Host smart-f4079e7b-0b90-415f-bd3a-052201acc141
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593981922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1593981922
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1785577412
Short name T1126
Test name
Test status
Simulation time 124395904138 ps
CPU time 453.12 seconds
Started Jul 20 06:04:00 PM PDT 24
Finished Jul 20 06:11:34 PM PDT 24
Peak memory 200180 kb
Host smart-18e66642-f8f0-48fb-bd5b-1f23d1cbd1a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785577412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1785577412
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3004958268
Short name T741
Test name
Test status
Simulation time 7053625301 ps
CPU time 12.35 seconds
Started Jul 20 06:03:57 PM PDT 24
Finished Jul 20 06:04:10 PM PDT 24
Peak memory 199680 kb
Host smart-72255812-0f35-4ad0-b289-f7d189c09755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004958268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3004958268
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3098852196
Short name T1065
Test name
Test status
Simulation time 95154496096 ps
CPU time 9.57 seconds
Started Jul 20 06:04:00 PM PDT 24
Finished Jul 20 06:04:10 PM PDT 24
Peak memory 199016 kb
Host smart-4b013bd7-fa2d-4f15-a71d-1e3028884822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098852196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3098852196
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.4056177844
Short name T245
Test name
Test status
Simulation time 24918380018 ps
CPU time 1134.65 seconds
Started Jul 20 06:04:00 PM PDT 24
Finished Jul 20 06:22:55 PM PDT 24
Peak memory 200132 kb
Host smart-66185a0e-f333-453f-9fe0-47cf6b953459
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056177844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.4056177844
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1073720657
Short name T596
Test name
Test status
Simulation time 4848691177 ps
CPU time 6.01 seconds
Started Jul 20 06:03:59 PM PDT 24
Finished Jul 20 06:04:05 PM PDT 24
Peak memory 199324 kb
Host smart-12cb1cd3-d760-44e2-9df7-cbd306a6d0b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1073720657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1073720657
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1119101238
Short name T552
Test name
Test status
Simulation time 129145976059 ps
CPU time 72.61 seconds
Started Jul 20 06:03:58 PM PDT 24
Finished Jul 20 06:05:11 PM PDT 24
Peak memory 200172 kb
Host smart-a2566f1a-cf20-4838-b583-4528520016cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119101238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1119101238
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.307817745
Short name T916
Test name
Test status
Simulation time 39719050598 ps
CPU time 26.35 seconds
Started Jul 20 06:03:58 PM PDT 24
Finished Jul 20 06:04:25 PM PDT 24
Peak memory 196208 kb
Host smart-02ee37db-5f49-44fe-9ee0-51308c0d78df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307817745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.307817745
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.504880524
Short name T602
Test name
Test status
Simulation time 529882440 ps
CPU time 2.67 seconds
Started Jul 20 06:03:53 PM PDT 24
Finished Jul 20 06:03:56 PM PDT 24
Peak memory 199576 kb
Host smart-61b8ceb7-a991-4948-8f11-6e127042d4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504880524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.504880524
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.2104730017
Short name T459
Test name
Test status
Simulation time 298101633973 ps
CPU time 536.92 seconds
Started Jul 20 06:03:56 PM PDT 24
Finished Jul 20 06:12:54 PM PDT 24
Peak memory 208404 kb
Host smart-adb8fec9-efbd-4dcb-bee4-6b8b10507d39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104730017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2104730017
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3744308570
Short name T836
Test name
Test status
Simulation time 82524182483 ps
CPU time 580.45 seconds
Started Jul 20 06:04:00 PM PDT 24
Finished Jul 20 06:13:41 PM PDT 24
Peak memory 215896 kb
Host smart-5f5a6b04-01c5-426c-95eb-001ad2319623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744308570 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3744308570
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2973453458
Short name T883
Test name
Test status
Simulation time 722348193 ps
CPU time 1.98 seconds
Started Jul 20 06:03:59 PM PDT 24
Finished Jul 20 06:04:01 PM PDT 24
Peak memory 198664 kb
Host smart-8b0c39a3-316f-4994-afc7-8eb99bbfba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973453458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2973453458
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2584929522
Short name T848
Test name
Test status
Simulation time 37177182478 ps
CPU time 17.18 seconds
Started Jul 20 06:03:50 PM PDT 24
Finished Jul 20 06:04:07 PM PDT 24
Peak memory 200200 kb
Host smart-7703d45c-3107-476a-8173-0c077868e21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584929522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2584929522
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3964599624
Short name T209
Test name
Test status
Simulation time 131819410409 ps
CPU time 201.65 seconds
Started Jul 20 06:08:42 PM PDT 24
Finished Jul 20 06:12:04 PM PDT 24
Peak memory 200132 kb
Host smart-055a43bd-f014-49b9-8300-ca10a9dee3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964599624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3964599624
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2013876690
Short name T311
Test name
Test status
Simulation time 34770108420 ps
CPU time 46.21 seconds
Started Jul 20 06:08:41 PM PDT 24
Finished Jul 20 06:09:28 PM PDT 24
Peak memory 200180 kb
Host smart-1adf8ef7-799c-4662-97a2-dd88d7f49f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013876690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2013876690
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3002485731
Short name T523
Test name
Test status
Simulation time 11795041463 ps
CPU time 12.16 seconds
Started Jul 20 06:08:42 PM PDT 24
Finished Jul 20 06:08:54 PM PDT 24
Peak memory 200132 kb
Host smart-16437376-0c19-4cfc-bc75-8e46d8f3575d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002485731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3002485731
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1896278835
Short name T1164
Test name
Test status
Simulation time 18026663107 ps
CPU time 13.23 seconds
Started Jul 20 06:08:45 PM PDT 24
Finished Jul 20 06:08:59 PM PDT 24
Peak memory 200192 kb
Host smart-590c0db4-1b7b-487f-9f76-3faf8929e64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896278835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1896278835
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2540484888
Short name T686
Test name
Test status
Simulation time 66637813386 ps
CPU time 42.32 seconds
Started Jul 20 06:08:44 PM PDT 24
Finished Jul 20 06:09:28 PM PDT 24
Peak memory 200120 kb
Host smart-6953d870-886f-4f00-bb10-17eda2a04932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540484888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2540484888
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.4072897024
Short name T862
Test name
Test status
Simulation time 8901232304 ps
CPU time 24.33 seconds
Started Jul 20 06:08:40 PM PDT 24
Finished Jul 20 06:09:05 PM PDT 24
Peak memory 200144 kb
Host smart-ea8b4dea-7caa-48d2-a55e-704f026d7c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072897024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.4072897024
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.608964634
Short name T730
Test name
Test status
Simulation time 18821496494 ps
CPU time 30.37 seconds
Started Jul 20 06:08:44 PM PDT 24
Finished Jul 20 06:09:16 PM PDT 24
Peak memory 200196 kb
Host smart-80ff0bfd-4bcd-4317-b91c-9b1dcf02f973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608964634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.608964634
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3320310664
Short name T913
Test name
Test status
Simulation time 12689355731 ps
CPU time 19.14 seconds
Started Jul 20 06:08:44 PM PDT 24
Finished Jul 20 06:09:05 PM PDT 24
Peak memory 200116 kb
Host smart-5b6845f8-9c8a-43a6-be8c-5628dd5c72aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320310664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3320310664
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3355280530
Short name T97
Test name
Test status
Simulation time 140061422072 ps
CPU time 57.24 seconds
Started Jul 20 06:08:41 PM PDT 24
Finished Jul 20 06:09:39 PM PDT 24
Peak memory 200100 kb
Host smart-e9754b40-a3fb-48b9-b538-88800f304f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355280530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3355280530
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3702371528
Short name T675
Test name
Test status
Simulation time 33062796 ps
CPU time 0.55 seconds
Started Jul 20 06:04:06 PM PDT 24
Finished Jul 20 06:04:07 PM PDT 24
Peak memory 195880 kb
Host smart-ac61ede1-1177-4ce6-854b-890450b2b223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702371528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3702371528
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.79335199
Short name T809
Test name
Test status
Simulation time 38759089249 ps
CPU time 16.91 seconds
Started Jul 20 06:03:57 PM PDT 24
Finished Jul 20 06:04:14 PM PDT 24
Peak memory 200148 kb
Host smart-f6421886-22c1-4913-a523-edc7bb93c32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79335199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.79335199
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1107334960
Short name T395
Test name
Test status
Simulation time 10390400838 ps
CPU time 11.74 seconds
Started Jul 20 06:04:00 PM PDT 24
Finished Jul 20 06:04:12 PM PDT 24
Peak memory 199672 kb
Host smart-28d62cb1-3240-4565-bd72-08bd49a367b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107334960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1107334960
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.921173857
Short name T882
Test name
Test status
Simulation time 42992902481 ps
CPU time 20.7 seconds
Started Jul 20 06:03:58 PM PDT 24
Finished Jul 20 06:04:19 PM PDT 24
Peak memory 200176 kb
Host smart-866dc0c8-7dba-45a3-ae9e-f46a2047e2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921173857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.921173857
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1038332592
Short name T870
Test name
Test status
Simulation time 23624790137 ps
CPU time 20.95 seconds
Started Jul 20 06:04:11 PM PDT 24
Finished Jul 20 06:04:32 PM PDT 24
Peak memory 199968 kb
Host smart-b63c8e25-bc1c-4df5-9b7b-425ffb312203
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038332592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1038332592
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.4199033919
Short name T952
Test name
Test status
Simulation time 88391882848 ps
CPU time 528.93 seconds
Started Jul 20 06:04:07 PM PDT 24
Finished Jul 20 06:12:57 PM PDT 24
Peak memory 200116 kb
Host smart-538dac00-1074-4049-ac1f-ef4f0935fef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199033919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.4199033919
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1503288786
Short name T1142
Test name
Test status
Simulation time 7752852837 ps
CPU time 13.45 seconds
Started Jul 20 06:04:08 PM PDT 24
Finished Jul 20 06:04:22 PM PDT 24
Peak memory 200004 kb
Host smart-2912756a-33b4-4bc9-ba5c-aa2a3174f06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503288786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1503288786
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.16119087
Short name T742
Test name
Test status
Simulation time 94353873737 ps
CPU time 169.75 seconds
Started Jul 20 06:04:08 PM PDT 24
Finished Jul 20 06:06:58 PM PDT 24
Peak memory 200272 kb
Host smart-e688e3cc-b611-44e1-a0f3-337eee18684f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16119087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.16119087
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.357538494
Short name T415
Test name
Test status
Simulation time 20020721209 ps
CPU time 588.13 seconds
Started Jul 20 06:04:07 PM PDT 24
Finished Jul 20 06:13:56 PM PDT 24
Peak memory 200204 kb
Host smart-0eac9a72-c968-43cd-b8b6-b0b292663e15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=357538494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.357538494
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1110139910
Short name T448
Test name
Test status
Simulation time 4703730084 ps
CPU time 22.29 seconds
Started Jul 20 06:04:10 PM PDT 24
Finished Jul 20 06:04:33 PM PDT 24
Peak memory 199148 kb
Host smart-11ae14b2-2729-44af-8ebb-3515c0f1ccbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1110139910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1110139910
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3037094057
Short name T177
Test name
Test status
Simulation time 36165904295 ps
CPU time 55.74 seconds
Started Jul 20 06:04:08 PM PDT 24
Finished Jul 20 06:05:05 PM PDT 24
Peak memory 200064 kb
Host smart-2b084024-6a5e-465b-b7ca-d100d95b09c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037094057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3037094057
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2577578932
Short name T416
Test name
Test status
Simulation time 2833710345 ps
CPU time 5.01 seconds
Started Jul 20 06:04:08 PM PDT 24
Finished Jul 20 06:04:14 PM PDT 24
Peak memory 196204 kb
Host smart-70956f91-3de6-4d40-b85e-4ff738046308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577578932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2577578932
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3789449175
Short name T362
Test name
Test status
Simulation time 5725692631 ps
CPU time 16.41 seconds
Started Jul 20 06:04:02 PM PDT 24
Finished Jul 20 06:04:18 PM PDT 24
Peak memory 200172 kb
Host smart-93e989ef-e08c-4e8e-8dd0-d61395765f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789449175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3789449175
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3215091883
Short name T700
Test name
Test status
Simulation time 173351814356 ps
CPU time 1102.52 seconds
Started Jul 20 06:04:07 PM PDT 24
Finished Jul 20 06:22:30 PM PDT 24
Peak memory 208660 kb
Host smart-a233c7b6-e5cc-474a-adf3-db40d49d9b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215091883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3215091883
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1009788107
Short name T50
Test name
Test status
Simulation time 30580510148 ps
CPU time 250.53 seconds
Started Jul 20 06:04:06 PM PDT 24
Finished Jul 20 06:08:17 PM PDT 24
Peak memory 216576 kb
Host smart-024d8cef-d398-4437-95dc-1c4edaa9d57a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009788107 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1009788107
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.801061012
Short name T347
Test name
Test status
Simulation time 4130954992 ps
CPU time 2.2 seconds
Started Jul 20 06:04:06 PM PDT 24
Finished Jul 20 06:04:09 PM PDT 24
Peak memory 199260 kb
Host smart-8e221381-650c-4b7a-b9f0-336fc759fa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801061012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.801061012
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3004741433
Short name T283
Test name
Test status
Simulation time 28574120456 ps
CPU time 46.63 seconds
Started Jul 20 06:03:57 PM PDT 24
Finished Jul 20 06:04:44 PM PDT 24
Peak memory 200180 kb
Host smart-808c8f6e-7739-45c7-a711-114ee59752fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004741433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3004741433
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1154567437
Short name T820
Test name
Test status
Simulation time 49782215698 ps
CPU time 18.2 seconds
Started Jul 20 06:08:43 PM PDT 24
Finished Jul 20 06:09:02 PM PDT 24
Peak memory 200056 kb
Host smart-148f040b-a0a0-4607-a87c-08f4a708f5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154567437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1154567437
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1699109846
Short name T169
Test name
Test status
Simulation time 21373943918 ps
CPU time 18.77 seconds
Started Jul 20 06:08:46 PM PDT 24
Finished Jul 20 06:09:06 PM PDT 24
Peak memory 200188 kb
Host smart-69171d69-c7c0-4bdb-8b5b-53f89a3080c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699109846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1699109846
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2843241423
Short name T335
Test name
Test status
Simulation time 55708518182 ps
CPU time 188.98 seconds
Started Jul 20 06:08:46 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 200188 kb
Host smart-d3d3fbf7-9eaa-4c77-bd75-31a8913d0537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843241423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2843241423
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1745638210
Short name T560
Test name
Test status
Simulation time 89657524200 ps
CPU time 123.12 seconds
Started Jul 20 06:08:44 PM PDT 24
Finished Jul 20 06:10:48 PM PDT 24
Peak memory 200072 kb
Host smart-697e9b39-90f7-471c-a641-4aeebe59845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745638210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1745638210
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3510731664
Short name T1167
Test name
Test status
Simulation time 196847982491 ps
CPU time 51.82 seconds
Started Jul 20 06:08:45 PM PDT 24
Finished Jul 20 06:09:38 PM PDT 24
Peak memory 200072 kb
Host smart-a7794538-e8d9-4db8-bd33-e57e19a723f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510731664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3510731664
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3205789220
Short name T277
Test name
Test status
Simulation time 49893626465 ps
CPU time 36.65 seconds
Started Jul 20 06:08:44 PM PDT 24
Finished Jul 20 06:09:21 PM PDT 24
Peak memory 200196 kb
Host smart-93d42b67-d1ee-41b0-90f0-a26f1ba5b69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205789220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3205789220
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3402692791
Short name T121
Test name
Test status
Simulation time 80244845837 ps
CPU time 27.91 seconds
Started Jul 20 06:08:44 PM PDT 24
Finished Jul 20 06:09:13 PM PDT 24
Peak memory 200124 kb
Host smart-149b8f31-996e-47e3-a62c-dfb8a379bd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402692791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3402692791
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2540404840
Short name T227
Test name
Test status
Simulation time 84695771394 ps
CPU time 38.05 seconds
Started Jul 20 06:08:44 PM PDT 24
Finished Jul 20 06:09:23 PM PDT 24
Peak memory 200156 kb
Host smart-b341807a-26d6-4cca-a119-388ac1ec7e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540404840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2540404840
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3766049840
Short name T881
Test name
Test status
Simulation time 4938730450 ps
CPU time 8.95 seconds
Started Jul 20 06:08:46 PM PDT 24
Finished Jul 20 06:08:56 PM PDT 24
Peak memory 200132 kb
Host smart-35fa8c86-832a-4b5d-8443-3b36aceda54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766049840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3766049840
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.58542450
Short name T847
Test name
Test status
Simulation time 43864048 ps
CPU time 0.57 seconds
Started Jul 20 06:04:16 PM PDT 24
Finished Jul 20 06:04:17 PM PDT 24
Peak memory 195528 kb
Host smart-40920ab7-7e23-4b8b-9778-5663776c02f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58542450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.58542450
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2596300379
Short name T1144
Test name
Test status
Simulation time 55060061465 ps
CPU time 20.97 seconds
Started Jul 20 06:04:11 PM PDT 24
Finished Jul 20 06:04:32 PM PDT 24
Peak memory 200148 kb
Host smart-87542a9d-84c0-4448-b69e-5768c6dbcd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596300379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2596300379
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.590191507
Short name T477
Test name
Test status
Simulation time 54944903086 ps
CPU time 105.68 seconds
Started Jul 20 06:04:08 PM PDT 24
Finished Jul 20 06:05:55 PM PDT 24
Peak memory 200172 kb
Host smart-0dd6b0ae-f4b0-43a0-8376-e5e462e7c398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590191507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.590191507
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.4149151684
Short name T422
Test name
Test status
Simulation time 41457829662 ps
CPU time 15.19 seconds
Started Jul 20 06:04:11 PM PDT 24
Finished Jul 20 06:04:27 PM PDT 24
Peak memory 199224 kb
Host smart-fe8c97a2-f9f1-489f-a543-a3a06cce71fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149151684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.4149151684
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1088818410
Short name T445
Test name
Test status
Simulation time 43231531891 ps
CPU time 376.13 seconds
Started Jul 20 06:04:16 PM PDT 24
Finished Jul 20 06:10:33 PM PDT 24
Peak memory 200032 kb
Host smart-294143e1-2352-449d-ac2c-5506ec857046
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088818410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1088818410
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.350977619
Short name T342
Test name
Test status
Simulation time 7383359968 ps
CPU time 6.37 seconds
Started Jul 20 06:04:13 PM PDT 24
Finished Jul 20 06:04:20 PM PDT 24
Peak memory 199840 kb
Host smart-88d66814-4703-4ff0-b894-29a91c3cbc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350977619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.350977619
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3408690261
Short name T1093
Test name
Test status
Simulation time 31941767760 ps
CPU time 51.15 seconds
Started Jul 20 06:04:16 PM PDT 24
Finished Jul 20 06:05:07 PM PDT 24
Peak memory 200304 kb
Host smart-24ac806f-efa5-412b-92af-9bc613ad1d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408690261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3408690261
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2355978682
Short name T524
Test name
Test status
Simulation time 21090766457 ps
CPU time 59.01 seconds
Started Jul 20 06:04:17 PM PDT 24
Finished Jul 20 06:05:17 PM PDT 24
Peak memory 200204 kb
Host smart-cb78d6ec-b95d-4965-a9e3-1647aa31267f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355978682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2355978682
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.780823926
Short name T663
Test name
Test status
Simulation time 2163196714 ps
CPU time 1.39 seconds
Started Jul 20 06:04:11 PM PDT 24
Finished Jul 20 06:04:12 PM PDT 24
Peak memory 198584 kb
Host smart-d2541714-f249-403c-bd2c-2bba34d2ad9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=780823926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.780823926
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1884968492
Short name T123
Test name
Test status
Simulation time 61242362608 ps
CPU time 13.72 seconds
Started Jul 20 06:04:17 PM PDT 24
Finished Jul 20 06:04:32 PM PDT 24
Peak memory 199848 kb
Host smart-29b00832-3050-4212-a2f9-8145a9887d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884968492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1884968492
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3235067069
Short name T538
Test name
Test status
Simulation time 5078756486 ps
CPU time 2.49 seconds
Started Jul 20 06:04:17 PM PDT 24
Finished Jul 20 06:04:21 PM PDT 24
Peak memory 196612 kb
Host smart-f3b657ad-e7ba-4278-b1d9-0f03c49f13ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235067069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3235067069
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3167496248
Short name T1061
Test name
Test status
Simulation time 902249687 ps
CPU time 2.04 seconds
Started Jul 20 06:04:10 PM PDT 24
Finished Jul 20 06:04:13 PM PDT 24
Peak memory 198564 kb
Host smart-569ddd1c-3f85-40d5-aa6a-fddab79a6625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167496248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3167496248
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.797443237
Short name T529
Test name
Test status
Simulation time 472586788188 ps
CPU time 352.09 seconds
Started Jul 20 06:04:14 PM PDT 24
Finished Jul 20 06:10:07 PM PDT 24
Peak memory 200172 kb
Host smart-15a2ca28-98b4-4c3b-8ff3-364d59f215dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797443237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.797443237
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.727396002
Short name T74
Test name
Test status
Simulation time 223239570450 ps
CPU time 637.92 seconds
Started Jul 20 06:04:21 PM PDT 24
Finished Jul 20 06:15:00 PM PDT 24
Peak memory 224992 kb
Host smart-e4106dea-7257-4ed9-8408-75003aa72621
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727396002 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.727396002
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4291939187
Short name T272
Test name
Test status
Simulation time 1067408945 ps
CPU time 1.48 seconds
Started Jul 20 06:04:17 PM PDT 24
Finished Jul 20 06:04:20 PM PDT 24
Peak memory 198828 kb
Host smart-b32f4b28-9eb8-461b-bb5a-8e374d87f37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291939187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4291939187
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1385418149
Short name T788
Test name
Test status
Simulation time 63210781623 ps
CPU time 8.52 seconds
Started Jul 20 06:04:08 PM PDT 24
Finished Jul 20 06:04:18 PM PDT 24
Peak memory 197308 kb
Host smart-2d467b43-0749-41a0-a6fc-8426566821a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385418149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1385418149
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1840377006
Short name T393
Test name
Test status
Simulation time 39220205263 ps
CPU time 57.65 seconds
Started Jul 20 06:08:44 PM PDT 24
Finished Jul 20 06:09:43 PM PDT 24
Peak memory 200200 kb
Host smart-2773860b-b8dd-45d8-ad94-fdbf2b0c62c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840377006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1840377006
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2806850980
Short name T790
Test name
Test status
Simulation time 77043846750 ps
CPU time 27.96 seconds
Started Jul 20 06:08:51 PM PDT 24
Finished Jul 20 06:09:20 PM PDT 24
Peak memory 200184 kb
Host smart-6a5d1ab3-941a-457b-8360-c90d43823ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806850980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2806850980
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1428518908
Short name T772
Test name
Test status
Simulation time 46397077178 ps
CPU time 66.25 seconds
Started Jul 20 06:08:52 PM PDT 24
Finished Jul 20 06:09:59 PM PDT 24
Peak memory 200200 kb
Host smart-6e68f8df-9dc2-4ffe-ad25-da568b37b7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428518908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1428518908
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.4232494916
Short name T1059
Test name
Test status
Simulation time 163346596804 ps
CPU time 269.81 seconds
Started Jul 20 06:08:53 PM PDT 24
Finished Jul 20 06:13:23 PM PDT 24
Peak memory 200192 kb
Host smart-2128cd37-9f75-4f90-9b83-bd80b92de125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232494916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.4232494916
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.898980483
Short name T873
Test name
Test status
Simulation time 126138096831 ps
CPU time 58.93 seconds
Started Jul 20 06:08:52 PM PDT 24
Finished Jul 20 06:09:52 PM PDT 24
Peak memory 200112 kb
Host smart-b3715648-9696-4754-af0a-808cf46f6dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898980483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.898980483
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.466584518
Short name T221
Test name
Test status
Simulation time 143763430917 ps
CPU time 69.58 seconds
Started Jul 20 06:08:53 PM PDT 24
Finished Jul 20 06:10:03 PM PDT 24
Peak memory 200128 kb
Host smart-c4a90610-8a61-4048-b63c-bb269d6073fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466584518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.466584518
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2162644186
Short name T822
Test name
Test status
Simulation time 49121058010 ps
CPU time 105.9 seconds
Started Jul 20 06:08:53 PM PDT 24
Finished Jul 20 06:10:39 PM PDT 24
Peak memory 200108 kb
Host smart-c7a8e4ca-9916-4499-b5bf-c9be63c88cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162644186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2162644186
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1264574171
Short name T1022
Test name
Test status
Simulation time 18429160 ps
CPU time 0.53 seconds
Started Jul 20 06:04:26 PM PDT 24
Finished Jul 20 06:04:27 PM PDT 24
Peak memory 195020 kb
Host smart-5aa0eaae-2bae-47d7-b98a-537f80dd8a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264574171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1264574171
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.138109213
Short name T269
Test name
Test status
Simulation time 98341956812 ps
CPU time 259.25 seconds
Started Jul 20 06:04:18 PM PDT 24
Finished Jul 20 06:08:38 PM PDT 24
Peak memory 200196 kb
Host smart-3e282bdb-9713-4a34-95d5-d605616fac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138109213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.138109213
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3244318014
Short name T147
Test name
Test status
Simulation time 25378627209 ps
CPU time 11.74 seconds
Started Jul 20 06:04:18 PM PDT 24
Finished Jul 20 06:04:31 PM PDT 24
Peak memory 200192 kb
Host smart-15e4eefc-1ac7-4301-b02c-8e16abfa4c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244318014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3244318014
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.3302758761
Short name T372
Test name
Test status
Simulation time 333425609433 ps
CPU time 459.62 seconds
Started Jul 20 06:04:16 PM PDT 24
Finished Jul 20 06:11:57 PM PDT 24
Peak memory 200192 kb
Host smart-7af2667c-cddc-41f9-bb2c-cb11bcc0c5b1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302758761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3302758761
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.419730624
Short name T1047
Test name
Test status
Simulation time 88397141847 ps
CPU time 848.81 seconds
Started Jul 20 06:04:16 PM PDT 24
Finished Jul 20 06:18:25 PM PDT 24
Peak memory 200092 kb
Host smart-f4b23567-7350-4aa4-9757-f2e9a93c7965
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419730624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.419730624
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1720008661
Short name T690
Test name
Test status
Simulation time 3026991661 ps
CPU time 8.68 seconds
Started Jul 20 06:04:15 PM PDT 24
Finished Jul 20 06:04:24 PM PDT 24
Peak memory 199160 kb
Host smart-335bd413-026e-4019-a612-f64bdd1fe89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720008661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1720008661
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1770831324
Short name T674
Test name
Test status
Simulation time 206237509833 ps
CPU time 42.98 seconds
Started Jul 20 06:04:20 PM PDT 24
Finished Jul 20 06:05:03 PM PDT 24
Peak memory 199752 kb
Host smart-ac6c5d85-ebf9-458e-b935-d650f6508eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770831324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1770831324
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.4279903789
Short name T599
Test name
Test status
Simulation time 24201577241 ps
CPU time 144.93 seconds
Started Jul 20 06:04:17 PM PDT 24
Finished Jul 20 06:06:43 PM PDT 24
Peak memory 200152 kb
Host smart-0bb45892-8f82-4313-bc43-fc9b6f8a79b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279903789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.4279903789
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3280808980
Short name T983
Test name
Test status
Simulation time 2199063183 ps
CPU time 6.58 seconds
Started Jul 20 06:04:20 PM PDT 24
Finished Jul 20 06:04:27 PM PDT 24
Peak memory 198424 kb
Host smart-171d3d81-e46c-4eb3-af7e-e1ed33cac0a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3280808980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3280808980
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.385397212
Short name T148
Test name
Test status
Simulation time 198947590056 ps
CPU time 59.77 seconds
Started Jul 20 06:04:17 PM PDT 24
Finished Jul 20 06:05:17 PM PDT 24
Peak memory 200016 kb
Host smart-36ebb52f-267d-4e93-a7f6-c97983d20f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385397212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.385397212
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2380628271
Short name T428
Test name
Test status
Simulation time 34125666094 ps
CPU time 54.28 seconds
Started Jul 20 06:04:18 PM PDT 24
Finished Jul 20 06:05:13 PM PDT 24
Peak memory 195992 kb
Host smart-4cad75c3-f648-4552-8286-c7c83e856f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380628271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2380628271
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.430161538
Short name T306
Test name
Test status
Simulation time 324034644 ps
CPU time 1.34 seconds
Started Jul 20 06:04:16 PM PDT 24
Finished Jul 20 06:04:18 PM PDT 24
Peak memory 200092 kb
Host smart-b6d3365a-01a0-47fb-bda8-8e8c7c0bede9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430161538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.430161538
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2813705377
Short name T754
Test name
Test status
Simulation time 334230660153 ps
CPU time 550.61 seconds
Started Jul 20 06:04:16 PM PDT 24
Finished Jul 20 06:13:27 PM PDT 24
Peak memory 208508 kb
Host smart-5aff75c3-d652-41d2-b846-b7b191087824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813705377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2813705377
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2961325525
Short name T636
Test name
Test status
Simulation time 321094292 ps
CPU time 1.23 seconds
Started Jul 20 06:04:17 PM PDT 24
Finished Jul 20 06:04:19 PM PDT 24
Peak memory 197560 kb
Host smart-8a782965-fbe6-4469-b5cc-a5ab6bbfc8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961325525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2961325525
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2432204143
Short name T1004
Test name
Test status
Simulation time 7523627744 ps
CPU time 11.06 seconds
Started Jul 20 06:04:16 PM PDT 24
Finished Jul 20 06:04:28 PM PDT 24
Peak memory 197148 kb
Host smart-f2d4f740-2dc8-436f-b724-eb002514dcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432204143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2432204143
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3609606853
Short name T1046
Test name
Test status
Simulation time 96643395357 ps
CPU time 151.85 seconds
Started Jul 20 06:08:51 PM PDT 24
Finished Jul 20 06:11:24 PM PDT 24
Peak memory 200184 kb
Host smart-6cbba8fe-1759-4194-80a4-dfe290e7ebe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609606853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3609606853
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3469568195
Short name T1080
Test name
Test status
Simulation time 81736640084 ps
CPU time 125.91 seconds
Started Jul 20 06:08:51 PM PDT 24
Finished Jul 20 06:10:57 PM PDT 24
Peak memory 200088 kb
Host smart-02b398e7-c5fc-442a-b6f2-21ffa4eeb23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469568195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3469568195
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3297924643
Short name T186
Test name
Test status
Simulation time 66918990654 ps
CPU time 142.49 seconds
Started Jul 20 06:08:53 PM PDT 24
Finished Jul 20 06:11:16 PM PDT 24
Peak memory 200196 kb
Host smart-7ec44ab8-fe02-4fd1-b1ce-c2887c29efee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297924643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3297924643
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2947208312
Short name T516
Test name
Test status
Simulation time 83306303007 ps
CPU time 23.54 seconds
Started Jul 20 06:08:52 PM PDT 24
Finished Jul 20 06:09:16 PM PDT 24
Peak memory 200072 kb
Host smart-cf36856d-f5c7-4c0d-a1e2-fcfcdbfde9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947208312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2947208312
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2160734502
Short name T214
Test name
Test status
Simulation time 181666074643 ps
CPU time 177.43 seconds
Started Jul 20 06:08:51 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 200048 kb
Host smart-9f8a45e3-33eb-41ce-a6a4-9509d1ebfbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160734502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2160734502
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1251488873
Short name T224
Test name
Test status
Simulation time 66164708804 ps
CPU time 26.64 seconds
Started Jul 20 06:08:53 PM PDT 24
Finished Jul 20 06:09:20 PM PDT 24
Peak memory 200128 kb
Host smart-b6232bbc-e18d-4c81-84e9-ae20aea8a18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251488873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1251488873
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.642050718
Short name T207
Test name
Test status
Simulation time 101133726030 ps
CPU time 41.67 seconds
Started Jul 20 06:08:50 PM PDT 24
Finished Jul 20 06:09:32 PM PDT 24
Peak memory 200008 kb
Host smart-39e26f7b-cb60-4b5a-be5f-23f2b714d088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642050718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.642050718
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2331354670
Short name T941
Test name
Test status
Simulation time 63208155564 ps
CPU time 22.38 seconds
Started Jul 20 06:08:51 PM PDT 24
Finished Jul 20 06:09:14 PM PDT 24
Peak memory 199012 kb
Host smart-11240fc9-dc4a-4881-87d6-c482660eb603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331354670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2331354670
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2288132608
Short name T767
Test name
Test status
Simulation time 13982533 ps
CPU time 0.53 seconds
Started Jul 20 06:04:34 PM PDT 24
Finished Jul 20 06:04:35 PM PDT 24
Peak memory 194524 kb
Host smart-44d0e027-6d1d-49fc-a2c5-99d358f6c06f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288132608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2288132608
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3544323618
Short name T667
Test name
Test status
Simulation time 45161327754 ps
CPU time 62.63 seconds
Started Jul 20 06:04:28 PM PDT 24
Finished Jul 20 06:05:31 PM PDT 24
Peak memory 200124 kb
Host smart-09077f13-2cfe-415e-b0b5-c5b88ca986af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544323618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3544323618
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2412984421
Short name T1086
Test name
Test status
Simulation time 194240675649 ps
CPU time 31.9 seconds
Started Jul 20 06:04:24 PM PDT 24
Finished Jul 20 06:04:57 PM PDT 24
Peak memory 200120 kb
Host smart-43217f8c-b712-4351-b8c7-eedaa8d082e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412984421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2412984421
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1675226212
Short name T774
Test name
Test status
Simulation time 12684011280 ps
CPU time 18.49 seconds
Started Jul 20 06:04:24 PM PDT 24
Finished Jul 20 06:04:43 PM PDT 24
Peak memory 200032 kb
Host smart-14c34c0d-9d89-4dce-b5e4-ffaa5cf2425e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675226212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1675226212
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2294020068
Short name T701
Test name
Test status
Simulation time 20752104565 ps
CPU time 6.38 seconds
Started Jul 20 06:04:26 PM PDT 24
Finished Jul 20 06:04:33 PM PDT 24
Peak memory 200200 kb
Host smart-9facab1b-46cd-4c4d-a4d7-e6b636d8ea0f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294020068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2294020068
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3308188068
Short name T902
Test name
Test status
Simulation time 55257584826 ps
CPU time 113.58 seconds
Started Jul 20 06:04:28 PM PDT 24
Finished Jul 20 06:06:23 PM PDT 24
Peak memory 200180 kb
Host smart-2f7ad5cc-57a8-43d1-a522-1710faae65b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308188068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3308188068
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1643009586
Short name T18
Test name
Test status
Simulation time 5224196476 ps
CPU time 6.06 seconds
Started Jul 20 06:04:26 PM PDT 24
Finished Jul 20 06:04:33 PM PDT 24
Peak memory 198756 kb
Host smart-07424546-75e6-4083-a9a0-e394de43593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643009586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1643009586
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1346687272
Short name T1085
Test name
Test status
Simulation time 58939509261 ps
CPU time 25.25 seconds
Started Jul 20 06:04:26 PM PDT 24
Finished Jul 20 06:04:52 PM PDT 24
Peak memory 200168 kb
Host smart-5550c468-602d-40bb-b916-3e25af121e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346687272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1346687272
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3345116609
Short name T1006
Test name
Test status
Simulation time 17461946965 ps
CPU time 138.84 seconds
Started Jul 20 06:04:26 PM PDT 24
Finished Jul 20 06:06:46 PM PDT 24
Peak memory 200148 kb
Host smart-7c9ccbcc-57ba-4f4d-9a94-5bc1a6373238
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345116609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3345116609
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2561212914
Short name T37
Test name
Test status
Simulation time 6188450871 ps
CPU time 13.07 seconds
Started Jul 20 06:04:29 PM PDT 24
Finished Jul 20 06:04:42 PM PDT 24
Peak memory 199420 kb
Host smart-43ee53cf-f798-4f35-bbb1-3eebfec51d7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2561212914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2561212914
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1774695711
Short name T928
Test name
Test status
Simulation time 138966641594 ps
CPU time 121.61 seconds
Started Jul 20 06:04:29 PM PDT 24
Finished Jul 20 06:06:31 PM PDT 24
Peak memory 200068 kb
Host smart-af6acb26-a14a-4baa-9faa-f1cc6d9b79e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774695711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1774695711
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2589789498
Short name T1145
Test name
Test status
Simulation time 23939909358 ps
CPU time 19.16 seconds
Started Jul 20 06:04:27 PM PDT 24
Finished Jul 20 06:04:47 PM PDT 24
Peak memory 196964 kb
Host smart-dd0de29b-7d1a-4ff5-bdc1-7d39be10ad5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589789498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2589789498
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3492005685
Short name T794
Test name
Test status
Simulation time 1001771573 ps
CPU time 2.13 seconds
Started Jul 20 06:04:26 PM PDT 24
Finished Jul 20 06:04:29 PM PDT 24
Peak memory 200012 kb
Host smart-fa16c787-092c-4ddc-89ed-4bc9907cb891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492005685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3492005685
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.304533197
Short name T714
Test name
Test status
Simulation time 204131006751 ps
CPU time 351.81 seconds
Started Jul 20 06:04:24 PM PDT 24
Finished Jul 20 06:10:16 PM PDT 24
Peak memory 200280 kb
Host smart-782d3e24-7ecc-4552-a154-12234e3776ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304533197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.304533197
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1530325618
Short name T106
Test name
Test status
Simulation time 108741795860 ps
CPU time 355.56 seconds
Started Jul 20 06:04:25 PM PDT 24
Finished Jul 20 06:10:21 PM PDT 24
Peak memory 216520 kb
Host smart-0aaab092-6c4e-4c53-8cd3-1dc450e618c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530325618 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1530325618
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1776449555
Short name T699
Test name
Test status
Simulation time 1211592706 ps
CPU time 1.21 seconds
Started Jul 20 06:04:28 PM PDT 24
Finished Jul 20 06:04:30 PM PDT 24
Peak memory 196868 kb
Host smart-22c5f11d-df03-41f7-8ce2-99865c6ff88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776449555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1776449555
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2119800932
Short name T547
Test name
Test status
Simulation time 55600967530 ps
CPU time 44.36 seconds
Started Jul 20 06:04:25 PM PDT 24
Finished Jul 20 06:05:10 PM PDT 24
Peak memory 200180 kb
Host smart-8e3396c1-3f48-4b39-93b8-8f60430f2409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119800932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2119800932
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.4135220214
Short name T285
Test name
Test status
Simulation time 59195983051 ps
CPU time 36.07 seconds
Started Jul 20 06:09:06 PM PDT 24
Finished Jul 20 06:09:43 PM PDT 24
Peak memory 200100 kb
Host smart-084c6610-e577-4849-be66-c7f7892f1db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135220214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.4135220214
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3207401867
Short name T901
Test name
Test status
Simulation time 23592242296 ps
CPU time 11.11 seconds
Started Jul 20 06:09:04 PM PDT 24
Finished Jul 20 06:09:16 PM PDT 24
Peak memory 200100 kb
Host smart-792b8562-b8ef-4b63-8368-aae9cd5a6c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207401867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3207401867
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.580573504
Short name T183
Test name
Test status
Simulation time 32672791523 ps
CPU time 58.5 seconds
Started Jul 20 06:09:01 PM PDT 24
Finished Jul 20 06:09:59 PM PDT 24
Peak memory 200128 kb
Host smart-32a5dc94-74f3-46ea-8d38-11031cdddbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580573504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.580573504
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.471747673
Short name T193
Test name
Test status
Simulation time 51812780078 ps
CPU time 26.04 seconds
Started Jul 20 06:09:05 PM PDT 24
Finished Jul 20 06:09:32 PM PDT 24
Peak memory 200184 kb
Host smart-72b4ac1c-8e4b-471b-a87c-54e2f131c91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471747673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.471747673
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3048645222
Short name T746
Test name
Test status
Simulation time 96276291998 ps
CPU time 132.68 seconds
Started Jul 20 06:08:56 PM PDT 24
Finished Jul 20 06:11:09 PM PDT 24
Peak memory 200132 kb
Host smart-400d7a00-d4c1-44fc-bb28-6a6b4561ba22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048645222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3048645222
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1892315171
Short name T191
Test name
Test status
Simulation time 27479088347 ps
CPU time 36.04 seconds
Started Jul 20 06:09:05 PM PDT 24
Finished Jul 20 06:09:41 PM PDT 24
Peak memory 200096 kb
Host smart-f0eeee1f-3686-49af-a5cb-b040a044d818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892315171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1892315171
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.4188782810
Short name T161
Test name
Test status
Simulation time 83551285746 ps
CPU time 74.73 seconds
Started Jul 20 06:08:59 PM PDT 24
Finished Jul 20 06:10:14 PM PDT 24
Peak memory 200088 kb
Host smart-25a9fdeb-c240-446e-b980-a6fe541d954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188782810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.4188782810
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2907186999
Short name T483
Test name
Test status
Simulation time 49694332 ps
CPU time 0.57 seconds
Started Jul 20 06:04:37 PM PDT 24
Finished Jul 20 06:04:38 PM PDT 24
Peak memory 195852 kb
Host smart-41521eba-6f3b-4a06-94d3-3a60bcbeed33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907186999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2907186999
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.224021633
Short name T127
Test name
Test status
Simulation time 102589136772 ps
CPU time 20.62 seconds
Started Jul 20 06:04:34 PM PDT 24
Finished Jul 20 06:04:56 PM PDT 24
Peak memory 200100 kb
Host smart-4155d86d-6c38-4011-9032-fc93e97a50d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224021633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.224021633
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2196592592
Short name T360
Test name
Test status
Simulation time 35667874757 ps
CPU time 40.2 seconds
Started Jul 20 06:04:35 PM PDT 24
Finished Jul 20 06:05:16 PM PDT 24
Peak memory 199648 kb
Host smart-6efea5b5-06bb-46ff-87c0-52a6d28d8cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196592592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2196592592
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2757979922
Short name T566
Test name
Test status
Simulation time 15005373692 ps
CPU time 5.75 seconds
Started Jul 20 06:04:35 PM PDT 24
Finished Jul 20 06:04:41 PM PDT 24
Peak memory 199380 kb
Host smart-0c808081-078c-42ab-9169-81bc66830dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757979922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2757979922
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.732843013
Short name T612
Test name
Test status
Simulation time 133260655490 ps
CPU time 321.58 seconds
Started Jul 20 06:04:36 PM PDT 24
Finished Jul 20 06:09:58 PM PDT 24
Peak memory 200072 kb
Host smart-45e5b3c6-b7e3-481e-b146-e1046877ab2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732843013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.732843013
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2139727271
Short name T1165
Test name
Test status
Simulation time 37790389347 ps
CPU time 40.88 seconds
Started Jul 20 06:04:36 PM PDT 24
Finished Jul 20 06:05:17 PM PDT 24
Peak memory 200168 kb
Host smart-9fb7fe58-5475-4f14-8932-2d0947032b55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139727271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2139727271
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.1416783725
Short name T1124
Test name
Test status
Simulation time 11208003255 ps
CPU time 19.34 seconds
Started Jul 20 06:04:38 PM PDT 24
Finished Jul 20 06:04:58 PM PDT 24
Peak memory 200132 kb
Host smart-a964ef03-72b6-4f00-9459-766bad9839e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416783725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1416783725
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.689012152
Short name T1078
Test name
Test status
Simulation time 151356182544 ps
CPU time 66.69 seconds
Started Jul 20 06:04:33 PM PDT 24
Finished Jul 20 06:05:40 PM PDT 24
Peak memory 208452 kb
Host smart-0cd16444-34f1-478e-8882-252a86d8a980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689012152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.689012152
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2228245212
Short name T782
Test name
Test status
Simulation time 20485870974 ps
CPU time 990.33 seconds
Started Jul 20 06:04:37 PM PDT 24
Finished Jul 20 06:21:08 PM PDT 24
Peak memory 200104 kb
Host smart-c4151f7f-de0d-46ec-b65f-db6b2db20dca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2228245212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2228245212
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.607701147
Short name T100
Test name
Test status
Simulation time 5795873555 ps
CPU time 9.89 seconds
Started Jul 20 06:04:37 PM PDT 24
Finished Jul 20 06:04:47 PM PDT 24
Peak memory 199196 kb
Host smart-40715ff8-6e0c-44e7-8f92-9700087a3e1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607701147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.607701147
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1806019373
Short name T734
Test name
Test status
Simulation time 217081777378 ps
CPU time 22 seconds
Started Jul 20 06:04:37 PM PDT 24
Finished Jul 20 06:04:59 PM PDT 24
Peak memory 200004 kb
Host smart-58504d89-db36-4d6a-8b8a-36a1a2944aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806019373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1806019373
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.25800562
Short name T585
Test name
Test status
Simulation time 2044582104 ps
CPU time 3.57 seconds
Started Jul 20 06:04:34 PM PDT 24
Finished Jul 20 06:04:39 PM PDT 24
Peak memory 195660 kb
Host smart-1466b4be-28d9-48c1-b55e-8056d08f3245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25800562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.25800562
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3393156702
Short name T465
Test name
Test status
Simulation time 533798907 ps
CPU time 1.36 seconds
Started Jul 20 06:04:35 PM PDT 24
Finished Jul 20 06:04:37 PM PDT 24
Peak memory 198632 kb
Host smart-af5ec5c7-5607-4898-9f70-333add5e429d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393156702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3393156702
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.944748977
Short name T1120
Test name
Test status
Simulation time 118108726157 ps
CPU time 77.72 seconds
Started Jul 20 06:04:38 PM PDT 24
Finished Jul 20 06:05:57 PM PDT 24
Peak memory 200124 kb
Host smart-1684bf28-ebaf-4a1f-8212-efb9d3db575e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944748977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.944748977
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2727181628
Short name T892
Test name
Test status
Simulation time 54753605525 ps
CPU time 1517.59 seconds
Started Jul 20 06:04:34 PM PDT 24
Finished Jul 20 06:29:53 PM PDT 24
Peak memory 216600 kb
Host smart-ec19cb0c-b3ce-48e5-8f00-c031f9bc8d87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727181628 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2727181628
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3421918252
Short name T407
Test name
Test status
Simulation time 470743400 ps
CPU time 2.04 seconds
Started Jul 20 06:04:38 PM PDT 24
Finished Jul 20 06:04:41 PM PDT 24
Peak memory 200060 kb
Host smart-29937738-a042-44d6-9011-d39f575dd94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421918252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3421918252
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1181744009
Short name T905
Test name
Test status
Simulation time 6841122855 ps
CPU time 12.22 seconds
Started Jul 20 06:08:58 PM PDT 24
Finished Jul 20 06:09:11 PM PDT 24
Peak memory 200128 kb
Host smart-8ed81339-ecbd-4f2e-be01-d83c1ad5c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181744009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1181744009
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3127661664
Short name T439
Test name
Test status
Simulation time 87154133855 ps
CPU time 239.35 seconds
Started Jul 20 06:09:01 PM PDT 24
Finished Jul 20 06:13:01 PM PDT 24
Peak memory 200196 kb
Host smart-2587e758-6e11-4dc9-acde-9ae69c61b679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127661664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3127661664
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.619810030
Short name T1148
Test name
Test status
Simulation time 34894289090 ps
CPU time 14.04 seconds
Started Jul 20 06:09:00 PM PDT 24
Finished Jul 20 06:09:14 PM PDT 24
Peak memory 200020 kb
Host smart-1d01f7ab-e604-41bf-a21b-7b8885fdfe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619810030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.619810030
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.81184273
Short name T305
Test name
Test status
Simulation time 18313596352 ps
CPU time 40.89 seconds
Started Jul 20 06:09:00 PM PDT 24
Finished Jul 20 06:09:41 PM PDT 24
Peak memory 200108 kb
Host smart-9f0181b1-ab17-48b3-92c3-a7e4598f3534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81184273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.81184273
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.758959907
Short name T472
Test name
Test status
Simulation time 117167747126 ps
CPU time 168.37 seconds
Started Jul 20 06:09:01 PM PDT 24
Finished Jul 20 06:11:49 PM PDT 24
Peak memory 200132 kb
Host smart-e5931f6b-8bf9-4561-8830-6a0d9c7dc1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758959907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.758959907
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1192750623
Short name T890
Test name
Test status
Simulation time 38026691590 ps
CPU time 29.74 seconds
Started Jul 20 06:08:58 PM PDT 24
Finished Jul 20 06:09:28 PM PDT 24
Peak memory 200188 kb
Host smart-352692bb-eb68-4e01-bca2-caa07b3e8b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192750623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1192750623
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2285706324
Short name T202
Test name
Test status
Simulation time 85194945895 ps
CPU time 100.35 seconds
Started Jul 20 06:09:03 PM PDT 24
Finished Jul 20 06:10:44 PM PDT 24
Peak memory 200024 kb
Host smart-29dbe8c6-00ed-4bb1-9845-4949abead197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285706324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2285706324
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1775519511
Short name T149
Test name
Test status
Simulation time 19106712778 ps
CPU time 33.58 seconds
Started Jul 20 06:08:57 PM PDT 24
Finished Jul 20 06:09:31 PM PDT 24
Peak memory 200200 kb
Host smart-98c3cd88-3b6f-4d68-8fbe-20d3e52a7f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775519511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1775519511
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1000896897
Short name T447
Test name
Test status
Simulation time 82268874388 ps
CPU time 29.61 seconds
Started Jul 20 06:09:06 PM PDT 24
Finished Jul 20 06:09:36 PM PDT 24
Peak memory 200072 kb
Host smart-f5e72eb8-083c-4f5f-b8a2-c4bedf3b718c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000896897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1000896897
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2842950646
Short name T533
Test name
Test status
Simulation time 66324664 ps
CPU time 0.55 seconds
Started Jul 20 06:04:41 PM PDT 24
Finished Jul 20 06:04:42 PM PDT 24
Peak memory 195580 kb
Host smart-6ccae2c6-8120-4a20-96de-b9fcf82eb77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842950646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2842950646
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1856515154
Short name T828
Test name
Test status
Simulation time 132255144841 ps
CPU time 50.52 seconds
Started Jul 20 06:04:37 PM PDT 24
Finished Jul 20 06:05:29 PM PDT 24
Peak memory 200180 kb
Host smart-665d8f73-9b0a-4678-9283-80a7b9bd1163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856515154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1856515154
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.658648244
Short name T709
Test name
Test status
Simulation time 98498884934 ps
CPU time 465.66 seconds
Started Jul 20 06:04:34 PM PDT 24
Finished Jul 20 06:12:21 PM PDT 24
Peak memory 200136 kb
Host smart-af5f20a3-9dac-415d-a07b-c053c77b302a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658648244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.658648244
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2598307792
Short name T319
Test name
Test status
Simulation time 123923261611 ps
CPU time 107.76 seconds
Started Jul 20 06:04:36 PM PDT 24
Finished Jul 20 06:06:24 PM PDT 24
Peak memory 200200 kb
Host smart-7b92f46e-2951-4b10-bb78-8c536f97f427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598307792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2598307792
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.484705775
Short name T489
Test name
Test status
Simulation time 41462557586 ps
CPU time 34.38 seconds
Started Jul 20 06:04:38 PM PDT 24
Finished Jul 20 06:05:13 PM PDT 24
Peak memory 200124 kb
Host smart-a4209da6-a8c0-4041-8aa8-48c34b26c4bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484705775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.484705775
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1107025993
Short name T530
Test name
Test status
Simulation time 161519244623 ps
CPU time 361.02 seconds
Started Jul 20 06:04:45 PM PDT 24
Finished Jul 20 06:10:47 PM PDT 24
Peak memory 200172 kb
Host smart-8b36a145-1f9f-4947-bc7c-dcc24be237ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1107025993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1107025993
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3024235580
Short name T798
Test name
Test status
Simulation time 1951003295 ps
CPU time 3.61 seconds
Started Jul 20 06:04:42 PM PDT 24
Finished Jul 20 06:04:46 PM PDT 24
Peak memory 198800 kb
Host smart-12742753-dc1e-451e-b91a-e189289c8a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024235580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3024235580
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2354540233
Short name T328
Test name
Test status
Simulation time 15836280608 ps
CPU time 28.13 seconds
Started Jul 20 06:04:36 PM PDT 24
Finished Jul 20 06:05:05 PM PDT 24
Peak memory 200280 kb
Host smart-2cd780b6-ff5a-4a2c-b911-70e2b1baff6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354540233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2354540233
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.311210972
Short name T705
Test name
Test status
Simulation time 19698994874 ps
CPU time 661.03 seconds
Started Jul 20 06:04:44 PM PDT 24
Finished Jul 20 06:15:46 PM PDT 24
Peak memory 200148 kb
Host smart-37a5a357-ff5d-4ac1-a215-84a45a02945e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311210972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.311210972
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1206493269
Short name T738
Test name
Test status
Simulation time 4436648095 ps
CPU time 40.16 seconds
Started Jul 20 06:04:34 PM PDT 24
Finished Jul 20 06:05:15 PM PDT 24
Peak memory 198304 kb
Host smart-f1fa58d0-e603-4283-afdf-1a5c0cd89c28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1206493269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1206493269
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.98346340
Short name T910
Test name
Test status
Simulation time 17456733761 ps
CPU time 7.01 seconds
Started Jul 20 06:04:43 PM PDT 24
Finished Jul 20 06:04:50 PM PDT 24
Peak memory 200116 kb
Host smart-a515e93b-679e-4246-8438-b5a3026b4b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98346340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.98346340
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1962076542
Short name T977
Test name
Test status
Simulation time 36326185713 ps
CPU time 14.17 seconds
Started Jul 20 06:04:34 PM PDT 24
Finished Jul 20 06:04:48 PM PDT 24
Peak memory 196184 kb
Host smart-6faee25e-840d-45da-b8e1-fe6529cc8b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962076542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1962076542
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.599426184
Short name T985
Test name
Test status
Simulation time 429379595 ps
CPU time 1.69 seconds
Started Jul 20 06:04:32 PM PDT 24
Finished Jul 20 06:04:35 PM PDT 24
Peak memory 199016 kb
Host smart-95af6de9-e0ae-4e4a-828d-1b98caa92610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599426184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.599426184
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2669526962
Short name T999
Test name
Test status
Simulation time 1047653906390 ps
CPU time 848.99 seconds
Started Jul 20 06:04:43 PM PDT 24
Finished Jul 20 06:18:53 PM PDT 24
Peak memory 225036 kb
Host smart-9f45301f-dc29-4ee4-8736-55c580c0213c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669526962 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2669526962
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1513646543
Short name T951
Test name
Test status
Simulation time 8983698811 ps
CPU time 1.68 seconds
Started Jul 20 06:04:43 PM PDT 24
Finished Jul 20 06:04:45 PM PDT 24
Peak memory 199364 kb
Host smart-ba9b1df4-cce1-45d1-a79c-810318e4c3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513646543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1513646543
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2464028902
Short name T634
Test name
Test status
Simulation time 46332128616 ps
CPU time 72.03 seconds
Started Jul 20 06:04:33 PM PDT 24
Finished Jul 20 06:05:46 PM PDT 24
Peak memory 200104 kb
Host smart-c9a79502-d100-4c7f-a8e7-482e3206e502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464028902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2464028902
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.919379545
Short name T1083
Test name
Test status
Simulation time 134782039234 ps
CPU time 28.04 seconds
Started Jul 20 06:09:07 PM PDT 24
Finished Jul 20 06:09:36 PM PDT 24
Peak memory 200132 kb
Host smart-7c1ac497-4b0d-45bd-925f-e200c400a4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919379545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.919379545
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3628219767
Short name T471
Test name
Test status
Simulation time 31312584308 ps
CPU time 24.75 seconds
Started Jul 20 06:09:07 PM PDT 24
Finished Jul 20 06:09:32 PM PDT 24
Peak memory 200148 kb
Host smart-d26ae94c-b7e0-400c-89e3-12b1e1c5a158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628219767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3628219767
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1487478277
Short name T992
Test name
Test status
Simulation time 37200113760 ps
CPU time 53.69 seconds
Started Jul 20 06:09:06 PM PDT 24
Finished Jul 20 06:10:00 PM PDT 24
Peak memory 200196 kb
Host smart-9fa5fb41-b282-40d6-8724-ab952e99e3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487478277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1487478277
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2523628924
Short name T614
Test name
Test status
Simulation time 168226933743 ps
CPU time 72.85 seconds
Started Jul 20 06:09:11 PM PDT 24
Finished Jul 20 06:10:25 PM PDT 24
Peak memory 200168 kb
Host smart-d68e99a7-2fb0-4b12-bcf2-6cb6b7221f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523628924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2523628924
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1107639032
Short name T1030
Test name
Test status
Simulation time 189710234089 ps
CPU time 17.85 seconds
Started Jul 20 06:09:07 PM PDT 24
Finished Jul 20 06:09:26 PM PDT 24
Peak memory 199924 kb
Host smart-127e506f-cbab-4205-bd02-1b22ca82b59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107639032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1107639032
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1104286010
Short name T1044
Test name
Test status
Simulation time 56238021265 ps
CPU time 22.87 seconds
Started Jul 20 06:09:05 PM PDT 24
Finished Jul 20 06:09:29 PM PDT 24
Peak memory 200180 kb
Host smart-c725c687-819a-4a8b-b9c9-aa10791c8c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104286010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1104286010
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.591162129
Short name T937
Test name
Test status
Simulation time 13832619006 ps
CPU time 6.46 seconds
Started Jul 20 06:09:05 PM PDT 24
Finished Jul 20 06:09:13 PM PDT 24
Peak memory 200136 kb
Host smart-45c28322-4ff5-48f3-b1d8-1c7586833c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591162129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.591162129
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1291672087
Short name T906
Test name
Test status
Simulation time 31143292275 ps
CPU time 61.08 seconds
Started Jul 20 06:09:06 PM PDT 24
Finished Jul 20 06:10:08 PM PDT 24
Peak memory 200180 kb
Host smart-00b5e7ab-884b-4a3c-97d2-32d1d86cbcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291672087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1291672087
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3984929423
Short name T1005
Test name
Test status
Simulation time 114011298164 ps
CPU time 56.87 seconds
Started Jul 20 06:09:09 PM PDT 24
Finished Jul 20 06:10:07 PM PDT 24
Peak memory 200192 kb
Host smart-ba6a3de0-8713-4473-9992-d28fe5974428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984929423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3984929423
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.485746047
Short name T63
Test name
Test status
Simulation time 26850742 ps
CPU time 0.53 seconds
Started Jul 20 06:04:50 PM PDT 24
Finished Jul 20 06:04:52 PM PDT 24
Peak memory 194556 kb
Host smart-c26554c0-45bb-401f-be74-6d5b6c89a34b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485746047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.485746047
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1058411267
Short name T1168
Test name
Test status
Simulation time 24302268692 ps
CPU time 41.5 seconds
Started Jul 20 06:04:40 PM PDT 24
Finished Jul 20 06:05:22 PM PDT 24
Peak memory 200088 kb
Host smart-f6447a92-b0fb-49d7-a2c6-dea707bbef49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058411267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1058411267
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1236190672
Short name T1039
Test name
Test status
Simulation time 30812138202 ps
CPU time 17.18 seconds
Started Jul 20 06:04:41 PM PDT 24
Finished Jul 20 06:04:59 PM PDT 24
Peak memory 200144 kb
Host smart-2171e96d-d629-4622-aadf-1d6c9b2554a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236190672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1236190672
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.4132721710
Short name T261
Test name
Test status
Simulation time 39788620714 ps
CPU time 123.16 seconds
Started Jul 20 06:04:45 PM PDT 24
Finished Jul 20 06:06:49 PM PDT 24
Peak memory 200156 kb
Host smart-e30e1b46-d497-47e6-85dd-decaf60527c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132721710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.4132721710
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3609230067
Short name T115
Test name
Test status
Simulation time 61213697561 ps
CPU time 83.01 seconds
Started Jul 20 06:04:43 PM PDT 24
Finished Jul 20 06:06:07 PM PDT 24
Peak memory 199152 kb
Host smart-34d7d738-c2b8-4de8-8e7f-31ea2ec330ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609230067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3609230067
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3712076459
Short name T1162
Test name
Test status
Simulation time 47930007377 ps
CPU time 58.75 seconds
Started Jul 20 06:04:52 PM PDT 24
Finished Jul 20 06:05:53 PM PDT 24
Peak memory 200132 kb
Host smart-b806a083-8f55-473d-ba43-fb3bfe645f70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712076459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3712076459
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2772865583
Short name T843
Test name
Test status
Simulation time 1114272208 ps
CPU time 8.35 seconds
Started Jul 20 06:04:54 PM PDT 24
Finished Jul 20 06:05:03 PM PDT 24
Peak memory 198228 kb
Host smart-ddd519f9-62a1-4166-800e-430cc5debaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772865583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2772865583
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2875528682
Short name T781
Test name
Test status
Simulation time 161356248627 ps
CPU time 108.84 seconds
Started Jul 20 06:04:41 PM PDT 24
Finished Jul 20 06:06:30 PM PDT 24
Peak memory 208460 kb
Host smart-ea0d6636-a8cd-421f-bb8c-eb2499737b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875528682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2875528682
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.165707734
Short name T1042
Test name
Test status
Simulation time 14016670886 ps
CPU time 613.68 seconds
Started Jul 20 06:04:52 PM PDT 24
Finished Jul 20 06:15:08 PM PDT 24
Peak memory 200132 kb
Host smart-b5207a55-16a8-4277-9beb-2882bbf17ff8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165707734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.165707734
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.311503582
Short name T388
Test name
Test status
Simulation time 5230022717 ps
CPU time 21.51 seconds
Started Jul 20 06:04:43 PM PDT 24
Finished Jul 20 06:05:05 PM PDT 24
Peak memory 198352 kb
Host smart-c730b456-4114-4cb9-b039-b97a9d0f060b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311503582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.311503582
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1634866058
Short name T301
Test name
Test status
Simulation time 67045268234 ps
CPU time 108.32 seconds
Started Jul 20 06:04:51 PM PDT 24
Finished Jul 20 06:06:41 PM PDT 24
Peak memory 200132 kb
Host smart-2325dd31-0a5d-43b4-89d7-6e8483eec98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634866058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1634866058
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1302262345
Short name T95
Test name
Test status
Simulation time 3798297857 ps
CPU time 3.19 seconds
Started Jul 20 06:04:49 PM PDT 24
Finished Jul 20 06:04:52 PM PDT 24
Peak memory 196320 kb
Host smart-fefd06ee-860c-4c63-af04-48ded66762b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302262345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1302262345
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1204724939
Short name T1096
Test name
Test status
Simulation time 124144975 ps
CPU time 1.27 seconds
Started Jul 20 06:04:45 PM PDT 24
Finished Jul 20 06:04:47 PM PDT 24
Peak memory 199476 kb
Host smart-83808c00-26f4-4ac9-8868-814f7fb5566d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204724939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1204724939
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.343928357
Short name T525
Test name
Test status
Simulation time 595272903501 ps
CPU time 847.54 seconds
Started Jul 20 06:04:50 PM PDT 24
Finished Jul 20 06:18:59 PM PDT 24
Peak memory 215336 kb
Host smart-f951b85d-5b4f-42ab-942a-0771bc374330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343928357 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.343928357
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.4212972847
Short name T367
Test name
Test status
Simulation time 1266230413 ps
CPU time 2.15 seconds
Started Jul 20 06:04:51 PM PDT 24
Finished Jul 20 06:04:55 PM PDT 24
Peak memory 199076 kb
Host smart-ebfba2d7-c377-47a4-86f8-3b8137f8a13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212972847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.4212972847
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2580007104
Short name T531
Test name
Test status
Simulation time 59602864303 ps
CPU time 72.65 seconds
Started Jul 20 06:04:40 PM PDT 24
Finished Jul 20 06:05:53 PM PDT 24
Peak memory 200164 kb
Host smart-a7c33732-4361-4005-9c62-2f33780067ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580007104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2580007104
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3139666124
Short name T457
Test name
Test status
Simulation time 9862834695 ps
CPU time 9.44 seconds
Started Jul 20 06:09:08 PM PDT 24
Finished Jul 20 06:09:18 PM PDT 24
Peak memory 200176 kb
Host smart-816251f6-1c40-4af4-a748-ff3ca95d7134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139666124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3139666124
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1714971511
Short name T181
Test name
Test status
Simulation time 23016125029 ps
CPU time 41.15 seconds
Started Jul 20 06:09:08 PM PDT 24
Finished Jul 20 06:09:50 PM PDT 24
Peak memory 200196 kb
Host smart-3c8a2240-be09-467e-8ea6-e1e199567c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714971511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1714971511
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1018211484
Short name T751
Test name
Test status
Simulation time 153640914207 ps
CPU time 305.38 seconds
Started Jul 20 06:09:07 PM PDT 24
Finished Jul 20 06:14:13 PM PDT 24
Peak memory 200140 kb
Host smart-e2cbc8d6-974d-4508-8e29-13897a7965ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018211484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1018211484
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3020049704
Short name T185
Test name
Test status
Simulation time 31059361747 ps
CPU time 45.1 seconds
Started Jul 20 06:09:10 PM PDT 24
Finished Jul 20 06:09:55 PM PDT 24
Peak memory 200196 kb
Host smart-84f6eb0c-8649-4b16-b357-5b3d8fba1f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020049704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3020049704
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1427878036
Short name T971
Test name
Test status
Simulation time 30704217557 ps
CPU time 10.74 seconds
Started Jul 20 06:09:15 PM PDT 24
Finished Jul 20 06:09:26 PM PDT 24
Peak memory 200136 kb
Host smart-b1b04779-8a77-4352-ae7f-566aca9166ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427878036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1427878036
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.4078620170
Short name T795
Test name
Test status
Simulation time 13270041206 ps
CPU time 12.41 seconds
Started Jul 20 06:09:15 PM PDT 24
Finished Jul 20 06:09:28 PM PDT 24
Peak memory 200056 kb
Host smart-ef3d3b23-43f6-45c9-9b81-8c605e519388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078620170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4078620170
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2493925450
Short name T327
Test name
Test status
Simulation time 51343786863 ps
CPU time 92.32 seconds
Started Jul 20 06:09:22 PM PDT 24
Finished Jul 20 06:10:55 PM PDT 24
Peak memory 200040 kb
Host smart-bd918a23-9bb1-40ec-89f7-423a76ccf489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493925450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2493925450
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1145189884
Short name T189
Test name
Test status
Simulation time 34564720085 ps
CPU time 24.88 seconds
Started Jul 20 06:09:17 PM PDT 24
Finished Jul 20 06:09:42 PM PDT 24
Peak memory 199332 kb
Host smart-b9cac955-364b-4987-abc5-660164521796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145189884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1145189884
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1705087099
Short name T414
Test name
Test status
Simulation time 81699813184 ps
CPU time 210.54 seconds
Started Jul 20 06:09:14 PM PDT 24
Finished Jul 20 06:12:45 PM PDT 24
Peak memory 200196 kb
Host smart-fc40a48e-d502-40e5-9ce7-60573b9561cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705087099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1705087099
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3210420528
Short name T424
Test name
Test status
Simulation time 37537744 ps
CPU time 0.57 seconds
Started Jul 20 06:02:31 PM PDT 24
Finished Jul 20 06:02:31 PM PDT 24
Peak memory 195516 kb
Host smart-f5caf7ae-0675-4957-ba0c-c13a3aa224ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210420528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3210420528
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.4018269765
Short name T579
Test name
Test status
Simulation time 176721766560 ps
CPU time 297.97 seconds
Started Jul 20 06:02:13 PM PDT 24
Finished Jul 20 06:07:12 PM PDT 24
Peak memory 200196 kb
Host smart-973abfae-e57e-477d-b4e0-275dcde6ef39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018269765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.4018269765
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.172624905
Short name T872
Test name
Test status
Simulation time 6836215634 ps
CPU time 9.01 seconds
Started Jul 20 06:02:10 PM PDT 24
Finished Jul 20 06:02:19 PM PDT 24
Peak memory 200088 kb
Host smart-4e16fd4f-a2f9-4212-b63c-97fd191c04bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172624905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.172624905
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1599929276
Short name T421
Test name
Test status
Simulation time 13128164749 ps
CPU time 8.1 seconds
Started Jul 20 06:02:21 PM PDT 24
Finished Jul 20 06:02:29 PM PDT 24
Peak memory 200192 kb
Host smart-bf23800c-1d35-4a76-905f-279dfd0e67cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599929276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1599929276
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.525062926
Short name T322
Test name
Test status
Simulation time 18070516060 ps
CPU time 23.41 seconds
Started Jul 20 06:02:21 PM PDT 24
Finished Jul 20 06:02:45 PM PDT 24
Peak memory 197148 kb
Host smart-b40578ae-3486-4438-a6a6-a790993d46f2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525062926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.525062926
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.485370245
Short name T254
Test name
Test status
Simulation time 96053414196 ps
CPU time 184.63 seconds
Started Jul 20 06:02:23 PM PDT 24
Finished Jul 20 06:05:28 PM PDT 24
Peak memory 200160 kb
Host smart-aa013d91-5ef2-4d3e-873d-14f7de896bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485370245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.485370245
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1089770275
Short name T970
Test name
Test status
Simulation time 4224065586 ps
CPU time 9.85 seconds
Started Jul 20 06:02:21 PM PDT 24
Finished Jul 20 06:02:31 PM PDT 24
Peak memory 200148 kb
Host smart-3950f809-c407-4edc-a0e3-35601de72711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089770275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1089770275
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3007552586
Short name T706
Test name
Test status
Simulation time 83117139001 ps
CPU time 12.24 seconds
Started Jul 20 06:02:21 PM PDT 24
Finished Jul 20 06:02:33 PM PDT 24
Peak memory 200368 kb
Host smart-0b0fb36e-624b-445e-a8a6-d81e693c071c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007552586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3007552586
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.4277056922
Short name T947
Test name
Test status
Simulation time 8872212888 ps
CPU time 461.96 seconds
Started Jul 20 06:02:24 PM PDT 24
Finished Jul 20 06:10:06 PM PDT 24
Peak memory 200128 kb
Host smart-d13938c9-3efe-48c0-9bee-d0fdca17c605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277056922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.4277056922
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.524867638
Short name T582
Test name
Test status
Simulation time 4094461746 ps
CPU time 31.33 seconds
Started Jul 20 06:02:21 PM PDT 24
Finished Jul 20 06:02:53 PM PDT 24
Peak memory 198224 kb
Host smart-4928708d-fa31-41b3-a2ab-ed5041f27618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524867638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.524867638
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2034558590
Short name T139
Test name
Test status
Simulation time 96876151526 ps
CPU time 39.89 seconds
Started Jul 20 06:02:19 PM PDT 24
Finished Jul 20 06:03:00 PM PDT 24
Peak memory 200092 kb
Host smart-d30ae2c5-b3ea-408e-8e8a-882cc9480f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034558590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2034558590
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2105898883
Short name T723
Test name
Test status
Simulation time 49174510628 ps
CPU time 16.25 seconds
Started Jul 20 06:02:24 PM PDT 24
Finished Jul 20 06:02:40 PM PDT 24
Peak memory 196500 kb
Host smart-630f0a5f-ed9c-4cf3-a4c9-fc9d6e1e400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105898883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2105898883
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1667349699
Short name T25
Test name
Test status
Simulation time 60969697 ps
CPU time 0.82 seconds
Started Jul 20 06:02:31 PM PDT 24
Finished Jul 20 06:02:32 PM PDT 24
Peak memory 218456 kb
Host smart-f2ebc37a-0594-4cb1-b53b-c241e9be2880
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667349699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1667349699
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1905016087
Short name T959
Test name
Test status
Simulation time 761832515 ps
CPU time 1.62 seconds
Started Jul 20 06:02:12 PM PDT 24
Finished Jul 20 06:02:14 PM PDT 24
Peak memory 199196 kb
Host smart-c6020133-8166-48c2-bd8e-8ef2b3e8cd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905016087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1905016087
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3015599890
Short name T425
Test name
Test status
Simulation time 139777893377 ps
CPU time 792.29 seconds
Started Jul 20 06:02:23 PM PDT 24
Finished Jul 20 06:15:35 PM PDT 24
Peak memory 200176 kb
Host smart-d1e51f12-787f-48d9-810a-bf7d5e717a5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015599890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3015599890
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.638026495
Short name T546
Test name
Test status
Simulation time 18533677345 ps
CPU time 216.51 seconds
Started Jul 20 06:02:23 PM PDT 24
Finished Jul 20 06:06:00 PM PDT 24
Peak memory 208532 kb
Host smart-e4a1681b-fb9a-4c83-a3fe-80c4d14b0c7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638026495 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.638026495
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2536661584
Short name T920
Test name
Test status
Simulation time 6718675431 ps
CPU time 12.13 seconds
Started Jul 20 06:02:22 PM PDT 24
Finished Jul 20 06:02:35 PM PDT 24
Peak memory 200184 kb
Host smart-b98e840d-ebc4-4ea7-aa7a-fadbdf786cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536661584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2536661584
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3398801653
Short name T693
Test name
Test status
Simulation time 102611340678 ps
CPU time 62.48 seconds
Started Jul 20 06:02:13 PM PDT 24
Finished Jul 20 06:03:16 PM PDT 24
Peak memory 200116 kb
Host smart-702172ec-107d-47f1-9ce3-57649d202419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398801653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3398801653
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.377027886
Short name T343
Test name
Test status
Simulation time 14513981 ps
CPU time 0.55 seconds
Started Jul 20 06:04:53 PM PDT 24
Finished Jul 20 06:04:55 PM PDT 24
Peak memory 195576 kb
Host smart-3a813618-99a9-4eef-a71d-6e9213adeb69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377027886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.377027886
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3592356980
Short name T903
Test name
Test status
Simulation time 374177217848 ps
CPU time 34.33 seconds
Started Jul 20 06:04:51 PM PDT 24
Finished Jul 20 06:05:27 PM PDT 24
Peak memory 200180 kb
Host smart-280039df-1ba4-4936-a835-e73b7a9cf707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592356980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3592356980
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.4146648413
Short name T297
Test name
Test status
Simulation time 208299056829 ps
CPU time 44.96 seconds
Started Jul 20 06:04:51 PM PDT 24
Finished Jul 20 06:05:37 PM PDT 24
Peak memory 200188 kb
Host smart-01658967-54ca-4f93-bcc2-6c9deb27bed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146648413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.4146648413
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1564089501
Short name T401
Test name
Test status
Simulation time 150218543357 ps
CPU time 252.86 seconds
Started Jul 20 06:04:50 PM PDT 24
Finished Jul 20 06:09:04 PM PDT 24
Peak memory 200180 kb
Host smart-0cb91f44-2f3e-4321-aab8-fe5ed642113d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564089501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1564089501
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.907810581
Short name T1095
Test name
Test status
Simulation time 19774313003 ps
CPU time 29.36 seconds
Started Jul 20 06:04:50 PM PDT 24
Finished Jul 20 06:05:22 PM PDT 24
Peak memory 200144 kb
Host smart-d59990cd-97a5-4031-ae2d-1f942edfb3e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907810581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.907810581
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.554563314
Short name T1027
Test name
Test status
Simulation time 136101057270 ps
CPU time 1015.9 seconds
Started Jul 20 06:04:49 PM PDT 24
Finished Jul 20 06:21:46 PM PDT 24
Peak memory 200164 kb
Host smart-7649a8b7-7ea9-4f5f-9cfe-87ed93cbaabb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=554563314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.554563314
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.300438292
Short name T691
Test name
Test status
Simulation time 6372886109 ps
CPU time 3.78 seconds
Started Jul 20 06:04:50 PM PDT 24
Finished Jul 20 06:04:56 PM PDT 24
Peak memory 198288 kb
Host smart-2882e2a0-74c4-4720-9bd0-83901af8beae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300438292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.300438292
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3614447879
Short name T633
Test name
Test status
Simulation time 82474915254 ps
CPU time 58.85 seconds
Started Jul 20 06:04:48 PM PDT 24
Finished Jul 20 06:05:47 PM PDT 24
Peak memory 200324 kb
Host smart-5124f704-251d-4a98-ad2a-e53120e77c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614447879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3614447879
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2004163784
Short name T1016
Test name
Test status
Simulation time 19180976877 ps
CPU time 548.95 seconds
Started Jul 20 06:04:51 PM PDT 24
Finished Jul 20 06:14:02 PM PDT 24
Peak memory 200112 kb
Host smart-f49d7c67-86fe-4b9a-98fe-24f24012e7e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2004163784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2004163784
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3992812807
Short name T823
Test name
Test status
Simulation time 6739119309 ps
CPU time 29.44 seconds
Started Jul 20 06:04:53 PM PDT 24
Finished Jul 20 06:05:24 PM PDT 24
Peak memory 198512 kb
Host smart-7c49b6f0-2699-4701-a762-59445ae0e745
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3992812807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3992812807
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.795740413
Short name T159
Test name
Test status
Simulation time 25507068753 ps
CPU time 22.03 seconds
Started Jul 20 06:04:52 PM PDT 24
Finished Jul 20 06:05:16 PM PDT 24
Peak memory 200164 kb
Host smart-da91370e-5daf-4951-8814-e7a1714861ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795740413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.795740413
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.872724751
Short name T307
Test name
Test status
Simulation time 34679756552 ps
CPU time 47.12 seconds
Started Jul 20 06:04:51 PM PDT 24
Finished Jul 20 06:05:40 PM PDT 24
Peak memory 195976 kb
Host smart-82c0c2b8-07ca-41cb-b75c-f82792fa7097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872724751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.872724751
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2070632500
Short name T423
Test name
Test status
Simulation time 737482182 ps
CPU time 4.27 seconds
Started Jul 20 06:04:52 PM PDT 24
Finished Jul 20 06:04:58 PM PDT 24
Peak memory 198520 kb
Host smart-3fdd82cf-24e4-420c-85aa-21fce70b46f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070632500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2070632500
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3734651614
Short name T1099
Test name
Test status
Simulation time 91336307337 ps
CPU time 194.28 seconds
Started Jul 20 06:04:51 PM PDT 24
Finished Jul 20 06:08:07 PM PDT 24
Peak memory 200168 kb
Host smart-436f1ea3-bf28-49e6-912e-e430735f7395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734651614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3734651614
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2980869884
Short name T908
Test name
Test status
Simulation time 651106992856 ps
CPU time 840.13 seconds
Started Jul 20 06:04:49 PM PDT 24
Finished Jul 20 06:18:51 PM PDT 24
Peak memory 226100 kb
Host smart-b9bdcf5f-5f37-4858-93e1-c2f2dc67a3cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980869884 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2980869884
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2432255206
Short name T349
Test name
Test status
Simulation time 2264585392 ps
CPU time 1.71 seconds
Started Jul 20 06:04:52 PM PDT 24
Finished Jul 20 06:04:55 PM PDT 24
Peak memory 198480 kb
Host smart-9e61d847-71b3-479d-9572-22a1dfc8c9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432255206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2432255206
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.499260539
Short name T1153
Test name
Test status
Simulation time 104479726059 ps
CPU time 277.19 seconds
Started Jul 20 06:04:51 PM PDT 24
Finished Jul 20 06:09:30 PM PDT 24
Peak memory 200184 kb
Host smart-944fe658-a426-4914-a4c3-7fb19cecf461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499260539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.499260539
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2954670343
Short name T172
Test name
Test status
Simulation time 58110047204 ps
CPU time 25.54 seconds
Started Jul 20 06:09:16 PM PDT 24
Finished Jul 20 06:09:42 PM PDT 24
Peak memory 200132 kb
Host smart-12c09a9d-e84a-4b59-8551-0d0ff36286ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954670343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2954670343
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1283577286
Short name T1135
Test name
Test status
Simulation time 82008232486 ps
CPU time 124.58 seconds
Started Jul 20 06:09:22 PM PDT 24
Finished Jul 20 06:11:27 PM PDT 24
Peak memory 200100 kb
Host smart-3233760d-d49a-4098-915f-0dafed777cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283577286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1283577286
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3433509692
Short name T799
Test name
Test status
Simulation time 31293398915 ps
CPU time 31.88 seconds
Started Jul 20 06:09:17 PM PDT 24
Finished Jul 20 06:09:49 PM PDT 24
Peak memory 200120 kb
Host smart-6139989e-e3a1-4fe4-b5d2-b226b04f7f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433509692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3433509692
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.898972246
Short name T419
Test name
Test status
Simulation time 61946932969 ps
CPU time 84.35 seconds
Started Jul 20 06:09:15 PM PDT 24
Finished Jul 20 06:10:40 PM PDT 24
Peak memory 200112 kb
Host smart-65bd6ee5-436c-4319-a77a-2ef8c82d1c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898972246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.898972246
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2602499668
Short name T466
Test name
Test status
Simulation time 41291842617 ps
CPU time 71 seconds
Started Jul 20 06:09:23 PM PDT 24
Finished Jul 20 06:10:35 PM PDT 24
Peak memory 200100 kb
Host smart-5732d4dd-f872-45a0-9407-b6b07cd28a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602499668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2602499668
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2617426440
Short name T129
Test name
Test status
Simulation time 134216947949 ps
CPU time 51 seconds
Started Jul 20 06:09:15 PM PDT 24
Finished Jul 20 06:10:06 PM PDT 24
Peak memory 200124 kb
Host smart-c03186f0-fc92-43f9-9110-c11a774fb9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617426440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2617426440
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.847911261
Short name T869
Test name
Test status
Simulation time 114746344615 ps
CPU time 41.83 seconds
Started Jul 20 06:09:17 PM PDT 24
Finished Jul 20 06:09:59 PM PDT 24
Peak memory 200192 kb
Host smart-d15476dc-4305-4def-86cd-5337cb4b5c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847911261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.847911261
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.234865329
Short name T1040
Test name
Test status
Simulation time 114868119356 ps
CPU time 98.83 seconds
Started Jul 20 06:09:14 PM PDT 24
Finished Jul 20 06:10:53 PM PDT 24
Peak memory 200188 kb
Host smart-c72eaea9-c7a5-4946-b91a-f4dc7cd99f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234865329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.234865329
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3239162564
Short name T1035
Test name
Test status
Simulation time 14367730795 ps
CPU time 13.41 seconds
Started Jul 20 06:09:12 PM PDT 24
Finished Jul 20 06:09:26 PM PDT 24
Peak memory 200172 kb
Host smart-7b1efd83-fdc0-4cb6-ab77-a477be512a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239162564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3239162564
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1298999408
Short name T274
Test name
Test status
Simulation time 32548306670 ps
CPU time 41.13 seconds
Started Jul 20 06:09:22 PM PDT 24
Finished Jul 20 06:10:04 PM PDT 24
Peak memory 200124 kb
Host smart-e516f566-5e13-4251-82b1-14fa675dda39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298999408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1298999408
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3927240230
Short name T355
Test name
Test status
Simulation time 38605752 ps
CPU time 0.55 seconds
Started Jul 20 06:04:56 PM PDT 24
Finished Jul 20 06:04:57 PM PDT 24
Peak memory 194924 kb
Host smart-baba64d3-eb8f-4979-92fc-b29bbd8c0822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927240230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3927240230
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.334962328
Short name T1171
Test name
Test status
Simulation time 15650613130 ps
CPU time 24.3 seconds
Started Jul 20 06:04:59 PM PDT 24
Finished Jul 20 06:05:24 PM PDT 24
Peak memory 200120 kb
Host smart-dffdba17-2e44-432f-949c-9529dddc3db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334962328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.334962328
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.4243683760
Short name T735
Test name
Test status
Simulation time 23214496742 ps
CPU time 9.52 seconds
Started Jul 20 06:04:59 PM PDT 24
Finished Jul 20 06:05:10 PM PDT 24
Peak memory 199748 kb
Host smart-ea5ee0db-340a-4fbd-a86f-ce9c43127d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243683760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.4243683760
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3854580981
Short name T898
Test name
Test status
Simulation time 142952304914 ps
CPU time 58.9 seconds
Started Jul 20 06:04:59 PM PDT 24
Finished Jul 20 06:05:59 PM PDT 24
Peak memory 200144 kb
Host smart-4d36c9f0-db27-4f58-b814-eb370e75a441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854580981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3854580981
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.636060543
Short name T726
Test name
Test status
Simulation time 42989925590 ps
CPU time 67.35 seconds
Started Jul 20 06:04:59 PM PDT 24
Finished Jul 20 06:06:08 PM PDT 24
Peak memory 200196 kb
Host smart-fb42e118-b1c1-4f01-96ff-e6ccc8952140
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636060543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.636060543
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3457383611
Short name T549
Test name
Test status
Simulation time 110222301359 ps
CPU time 702.54 seconds
Started Jul 20 06:04:59 PM PDT 24
Finished Jul 20 06:16:42 PM PDT 24
Peak memory 200128 kb
Host smart-f19bc1c2-2eb3-4688-9078-2c633f2181e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457383611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3457383611
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.35520962
Short name T381
Test name
Test status
Simulation time 4269355754 ps
CPU time 7.18 seconds
Started Jul 20 06:04:58 PM PDT 24
Finished Jul 20 06:05:06 PM PDT 24
Peak memory 199828 kb
Host smart-34159819-483b-45f9-8980-4ebe3a5db37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35520962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.35520962
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3505055662
Short name T554
Test name
Test status
Simulation time 589827147874 ps
CPU time 110.92 seconds
Started Jul 20 06:04:58 PM PDT 24
Finished Jul 20 06:06:50 PM PDT 24
Peak memory 200264 kb
Host smart-61708e7f-95bb-4812-8697-e15ec8cd7696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505055662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3505055662
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2321677790
Short name T503
Test name
Test status
Simulation time 15304228295 ps
CPU time 218.24 seconds
Started Jul 20 06:04:59 PM PDT 24
Finished Jul 20 06:08:38 PM PDT 24
Peak memory 200168 kb
Host smart-1cafd200-8680-4286-ab35-288f555db22c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2321677790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2321677790
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3883806115
Short name T10
Test name
Test status
Simulation time 6956569797 ps
CPU time 30.38 seconds
Started Jul 20 06:04:59 PM PDT 24
Finished Jul 20 06:05:30 PM PDT 24
Peak memory 198916 kb
Host smart-0dffb767-71dd-4ecf-8b1a-fcb4e2d72d6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3883806115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3883806115
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2739372967
Short name T807
Test name
Test status
Simulation time 104222394346 ps
CPU time 41.29 seconds
Started Jul 20 06:04:58 PM PDT 24
Finished Jul 20 06:05:40 PM PDT 24
Peak memory 200192 kb
Host smart-4787ee0b-e375-4ea0-895a-e6e1e32edc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739372967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2739372967
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2280720866
Short name T957
Test name
Test status
Simulation time 2019487736 ps
CPU time 2.35 seconds
Started Jul 20 06:04:57 PM PDT 24
Finished Jul 20 06:05:00 PM PDT 24
Peak memory 195568 kb
Host smart-33516436-1a66-4562-aa6e-5d59cddc33f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280720866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2280720866
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1192039731
Short name T432
Test name
Test status
Simulation time 101425318 ps
CPU time 0.89 seconds
Started Jul 20 06:04:52 PM PDT 24
Finished Jul 20 06:04:54 PM PDT 24
Peak memory 197344 kb
Host smart-996934ed-6ff5-4c23-80c0-4f246187b278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192039731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1192039731
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.215113639
Short name T715
Test name
Test status
Simulation time 87168945129 ps
CPU time 144.07 seconds
Started Jul 20 06:04:59 PM PDT 24
Finished Jul 20 06:07:24 PM PDT 24
Peak memory 200108 kb
Host smart-34c42d6b-730e-464d-b3d8-a5524c6a39a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215113639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.215113639
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.741488127
Short name T880
Test name
Test status
Simulation time 87209372545 ps
CPU time 1013.18 seconds
Started Jul 20 06:05:01 PM PDT 24
Finished Jul 20 06:21:55 PM PDT 24
Peak memory 226804 kb
Host smart-dbf3421f-023f-4d91-81b8-55fab3523519
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741488127 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.741488127
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3478557151
Short name T750
Test name
Test status
Simulation time 6743026481 ps
CPU time 13.39 seconds
Started Jul 20 06:05:00 PM PDT 24
Finished Jul 20 06:05:14 PM PDT 24
Peak memory 200168 kb
Host smart-7a974f48-6e56-4f20-96b4-81c6ec30a8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478557151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3478557151
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.906953646
Short name T273
Test name
Test status
Simulation time 93605858007 ps
CPU time 142.37 seconds
Started Jul 20 06:04:50 PM PDT 24
Finished Jul 20 06:07:13 PM PDT 24
Peak memory 200124 kb
Host smart-a8384bda-ee46-427c-abf1-73a97aaa6e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906953646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.906953646
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.760394639
Short name T7
Test name
Test status
Simulation time 8389268957 ps
CPU time 13.19 seconds
Started Jul 20 06:09:26 PM PDT 24
Finished Jul 20 06:09:40 PM PDT 24
Peak memory 200204 kb
Host smart-47768cef-39b0-47ab-9f44-01b4fd78a749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760394639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.760394639
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2232159824
Short name T577
Test name
Test status
Simulation time 54104728432 ps
CPU time 48.38 seconds
Started Jul 20 06:09:23 PM PDT 24
Finished Jul 20 06:10:12 PM PDT 24
Peak memory 200004 kb
Host smart-4506d9fe-98b3-49ed-aa1d-ced8c9cffbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232159824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2232159824
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2644008412
Short name T535
Test name
Test status
Simulation time 179497489088 ps
CPU time 66.38 seconds
Started Jul 20 06:09:27 PM PDT 24
Finished Jul 20 06:10:34 PM PDT 24
Peak memory 200132 kb
Host smart-3126b84b-ef95-4d85-9b2b-6b4d5b74ff55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644008412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2644008412
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.484911399
Short name T443
Test name
Test status
Simulation time 105668338004 ps
CPU time 31.76 seconds
Started Jul 20 06:09:26 PM PDT 24
Finished Jul 20 06:09:59 PM PDT 24
Peak memory 200076 kb
Host smart-92083a16-27d7-49ce-b918-abf3927e2c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484911399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.484911399
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3904792095
Short name T215
Test name
Test status
Simulation time 7779340586 ps
CPU time 10.07 seconds
Started Jul 20 06:09:25 PM PDT 24
Finished Jul 20 06:09:36 PM PDT 24
Peak memory 199984 kb
Host smart-691ee355-1320-4e79-9d58-c8a8d66eba1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904792095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3904792095
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.722390006
Short name T613
Test name
Test status
Simulation time 286796976651 ps
CPU time 21.32 seconds
Started Jul 20 06:09:26 PM PDT 24
Finished Jul 20 06:09:48 PM PDT 24
Peak memory 199988 kb
Host smart-ad6213ad-e121-41d7-a476-ae7e90a744be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722390006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.722390006
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1606350946
Short name T802
Test name
Test status
Simulation time 25000974593 ps
CPU time 43.58 seconds
Started Jul 20 06:09:26 PM PDT 24
Finished Jul 20 06:10:11 PM PDT 24
Peak memory 200112 kb
Host smart-47c35724-bf86-4c74-bbc9-70ced1a8c880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606350946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1606350946
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2647975849
Short name T777
Test name
Test status
Simulation time 35515232577 ps
CPU time 37.95 seconds
Started Jul 20 06:09:22 PM PDT 24
Finished Jul 20 06:10:00 PM PDT 24
Peak memory 200212 kb
Host smart-afced2fa-3b4d-44d5-8c37-ab26dbb79645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647975849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2647975849
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.954222014
Short name T164
Test name
Test status
Simulation time 127727797049 ps
CPU time 51.98 seconds
Started Jul 20 06:09:27 PM PDT 24
Finished Jul 20 06:10:20 PM PDT 24
Peak memory 200140 kb
Host smart-77aeafc2-89c2-42e8-9d7b-88bdcb1a5855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954222014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.954222014
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3591475600
Short name T668
Test name
Test status
Simulation time 11774662 ps
CPU time 0.53 seconds
Started Jul 20 06:05:09 PM PDT 24
Finished Jul 20 06:05:11 PM PDT 24
Peak memory 195496 kb
Host smart-a0747645-d028-4d8c-9376-9bb6cbc940a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591475600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3591475600
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3045402953
Short name T312
Test name
Test status
Simulation time 138665865508 ps
CPU time 47.28 seconds
Started Jul 20 06:04:58 PM PDT 24
Finished Jul 20 06:05:46 PM PDT 24
Peak memory 200172 kb
Host smart-dec162d0-25b7-4777-845a-c7be3ee25eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045402953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3045402953
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3414829645
Short name T122
Test name
Test status
Simulation time 69668026475 ps
CPU time 20.94 seconds
Started Jul 20 06:04:56 PM PDT 24
Finished Jul 20 06:05:18 PM PDT 24
Peak memory 199788 kb
Host smart-56ff43d3-a7cb-4946-bbb2-f3a95ceaed3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414829645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3414829645
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.432069919
Short name T710
Test name
Test status
Simulation time 48422816755 ps
CPU time 73.99 seconds
Started Jul 20 06:04:58 PM PDT 24
Finished Jul 20 06:06:14 PM PDT 24
Peak memory 200056 kb
Host smart-2acbd0fc-de9f-47c7-a0f6-1ecc851eac77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432069919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.432069919
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1545702632
Short name T541
Test name
Test status
Simulation time 14617144822 ps
CPU time 5.01 seconds
Started Jul 20 06:04:58 PM PDT 24
Finished Jul 20 06:05:04 PM PDT 24
Peak memory 197476 kb
Host smart-dea15a21-060a-4aad-b141-178780f52bd9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545702632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1545702632
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1755452742
Short name T248
Test name
Test status
Simulation time 100180904357 ps
CPU time 383.12 seconds
Started Jul 20 06:05:06 PM PDT 24
Finished Jul 20 06:11:30 PM PDT 24
Peak memory 200032 kb
Host smart-4c6facf8-ab1a-4c65-8956-27e518b91690
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755452742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1755452742
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1264663358
Short name T1134
Test name
Test status
Simulation time 10426092715 ps
CPU time 12.58 seconds
Started Jul 20 06:05:11 PM PDT 24
Finished Jul 20 06:05:24 PM PDT 24
Peak memory 200144 kb
Host smart-3d74cfc1-b3b1-49cf-ad47-c3bf8deb9a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264663358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1264663358
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.34128902
Short name T683
Test name
Test status
Simulation time 115887041297 ps
CPU time 84 seconds
Started Jul 20 06:04:57 PM PDT 24
Finished Jul 20 06:06:22 PM PDT 24
Peak memory 200260 kb
Host smart-be2cff0a-fcab-41ab-a0ff-ac61e8a68d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34128902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.34128902
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.764328923
Short name T904
Test name
Test status
Simulation time 7954167486 ps
CPU time 445.37 seconds
Started Jul 20 06:05:08 PM PDT 24
Finished Jul 20 06:12:34 PM PDT 24
Peak memory 200112 kb
Host smart-429b2603-577c-4b07-82e1-c759489845f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764328923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.764328923
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1886012529
Short name T397
Test name
Test status
Simulation time 5414360443 ps
CPU time 13.42 seconds
Started Jul 20 06:04:56 PM PDT 24
Finished Jul 20 06:05:10 PM PDT 24
Peak memory 199480 kb
Host smart-da400bf0-ac26-47d4-8dfb-21343a2b930c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886012529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1886012529
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2635040415
Short name T460
Test name
Test status
Simulation time 78019856777 ps
CPU time 30.65 seconds
Started Jul 20 06:05:09 PM PDT 24
Finished Jul 20 06:05:40 PM PDT 24
Peak memory 200132 kb
Host smart-5288b0e3-598f-4f9e-b2fb-e93cfbdbcb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635040415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2635040415
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3700900996
Short name T610
Test name
Test status
Simulation time 44490753331 ps
CPU time 35.1 seconds
Started Jul 20 06:05:01 PM PDT 24
Finished Jul 20 06:05:37 PM PDT 24
Peak memory 196028 kb
Host smart-e9ce32be-012c-4c48-b3b8-9bb72585b847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700900996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3700900996
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3933753037
Short name T426
Test name
Test status
Simulation time 307676493 ps
CPU time 1.18 seconds
Started Jul 20 06:04:57 PM PDT 24
Finished Jul 20 06:04:59 PM PDT 24
Peak memory 200092 kb
Host smart-7648d35a-39ad-48a5-b05d-5f54adf82795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933753037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3933753037
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3209686520
Short name T265
Test name
Test status
Simulation time 147029375424 ps
CPU time 381.64 seconds
Started Jul 20 06:05:09 PM PDT 24
Finished Jul 20 06:11:32 PM PDT 24
Peak memory 200180 kb
Host smart-ccf3b707-d478-45c2-9205-9f3f74cd4ace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209686520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3209686520
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.674367415
Short name T506
Test name
Test status
Simulation time 228927509772 ps
CPU time 606.93 seconds
Started Jul 20 06:05:10 PM PDT 24
Finished Jul 20 06:15:18 PM PDT 24
Peak memory 225028 kb
Host smart-57e3f8a6-e54a-4f78-83de-2262ea0c80b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674367415 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.674367415
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3922717249
Short name T418
Test name
Test status
Simulation time 845706309 ps
CPU time 2.67 seconds
Started Jul 20 06:05:09 PM PDT 24
Finished Jul 20 06:05:13 PM PDT 24
Peak memory 198584 kb
Host smart-4b062852-ccab-4f0b-9b16-9643ed048eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922717249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3922717249
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1839435520
Short name T1098
Test name
Test status
Simulation time 20439988299 ps
CPU time 25.62 seconds
Started Jul 20 06:04:59 PM PDT 24
Finished Jul 20 06:05:26 PM PDT 24
Peak memory 199988 kb
Host smart-55c50e1a-9bcc-4f66-aa9a-4e71bf922da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839435520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1839435520
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2212270346
Short name T178
Test name
Test status
Simulation time 112285580806 ps
CPU time 28.89 seconds
Started Jul 20 06:09:27 PM PDT 24
Finished Jul 20 06:09:57 PM PDT 24
Peak memory 200112 kb
Host smart-2faaf803-31d9-4dfd-b1d4-147427db4183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212270346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2212270346
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2088575707
Short name T45
Test name
Test status
Simulation time 52412391812 ps
CPU time 35.36 seconds
Started Jul 20 06:09:25 PM PDT 24
Finished Jul 20 06:10:01 PM PDT 24
Peak memory 200096 kb
Host smart-8af3fbd6-8468-43b5-91b7-e71a6a0f2eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088575707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2088575707
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2074209148
Short name T778
Test name
Test status
Simulation time 37021784421 ps
CPU time 5.23 seconds
Started Jul 20 06:09:25 PM PDT 24
Finished Jul 20 06:09:31 PM PDT 24
Peak memory 200136 kb
Host smart-b405e725-a570-40d8-b5c8-02f04693ce7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074209148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2074209148
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.4235945901
Short name T662
Test name
Test status
Simulation time 17244774168 ps
CPU time 25.63 seconds
Started Jul 20 06:09:26 PM PDT 24
Finished Jul 20 06:09:52 PM PDT 24
Peak memory 199828 kb
Host smart-7512bb2e-2f13-47e2-aacc-14f12639f1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235945901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.4235945901
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2540719973
Short name T733
Test name
Test status
Simulation time 23283114643 ps
CPU time 18.59 seconds
Started Jul 20 06:09:32 PM PDT 24
Finished Jul 20 06:09:51 PM PDT 24
Peak memory 199720 kb
Host smart-8a142813-191c-472e-82cf-b6331255bb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540719973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2540719973
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1336704923
Short name T555
Test name
Test status
Simulation time 33110402714 ps
CPU time 49.61 seconds
Started Jul 20 06:09:37 PM PDT 24
Finished Jul 20 06:10:27 PM PDT 24
Peak memory 200100 kb
Host smart-08350a65-5dff-49b4-be65-b7de23e47f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336704923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1336704923
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3506098849
Short name T132
Test name
Test status
Simulation time 26827928466 ps
CPU time 49.62 seconds
Started Jul 20 06:09:33 PM PDT 24
Finished Jul 20 06:10:23 PM PDT 24
Peak memory 200192 kb
Host smart-98c18705-c2e5-4c17-97bd-4ada314ae16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506098849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3506098849
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2932492354
Short name T835
Test name
Test status
Simulation time 98665999799 ps
CPU time 91.83 seconds
Started Jul 20 06:09:33 PM PDT 24
Finished Jul 20 06:11:06 PM PDT 24
Peak memory 200192 kb
Host smart-17c2756a-f6f2-48a6-a5a8-d52e97aff7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932492354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2932492354
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3382021264
Short name T190
Test name
Test status
Simulation time 176888736855 ps
CPU time 34.34 seconds
Started Jul 20 06:09:32 PM PDT 24
Finished Jul 20 06:10:07 PM PDT 24
Peak memory 199948 kb
Host smart-1175f701-9a44-44d9-8461-16880f175ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382021264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3382021264
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3093047784
Short name T925
Test name
Test status
Simulation time 82609518744 ps
CPU time 141.5 seconds
Started Jul 20 06:09:34 PM PDT 24
Finished Jul 20 06:11:56 PM PDT 24
Peak memory 200036 kb
Host smart-289a1572-6116-46da-9689-bda522a2ae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093047784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3093047784
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.4144289709
Short name T1102
Test name
Test status
Simulation time 39443833 ps
CPU time 0.59 seconds
Started Jul 20 06:05:20 PM PDT 24
Finished Jul 20 06:05:21 PM PDT 24
Peak memory 195580 kb
Host smart-13882fec-0292-438d-83b3-54f512356780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144289709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.4144289709
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.4082954333
Short name T175
Test name
Test status
Simulation time 57673752774 ps
CPU time 50.33 seconds
Started Jul 20 06:05:10 PM PDT 24
Finished Jul 20 06:06:01 PM PDT 24
Peak memory 200120 kb
Host smart-92f41068-a8b4-4754-992b-f77e50650703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082954333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4082954333
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2397190985
Short name T770
Test name
Test status
Simulation time 30937000024 ps
CPU time 49.04 seconds
Started Jul 20 06:05:08 PM PDT 24
Finished Jul 20 06:05:58 PM PDT 24
Peak memory 200188 kb
Host smart-4e98a9b8-a5a8-45de-869f-07aad6edd146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397190985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2397190985
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2353278955
Short name T1018
Test name
Test status
Simulation time 85087156133 ps
CPU time 603.33 seconds
Started Jul 20 06:05:16 PM PDT 24
Finished Jul 20 06:15:20 PM PDT 24
Peak memory 200176 kb
Host smart-18909cf9-63b1-4a3d-934d-250600ea2454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353278955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2353278955
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3558918650
Short name T655
Test name
Test status
Simulation time 3622275165 ps
CPU time 6.38 seconds
Started Jul 20 06:05:11 PM PDT 24
Finished Jul 20 06:05:18 PM PDT 24
Peak memory 200116 kb
Host smart-6ab4405a-7c27-4eba-bb19-b5fcb88ad2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558918650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3558918650
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.198947665
Short name T645
Test name
Test status
Simulation time 54071894591 ps
CPU time 277.47 seconds
Started Jul 20 06:05:09 PM PDT 24
Finished Jul 20 06:09:48 PM PDT 24
Peak memory 199396 kb
Host smart-74c1785c-5afa-4689-838a-a917c99c1d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198947665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.198947665
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3793518037
Short name T1136
Test name
Test status
Simulation time 3226891995 ps
CPU time 43.45 seconds
Started Jul 20 06:05:06 PM PDT 24
Finished Jul 20 06:05:50 PM PDT 24
Peak memory 200104 kb
Host smart-1b8be8be-fa35-41f6-9f8f-b73c9953abe4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3793518037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3793518037
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2089511508
Short name T671
Test name
Test status
Simulation time 5914647314 ps
CPU time 13.26 seconds
Started Jul 20 06:05:09 PM PDT 24
Finished Jul 20 06:05:23 PM PDT 24
Peak memory 198864 kb
Host smart-2c502495-f969-420b-a1ca-7609c53a2115
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2089511508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2089511508
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1389983400
Short name T321
Test name
Test status
Simulation time 205404196924 ps
CPU time 41.83 seconds
Started Jul 20 06:05:10 PM PDT 24
Finished Jul 20 06:05:53 PM PDT 24
Peak memory 200188 kb
Host smart-5dfa0d17-f770-41db-a708-a3fa8ced18e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389983400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1389983400
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3351381795
Short name T497
Test name
Test status
Simulation time 5323291215 ps
CPU time 2.56 seconds
Started Jul 20 06:05:06 PM PDT 24
Finished Jul 20 06:05:09 PM PDT 24
Peak memory 196292 kb
Host smart-e2d7a16a-e4ce-4794-a607-f7eaaeb6e99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351381795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3351381795
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1368092457
Short name T852
Test name
Test status
Simulation time 671354253 ps
CPU time 2.01 seconds
Started Jul 20 06:05:08 PM PDT 24
Finished Jul 20 06:05:11 PM PDT 24
Peak memory 199732 kb
Host smart-a519b17d-0cfe-42d3-90d6-34c7e9ece685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368092457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1368092457
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3855544785
Short name T918
Test name
Test status
Simulation time 249542838628 ps
CPU time 1009.22 seconds
Started Jul 20 06:05:16 PM PDT 24
Finished Jul 20 06:22:06 PM PDT 24
Peak memory 224980 kb
Host smart-315fc678-b036-4a68-bb7f-ebbe8e4cda8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855544785 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3855544785
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2086256397
Short name T1002
Test name
Test status
Simulation time 8420774759 ps
CPU time 8.85 seconds
Started Jul 20 06:05:09 PM PDT 24
Finished Jul 20 06:05:19 PM PDT 24
Peak memory 200020 kb
Host smart-92f39bf9-fd73-4977-8b32-9a923b61c2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086256397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2086256397
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3348995561
Short name T689
Test name
Test status
Simulation time 210641988764 ps
CPU time 94.72 seconds
Started Jul 20 06:05:10 PM PDT 24
Finished Jul 20 06:06:46 PM PDT 24
Peak memory 200200 kb
Host smart-3a78a2fe-b45b-4cce-ac04-e1087197d46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348995561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3348995561
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2411391356
Short name T643
Test name
Test status
Simulation time 31220844401 ps
CPU time 15.96 seconds
Started Jul 20 06:09:33 PM PDT 24
Finished Jul 20 06:09:50 PM PDT 24
Peak memory 199244 kb
Host smart-8d25b6c8-0578-4d26-9255-bff857d04c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411391356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2411391356
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2183304543
Short name T954
Test name
Test status
Simulation time 113749853416 ps
CPU time 163.82 seconds
Started Jul 20 06:09:32 PM PDT 24
Finished Jul 20 06:12:16 PM PDT 24
Peak memory 200040 kb
Host smart-ec793eca-25a4-4557-bf5c-48c9ec19d494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183304543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2183304543
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3199880589
Short name T206
Test name
Test status
Simulation time 23130617432 ps
CPU time 16.25 seconds
Started Jul 20 06:09:29 PM PDT 24
Finished Jul 20 06:09:46 PM PDT 24
Peak memory 199880 kb
Host smart-df1ae57c-2fa4-44f4-b254-0fb7f9317c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199880589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3199880589
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2651850578
Short name T677
Test name
Test status
Simulation time 229698137400 ps
CPU time 34.11 seconds
Started Jul 20 06:09:34 PM PDT 24
Finished Jul 20 06:10:09 PM PDT 24
Peak memory 200200 kb
Host smart-365538c7-333b-4c77-beb3-ffa825964789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651850578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2651850578
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3566091975
Short name T520
Test name
Test status
Simulation time 42503336426 ps
CPU time 63.15 seconds
Started Jul 20 06:09:33 PM PDT 24
Finished Jul 20 06:10:37 PM PDT 24
Peak memory 200120 kb
Host smart-0a1f099c-a915-48cb-ab90-c1c8b510e829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566091975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3566091975
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2221577332
Short name T659
Test name
Test status
Simulation time 386015900646 ps
CPU time 36.83 seconds
Started Jul 20 06:09:37 PM PDT 24
Finished Jul 20 06:10:15 PM PDT 24
Peak memory 200100 kb
Host smart-82bb2d12-8281-467f-8f74-d325e420b1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221577332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2221577332
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1221481580
Short name T1143
Test name
Test status
Simulation time 20032536703 ps
CPU time 32.83 seconds
Started Jul 20 06:09:29 PM PDT 24
Finished Jul 20 06:10:03 PM PDT 24
Peak memory 200204 kb
Host smart-d9dd8009-f85a-4f8b-8b67-ebe68924c331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221481580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1221481580
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2026956459
Short name T195
Test name
Test status
Simulation time 112484853304 ps
CPU time 154.79 seconds
Started Jul 20 06:09:33 PM PDT 24
Finished Jul 20 06:12:09 PM PDT 24
Peak memory 200068 kb
Host smart-874ad133-90e2-4341-be89-a68b4b2a3db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026956459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2026956459
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2065719576
Short name T236
Test name
Test status
Simulation time 42463171318 ps
CPU time 12.71 seconds
Started Jul 20 06:09:34 PM PDT 24
Finished Jul 20 06:09:47 PM PDT 24
Peak memory 200116 kb
Host smart-25addb27-3530-475c-a06d-ccafe917e6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065719576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2065719576
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1857784495
Short name T102
Test name
Test status
Simulation time 23617099 ps
CPU time 0.56 seconds
Started Jul 20 06:05:19 PM PDT 24
Finished Jul 20 06:05:20 PM PDT 24
Peak memory 195864 kb
Host smart-a6bf7fcc-05cb-4ef5-bc15-90aeaef60e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857784495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1857784495
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2406402205
Short name T481
Test name
Test status
Simulation time 32490756956 ps
CPU time 13.84 seconds
Started Jul 20 06:05:18 PM PDT 24
Finished Jul 20 06:05:32 PM PDT 24
Peak memory 199340 kb
Host smart-b0453fc4-432b-4ccb-a0d7-a27a18f29b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406402205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2406402205
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1703550693
Short name T995
Test name
Test status
Simulation time 57437903154 ps
CPU time 26.35 seconds
Started Jul 20 06:05:16 PM PDT 24
Finished Jul 20 06:05:43 PM PDT 24
Peak memory 200188 kb
Host smart-34b02940-1b07-43bf-8495-ad45424fd4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703550693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1703550693
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3090564293
Short name T642
Test name
Test status
Simulation time 36430367496 ps
CPU time 36.9 seconds
Started Jul 20 06:05:16 PM PDT 24
Finished Jul 20 06:05:53 PM PDT 24
Peak memory 200204 kb
Host smart-a393d1a9-8bdd-4fad-8590-509f656f2ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090564293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3090564293
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.227307210
Short name T350
Test name
Test status
Simulation time 225528682996 ps
CPU time 335.81 seconds
Started Jul 20 06:05:18 PM PDT 24
Finished Jul 20 06:10:54 PM PDT 24
Peak memory 200172 kb
Host smart-b8bc49ac-14ec-42d0-a1c8-6aca506b8ad4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227307210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.227307210
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3545246021
Short name T1070
Test name
Test status
Simulation time 96781903844 ps
CPU time 570.67 seconds
Started Jul 20 06:05:20 PM PDT 24
Finished Jul 20 06:14:51 PM PDT 24
Peak memory 200032 kb
Host smart-01c6f7e7-574f-4811-9a43-e9577bae31fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3545246021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3545246021
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.810882418
Short name T408
Test name
Test status
Simulation time 9045033019 ps
CPU time 6.04 seconds
Started Jul 20 06:05:19 PM PDT 24
Finished Jul 20 06:05:26 PM PDT 24
Peak memory 199884 kb
Host smart-20292417-ab61-453a-a064-5a2e4b0183ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810882418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.810882418
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.4015832810
Short name T507
Test name
Test status
Simulation time 55402803784 ps
CPU time 79.6 seconds
Started Jul 20 06:05:18 PM PDT 24
Finished Jul 20 06:06:38 PM PDT 24
Peak memory 199320 kb
Host smart-edea9b14-2943-47ab-93a3-05d7b3236d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015832810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4015832810
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2181278010
Short name T960
Test name
Test status
Simulation time 15258093024 ps
CPU time 205.84 seconds
Started Jul 20 06:05:17 PM PDT 24
Finished Jul 20 06:08:43 PM PDT 24
Peak memory 200200 kb
Host smart-db885f82-7570-4b13-9e61-5275a34ce0ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181278010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2181278010
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3243288150
Short name T1037
Test name
Test status
Simulation time 7568065199 ps
CPU time 62.96 seconds
Started Jul 20 06:05:14 PM PDT 24
Finished Jul 20 06:06:18 PM PDT 24
Peak memory 198304 kb
Host smart-06081443-ad9b-4b60-9918-7714fc86e6f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3243288150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3243288150
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1488225719
Short name T142
Test name
Test status
Simulation time 21291881645 ps
CPU time 35.69 seconds
Started Jul 20 06:05:18 PM PDT 24
Finished Jul 20 06:05:54 PM PDT 24
Peak memory 200184 kb
Host smart-93c03e2e-302b-486c-86bb-4578167fec62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488225719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1488225719
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1728698885
Short name T313
Test name
Test status
Simulation time 3276162808 ps
CPU time 1.18 seconds
Started Jul 20 06:05:15 PM PDT 24
Finished Jul 20 06:05:16 PM PDT 24
Peak memory 197048 kb
Host smart-4eab156d-e17c-4ab9-b261-f88c3b5fa80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728698885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1728698885
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1291857796
Short name T68
Test name
Test status
Simulation time 717105307 ps
CPU time 1.44 seconds
Started Jul 20 06:05:17 PM PDT 24
Finished Jul 20 06:05:19 PM PDT 24
Peak memory 199072 kb
Host smart-77417f76-60d2-42a1-960f-eb27a90dd5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291857796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1291857796
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.536656993
Short name T982
Test name
Test status
Simulation time 142038002863 ps
CPU time 209.27 seconds
Started Jul 20 06:05:15 PM PDT 24
Finished Jul 20 06:08:44 PM PDT 24
Peak memory 200244 kb
Host smart-0a95e5f3-f492-4aa2-ba14-7add65439f1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536656993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.536656993
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3991353354
Short name T492
Test name
Test status
Simulation time 146608098299 ps
CPU time 166.08 seconds
Started Jul 20 06:05:17 PM PDT 24
Finished Jul 20 06:08:04 PM PDT 24
Peak memory 214436 kb
Host smart-b156ab49-dbbd-41be-8f30-71c72b7c01a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991353354 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3991353354
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.585775199
Short name T1074
Test name
Test status
Simulation time 838423540 ps
CPU time 3.06 seconds
Started Jul 20 06:05:20 PM PDT 24
Finished Jul 20 06:05:24 PM PDT 24
Peak memory 198948 kb
Host smart-fb014224-0385-4a9b-a6f4-cc8af3ff3fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585775199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.585775199
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2879344494
Short name T745
Test name
Test status
Simulation time 35650835429 ps
CPU time 60.4 seconds
Started Jul 20 06:05:18 PM PDT 24
Finished Jul 20 06:06:19 PM PDT 24
Peak memory 200180 kb
Host smart-872a4731-8bb0-4f57-80b9-ac52374e8d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879344494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2879344494
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2646804784
Short name T266
Test name
Test status
Simulation time 104433313224 ps
CPU time 44.81 seconds
Started Jul 20 06:09:32 PM PDT 24
Finished Jul 20 06:10:17 PM PDT 24
Peak memory 200184 kb
Host smart-39f9d93d-6599-4aa1-b619-fa10fe04c101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646804784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2646804784
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3750805022
Short name T71
Test name
Test status
Simulation time 148256771802 ps
CPU time 24.25 seconds
Started Jul 20 06:09:31 PM PDT 24
Finished Jul 20 06:09:55 PM PDT 24
Peak memory 200100 kb
Host smart-d88a9e84-5bc7-40d0-a3e6-3f5ed1467921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750805022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3750805022
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3976527544
Short name T41
Test name
Test status
Simulation time 153944704099 ps
CPU time 61.92 seconds
Started Jul 20 06:09:29 PM PDT 24
Finished Jul 20 06:10:31 PM PDT 24
Peak memory 200192 kb
Host smart-0a19e863-b4f5-4c7a-9c39-5f55b6299c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976527544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3976527544
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.78571942
Short name T877
Test name
Test status
Simulation time 33812484644 ps
CPU time 15.45 seconds
Started Jul 20 06:09:31 PM PDT 24
Finished Jul 20 06:09:47 PM PDT 24
Peak memory 200192 kb
Host smart-e5a8cc1c-bcd7-4f8b-b25f-aa58611304e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78571942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.78571942
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3413230456
Short name T67
Test name
Test status
Simulation time 97321943230 ps
CPU time 15.46 seconds
Started Jul 20 06:09:33 PM PDT 24
Finished Jul 20 06:09:49 PM PDT 24
Peak memory 200120 kb
Host smart-179e7fc9-d057-4d66-824a-bcf78cd7f1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413230456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3413230456
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2839776784
Short name T1021
Test name
Test status
Simulation time 75664569635 ps
CPU time 40.9 seconds
Started Jul 20 06:09:33 PM PDT 24
Finished Jul 20 06:10:14 PM PDT 24
Peak memory 200196 kb
Host smart-2225e144-ab5b-4e3e-b28a-b9808800663f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839776784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2839776784
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.544738326
Short name T810
Test name
Test status
Simulation time 264527822774 ps
CPU time 385.89 seconds
Started Jul 20 06:09:33 PM PDT 24
Finished Jul 20 06:16:00 PM PDT 24
Peak memory 200192 kb
Host smart-c789fb0c-596f-4ca1-ba86-9c48cad02538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544738326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.544738326
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1131264561
Short name T859
Test name
Test status
Simulation time 49342038756 ps
CPU time 20.3 seconds
Started Jul 20 06:09:34 PM PDT 24
Finished Jul 20 06:09:55 PM PDT 24
Peak memory 200124 kb
Host smart-678834ed-edb6-49d0-bbc9-41641851b45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131264561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1131264561
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.909649279
Short name T543
Test name
Test status
Simulation time 11225775 ps
CPU time 0.56 seconds
Started Jul 20 06:05:30 PM PDT 24
Finished Jul 20 06:05:31 PM PDT 24
Peak memory 195572 kb
Host smart-0c103264-0027-40e9-9f6a-9bdbeba7d95b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909649279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.909649279
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1648149655
Short name T1109
Test name
Test status
Simulation time 24825230581 ps
CPU time 20.38 seconds
Started Jul 20 06:05:16 PM PDT 24
Finished Jul 20 06:05:37 PM PDT 24
Peak memory 200144 kb
Host smart-37bcf6dd-da52-463f-b4ec-9b3feca77d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648149655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1648149655
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2718836107
Short name T589
Test name
Test status
Simulation time 131569437556 ps
CPU time 53.14 seconds
Started Jul 20 06:05:18 PM PDT 24
Finished Jul 20 06:06:12 PM PDT 24
Peak memory 200036 kb
Host smart-cdf3aafa-7daa-433b-b1a5-b4cc52e67155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718836107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2718836107
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3095571269
Short name T559
Test name
Test status
Simulation time 105761357740 ps
CPU time 98 seconds
Started Jul 20 06:05:19 PM PDT 24
Finished Jul 20 06:06:58 PM PDT 24
Peak memory 200096 kb
Host smart-0f5787a1-4b7c-425b-a4cb-80c5a622f8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095571269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3095571269
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2486184250
Short name T348
Test name
Test status
Simulation time 21475961432 ps
CPU time 32.12 seconds
Started Jul 20 06:05:18 PM PDT 24
Finished Jul 20 06:05:51 PM PDT 24
Peak memory 198484 kb
Host smart-25614829-79bc-4b96-868f-ef3a43ac2596
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486184250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2486184250
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3425952981
Short name T413
Test name
Test status
Simulation time 87386355455 ps
CPU time 471.79 seconds
Started Jul 20 06:05:28 PM PDT 24
Finished Jul 20 06:13:21 PM PDT 24
Peak memory 200116 kb
Host smart-0e02d886-9fa2-4349-8a7c-cc3c7a880780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425952981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3425952981
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3744829194
Short name T1122
Test name
Test status
Simulation time 3497126310 ps
CPU time 9.69 seconds
Started Jul 20 06:05:28 PM PDT 24
Finished Jul 20 06:05:38 PM PDT 24
Peak memory 199868 kb
Host smart-758e7e99-5bf9-4a0e-b723-31882ebaf673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744829194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3744829194
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3935418379
Short name T565
Test name
Test status
Simulation time 44973745866 ps
CPU time 60.69 seconds
Started Jul 20 06:05:27 PM PDT 24
Finished Jul 20 06:06:28 PM PDT 24
Peak memory 200304 kb
Host smart-54fbb581-7cce-414f-afba-217e5ddc8c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935418379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3935418379
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.4077304951
Short name T637
Test name
Test status
Simulation time 9310934533 ps
CPU time 550.81 seconds
Started Jul 20 06:05:31 PM PDT 24
Finished Jul 20 06:14:42 PM PDT 24
Peak memory 200112 kb
Host smart-a83ff248-4617-41a4-bd73-b248803f5ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077304951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.4077304951
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1038460807
Short name T446
Test name
Test status
Simulation time 7665741428 ps
CPU time 9.6 seconds
Started Jul 20 06:05:19 PM PDT 24
Finished Jul 20 06:05:29 PM PDT 24
Peak memory 198368 kb
Host smart-e9d1355b-f396-4aed-bdb1-92fa07087cb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1038460807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1038460807
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1435550459
Short name T1160
Test name
Test status
Simulation time 14632963577 ps
CPU time 14.46 seconds
Started Jul 20 06:05:29 PM PDT 24
Finished Jul 20 06:05:44 PM PDT 24
Peak memory 200092 kb
Host smart-5ec8ab6d-8c02-4a4d-ab39-a2df3b807cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435550459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1435550459
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2341567379
Short name T857
Test name
Test status
Simulation time 36633517139 ps
CPU time 14.59 seconds
Started Jul 20 06:05:29 PM PDT 24
Finished Jul 20 06:05:45 PM PDT 24
Peak memory 197000 kb
Host smart-ea62aac6-9e47-43a1-87d0-59612c7b1d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341567379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2341567379
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2397458111
Short name T429
Test name
Test status
Simulation time 5542115220 ps
CPU time 10.03 seconds
Started Jul 20 06:05:18 PM PDT 24
Finished Jul 20 06:05:29 PM PDT 24
Peak memory 200184 kb
Host smart-cfffb183-9af6-44dd-b3f9-f45b00917f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397458111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2397458111
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1752145258
Short name T929
Test name
Test status
Simulation time 171785196294 ps
CPU time 232.85 seconds
Started Jul 20 06:05:29 PM PDT 24
Finished Jul 20 06:09:22 PM PDT 24
Peak memory 200156 kb
Host smart-09ccdd8d-276a-4f7f-81e6-6d96781945b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752145258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1752145258
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.113616960
Short name T47
Test name
Test status
Simulation time 107004694315 ps
CPU time 182.65 seconds
Started Jul 20 06:05:28 PM PDT 24
Finished Jul 20 06:08:31 PM PDT 24
Peak memory 216804 kb
Host smart-2f93883a-c02f-47ab-b7e9-b211aa206691
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113616960 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.113616960
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2030394233
Short name T1007
Test name
Test status
Simulation time 12843227478 ps
CPU time 20.39 seconds
Started Jul 20 06:05:26 PM PDT 24
Finished Jul 20 06:05:47 PM PDT 24
Peak memory 200184 kb
Host smart-6a547dd2-596e-44d0-9680-b0aa8dee7c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030394233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2030394233
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1908806551
Short name T130
Test name
Test status
Simulation time 94896259110 ps
CPU time 39.84 seconds
Started Jul 20 06:09:31 PM PDT 24
Finished Jul 20 06:10:12 PM PDT 24
Peak memory 200204 kb
Host smart-35fa127c-27ba-46c7-9349-3f056050bce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908806551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1908806551
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1889080032
Short name T921
Test name
Test status
Simulation time 193939038014 ps
CPU time 35.29 seconds
Started Jul 20 06:09:33 PM PDT 24
Finished Jul 20 06:10:08 PM PDT 24
Peak memory 200076 kb
Host smart-b91c25df-902b-402d-bc7d-6a8eb1090bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889080032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1889080032
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1337857917
Short name T926
Test name
Test status
Simulation time 111145850081 ps
CPU time 159.75 seconds
Started Jul 20 06:09:30 PM PDT 24
Finished Jul 20 06:12:10 PM PDT 24
Peak memory 200252 kb
Host smart-371d7780-ee64-47db-a3c2-29ef1a084b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337857917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1337857917
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2821499515
Short name T486
Test name
Test status
Simulation time 144953686289 ps
CPU time 47.31 seconds
Started Jul 20 06:09:40 PM PDT 24
Finished Jul 20 06:10:28 PM PDT 24
Peak memory 200184 kb
Host smart-6ce3b682-6a9f-4ffe-9b1f-f894f5204731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821499515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2821499515
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.4260846464
Short name T208
Test name
Test status
Simulation time 9875752261 ps
CPU time 16.98 seconds
Started Jul 20 06:09:38 PM PDT 24
Finished Jul 20 06:09:56 PM PDT 24
Peak memory 199996 kb
Host smart-08b7a4d2-e1ec-4ca7-bcf6-a558364e047d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260846464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.4260846464
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1808707374
Short name T849
Test name
Test status
Simulation time 82782571165 ps
CPU time 312.35 seconds
Started Jul 20 06:09:38 PM PDT 24
Finished Jul 20 06:14:51 PM PDT 24
Peak memory 200176 kb
Host smart-caa3a183-6f14-40c8-8cb5-f69e8c08f965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808707374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1808707374
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3415626802
Short name T1116
Test name
Test status
Simulation time 51455103885 ps
CPU time 30.08 seconds
Started Jul 20 06:09:41 PM PDT 24
Finished Jul 20 06:10:12 PM PDT 24
Peak memory 200180 kb
Host smart-e6833afd-a469-4c9c-a17b-41bb38ab448a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415626802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3415626802
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.262729634
Short name T968
Test name
Test status
Simulation time 22373696 ps
CPU time 0.57 seconds
Started Jul 20 06:05:45 PM PDT 24
Finished Jul 20 06:05:46 PM PDT 24
Peak memory 195568 kb
Host smart-c111fd6c-39ed-44ea-8080-f89f44bcd8a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262729634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.262729634
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2374089893
Short name T713
Test name
Test status
Simulation time 14416787228 ps
CPU time 13.51 seconds
Started Jul 20 06:05:26 PM PDT 24
Finished Jul 20 06:05:40 PM PDT 24
Peak memory 200112 kb
Host smart-203e0e78-7a8c-43aa-8cef-041ace8b5a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374089893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2374089893
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2497612614
Short name T176
Test name
Test status
Simulation time 15438372516 ps
CPU time 31.79 seconds
Started Jul 20 06:05:28 PM PDT 24
Finished Jul 20 06:06:00 PM PDT 24
Peak memory 200192 kb
Host smart-014f2ffa-8b0e-4f89-a736-995ba2c0b5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497612614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2497612614
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3241014266
Short name T15
Test name
Test status
Simulation time 29560667047 ps
CPU time 21.22 seconds
Started Jul 20 06:05:27 PM PDT 24
Finished Jul 20 06:05:48 PM PDT 24
Peak memory 200228 kb
Host smart-9e3f32fd-c4f7-43c2-b54f-adbed23a7116
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241014266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3241014266
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1117452720
Short name T938
Test name
Test status
Simulation time 248120317685 ps
CPU time 508.75 seconds
Started Jul 20 06:05:41 PM PDT 24
Finished Jul 20 06:14:10 PM PDT 24
Peak memory 200060 kb
Host smart-0278207b-a0a4-4b80-89d8-c0f4a128cc35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117452720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1117452720
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2392632960
Short name T961
Test name
Test status
Simulation time 2485834994 ps
CPU time 2.72 seconds
Started Jul 20 06:05:38 PM PDT 24
Finished Jul 20 06:05:42 PM PDT 24
Peak memory 198760 kb
Host smart-ff8e7f81-7ab5-4840-b704-f12194465a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392632960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2392632960
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.872899871
Short name T611
Test name
Test status
Simulation time 136923421325 ps
CPU time 57.48 seconds
Started Jul 20 06:05:28 PM PDT 24
Finished Jul 20 06:06:26 PM PDT 24
Peak memory 200228 kb
Host smart-ba8134f3-535f-4ffa-a688-167958faebe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872899871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.872899871
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3926837814
Short name T654
Test name
Test status
Simulation time 3912611427 ps
CPU time 243.56 seconds
Started Jul 20 06:05:44 PM PDT 24
Finished Jul 20 06:09:48 PM PDT 24
Peak memory 200172 kb
Host smart-69d12b58-0cb0-415f-9f6a-e4ff71efa240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926837814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3926837814
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1463364396
Short name T338
Test name
Test status
Simulation time 7824500409 ps
CPU time 9.75 seconds
Started Jul 20 06:05:29 PM PDT 24
Finished Jul 20 06:05:39 PM PDT 24
Peak memory 197984 kb
Host smart-c1bf7e5a-bf2a-4461-8dcf-4f4af5b9785d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463364396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1463364396
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.166711802
Short name T783
Test name
Test status
Simulation time 155560530856 ps
CPU time 63.93 seconds
Started Jul 20 06:05:37 PM PDT 24
Finished Jul 20 06:06:42 PM PDT 24
Peak memory 200136 kb
Host smart-32313f9e-56db-44e9-b07e-e5e245710c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166711802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.166711802
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3384661751
Short name T278
Test name
Test status
Simulation time 35184495064 ps
CPU time 28.04 seconds
Started Jul 20 06:05:26 PM PDT 24
Finished Jul 20 06:05:55 PM PDT 24
Peak memory 196500 kb
Host smart-6747d8e5-b509-4de4-a9f1-ca9223b1fd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384661751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3384661751
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.4224996505
Short name T815
Test name
Test status
Simulation time 268729312 ps
CPU time 1.27 seconds
Started Jul 20 06:05:30 PM PDT 24
Finished Jul 20 06:05:32 PM PDT 24
Peak memory 198716 kb
Host smart-2aff512a-fa5d-432b-bdac-faed17af199e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224996505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.4224996505
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3382907819
Short name T1055
Test name
Test status
Simulation time 11016097890 ps
CPU time 221.74 seconds
Started Jul 20 06:05:35 PM PDT 24
Finished Jul 20 06:09:17 PM PDT 24
Peak memory 208520 kb
Host smart-713ed031-12f7-4ff1-9d67-5464c42b7c09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382907819 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3382907819
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.778578425
Short name T978
Test name
Test status
Simulation time 1408707126 ps
CPU time 1.39 seconds
Started Jul 20 06:05:36 PM PDT 24
Finished Jul 20 06:05:38 PM PDT 24
Peak memory 197192 kb
Host smart-65a954e6-6838-4d16-afbc-b569dde47e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778578425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.778578425
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3309458218
Short name T803
Test name
Test status
Simulation time 8699556481 ps
CPU time 4.38 seconds
Started Jul 20 06:05:28 PM PDT 24
Finished Jul 20 06:05:33 PM PDT 24
Peak memory 200120 kb
Host smart-bfe24086-bc9c-4806-89c5-23ed3a2776b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309458218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3309458218
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3204943630
Short name T1088
Test name
Test status
Simulation time 181118074451 ps
CPU time 41.9 seconds
Started Jul 20 06:09:40 PM PDT 24
Finished Jul 20 06:10:23 PM PDT 24
Peak memory 200184 kb
Host smart-374c33f0-e745-4b9b-a8a9-395303411eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204943630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3204943630
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.4085125107
Short name T672
Test name
Test status
Simulation time 75093585074 ps
CPU time 13.84 seconds
Started Jul 20 06:09:40 PM PDT 24
Finished Jul 20 06:09:55 PM PDT 24
Peak memory 200076 kb
Host smart-77e457b7-83ba-4ca3-8276-f867316e9ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085125107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.4085125107
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.133728830
Short name T639
Test name
Test status
Simulation time 105519347484 ps
CPU time 150.28 seconds
Started Jul 20 06:09:40 PM PDT 24
Finished Jul 20 06:12:11 PM PDT 24
Peak memory 200184 kb
Host smart-8884f752-802e-451c-aa7d-754bf178eac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133728830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.133728830
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2347684131
Short name T1077
Test name
Test status
Simulation time 51865867482 ps
CPU time 24.31 seconds
Started Jul 20 06:09:38 PM PDT 24
Finished Jul 20 06:10:03 PM PDT 24
Peak memory 200112 kb
Host smart-917fe6c9-5074-415d-ad2e-7ae9feff47a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347684131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2347684131
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.7762594
Short name T651
Test name
Test status
Simulation time 136545674902 ps
CPU time 62.53 seconds
Started Jul 20 06:09:42 PM PDT 24
Finished Jul 20 06:10:46 PM PDT 24
Peak memory 200172 kb
Host smart-15bfe3e3-ed9b-448f-b91d-e9cbeced15da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7762594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.7762594
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.4276965360
Short name T461
Test name
Test status
Simulation time 86998987947 ps
CPU time 255.98 seconds
Started Jul 20 06:09:39 PM PDT 24
Finished Jul 20 06:13:55 PM PDT 24
Peak memory 200316 kb
Host smart-68d0dc59-4a70-4f06-98b2-c52bea933944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276965360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.4276965360
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3842172236
Short name T986
Test name
Test status
Simulation time 27123035403 ps
CPU time 43.11 seconds
Started Jul 20 06:09:41 PM PDT 24
Finished Jul 20 06:10:24 PM PDT 24
Peak memory 200136 kb
Host smart-42eb0437-24ae-4ad5-a8a2-880d3ff407fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842172236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3842172236
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1375823746
Short name T569
Test name
Test status
Simulation time 23280227449 ps
CPU time 51.06 seconds
Started Jul 20 06:09:40 PM PDT 24
Finished Jul 20 06:10:31 PM PDT 24
Peak memory 200136 kb
Host smart-9b8b73c4-644f-48c5-a26f-09f95a623981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375823746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1375823746
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.804515227
Short name T152
Test name
Test status
Simulation time 65045854977 ps
CPU time 27.57 seconds
Started Jul 20 06:09:44 PM PDT 24
Finished Jul 20 06:10:12 PM PDT 24
Peak memory 200124 kb
Host smart-bc46109b-6f3e-4177-9408-5f39e1184b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804515227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.804515227
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.954949504
Short name T235
Test name
Test status
Simulation time 72509849824 ps
CPU time 29.57 seconds
Started Jul 20 06:09:38 PM PDT 24
Finished Jul 20 06:10:08 PM PDT 24
Peak memory 200224 kb
Host smart-98ea09e3-b81a-4f7f-b655-0ba1c741b061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954949504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.954949504
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3430031309
Short name T618
Test name
Test status
Simulation time 19878269 ps
CPU time 0.58 seconds
Started Jul 20 06:05:38 PM PDT 24
Finished Jul 20 06:05:40 PM PDT 24
Peak memory 195756 kb
Host smart-df0f4db7-409d-43f5-ba7e-1177f0b499ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430031309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3430031309
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3076533717
Short name T973
Test name
Test status
Simulation time 10096781583 ps
CPU time 15.7 seconds
Started Jul 20 06:05:38 PM PDT 24
Finished Jul 20 06:05:55 PM PDT 24
Peak memory 199984 kb
Host smart-fbd538d0-406a-4f3f-9885-de80fa0f6a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076533717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3076533717
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2597102042
Short name T1125
Test name
Test status
Simulation time 80317164963 ps
CPU time 32.41 seconds
Started Jul 20 06:05:38 PM PDT 24
Finished Jul 20 06:06:11 PM PDT 24
Peak memory 200112 kb
Host smart-165691da-e115-4a93-a211-fdb44e197a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597102042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2597102042
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1862192243
Short name T868
Test name
Test status
Simulation time 37853096646 ps
CPU time 18.74 seconds
Started Jul 20 06:05:36 PM PDT 24
Finished Jul 20 06:05:56 PM PDT 24
Peak memory 199896 kb
Host smart-552ec8e3-151b-48e9-9ffd-773d174f8d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862192243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1862192243
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2334610495
Short name T1100
Test name
Test status
Simulation time 152945158837 ps
CPU time 45.01 seconds
Started Jul 20 06:05:40 PM PDT 24
Finished Jul 20 06:06:26 PM PDT 24
Peak memory 199168 kb
Host smart-30253543-0514-4583-8102-95eae88c6862
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334610495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2334610495
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.4227311362
Short name T256
Test name
Test status
Simulation time 84622356228 ps
CPU time 912.49 seconds
Started Jul 20 06:05:36 PM PDT 24
Finished Jul 20 06:20:49 PM PDT 24
Peak memory 200156 kb
Host smart-26049663-61ee-4ee4-bd24-c7ac5d428f05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227311362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.4227311362
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2482655005
Short name T518
Test name
Test status
Simulation time 5688365037 ps
CPU time 11.59 seconds
Started Jul 20 06:05:38 PM PDT 24
Finished Jul 20 06:05:51 PM PDT 24
Peak memory 199716 kb
Host smart-efd1a015-9bc2-428f-ab5f-e8d91eb75506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482655005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2482655005
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2163848304
Short name T1054
Test name
Test status
Simulation time 66831897552 ps
CPU time 60.03 seconds
Started Jul 20 06:05:35 PM PDT 24
Finished Jul 20 06:06:35 PM PDT 24
Peak memory 200304 kb
Host smart-6a4bdf81-e13c-4f48-8626-d89f217d7892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163848304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2163848304
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1114036578
Short name T1170
Test name
Test status
Simulation time 18676312998 ps
CPU time 166.54 seconds
Started Jul 20 06:05:37 PM PDT 24
Finished Jul 20 06:08:25 PM PDT 24
Peak memory 200128 kb
Host smart-6cc6eeec-4bba-447e-84f8-7de9aa47517b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114036578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1114036578
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1222974843
Short name T724
Test name
Test status
Simulation time 3032745104 ps
CPU time 20.59 seconds
Started Jul 20 06:05:45 PM PDT 24
Finished Jul 20 06:06:06 PM PDT 24
Peak memory 198252 kb
Host smart-da5a2af2-2380-4720-b4c9-a0a8702a6a33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222974843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1222974843
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.379627066
Short name T597
Test name
Test status
Simulation time 97195160462 ps
CPU time 197.38 seconds
Started Jul 20 06:05:37 PM PDT 24
Finished Jul 20 06:08:56 PM PDT 24
Peak memory 200200 kb
Host smart-872ec7ba-21c9-4bde-8a5e-effd3450e591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379627066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.379627066
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3498881755
Short name T936
Test name
Test status
Simulation time 61906501379 ps
CPU time 86.68 seconds
Started Jul 20 06:05:37 PM PDT 24
Finished Jul 20 06:07:04 PM PDT 24
Peak memory 196200 kb
Host smart-6909f4dc-c0c3-4fd1-9e35-0731ef729007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498881755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3498881755
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.570854778
Short name T648
Test name
Test status
Simulation time 248933252 ps
CPU time 1.02 seconds
Started Jul 20 06:05:40 PM PDT 24
Finished Jul 20 06:05:42 PM PDT 24
Peak memory 198560 kb
Host smart-ae67daec-4278-4d4c-b280-2f7d62069b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570854778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.570854778
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.2620608592
Short name T826
Test name
Test status
Simulation time 242671155845 ps
CPU time 220.38 seconds
Started Jul 20 06:05:38 PM PDT 24
Finished Jul 20 06:09:19 PM PDT 24
Peak memory 200104 kb
Host smart-d7e4c8b9-e600-47b8-b5e6-fb70a5934257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620608592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2620608592
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2436800245
Short name T108
Test name
Test status
Simulation time 267241786339 ps
CPU time 722.62 seconds
Started Jul 20 06:05:42 PM PDT 24
Finished Jul 20 06:17:46 PM PDT 24
Peak memory 216740 kb
Host smart-11c2bee2-b939-4ecf-b9a1-deac3ca0429a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436800245 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2436800245
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.275178360
Short name T915
Test name
Test status
Simulation time 6356621628 ps
CPU time 25.25 seconds
Started Jul 20 06:05:34 PM PDT 24
Finished Jul 20 06:06:00 PM PDT 24
Peak memory 200052 kb
Host smart-86b50ed0-2225-480d-ac6f-fdaa9e042c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275178360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.275178360
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3405781394
Short name T1104
Test name
Test status
Simulation time 33150428216 ps
CPU time 123.05 seconds
Started Jul 20 06:05:37 PM PDT 24
Finished Jul 20 06:07:41 PM PDT 24
Peak memory 200196 kb
Host smart-9be693c3-cc68-46af-aac3-862c3e8707f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405781394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3405781394
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.263963813
Short name T917
Test name
Test status
Simulation time 30935219803 ps
CPU time 16.15 seconds
Started Jul 20 06:09:41 PM PDT 24
Finished Jul 20 06:09:58 PM PDT 24
Peak memory 200196 kb
Host smart-b9b69e4a-0e79-4436-b259-cc9986109218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263963813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.263963813
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2224996689
Short name T1013
Test name
Test status
Simulation time 142782527760 ps
CPU time 52.91 seconds
Started Jul 20 06:09:39 PM PDT 24
Finished Jul 20 06:10:32 PM PDT 24
Peak memory 200184 kb
Host smart-3f12c9f5-4531-4a5b-90f7-1d784b04245e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224996689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2224996689
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2015648043
Short name T482
Test name
Test status
Simulation time 95527981939 ps
CPU time 30.22 seconds
Started Jul 20 06:09:50 PM PDT 24
Finished Jul 20 06:10:21 PM PDT 24
Peak memory 200128 kb
Host smart-80eef119-c915-47f4-9dba-4597a28cde28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015648043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2015648043
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3674985372
Short name T228
Test name
Test status
Simulation time 62670679704 ps
CPU time 45.22 seconds
Started Jul 20 06:09:49 PM PDT 24
Finished Jul 20 06:10:35 PM PDT 24
Peak memory 200116 kb
Host smart-a548cd69-cfe8-4ddf-b30b-be6ad4dedafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674985372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3674985372
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.4130162411
Short name T1017
Test name
Test status
Simulation time 81227970322 ps
CPU time 247.77 seconds
Started Jul 20 06:09:47 PM PDT 24
Finished Jul 20 06:13:56 PM PDT 24
Peak memory 200112 kb
Host smart-53dff807-7154-405c-a279-04440e7da225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130162411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.4130162411
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1908120984
Short name T508
Test name
Test status
Simulation time 102464121125 ps
CPU time 263.4 seconds
Started Jul 20 06:09:47 PM PDT 24
Finished Jul 20 06:14:11 PM PDT 24
Peak memory 200196 kb
Host smart-e9c6c5a2-b4df-482d-90be-11a5e6fc69f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908120984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1908120984
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.884976355
Short name T594
Test name
Test status
Simulation time 9353257018 ps
CPU time 14.08 seconds
Started Jul 20 06:09:47 PM PDT 24
Finished Jul 20 06:10:02 PM PDT 24
Peak memory 199740 kb
Host smart-6f1035c2-8dfc-4641-82e4-b128cc4b0df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884976355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.884976355
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3961648262
Short name T374
Test name
Test status
Simulation time 41837555662 ps
CPU time 35.04 seconds
Started Jul 20 06:09:50 PM PDT 24
Finished Jul 20 06:10:26 PM PDT 24
Peak memory 200196 kb
Host smart-f3f9b752-b7dc-41ff-8a70-983c986ebcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961648262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3961648262
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.277610241
Short name T888
Test name
Test status
Simulation time 44005560729 ps
CPU time 17.87 seconds
Started Jul 20 06:09:49 PM PDT 24
Finished Jul 20 06:10:08 PM PDT 24
Peak memory 200196 kb
Host smart-c8bd5a7f-3226-49fe-ba18-93ea28f370c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277610241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.277610241
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2158635360
Short name T20
Test name
Test status
Simulation time 14331675 ps
CPU time 0.62 seconds
Started Jul 20 06:05:46 PM PDT 24
Finished Jul 20 06:05:47 PM PDT 24
Peak memory 195472 kb
Host smart-203b5599-036e-4359-8250-646cd6e7bd10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158635360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2158635360
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3678134223
Short name T792
Test name
Test status
Simulation time 47817997449 ps
CPU time 15.14 seconds
Started Jul 20 06:05:39 PM PDT 24
Finished Jul 20 06:05:55 PM PDT 24
Peak memory 200120 kb
Host smart-0d1e4fce-37b8-427b-911d-0527add34b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678134223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3678134223
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3388410756
Short name T673
Test name
Test status
Simulation time 37208623312 ps
CPU time 76.06 seconds
Started Jul 20 06:05:40 PM PDT 24
Finished Jul 20 06:06:57 PM PDT 24
Peak memory 200188 kb
Host smart-ea6e92b3-8f56-4a65-a08d-57756a8f494d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388410756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3388410756
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3151506211
Short name T1113
Test name
Test status
Simulation time 250450252714 ps
CPU time 27.74 seconds
Started Jul 20 06:05:40 PM PDT 24
Finished Jul 20 06:06:09 PM PDT 24
Peak memory 200052 kb
Host smart-956f6732-5c43-4209-93f9-f52c309004d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151506211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3151506211
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1888059204
Short name T468
Test name
Test status
Simulation time 307093095423 ps
CPU time 533.09 seconds
Started Jul 20 06:05:44 PM PDT 24
Finished Jul 20 06:14:38 PM PDT 24
Peak memory 200128 kb
Host smart-5f3b3f04-9171-4192-a45d-6101504999f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888059204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1888059204
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1604830779
Short name T1000
Test name
Test status
Simulation time 74024487157 ps
CPU time 190.03 seconds
Started Jul 20 06:05:47 PM PDT 24
Finished Jul 20 06:08:58 PM PDT 24
Peak memory 200160 kb
Host smart-179e7566-0762-4ce7-ac59-059e14fdda7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604830779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1604830779
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1564823909
Short name T875
Test name
Test status
Simulation time 10031840488 ps
CPU time 12.3 seconds
Started Jul 20 06:05:46 PM PDT 24
Finished Jul 20 06:05:59 PM PDT 24
Peak memory 200104 kb
Host smart-71a86696-ad5e-4e43-a8bb-7300a8f755f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564823909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1564823909
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2132694894
Short name T909
Test name
Test status
Simulation time 54504505845 ps
CPU time 49.15 seconds
Started Jul 20 06:05:50 PM PDT 24
Finished Jul 20 06:06:39 PM PDT 24
Peak memory 198732 kb
Host smart-d85704ea-a419-4aae-a93f-37fbe1e8e1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132694894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2132694894
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.573766389
Short name T850
Test name
Test status
Simulation time 16761163409 ps
CPU time 380.58 seconds
Started Jul 20 06:05:48 PM PDT 24
Finished Jul 20 06:12:09 PM PDT 24
Peak memory 200180 kb
Host smart-9135d742-7d48-48bf-9bfa-f7e9d04a4702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573766389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.573766389
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1411416635
Short name T769
Test name
Test status
Simulation time 7505550316 ps
CPU time 67.42 seconds
Started Jul 20 06:05:41 PM PDT 24
Finished Jul 20 06:06:49 PM PDT 24
Peak memory 198284 kb
Host smart-d0ae0661-5cca-434f-b6a4-bb92fd98ca6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411416635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1411416635
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1739796868
Short name T717
Test name
Test status
Simulation time 38474565722 ps
CPU time 13.51 seconds
Started Jul 20 06:05:48 PM PDT 24
Finished Jul 20 06:06:02 PM PDT 24
Peak memory 200156 kb
Host smart-3564bada-1a39-4fa1-8a57-e196830242de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739796868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1739796868
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.932137603
Short name T351
Test name
Test status
Simulation time 3550732162 ps
CPU time 5.83 seconds
Started Jul 20 06:05:48 PM PDT 24
Finished Jul 20 06:05:54 PM PDT 24
Peak memory 196484 kb
Host smart-d35bd85a-6248-4c69-8b0e-d4426654592b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932137603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.932137603
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3333719010
Short name T1010
Test name
Test status
Simulation time 297194467 ps
CPU time 1.09 seconds
Started Jul 20 06:05:35 PM PDT 24
Finished Jul 20 06:05:36 PM PDT 24
Peak memory 198708 kb
Host smart-6c6c37f2-e2b5-4b84-b0c2-9adfa47e505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333719010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3333719010
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.971995961
Short name T1056
Test name
Test status
Simulation time 65683765973 ps
CPU time 583.02 seconds
Started Jul 20 06:05:47 PM PDT 24
Finished Jul 20 06:15:31 PM PDT 24
Peak memory 200180 kb
Host smart-abbde2f1-ace3-4907-a48c-3e3fa7adfd5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971995961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.971995961
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3533372383
Short name T53
Test name
Test status
Simulation time 43379442912 ps
CPU time 773.4 seconds
Started Jul 20 06:05:47 PM PDT 24
Finished Jul 20 06:18:41 PM PDT 24
Peak memory 225088 kb
Host smart-35c6d1db-b59b-4b81-b847-cfa41f17d88d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533372383 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3533372383
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3223351329
Short name T299
Test name
Test status
Simulation time 6694842523 ps
CPU time 24.63 seconds
Started Jul 20 06:05:47 PM PDT 24
Finished Jul 20 06:06:12 PM PDT 24
Peak memory 200088 kb
Host smart-7b56b4cc-0789-4784-8ecd-bcb622272bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223351329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3223351329
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.781517999
Short name T39
Test name
Test status
Simulation time 41456400392 ps
CPU time 19.25 seconds
Started Jul 20 06:05:39 PM PDT 24
Finished Jul 20 06:05:59 PM PDT 24
Peak memory 200172 kb
Host smart-05ec836a-1005-46af-af44-b4455f935df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781517999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.781517999
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3704766991
Short name T1058
Test name
Test status
Simulation time 21593244874 ps
CPU time 18.59 seconds
Started Jul 20 06:09:49 PM PDT 24
Finished Jul 20 06:10:08 PM PDT 24
Peak memory 200136 kb
Host smart-e8422ada-0085-41f2-9d33-addc817e2757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704766991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3704766991
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3150843304
Short name T548
Test name
Test status
Simulation time 144123867934 ps
CPU time 207.93 seconds
Started Jul 20 06:09:49 PM PDT 24
Finished Jul 20 06:13:18 PM PDT 24
Peak memory 200196 kb
Host smart-1409347b-f1a7-4947-a940-d6fe66960c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150843304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3150843304
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3830568273
Short name T128
Test name
Test status
Simulation time 102009127863 ps
CPU time 75.13 seconds
Started Jul 20 06:09:47 PM PDT 24
Finished Jul 20 06:11:02 PM PDT 24
Peak memory 200128 kb
Host smart-557f3757-ae7c-4ece-a66b-42ae3feb379c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830568273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3830568273
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.4140269347
Short name T137
Test name
Test status
Simulation time 93538288533 ps
CPU time 31.79 seconds
Started Jul 20 06:09:47 PM PDT 24
Finished Jul 20 06:10:19 PM PDT 24
Peak memory 200152 kb
Host smart-72795016-6abd-4de3-a745-3361924b37c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140269347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.4140269347
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3482118568
Short name T861
Test name
Test status
Simulation time 149719277631 ps
CPU time 128.16 seconds
Started Jul 20 06:09:51 PM PDT 24
Finished Jul 20 06:11:59 PM PDT 24
Peak memory 200144 kb
Host smart-24526af2-75cb-4657-a9fd-66dd3085aea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482118568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3482118568
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2969577077
Short name T64
Test name
Test status
Simulation time 152987400329 ps
CPU time 93.27 seconds
Started Jul 20 06:09:51 PM PDT 24
Finished Jul 20 06:11:25 PM PDT 24
Peak memory 200116 kb
Host smart-911fec89-7f6c-4885-93c7-b9ac6edfad78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969577077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2969577077
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.869211151
Short name T199
Test name
Test status
Simulation time 41887944297 ps
CPU time 49.05 seconds
Started Jul 20 06:09:47 PM PDT 24
Finished Jul 20 06:10:37 PM PDT 24
Peak memory 200120 kb
Host smart-34676e71-37ab-4abd-a039-766184372798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869211151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.869211151
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3629924296
Short name T450
Test name
Test status
Simulation time 35375927 ps
CPU time 0.53 seconds
Started Jul 20 06:05:55 PM PDT 24
Finished Jul 20 06:05:56 PM PDT 24
Peak memory 194560 kb
Host smart-c963762c-5414-4230-a7d0-86928a5ed66d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629924296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3629924296
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3631948641
Short name T289
Test name
Test status
Simulation time 10832634103 ps
CPU time 17.31 seconds
Started Jul 20 06:05:44 PM PDT 24
Finished Jul 20 06:06:02 PM PDT 24
Peak memory 199988 kb
Host smart-bba761c4-580d-4f17-86f2-0ec58197897d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631948641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3631948641
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2351947383
Short name T473
Test name
Test status
Simulation time 68541938777 ps
CPU time 21.49 seconds
Started Jul 20 06:05:44 PM PDT 24
Finished Jul 20 06:06:06 PM PDT 24
Peak memory 200176 kb
Host smart-07a505d9-d0d4-4410-bf9e-f828a987d10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351947383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2351947383
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.955960759
Short name T731
Test name
Test status
Simulation time 105983902200 ps
CPU time 16.5 seconds
Started Jul 20 06:05:45 PM PDT 24
Finished Jul 20 06:06:02 PM PDT 24
Peak memory 200116 kb
Host smart-7a637746-2e47-43aa-bc9c-c7dfdcbef30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955960759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.955960759
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.4018810682
Short name T967
Test name
Test status
Simulation time 155314883949 ps
CPU time 66.42 seconds
Started Jul 20 06:05:48 PM PDT 24
Finished Jul 20 06:06:55 PM PDT 24
Peak memory 200200 kb
Host smart-88da0b01-b8dc-48a5-8df1-d5398ff5c339
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018810682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.4018810682
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.481097687
Short name T578
Test name
Test status
Simulation time 53194587192 ps
CPU time 402.67 seconds
Started Jul 20 06:05:53 PM PDT 24
Finished Jul 20 06:12:36 PM PDT 24
Peak memory 200136 kb
Host smart-7373eaa9-0452-4760-af13-50f1be2a13e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=481097687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.481097687
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.534757595
Short name T575
Test name
Test status
Simulation time 2558934287 ps
CPU time 4.98 seconds
Started Jul 20 06:05:45 PM PDT 24
Finished Jul 20 06:05:50 PM PDT 24
Peak memory 198012 kb
Host smart-61fee82b-0351-42a9-87bc-df71078bebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534757595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.534757595
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3340991659
Short name T496
Test name
Test status
Simulation time 71881148944 ps
CPU time 17.72 seconds
Started Jul 20 06:05:46 PM PDT 24
Finished Jul 20 06:06:04 PM PDT 24
Peak memory 197964 kb
Host smart-6751513f-6a62-4ef0-b0c6-74d29a74a986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340991659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3340991659
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.78102145
Short name T491
Test name
Test status
Simulation time 8124562982 ps
CPU time 329.66 seconds
Started Jul 20 06:05:55 PM PDT 24
Finished Jul 20 06:11:25 PM PDT 24
Peak memory 200140 kb
Host smart-8d2b871a-4299-4357-97e5-94c84ec6fe47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78102145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.78102145
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.4059680012
Short name T876
Test name
Test status
Simulation time 1920329122 ps
CPU time 3.1 seconds
Started Jul 20 06:05:48 PM PDT 24
Finished Jul 20 06:05:51 PM PDT 24
Peak memory 198212 kb
Host smart-4ace2a8c-1052-44ca-8fe8-5bdaad6abce5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4059680012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.4059680012
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2083100037
Short name T162
Test name
Test status
Simulation time 31607333702 ps
CPU time 13.37 seconds
Started Jul 20 06:05:49 PM PDT 24
Finished Jul 20 06:06:02 PM PDT 24
Peak memory 199964 kb
Host smart-4301e388-665d-46f8-b39f-4b84e8b749ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083100037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2083100037
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2004671566
Short name T288
Test name
Test status
Simulation time 3280533178 ps
CPU time 1.81 seconds
Started Jul 20 06:05:47 PM PDT 24
Finished Jul 20 06:05:49 PM PDT 24
Peak memory 196656 kb
Host smart-85ed2a89-d077-4724-b491-3d10e13b08e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004671566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2004671566
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3721182441
Short name T601
Test name
Test status
Simulation time 653125554 ps
CPU time 1.61 seconds
Started Jul 20 06:05:47 PM PDT 24
Finished Jul 20 06:05:49 PM PDT 24
Peak memory 198648 kb
Host smart-6f0d3f4d-e48f-4019-a959-1a3e0164ffa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721182441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3721182441
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3427319123
Short name T1156
Test name
Test status
Simulation time 123294769001 ps
CPU time 232.97 seconds
Started Jul 20 06:05:56 PM PDT 24
Finished Jul 20 06:09:50 PM PDT 24
Peak memory 200120 kb
Host smart-baafa004-5458-4c3b-9c62-ce06b2d6d6dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427319123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3427319123
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.338854551
Short name T1146
Test name
Test status
Simulation time 126439921661 ps
CPU time 171.92 seconds
Started Jul 20 06:05:56 PM PDT 24
Finished Jul 20 06:08:48 PM PDT 24
Peak memory 216804 kb
Host smart-c13a41b7-717f-4f93-9fd9-d5bb1f229e0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338854551 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.338854551
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3415233701
Short name T563
Test name
Test status
Simulation time 6854899114 ps
CPU time 27.47 seconds
Started Jul 20 06:05:46 PM PDT 24
Finished Jul 20 06:06:14 PM PDT 24
Peak memory 200076 kb
Host smart-a1110662-99cf-46f7-93dd-5bd6912666cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415233701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3415233701
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3020763716
Short name T561
Test name
Test status
Simulation time 86484337906 ps
CPU time 39.27 seconds
Started Jul 20 06:05:48 PM PDT 24
Finished Jul 20 06:06:28 PM PDT 24
Peak memory 200164 kb
Host smart-5876f0d3-af61-4094-9667-8168094853de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020763716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3020763716
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1482882031
Short name T223
Test name
Test status
Simulation time 24896549089 ps
CPU time 8.82 seconds
Started Jul 20 06:09:58 PM PDT 24
Finished Jul 20 06:10:07 PM PDT 24
Peak memory 200092 kb
Host smart-8ee2178a-18b4-494c-b742-2c3ca9e4164e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482882031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1482882031
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.306975809
Short name T504
Test name
Test status
Simulation time 20850122218 ps
CPU time 33.66 seconds
Started Jul 20 06:09:57 PM PDT 24
Finished Jul 20 06:10:31 PM PDT 24
Peak memory 200080 kb
Host smart-f9283d5d-3cfe-4147-bc53-0d413dc743d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306975809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.306975809
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2399206928
Short name T198
Test name
Test status
Simulation time 359815859322 ps
CPU time 51.8 seconds
Started Jul 20 06:10:01 PM PDT 24
Finished Jul 20 06:10:54 PM PDT 24
Peak memory 200184 kb
Host smart-1e0ba1cf-50bb-4f3e-a941-161bc0244033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399206928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2399206928
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.4289368360
Short name T660
Test name
Test status
Simulation time 90687128047 ps
CPU time 25.02 seconds
Started Jul 20 06:09:58 PM PDT 24
Finished Jul 20 06:10:24 PM PDT 24
Peak memory 200156 kb
Host smart-c673b15f-3f42-4777-9fb4-c94c58f62322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289368360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.4289368360
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.979090541
Short name T644
Test name
Test status
Simulation time 205934651127 ps
CPU time 341.63 seconds
Started Jul 20 06:09:59 PM PDT 24
Finished Jul 20 06:15:41 PM PDT 24
Peak memory 200168 kb
Host smart-d5ef8405-9377-466b-b07b-7564e8094140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979090541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.979090541
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1927028559
Short name T1121
Test name
Test status
Simulation time 19285944094 ps
CPU time 29.12 seconds
Started Jul 20 06:09:57 PM PDT 24
Finished Jul 20 06:10:26 PM PDT 24
Peak memory 200128 kb
Host smart-f3e9d6c4-c0dc-493e-923b-3180460a3f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927028559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1927028559
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1536954110
Short name T891
Test name
Test status
Simulation time 11230629392 ps
CPU time 34.55 seconds
Started Jul 20 06:09:55 PM PDT 24
Finished Jul 20 06:10:30 PM PDT 24
Peak memory 200116 kb
Host smart-bcaa7d47-e5d6-474a-97f9-8d866bcec13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536954110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1536954110
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3978575516
Short name T284
Test name
Test status
Simulation time 39367791925 ps
CPU time 29.23 seconds
Started Jul 20 06:09:59 PM PDT 24
Finished Jul 20 06:10:29 PM PDT 24
Peak memory 200168 kb
Host smart-a85fcf2c-622a-4a99-a419-67beeaa28595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978575516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3978575516
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3558125865
Short name T1057
Test name
Test status
Simulation time 12894937 ps
CPU time 0.54 seconds
Started Jul 20 06:02:41 PM PDT 24
Finished Jul 20 06:02:42 PM PDT 24
Peak memory 194560 kb
Host smart-e4896c50-de0e-466d-9669-52190b24ac2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558125865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3558125865
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.376981695
Short name T831
Test name
Test status
Simulation time 46186980667 ps
CPU time 18.64 seconds
Started Jul 20 06:02:28 PM PDT 24
Finished Jul 20 06:02:47 PM PDT 24
Peak memory 200196 kb
Host smart-7e948223-21bc-47af-9529-bdc31c39cb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376981695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.376981695
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3718182762
Short name T628
Test name
Test status
Simulation time 75017593512 ps
CPU time 60.52 seconds
Started Jul 20 06:02:31 PM PDT 24
Finished Jul 20 06:03:32 PM PDT 24
Peak memory 200172 kb
Host smart-fe4fd2f7-6450-4131-8c8b-129bf72a6681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718182762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3718182762
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.553089613
Short name T166
Test name
Test status
Simulation time 29849462828 ps
CPU time 12.43 seconds
Started Jul 20 06:02:28 PM PDT 24
Finished Jul 20 06:02:41 PM PDT 24
Peak memory 200092 kb
Host smart-65f8a210-dc47-40de-86a1-9cc82b802c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553089613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.553089613
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.159501835
Short name T1028
Test name
Test status
Simulation time 12136110521 ps
CPU time 18.66 seconds
Started Jul 20 06:02:39 PM PDT 24
Finished Jul 20 06:02:58 PM PDT 24
Peak memory 197564 kb
Host smart-958f2ddb-8b05-4239-b10f-bed178901cc1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159501835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.159501835
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2958208813
Short name T567
Test name
Test status
Simulation time 108771148865 ps
CPU time 311.29 seconds
Started Jul 20 06:02:42 PM PDT 24
Finished Jul 20 06:07:53 PM PDT 24
Peak memory 200172 kb
Host smart-0f92192c-c0ec-4321-809a-c74242520c00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958208813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2958208813
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1600762941
Short name T384
Test name
Test status
Simulation time 10191458795 ps
CPU time 5.68 seconds
Started Jul 20 06:02:40 PM PDT 24
Finished Jul 20 06:02:46 PM PDT 24
Peak memory 200048 kb
Host smart-4f906d4a-fe26-4fc5-ab52-36a0fc9acb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600762941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1600762941
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.695815254
Short name T608
Test name
Test status
Simulation time 68697145658 ps
CPU time 113.31 seconds
Started Jul 20 06:02:43 PM PDT 24
Finished Jul 20 06:04:37 PM PDT 24
Peak memory 199500 kb
Host smart-b9ea1ccc-0f2c-41bd-99d0-7e9f59650a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695815254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.695815254
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3332458492
Short name T1019
Test name
Test status
Simulation time 6033934578 ps
CPU time 171.48 seconds
Started Jul 20 06:02:43 PM PDT 24
Finished Jul 20 06:05:35 PM PDT 24
Peak memory 200152 kb
Host smart-2cfdc236-17f9-4d52-9a78-5bfdfc530cfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3332458492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3332458492
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2548678692
Short name T341
Test name
Test status
Simulation time 5192037527 ps
CPU time 45.9 seconds
Started Jul 20 06:02:41 PM PDT 24
Finished Jul 20 06:03:27 PM PDT 24
Peak memory 199540 kb
Host smart-dabfff88-cec3-4d8c-95f6-25180a4ac659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2548678692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2548678692
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1616298530
Short name T712
Test name
Test status
Simulation time 58804410098 ps
CPU time 87.08 seconds
Started Jul 20 06:02:41 PM PDT 24
Finished Jul 20 06:04:08 PM PDT 24
Peak memory 200196 kb
Host smart-146a6707-25cf-4005-a250-63bc96b33cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616298530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1616298530
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3130454230
Short name T437
Test name
Test status
Simulation time 4001106089 ps
CPU time 2.33 seconds
Started Jul 20 06:02:41 PM PDT 24
Finished Jul 20 06:02:44 PM PDT 24
Peak memory 196496 kb
Host smart-bd2ee449-1df0-4904-a99b-f5865c55519d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130454230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3130454230
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2218643794
Short name T23
Test name
Test status
Simulation time 78913922 ps
CPU time 0.8 seconds
Started Jul 20 06:02:39 PM PDT 24
Finished Jul 20 06:02:40 PM PDT 24
Peak memory 218388 kb
Host smart-339852f2-c42d-4fc4-bbff-78f77e6d145a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218643794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2218643794
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.4093112808
Short name T375
Test name
Test status
Simulation time 521648134 ps
CPU time 1.43 seconds
Started Jul 20 06:02:31 PM PDT 24
Finished Jul 20 06:02:33 PM PDT 24
Peak memory 199756 kb
Host smart-22b7cc7c-7e10-49c4-988c-10dac4faa027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093112808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.4093112808
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3816146117
Short name T615
Test name
Test status
Simulation time 181281464374 ps
CPU time 287.5 seconds
Started Jul 20 06:02:41 PM PDT 24
Finished Jul 20 06:07:30 PM PDT 24
Peak memory 208512 kb
Host smart-6a07f5bc-ed41-43cc-8e52-08d59c7601a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816146117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3816146117
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1864813835
Short name T545
Test name
Test status
Simulation time 197782589536 ps
CPU time 668.54 seconds
Started Jul 20 06:02:43 PM PDT 24
Finished Jul 20 06:13:53 PM PDT 24
Peak memory 216748 kb
Host smart-41789a66-660f-47d8-b7a3-6157e544aead
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864813835 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1864813835
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1929711026
Short name T813
Test name
Test status
Simulation time 1913565644 ps
CPU time 2.6 seconds
Started Jul 20 06:02:40 PM PDT 24
Finished Jul 20 06:02:43 PM PDT 24
Peak memory 199084 kb
Host smart-9ae9200c-d34d-4b00-be6f-076089c7c62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929711026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1929711026
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2627211943
Short name T621
Test name
Test status
Simulation time 120216620811 ps
CPU time 92.54 seconds
Started Jul 20 06:02:30 PM PDT 24
Finished Jul 20 06:04:03 PM PDT 24
Peak memory 200148 kb
Host smart-cb6169d1-feb3-4dd9-bbeb-d0fe8da69225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627211943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2627211943
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2273831284
Short name T1087
Test name
Test status
Simulation time 42291380 ps
CPU time 0.55 seconds
Started Jul 20 06:05:56 PM PDT 24
Finished Jul 20 06:05:57 PM PDT 24
Peak memory 195568 kb
Host smart-21c6ee13-7288-4ed6-bc79-a4b7cb7ebfda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273831284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2273831284
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.383525501
Short name T1025
Test name
Test status
Simulation time 125096829258 ps
CPU time 43.45 seconds
Started Jul 20 06:05:55 PM PDT 24
Finished Jul 20 06:06:39 PM PDT 24
Peak memory 200196 kb
Host smart-0fa18a3e-10ce-4565-b8ea-2ba2ff22b158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383525501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.383525501
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1232745434
Short name T842
Test name
Test status
Simulation time 387336251556 ps
CPU time 265.41 seconds
Started Jul 20 06:05:55 PM PDT 24
Finished Jul 20 06:10:21 PM PDT 24
Peak memory 200124 kb
Host smart-7137dcd5-507a-4e82-a811-217543984911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232745434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1232745434
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3232568522
Short name T864
Test name
Test status
Simulation time 160360119961 ps
CPU time 138.65 seconds
Started Jul 20 06:05:57 PM PDT 24
Finished Jul 20 06:08:16 PM PDT 24
Peak memory 200136 kb
Host smart-ae42146b-925e-44f8-8c1d-dd533be00cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232568522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3232568522
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1985387428
Short name T276
Test name
Test status
Simulation time 302572430557 ps
CPU time 273.14 seconds
Started Jul 20 06:05:55 PM PDT 24
Finished Jul 20 06:10:29 PM PDT 24
Peak memory 200096 kb
Host smart-d48e5167-82d8-4ec2-a63c-701898099bdf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985387428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1985387428
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3281106365
Short name T267
Test name
Test status
Simulation time 110572970785 ps
CPU time 471.88 seconds
Started Jul 20 06:05:56 PM PDT 24
Finished Jul 20 06:13:48 PM PDT 24
Peak memory 200116 kb
Host smart-30052396-de61-428f-92d5-928fa14f95c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3281106365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3281106365
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2707514016
Short name T893
Test name
Test status
Simulation time 6094683242 ps
CPU time 4.56 seconds
Started Jul 20 06:05:53 PM PDT 24
Finished Jul 20 06:05:58 PM PDT 24
Peak memory 199904 kb
Host smart-e5b85b02-f6f7-4943-a37f-8982d94ef3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707514016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2707514016
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3310000724
Short name T955
Test name
Test status
Simulation time 62292464014 ps
CPU time 115.79 seconds
Started Jul 20 06:05:56 PM PDT 24
Finished Jul 20 06:07:53 PM PDT 24
Peak memory 200280 kb
Host smart-2633e8ab-f946-4514-ac56-fa009d042eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310000724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3310000724
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2790387725
Short name T592
Test name
Test status
Simulation time 17216049243 ps
CPU time 833.81 seconds
Started Jul 20 06:05:56 PM PDT 24
Finished Jul 20 06:19:50 PM PDT 24
Peak memory 200164 kb
Host smart-abb2b625-4d30-4e60-a34d-d570ba9aa1e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790387725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2790387725
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3889235206
Short name T762
Test name
Test status
Simulation time 3918125809 ps
CPU time 7.18 seconds
Started Jul 20 06:05:55 PM PDT 24
Finished Jul 20 06:06:02 PM PDT 24
Peak memory 199188 kb
Host smart-b41561e5-0b03-4c32-a0eb-0b7ad0eafdba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3889235206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3889235206
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3848626003
Short name T495
Test name
Test status
Simulation time 70239634919 ps
CPU time 62.8 seconds
Started Jul 20 06:05:58 PM PDT 24
Finished Jul 20 06:07:02 PM PDT 24
Peak memory 200192 kb
Host smart-a0696798-8f2d-4f80-8fe3-97b2dd1e8749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848626003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3848626003
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2003116880
Short name T885
Test name
Test status
Simulation time 3987165229 ps
CPU time 6.71 seconds
Started Jul 20 06:05:55 PM PDT 24
Finished Jul 20 06:06:02 PM PDT 24
Peak memory 196692 kb
Host smart-74470aaf-20e8-40ad-a2c8-68199f5f68fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003116880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2003116880
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3894837383
Short name T974
Test name
Test status
Simulation time 680374629 ps
CPU time 1.38 seconds
Started Jul 20 06:05:56 PM PDT 24
Finished Jul 20 06:05:58 PM PDT 24
Peak memory 198920 kb
Host smart-4a6283b4-9a1c-41d1-9e4f-84926f747853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894837383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3894837383
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1021171248
Short name T70
Test name
Test status
Simulation time 273994943216 ps
CPU time 141.73 seconds
Started Jul 20 06:05:58 PM PDT 24
Finished Jul 20 06:08:21 PM PDT 24
Peak memory 208508 kb
Host smart-e6de0330-1ca4-4afc-bd64-8a6cc7d310ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021171248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1021171248
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.395255377
Short name T966
Test name
Test status
Simulation time 537772923302 ps
CPU time 461.25 seconds
Started Jul 20 06:05:53 PM PDT 24
Finished Jul 20 06:13:35 PM PDT 24
Peak memory 216816 kb
Host smart-4912ddaf-aba3-4ce0-b900-3cfb09a378f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395255377 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.395255377
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1364394894
Short name T412
Test name
Test status
Simulation time 1319502911 ps
CPU time 2.47 seconds
Started Jul 20 06:05:57 PM PDT 24
Finished Jul 20 06:06:00 PM PDT 24
Peak memory 199316 kb
Host smart-c367f260-999c-4247-8122-02d3ab46178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364394894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1364394894
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1697301986
Short name T755
Test name
Test status
Simulation time 37742513678 ps
CPU time 30.92 seconds
Started Jul 20 06:05:53 PM PDT 24
Finished Jul 20 06:06:24 PM PDT 24
Peak memory 200188 kb
Host smart-16b9d13d-d4ac-4320-8902-7160cd253248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697301986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1697301986
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1097802896
Short name T470
Test name
Test status
Simulation time 24800284 ps
CPU time 0.57 seconds
Started Jul 20 06:06:03 PM PDT 24
Finished Jul 20 06:06:04 PM PDT 24
Peak memory 195544 kb
Host smart-9a9b6854-1e21-419b-8b11-aa34b8a77fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097802896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1097802896
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3823379837
Short name T120
Test name
Test status
Simulation time 40864955652 ps
CPU time 13.02 seconds
Started Jul 20 06:05:56 PM PDT 24
Finished Jul 20 06:06:10 PM PDT 24
Peak memory 200180 kb
Host smart-687f4ab4-8602-4369-a532-a78405227121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823379837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3823379837
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.505613232
Short name T378
Test name
Test status
Simulation time 41584148384 ps
CPU time 36.08 seconds
Started Jul 20 06:05:58 PM PDT 24
Finished Jul 20 06:06:35 PM PDT 24
Peak memory 200180 kb
Host smart-9fdf28bf-8bad-4161-ab52-83f8466b2a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505613232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.505613232
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3121375118
Short name T331
Test name
Test status
Simulation time 125858516278 ps
CPU time 395.32 seconds
Started Jul 20 06:05:56 PM PDT 24
Finished Jul 20 06:12:32 PM PDT 24
Peak memory 200136 kb
Host smart-73ad5104-72c2-4424-a7b3-d77bc735a917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121375118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3121375118
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2639856895
Short name T756
Test name
Test status
Simulation time 6806328333 ps
CPU time 5 seconds
Started Jul 20 06:06:03 PM PDT 24
Finished Jul 20 06:06:08 PM PDT 24
Peak memory 196924 kb
Host smart-d628bc0c-b86e-4da8-a7a9-22a527c12f42
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639856895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2639856895
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2184249500
Short name T703
Test name
Test status
Simulation time 60987315393 ps
CPU time 244.18 seconds
Started Jul 20 06:06:05 PM PDT 24
Finished Jul 20 06:10:10 PM PDT 24
Peak memory 200176 kb
Host smart-3675976e-89df-4b32-9dfb-5b7881f49be4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184249500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2184249500
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1091058653
Short name T478
Test name
Test status
Simulation time 9080827514 ps
CPU time 4.06 seconds
Started Jul 20 06:06:02 PM PDT 24
Finished Jul 20 06:06:07 PM PDT 24
Peak memory 199308 kb
Host smart-92330edc-1c83-4997-89ba-7dabb496bb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091058653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1091058653
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1495352520
Short name T580
Test name
Test status
Simulation time 120107532726 ps
CPU time 43.88 seconds
Started Jul 20 06:06:04 PM PDT 24
Finished Jul 20 06:06:48 PM PDT 24
Peak memory 200332 kb
Host smart-95f44d9f-d883-4886-81dd-dd1b9a356420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495352520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1495352520
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.793719257
Short name T1166
Test name
Test status
Simulation time 9110293958 ps
CPU time 109.22 seconds
Started Jul 20 06:06:02 PM PDT 24
Finished Jul 20 06:07:52 PM PDT 24
Peak memory 200060 kb
Host smart-00d46803-15ff-462a-9312-9180ff3a8f32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793719257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.793719257
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.124716595
Short name T972
Test name
Test status
Simulation time 4556447547 ps
CPU time 40.06 seconds
Started Jul 20 06:06:04 PM PDT 24
Finished Jul 20 06:06:45 PM PDT 24
Peak memory 198508 kb
Host smart-7793fbe4-abc8-43e8-b364-72d1594e967d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124716595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.124716595
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3167091755
Short name T66
Test name
Test status
Simulation time 18924883635 ps
CPU time 34.46 seconds
Started Jul 20 06:05:59 PM PDT 24
Finished Jul 20 06:06:34 PM PDT 24
Peak memory 200100 kb
Host smart-4de5b5ad-a6a0-4c06-abee-c7e3699bc40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167091755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3167091755
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.4185117633
Short name T747
Test name
Test status
Simulation time 4766342679 ps
CPU time 2.1 seconds
Started Jul 20 06:06:02 PM PDT 24
Finished Jul 20 06:06:05 PM PDT 24
Peak memory 196500 kb
Host smart-1ebc999c-47b4-41cc-a651-2127e26f6088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185117633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4185117633
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.865091116
Short name T676
Test name
Test status
Simulation time 839372210 ps
CPU time 4.55 seconds
Started Jul 20 06:06:02 PM PDT 24
Finished Jul 20 06:06:07 PM PDT 24
Peak memory 198488 kb
Host smart-5d4434b6-728d-453d-a174-e05cd294db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865091116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.865091116
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2452143372
Short name T786
Test name
Test status
Simulation time 93704815942 ps
CPU time 490.8 seconds
Started Jul 20 06:06:03 PM PDT 24
Finished Jul 20 06:14:14 PM PDT 24
Peak memory 200164 kb
Host smart-0b26a064-8871-4500-bca9-cf415255b119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452143372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2452143372
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2259754955
Short name T924
Test name
Test status
Simulation time 31860380732 ps
CPU time 530.43 seconds
Started Jul 20 06:06:04 PM PDT 24
Finished Jul 20 06:14:55 PM PDT 24
Peak memory 216808 kb
Host smart-cc7db63a-0642-46c6-9add-ccd06a3484b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259754955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2259754955
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1840448270
Short name T392
Test name
Test status
Simulation time 733941712 ps
CPU time 2.06 seconds
Started Jul 20 06:06:06 PM PDT 24
Finished Jul 20 06:06:09 PM PDT 24
Peak memory 199068 kb
Host smart-7e60ceb1-2682-4b7b-bd82-2212409f6149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840448270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1840448270
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2333116793
Short name T488
Test name
Test status
Simulation time 68449382904 ps
CPU time 124.21 seconds
Started Jul 20 06:05:54 PM PDT 24
Finished Jul 20 06:07:59 PM PDT 24
Peak memory 200184 kb
Host smart-3057094b-e14c-4c4e-a0e4-bc9a9a3050b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333116793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2333116793
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.649177800
Short name T404
Test name
Test status
Simulation time 70933272 ps
CPU time 0.57 seconds
Started Jul 20 06:06:14 PM PDT 24
Finished Jul 20 06:06:15 PM PDT 24
Peak memory 195556 kb
Host smart-4cc0a501-e1a3-4556-80aa-d504085235d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649177800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.649177800
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.4131907657
Short name T361
Test name
Test status
Simulation time 133651676247 ps
CPU time 175.73 seconds
Started Jul 20 06:06:03 PM PDT 24
Finished Jul 20 06:08:59 PM PDT 24
Peak memory 200192 kb
Host smart-b1d62dd0-31e6-4f63-a128-ee5c6b857b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131907657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.4131907657
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3681393129
Short name T722
Test name
Test status
Simulation time 102468645444 ps
CPU time 142.1 seconds
Started Jul 20 06:06:00 PM PDT 24
Finished Jul 20 06:08:23 PM PDT 24
Peak memory 200192 kb
Host smart-76838b75-986f-4dd2-8ffd-bf750c107ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681393129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3681393129
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_intr.3458220553
Short name T13
Test name
Test status
Simulation time 74746472943 ps
CPU time 115.1 seconds
Started Jul 20 06:06:00 PM PDT 24
Finished Jul 20 06:07:56 PM PDT 24
Peak memory 200196 kb
Host smart-014ad088-cdfc-4d02-a214-46367d43176b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458220553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3458220553
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.876148862
Short name T749
Test name
Test status
Simulation time 122391444915 ps
CPU time 1057.81 seconds
Started Jul 20 06:06:06 PM PDT 24
Finished Jul 20 06:23:45 PM PDT 24
Peak memory 200188 kb
Host smart-2af652f2-5870-4593-9af8-b7a3d52fc87c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=876148862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.876148862
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2366342406
Short name T383
Test name
Test status
Simulation time 2158865136 ps
CPU time 1.54 seconds
Started Jul 20 06:06:11 PM PDT 24
Finished Jul 20 06:06:13 PM PDT 24
Peak memory 195832 kb
Host smart-995aaebd-02b7-4078-bd55-9a1d20ce6c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366342406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2366342406
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.773736144
Short name T933
Test name
Test status
Simulation time 172309546473 ps
CPU time 202.13 seconds
Started Jul 20 06:06:05 PM PDT 24
Finished Jul 20 06:09:27 PM PDT 24
Peak memory 208212 kb
Host smart-df841fe3-6431-4013-b6c5-10d245953730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773736144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.773736144
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3636199552
Short name T865
Test name
Test status
Simulation time 17831473946 ps
CPU time 450.39 seconds
Started Jul 20 06:06:10 PM PDT 24
Finished Jul 20 06:13:41 PM PDT 24
Peak memory 200172 kb
Host smart-5c8d0b3b-d902-43ed-8f9e-6751dfe1b52a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636199552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3636199552
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.4017771383
Short name T851
Test name
Test status
Simulation time 4732182345 ps
CPU time 10.49 seconds
Started Jul 20 06:06:04 PM PDT 24
Finished Jul 20 06:06:15 PM PDT 24
Peak memory 198880 kb
Host smart-e6a7a50f-b0c6-4e05-a5ff-7cc54204e88f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4017771383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.4017771383
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2737903409
Short name T685
Test name
Test status
Simulation time 40259990760 ps
CPU time 16.3 seconds
Started Jul 20 06:06:12 PM PDT 24
Finished Jul 20 06:06:29 PM PDT 24
Peak memory 196504 kb
Host smart-f5f7f720-c83d-4956-81eb-c739f0853cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737903409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2737903409
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.156514173
Short name T897
Test name
Test status
Simulation time 898188222 ps
CPU time 3.2 seconds
Started Jul 20 06:06:04 PM PDT 24
Finished Jul 20 06:06:07 PM PDT 24
Peak memory 198432 kb
Host smart-6fb7bf30-4ca2-4322-acc1-39ae527ca492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156514173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.156514173
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.403735237
Short name T326
Test name
Test status
Simulation time 127320615893 ps
CPU time 568.34 seconds
Started Jul 20 06:06:13 PM PDT 24
Finished Jul 20 06:15:42 PM PDT 24
Peak memory 200188 kb
Host smart-1347b80b-fced-4a66-82a4-8bc1a0141023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403735237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.403735237
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.715845664
Short name T463
Test name
Test status
Simulation time 7121482168 ps
CPU time 7.77 seconds
Started Jul 20 06:06:09 PM PDT 24
Finished Jul 20 06:06:17 PM PDT 24
Peak memory 199876 kb
Host smart-91f583b7-0bec-410e-83b0-e5ec35dd4730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715845664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.715845664
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1128673090
Short name T268
Test name
Test status
Simulation time 132504101704 ps
CPU time 656.84 seconds
Started Jul 20 06:06:04 PM PDT 24
Finished Jul 20 06:17:01 PM PDT 24
Peak memory 200208 kb
Host smart-03272a2d-ed30-4d9a-90ad-24f656e021be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128673090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1128673090
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1436328454
Short name T949
Test name
Test status
Simulation time 10542591 ps
CPU time 0.52 seconds
Started Jul 20 06:06:19 PM PDT 24
Finished Jul 20 06:06:20 PM PDT 24
Peak memory 195020 kb
Host smart-facd6cfa-0b1a-47a7-a452-b113c55db335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436328454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1436328454
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2021687059
Short name T1081
Test name
Test status
Simulation time 15889961342 ps
CPU time 14.81 seconds
Started Jul 20 06:06:10 PM PDT 24
Finished Jul 20 06:06:25 PM PDT 24
Peak memory 200040 kb
Host smart-7f35f636-ddc7-40d2-a6d6-be0bcb8311b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021687059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2021687059
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3022235297
Short name T1103
Test name
Test status
Simulation time 43799779371 ps
CPU time 67.82 seconds
Started Jul 20 06:06:14 PM PDT 24
Finished Jul 20 06:07:22 PM PDT 24
Peak memory 200120 kb
Host smart-c038f8ff-aafc-485d-8620-cdce948a88f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022235297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3022235297
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.709700113
Short name T138
Test name
Test status
Simulation time 25535643955 ps
CPU time 39.42 seconds
Started Jul 20 06:06:19 PM PDT 24
Finished Jul 20 06:06:59 PM PDT 24
Peak memory 200196 kb
Host smart-0ce8d1b5-f160-4bbf-8a0f-4a058e015820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709700113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.709700113
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2449743142
Short name T501
Test name
Test status
Simulation time 53286438650 ps
CPU time 19.88 seconds
Started Jul 20 06:06:19 PM PDT 24
Finished Jul 20 06:06:40 PM PDT 24
Peak memory 200156 kb
Host smart-0eee5ce6-1e74-46cc-a698-2b4a88f91274
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449743142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2449743142
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1929443759
Short name T1038
Test name
Test status
Simulation time 305765438139 ps
CPU time 347.51 seconds
Started Jul 20 06:06:22 PM PDT 24
Finished Jul 20 06:12:10 PM PDT 24
Peak memory 200104 kb
Host smart-e76bfc94-dea0-47ec-aee2-3494d96a75fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929443759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1929443759
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2262023602
Short name T449
Test name
Test status
Simulation time 9960511972 ps
CPU time 7.59 seconds
Started Jul 20 06:06:22 PM PDT 24
Finished Jul 20 06:06:30 PM PDT 24
Peak memory 200168 kb
Host smart-faf79b4b-cc78-46dd-b39f-450b9abb66c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262023602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2262023602
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.925981769
Short name T249
Test name
Test status
Simulation time 98355838390 ps
CPU time 274.58 seconds
Started Jul 20 06:06:17 PM PDT 24
Finished Jul 20 06:10:52 PM PDT 24
Peak memory 199996 kb
Host smart-df264d1a-58b2-4a4b-8ab0-2a5bedbfc870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925981769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.925981769
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.836145077
Short name T739
Test name
Test status
Simulation time 17139038304 ps
CPU time 183.21 seconds
Started Jul 20 06:06:18 PM PDT 24
Finished Jul 20 06:09:22 PM PDT 24
Peak memory 200164 kb
Host smart-f11c0a1b-2375-4c84-9340-ff1e016a2f07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836145077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.836145077
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3636202012
Short name T339
Test name
Test status
Simulation time 4012475117 ps
CPU time 28.92 seconds
Started Jul 20 06:06:20 PM PDT 24
Finished Jul 20 06:06:49 PM PDT 24
Peak memory 198372 kb
Host smart-e2b4b300-cecf-4746-8ad7-63699bd3dae3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636202012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3636202012
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.4167991196
Short name T167
Test name
Test status
Simulation time 276153982454 ps
CPU time 255.68 seconds
Started Jul 20 06:06:21 PM PDT 24
Finished Jul 20 06:10:37 PM PDT 24
Peak memory 200192 kb
Host smart-e4b25ee3-678d-406d-87fd-a88651814ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167991196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.4167991196
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1078363960
Short name T829
Test name
Test status
Simulation time 38437570459 ps
CPU time 9.84 seconds
Started Jul 20 06:06:16 PM PDT 24
Finished Jul 20 06:06:26 PM PDT 24
Peak memory 196960 kb
Host smart-71f570a7-6ccb-46f8-9e4d-7786c6ad7a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078363960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1078363960
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1914183047
Short name T811
Test name
Test status
Simulation time 6227927463 ps
CPU time 9.17 seconds
Started Jul 20 06:06:10 PM PDT 24
Finished Jul 20 06:06:20 PM PDT 24
Peak memory 200112 kb
Host smart-cf7dd1a2-762b-463f-9ac4-667c2d5cfede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914183047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1914183047
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.978587734
Short name T1032
Test name
Test status
Simulation time 49700285097 ps
CPU time 576.93 seconds
Started Jul 20 06:06:17 PM PDT 24
Finished Jul 20 06:15:55 PM PDT 24
Peak memory 200404 kb
Host smart-53634f53-c5d7-4e7f-a8bd-1792e4d52f29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978587734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.978587734
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2645674670
Short name T623
Test name
Test status
Simulation time 181312885354 ps
CPU time 666.29 seconds
Started Jul 20 06:06:20 PM PDT 24
Finished Jul 20 06:17:27 PM PDT 24
Peak memory 225016 kb
Host smart-8a4e698d-d40c-43b7-ad19-d2a77c809259
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645674670 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2645674670
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2736887152
Short name T451
Test name
Test status
Simulation time 2353617594 ps
CPU time 1.56 seconds
Started Jul 20 06:06:17 PM PDT 24
Finished Jul 20 06:06:19 PM PDT 24
Peak memory 197696 kb
Host smart-e86577c2-be7f-45e0-979d-89a13654af43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736887152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2736887152
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.114702587
Short name T1064
Test name
Test status
Simulation time 22957427860 ps
CPU time 11.14 seconds
Started Jul 20 06:06:11 PM PDT 24
Finished Jul 20 06:06:22 PM PDT 24
Peak memory 200164 kb
Host smart-db540a51-1884-468d-a38d-c165e4ed109f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114702587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.114702587
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2175812018
Short name T889
Test name
Test status
Simulation time 14111097 ps
CPU time 0.54 seconds
Started Jul 20 06:06:27 PM PDT 24
Finished Jul 20 06:06:28 PM PDT 24
Peak memory 195572 kb
Host smart-1c438498-563e-43e3-b319-da380ff59868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175812018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2175812018
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3444144623
Short name T647
Test name
Test status
Simulation time 39439939743 ps
CPU time 50.8 seconds
Started Jul 20 06:06:20 PM PDT 24
Finished Jul 20 06:07:11 PM PDT 24
Peak memory 200116 kb
Host smart-9d6ec10d-58f8-41a4-96a1-baba2cd935ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444144623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3444144623
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1685266449
Short name T771
Test name
Test status
Simulation time 167429764208 ps
CPU time 315.05 seconds
Started Jul 20 06:06:19 PM PDT 24
Finished Jul 20 06:11:35 PM PDT 24
Peak memory 200128 kb
Host smart-21f51831-72db-411c-8d80-ea70480a8922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685266449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1685266449
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.385308778
Short name T666
Test name
Test status
Simulation time 479290246733 ps
CPU time 83.45 seconds
Started Jul 20 06:06:18 PM PDT 24
Finished Jul 20 06:07:42 PM PDT 24
Peak memory 200172 kb
Host smart-5ca95f48-5a48-430d-a950-37603570b1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385308778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.385308778
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3904414847
Short name T716
Test name
Test status
Simulation time 19927432866 ps
CPU time 8.71 seconds
Started Jul 20 06:06:16 PM PDT 24
Finished Jul 20 06:06:25 PM PDT 24
Peak memory 200052 kb
Host smart-24202b8f-8688-4531-9fc3-6493980e55b1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904414847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3904414847
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1121458239
Short name T1049
Test name
Test status
Simulation time 155908579982 ps
CPU time 479.98 seconds
Started Jul 20 06:06:28 PM PDT 24
Finished Jul 20 06:14:29 PM PDT 24
Peak memory 200028 kb
Host smart-c14a7cf6-d8bf-4e1a-915e-c99a5a426b51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121458239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1121458239
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1358925231
Short name T587
Test name
Test status
Simulation time 442383348 ps
CPU time 1.14 seconds
Started Jul 20 06:06:29 PM PDT 24
Finished Jul 20 06:06:31 PM PDT 24
Peak memory 198672 kb
Host smart-ab7de1c7-39d6-426c-87cb-65671fb74d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358925231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1358925231
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3783123757
Short name T895
Test name
Test status
Simulation time 63660036922 ps
CPU time 107.55 seconds
Started Jul 20 06:06:20 PM PDT 24
Finished Jul 20 06:08:08 PM PDT 24
Peak memory 200324 kb
Host smart-b697331f-ee0c-4055-923a-d191a77dc785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783123757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3783123757
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.289105177
Short name T1161
Test name
Test status
Simulation time 9297503644 ps
CPU time 268.77 seconds
Started Jul 20 06:06:28 PM PDT 24
Finished Jul 20 06:10:58 PM PDT 24
Peak memory 200176 kb
Host smart-e870fa15-5650-41c1-ab37-f8d3864925ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289105177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.289105177
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3847660346
Short name T616
Test name
Test status
Simulation time 2956885455 ps
CPU time 5.72 seconds
Started Jul 20 06:06:17 PM PDT 24
Finished Jul 20 06:06:23 PM PDT 24
Peak memory 197944 kb
Host smart-373fba49-9841-4730-8a65-87ff7f0b81fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3847660346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3847660346
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.4067943944
Short name T606
Test name
Test status
Simulation time 85523317452 ps
CPU time 63.96 seconds
Started Jul 20 06:06:26 PM PDT 24
Finished Jul 20 06:07:30 PM PDT 24
Peak memory 199940 kb
Host smart-83ab3776-59b9-49cd-9fe4-d059e26a3ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067943944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.4067943944
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3086919435
Short name T570
Test name
Test status
Simulation time 3053152384 ps
CPU time 4.83 seconds
Started Jul 20 06:06:19 PM PDT 24
Finished Jul 20 06:06:25 PM PDT 24
Peak memory 196660 kb
Host smart-049c66ee-6418-48da-886a-ee97dcf3bcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086919435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3086919435
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.4111318609
Short name T752
Test name
Test status
Simulation time 845685639 ps
CPU time 3.54 seconds
Started Jul 20 06:06:21 PM PDT 24
Finished Jul 20 06:06:25 PM PDT 24
Peak memory 199988 kb
Host smart-c8391f25-be04-4a52-b851-096b9d421ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111318609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.4111318609
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3872967606
Short name T320
Test name
Test status
Simulation time 361253495362 ps
CPU time 252.05 seconds
Started Jul 20 06:06:26 PM PDT 24
Finished Jul 20 06:10:38 PM PDT 24
Peak memory 208480 kb
Host smart-e7e0697b-4b3c-478c-82b3-bd8efff37ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872967606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3872967606
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.308007794
Short name T576
Test name
Test status
Simulation time 69539287208 ps
CPU time 281.94 seconds
Started Jul 20 06:06:29 PM PDT 24
Finished Jul 20 06:11:11 PM PDT 24
Peak memory 215700 kb
Host smart-0dad1ce6-5368-4470-b220-2e9e45da0eef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308007794 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.308007794
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3571255600
Short name T294
Test name
Test status
Simulation time 2921972161 ps
CPU time 2.84 seconds
Started Jul 20 06:06:31 PM PDT 24
Finished Jul 20 06:06:34 PM PDT 24
Peak memory 198556 kb
Host smart-e1fdc312-3d53-412e-a99e-dc736449c080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571255600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3571255600
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3797193868
Short name T1089
Test name
Test status
Simulation time 31457853106 ps
CPU time 50.47 seconds
Started Jul 20 06:06:19 PM PDT 24
Finished Jul 20 06:07:10 PM PDT 24
Peak memory 200128 kb
Host smart-45552ec8-25c1-4951-b44a-79fc9d137f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797193868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3797193868
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.912619943
Short name T768
Test name
Test status
Simulation time 12635835 ps
CPU time 0.57 seconds
Started Jul 20 06:06:36 PM PDT 24
Finished Jul 20 06:06:39 PM PDT 24
Peak memory 195876 kb
Host smart-28c8d088-5ef2-4224-9c24-f024112207a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912619943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.912619943
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2909734609
Short name T993
Test name
Test status
Simulation time 127578369570 ps
CPU time 72.41 seconds
Started Jul 20 06:06:30 PM PDT 24
Finished Jul 20 06:07:43 PM PDT 24
Peak memory 200192 kb
Host smart-a863db72-82e4-433d-a90c-6da473e6e397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909734609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2909734609
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2018435673
Short name T1147
Test name
Test status
Simulation time 57370281232 ps
CPU time 80.31 seconds
Started Jul 20 06:06:27 PM PDT 24
Finished Jul 20 06:07:48 PM PDT 24
Peak memory 200196 kb
Host smart-bac53ffe-083a-4ffe-9b3b-cbe2ffcf4757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018435673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2018435673
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.4022858626
Short name T484
Test name
Test status
Simulation time 49990026834 ps
CPU time 17.78 seconds
Started Jul 20 06:06:29 PM PDT 24
Finished Jul 20 06:06:48 PM PDT 24
Peak memory 200088 kb
Host smart-59c1addc-18e8-42e6-a949-a255351d7850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022858626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.4022858626
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3261656407
Short name T487
Test name
Test status
Simulation time 41701487251 ps
CPU time 16.22 seconds
Started Jul 20 06:06:28 PM PDT 24
Finished Jul 20 06:06:45 PM PDT 24
Peak memory 200104 kb
Host smart-433472e7-71b9-4126-aba7-12c459bc3dab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261656407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3261656407
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.940865820
Short name T101
Test name
Test status
Simulation time 99024102370 ps
CPU time 481.19 seconds
Started Jul 20 06:06:27 PM PDT 24
Finished Jul 20 06:14:28 PM PDT 24
Peak memory 200176 kb
Host smart-2f731b4c-253b-43d8-abb8-a57f2f482c97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940865820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.940865820
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2786379059
Short name T586
Test name
Test status
Simulation time 19625929 ps
CPU time 0.6 seconds
Started Jul 20 06:06:31 PM PDT 24
Finished Jul 20 06:06:32 PM PDT 24
Peak memory 195992 kb
Host smart-aef5a20c-5746-4d33-b00e-fa65be92a60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786379059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2786379059
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2191551999
Short name T403
Test name
Test status
Simulation time 33493448250 ps
CPU time 55.73 seconds
Started Jul 20 06:06:29 PM PDT 24
Finished Jul 20 06:07:26 PM PDT 24
Peak memory 200072 kb
Host smart-693502e6-b5b3-482b-9dc0-7558b57fad9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191551999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2191551999
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.78914300
Short name T400
Test name
Test status
Simulation time 1815217728 ps
CPU time 106.02 seconds
Started Jul 20 06:06:28 PM PDT 24
Finished Jul 20 06:08:15 PM PDT 24
Peak memory 200124 kb
Host smart-6bdd713a-cae9-4468-98c7-2c8857c7623e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78914300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.78914300
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.4102112576
Short name T657
Test name
Test status
Simulation time 6062447457 ps
CPU time 52.29 seconds
Started Jul 20 06:06:27 PM PDT 24
Finished Jul 20 06:07:20 PM PDT 24
Peak memory 199368 kb
Host smart-d0d6abc9-8b84-4459-8a31-3842edefb5ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102112576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.4102112576
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2077690579
Short name T453
Test name
Test status
Simulation time 109865855250 ps
CPU time 16.65 seconds
Started Jul 20 06:06:28 PM PDT 24
Finished Jul 20 06:06:46 PM PDT 24
Peak memory 200100 kb
Host smart-dab58e4e-d11a-4270-b06a-57c3f265d4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077690579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2077690579
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2689081449
Short name T804
Test name
Test status
Simulation time 31160950521 ps
CPU time 12.56 seconds
Started Jul 20 06:06:25 PM PDT 24
Finished Jul 20 06:06:38 PM PDT 24
Peak memory 196076 kb
Host smart-c081f97f-ca7b-436b-9e09-fe94f6b1dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689081449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2689081449
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3749642063
Short name T490
Test name
Test status
Simulation time 657712499 ps
CPU time 2.39 seconds
Started Jul 20 06:06:28 PM PDT 24
Finished Jul 20 06:06:32 PM PDT 24
Peak memory 199920 kb
Host smart-04e5b66d-af83-492c-a2dc-87ba0cceca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749642063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3749642063
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1141548763
Short name T1155
Test name
Test status
Simulation time 31014049785 ps
CPU time 9.51 seconds
Started Jul 20 06:06:34 PM PDT 24
Finished Jul 20 06:06:44 PM PDT 24
Peak memory 200124 kb
Host smart-fe473c11-2382-4e20-80a0-ded0591adf6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141548763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1141548763
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.248678635
Short name T1075
Test name
Test status
Simulation time 22849239813 ps
CPU time 190.95 seconds
Started Jul 20 06:06:28 PM PDT 24
Finished Jul 20 06:09:40 PM PDT 24
Peak memory 215964 kb
Host smart-87cc28bb-9548-4ef3-b786-410e7cbf8787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248678635 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.248678635
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1814088033
Short name T399
Test name
Test status
Simulation time 2564958168 ps
CPU time 2.15 seconds
Started Jul 20 06:06:25 PM PDT 24
Finished Jul 20 06:06:28 PM PDT 24
Peak memory 199020 kb
Host smart-2706d4a3-1a42-405f-a0f0-d021bdc581a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814088033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1814088033
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.252928179
Short name T281
Test name
Test status
Simulation time 66082693904 ps
CPU time 138.56 seconds
Started Jul 20 06:06:28 PM PDT 24
Finished Jul 20 06:08:48 PM PDT 24
Peak memory 200140 kb
Host smart-ac7f92f8-11fa-4a5e-a877-81100ab6c8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252928179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.252928179
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.169484949
Short name T1131
Test name
Test status
Simulation time 18487610 ps
CPU time 0.53 seconds
Started Jul 20 06:06:36 PM PDT 24
Finished Jul 20 06:06:39 PM PDT 24
Peak memory 194828 kb
Host smart-e3ba7dd7-66d6-4188-97b6-285054557095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169484949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.169484949
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2105807466
Short name T931
Test name
Test status
Simulation time 111784614191 ps
CPU time 52.94 seconds
Started Jul 20 06:06:36 PM PDT 24
Finished Jul 20 06:07:31 PM PDT 24
Peak memory 200096 kb
Host smart-7bbba84e-2fbc-41fb-8a4c-5ece4b7f5fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105807466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2105807466
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.80604748
Short name T996
Test name
Test status
Simulation time 253777683778 ps
CPU time 48.84 seconds
Started Jul 20 06:06:35 PM PDT 24
Finished Jul 20 06:07:25 PM PDT 24
Peak memory 199956 kb
Host smart-e9f15129-7afe-4ead-b93b-9588d7b666e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80604748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.80604748
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2531270021
Short name T187
Test name
Test status
Simulation time 26786953063 ps
CPU time 30.5 seconds
Started Jul 20 06:06:36 PM PDT 24
Finished Jul 20 06:07:09 PM PDT 24
Peak memory 200088 kb
Host smart-6e7422d8-8c2c-4758-929b-6c3ed971a2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531270021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2531270021
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3783932240
Short name T113
Test name
Test status
Simulation time 29383136929 ps
CPU time 46.88 seconds
Started Jul 20 06:06:39 PM PDT 24
Finished Jul 20 06:07:27 PM PDT 24
Peak memory 200160 kb
Host smart-8eec0fa7-7da0-453c-8a00-92f07faf6647
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783932240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3783932240
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2859583803
Short name T838
Test name
Test status
Simulation time 101096115344 ps
CPU time 363.66 seconds
Started Jul 20 06:06:34 PM PDT 24
Finished Jul 20 06:12:38 PM PDT 24
Peak memory 200108 kb
Host smart-b07a223b-01f1-408d-8ca1-bc73f6abaf20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2859583803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2859583803
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1066887625
Short name T337
Test name
Test status
Simulation time 4206062918 ps
CPU time 9.08 seconds
Started Jul 20 06:06:37 PM PDT 24
Finished Jul 20 06:06:48 PM PDT 24
Peak memory 199856 kb
Host smart-1680ca68-3152-408a-8016-95455cadb352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066887625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1066887625
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.533895573
Short name T953
Test name
Test status
Simulation time 34358895478 ps
CPU time 61.64 seconds
Started Jul 20 06:06:37 PM PDT 24
Finished Jul 20 06:07:40 PM PDT 24
Peak memory 199380 kb
Host smart-fe508a51-a8db-4dae-98e1-66cf59ce2410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533895573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.533895573
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.698651913
Short name T442
Test name
Test status
Simulation time 12564643930 ps
CPU time 667.66 seconds
Started Jul 20 06:06:37 PM PDT 24
Finished Jul 20 06:17:46 PM PDT 24
Peak memory 200204 kb
Host smart-aa4afa88-54a5-4dba-b547-9d79e3842371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=698651913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.698651913
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3057108930
Short name T371
Test name
Test status
Simulation time 1504452979 ps
CPU time 1.85 seconds
Started Jul 20 06:06:37 PM PDT 24
Finished Jul 20 06:06:41 PM PDT 24
Peak memory 198308 kb
Host smart-8641e92e-3496-4719-9150-79e90a8f76fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3057108930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3057108930
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.266606908
Short name T984
Test name
Test status
Simulation time 274517654106 ps
CPU time 40.74 seconds
Started Jul 20 06:06:39 PM PDT 24
Finished Jul 20 06:07:21 PM PDT 24
Peak memory 200096 kb
Host smart-019b46b4-f72b-40ce-ab71-7c5e80b60b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266606908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.266606908
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3954197956
Short name T370
Test name
Test status
Simulation time 34836540435 ps
CPU time 25.21 seconds
Started Jul 20 06:06:37 PM PDT 24
Finished Jul 20 06:07:04 PM PDT 24
Peak memory 197068 kb
Host smart-d32732bb-328c-4cd9-8e3c-2d3d9b0a0ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954197956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3954197956
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2928068748
Short name T988
Test name
Test status
Simulation time 5986170473 ps
CPU time 57.98 seconds
Started Jul 20 06:06:35 PM PDT 24
Finished Jul 20 06:07:35 PM PDT 24
Peak memory 200016 kb
Host smart-20aadb7e-f0e4-4be4-b72d-3e2caadea977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928068748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2928068748
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.4008208172
Short name T332
Test name
Test status
Simulation time 284008180520 ps
CPU time 630.11 seconds
Started Jul 20 06:06:37 PM PDT 24
Finished Jul 20 06:17:09 PM PDT 24
Peak memory 200156 kb
Host smart-b495510d-95e1-48fa-88b8-5754aa42f237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008208172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4008208172
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.814416793
Short name T390
Test name
Test status
Simulation time 1820343187 ps
CPU time 2.02 seconds
Started Jul 20 06:06:35 PM PDT 24
Finished Jul 20 06:06:38 PM PDT 24
Peak memory 198412 kb
Host smart-0a7258ac-92ca-4370-bc55-99a9414b8c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814416793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.814416793
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2256973941
Short name T329
Test name
Test status
Simulation time 78046289905 ps
CPU time 29.49 seconds
Started Jul 20 06:06:35 PM PDT 24
Finished Jul 20 06:07:05 PM PDT 24
Peak memory 200044 kb
Host smart-63a478d6-2df9-4fc3-b125-86d513c5f174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256973941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2256973941
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.4113651702
Short name T391
Test name
Test status
Simulation time 52242372 ps
CPU time 0.58 seconds
Started Jul 20 06:06:46 PM PDT 24
Finished Jul 20 06:06:48 PM PDT 24
Peak memory 195524 kb
Host smart-07a91447-2176-4b92-a566-752b7605a625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113651702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.4113651702
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1490738340
Short name T814
Test name
Test status
Simulation time 41306038520 ps
CPU time 16.93 seconds
Started Jul 20 06:06:38 PM PDT 24
Finished Jul 20 06:06:57 PM PDT 24
Peak memory 200180 kb
Host smart-161cfc3a-4d5d-491a-b67c-cd99756478f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490738340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1490738340
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.4062070152
Short name T259
Test name
Test status
Simulation time 113475825855 ps
CPU time 191.2 seconds
Started Jul 20 06:06:36 PM PDT 24
Finished Jul 20 06:09:48 PM PDT 24
Peak memory 200188 kb
Host smart-74d69f65-59a6-451b-bd8c-ef40ab417d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062070152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.4062070152
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1964807507
Short name T219
Test name
Test status
Simulation time 125635808949 ps
CPU time 191.43 seconds
Started Jul 20 06:06:35 PM PDT 24
Finished Jul 20 06:09:47 PM PDT 24
Peak memory 200132 kb
Host smart-9b7cb785-47f0-42a8-8ec5-a1935c5f045c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964807507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1964807507
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.3499958130
Short name T808
Test name
Test status
Simulation time 43223872408 ps
CPU time 14.49 seconds
Started Jul 20 06:06:37 PM PDT 24
Finished Jul 20 06:06:53 PM PDT 24
Peak memory 199080 kb
Host smart-05fcdfa4-1625-403c-b774-cb878fa4f740
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499958130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3499958130
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.611386094
Short name T841
Test name
Test status
Simulation time 97209617789 ps
CPU time 188.62 seconds
Started Jul 20 06:06:45 PM PDT 24
Finished Jul 20 06:09:56 PM PDT 24
Peak memory 200008 kb
Host smart-a5d24f57-fede-43ca-8809-bf0be74209ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=611386094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.611386094
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2569765076
Short name T493
Test name
Test status
Simulation time 3532988652 ps
CPU time 1.2 seconds
Started Jul 20 06:06:41 PM PDT 24
Finished Jul 20 06:06:43 PM PDT 24
Peak memory 198020 kb
Host smart-251cbcfb-6eae-4098-86a4-e9aeffd7f2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569765076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2569765076
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3235938689
Short name T1117
Test name
Test status
Simulation time 53959667773 ps
CPU time 77.25 seconds
Started Jul 20 06:06:36 PM PDT 24
Finished Jul 20 06:07:55 PM PDT 24
Peak memory 198888 kb
Host smart-0bc6bc1c-0cc3-458c-92ea-c09b481f0d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235938689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3235938689
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.3914088558
Short name T824
Test name
Test status
Simulation time 5588303536 ps
CPU time 245.69 seconds
Started Jul 20 06:06:42 PM PDT 24
Finished Jul 20 06:10:49 PM PDT 24
Peak memory 200152 kb
Host smart-6e5b1355-04b1-4f74-a6c4-d3e858b35e44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3914088558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3914088558
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2088124157
Short name T366
Test name
Test status
Simulation time 6029633392 ps
CPU time 11.66 seconds
Started Jul 20 06:06:36 PM PDT 24
Finished Jul 20 06:06:49 PM PDT 24
Peak memory 198360 kb
Host smart-021ec421-8550-4a56-9dfd-cd551f7dc82f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088124157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2088124157
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.887196867
Short name T363
Test name
Test status
Simulation time 14319397880 ps
CPU time 26.44 seconds
Started Jul 20 06:06:49 PM PDT 24
Finished Jul 20 06:07:16 PM PDT 24
Peak memory 200188 kb
Host smart-ba08d028-ac98-44af-81f3-46532d8358b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887196867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.887196867
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1876297216
Short name T551
Test name
Test status
Simulation time 3756808928 ps
CPU time 1.82 seconds
Started Jul 20 06:06:44 PM PDT 24
Finished Jul 20 06:06:47 PM PDT 24
Peak memory 196456 kb
Host smart-d7c447ea-55af-488c-831b-c2e701c2eae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876297216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1876297216
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2180967538
Short name T797
Test name
Test status
Simulation time 10571335133 ps
CPU time 27.5 seconds
Started Jul 20 06:06:38 PM PDT 24
Finished Jul 20 06:07:07 PM PDT 24
Peak memory 200152 kb
Host smart-2bb42629-7446-4756-9dc8-a2b1232f861e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180967538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2180967538
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3462082045
Short name T402
Test name
Test status
Simulation time 120352086385 ps
CPU time 258.29 seconds
Started Jul 20 06:06:42 PM PDT 24
Finished Jul 20 06:11:02 PM PDT 24
Peak memory 200168 kb
Host smart-6f525c91-8c49-4a26-a737-42e5170acee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462082045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3462082045
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.559296146
Short name T1091
Test name
Test status
Simulation time 2374095179 ps
CPU time 1.99 seconds
Started Jul 20 06:06:46 PM PDT 24
Finished Jul 20 06:06:49 PM PDT 24
Peak memory 199176 kb
Host smart-81723584-2f33-4576-9f8c-315c42ca51cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559296146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.559296146
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3240052117
Short name T1112
Test name
Test status
Simulation time 111544119793 ps
CPU time 42.72 seconds
Started Jul 20 06:06:36 PM PDT 24
Finished Jul 20 06:07:21 PM PDT 24
Peak memory 200192 kb
Host smart-115298d4-1f6a-4b27-bf9f-d636b31514c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240052117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3240052117
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1884443218
Short name T22
Test name
Test status
Simulation time 14052197 ps
CPU time 0.56 seconds
Started Jul 20 06:06:44 PM PDT 24
Finished Jul 20 06:06:46 PM PDT 24
Peak memory 195860 kb
Host smart-247d0c88-009a-47b0-bd20-94aebdb6c646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884443218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1884443218
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3647192807
Short name T485
Test name
Test status
Simulation time 36005330793 ps
CPU time 52.42 seconds
Started Jul 20 06:06:45 PM PDT 24
Finished Jul 20 06:07:39 PM PDT 24
Peak memory 200124 kb
Host smart-29feaea9-59f0-4753-9fbe-746bdf9a1fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647192807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3647192807
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3717214243
Short name T827
Test name
Test status
Simulation time 21066098623 ps
CPU time 29.9 seconds
Started Jul 20 06:06:45 PM PDT 24
Finished Jul 20 06:07:16 PM PDT 24
Peak memory 199892 kb
Host smart-f8319d97-933d-47f3-8f03-4a4ff65fb1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717214243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3717214243
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2745217689
Short name T290
Test name
Test status
Simulation time 97759813684 ps
CPU time 141.06 seconds
Started Jul 20 06:06:42 PM PDT 24
Finished Jul 20 06:09:05 PM PDT 24
Peak memory 200248 kb
Host smart-1196a074-d19e-4769-8c50-f73f19426384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745217689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2745217689
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3978808914
Short name T1139
Test name
Test status
Simulation time 42753314945 ps
CPU time 77.1 seconds
Started Jul 20 06:06:44 PM PDT 24
Finished Jul 20 06:08:02 PM PDT 24
Peak memory 200188 kb
Host smart-9aa9c7e6-276c-4b85-a35d-dbbbd04e3723
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978808914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3978808914
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1662442834
Short name T380
Test name
Test status
Simulation time 133850275090 ps
CPU time 248.58 seconds
Started Jul 20 06:06:44 PM PDT 24
Finished Jul 20 06:10:54 PM PDT 24
Peak memory 200180 kb
Host smart-96a175f0-7479-47e9-8816-f86c1e89df69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1662442834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1662442834
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.406132626
Short name T584
Test name
Test status
Simulation time 13256646728 ps
CPU time 24.12 seconds
Started Jul 20 06:06:45 PM PDT 24
Finished Jul 20 06:07:11 PM PDT 24
Peak memory 199984 kb
Host smart-58296c16-6249-477a-9f7f-1cdfb6d2ca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406132626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.406132626
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1917737242
Short name T821
Test name
Test status
Simulation time 53369819096 ps
CPU time 74.58 seconds
Started Jul 20 06:06:44 PM PDT 24
Finished Jul 20 06:08:00 PM PDT 24
Peak memory 199620 kb
Host smart-8d0708cf-9760-45c6-a422-c2a1035e8eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917737242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1917737242
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3874969027
Short name T1023
Test name
Test status
Simulation time 4625090857 ps
CPU time 55.11 seconds
Started Jul 20 06:06:46 PM PDT 24
Finished Jul 20 06:07:42 PM PDT 24
Peak memory 200160 kb
Host smart-92157223-4d3d-4a9a-900a-48158350750f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874969027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3874969027
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3791156286
Short name T368
Test name
Test status
Simulation time 1792981532 ps
CPU time 3.07 seconds
Started Jul 20 06:06:44 PM PDT 24
Finished Jul 20 06:06:48 PM PDT 24
Peak memory 198060 kb
Host smart-a8831a83-3669-48af-9b9c-f228e1fadf70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3791156286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3791156286
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2701849017
Short name T704
Test name
Test status
Simulation time 201725098788 ps
CPU time 126.26 seconds
Started Jul 20 06:06:45 PM PDT 24
Finished Jul 20 06:08:52 PM PDT 24
Peak memory 200200 kb
Host smart-19964752-817a-42b4-9315-9b0acfe9d9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701849017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2701849017
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3898372550
Short name T998
Test name
Test status
Simulation time 2843545260 ps
CPU time 2.88 seconds
Started Jul 20 06:06:46 PM PDT 24
Finished Jul 20 06:06:50 PM PDT 24
Peak memory 196032 kb
Host smart-88f8c167-c6fe-4292-a1a8-cb9d73269523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898372550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3898372550
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.764620886
Short name T1152
Test name
Test status
Simulation time 691327444 ps
CPU time 2.57 seconds
Started Jul 20 06:06:44 PM PDT 24
Finished Jul 20 06:06:48 PM PDT 24
Peak memory 199520 kb
Host smart-211039a6-7b5c-4c62-951f-3469d0c41bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764620886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.764620886
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.386115144
Short name T1123
Test name
Test status
Simulation time 921171729783 ps
CPU time 292.46 seconds
Started Jul 20 06:06:49 PM PDT 24
Finished Jul 20 06:11:42 PM PDT 24
Peak memory 208508 kb
Host smart-bdb280e6-f788-4864-99ad-39308af00244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386115144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.386115144
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1546551512
Short name T863
Test name
Test status
Simulation time 16278788625 ps
CPU time 311.36 seconds
Started Jul 20 06:06:41 PM PDT 24
Finished Jul 20 06:11:53 PM PDT 24
Peak memory 216360 kb
Host smart-b3ad4cf5-f6f2-4203-a6e8-e1ea3fb999eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546551512 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1546551512
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1424759184
Short name T252
Test name
Test status
Simulation time 972314413 ps
CPU time 3.55 seconds
Started Jul 20 06:06:46 PM PDT 24
Finished Jul 20 06:06:51 PM PDT 24
Peak memory 199920 kb
Host smart-4fe7dd73-8cda-4aa9-87dd-1b1bda7b86b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424759184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1424759184
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1625585334
Short name T1141
Test name
Test status
Simulation time 70544532961 ps
CPU time 79.97 seconds
Started Jul 20 06:06:46 PM PDT 24
Finished Jul 20 06:08:08 PM PDT 24
Peak memory 200204 kb
Host smart-8d597640-9ced-4e21-9f6f-87158a418317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625585334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1625585334
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.647352598
Short name T649
Test name
Test status
Simulation time 32881331 ps
CPU time 0.55 seconds
Started Jul 20 06:06:50 PM PDT 24
Finished Jul 20 06:06:51 PM PDT 24
Peak memory 195700 kb
Host smart-10780a5d-d2c0-4d8f-b918-6bf33f9d58e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647352598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.647352598
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2112653729
Short name T900
Test name
Test status
Simulation time 124389554210 ps
CPU time 157.61 seconds
Started Jul 20 06:06:47 PM PDT 24
Finished Jul 20 06:09:25 PM PDT 24
Peak memory 200180 kb
Host smart-c2c2b46a-aaab-43c2-8b14-83e7a83fb8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112653729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2112653729
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3488166584
Short name T1128
Test name
Test status
Simulation time 41150618325 ps
CPU time 53.85 seconds
Started Jul 20 06:06:52 PM PDT 24
Finished Jul 20 06:07:46 PM PDT 24
Peak memory 200092 kb
Host smart-ba2bb098-9074-44c9-b98e-490d54b0c27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488166584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3488166584
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2448204273
Short name T1009
Test name
Test status
Simulation time 26517399551 ps
CPU time 13.14 seconds
Started Jul 20 06:06:52 PM PDT 24
Finished Jul 20 06:07:06 PM PDT 24
Peak memory 200104 kb
Host smart-8496ba83-3d84-4e72-80de-180c1258497a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448204273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2448204273
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3951102353
Short name T785
Test name
Test status
Simulation time 42441369157 ps
CPU time 34.21 seconds
Started Jul 20 06:06:50 PM PDT 24
Finished Jul 20 06:07:25 PM PDT 24
Peak memory 200192 kb
Host smart-d94fa8f5-24a0-4c10-83c3-069568bb8e79
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951102353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3951102353
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1908398958
Short name T387
Test name
Test status
Simulation time 138818916848 ps
CPU time 298.52 seconds
Started Jul 20 06:06:52 PM PDT 24
Finished Jul 20 06:11:51 PM PDT 24
Peak memory 200080 kb
Host smart-3f07296b-7016-44f8-be31-fb60b8f9a5a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1908398958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1908398958
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2675485180
Short name T948
Test name
Test status
Simulation time 4434409816 ps
CPU time 4.9 seconds
Started Jul 20 06:06:55 PM PDT 24
Finished Jul 20 06:07:00 PM PDT 24
Peak memory 200032 kb
Host smart-74c20436-1992-4fbb-ad51-b2d67e001f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675485180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2675485180
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1634107566
Short name T944
Test name
Test status
Simulation time 167147325676 ps
CPU time 146.44 seconds
Started Jul 20 06:06:54 PM PDT 24
Finished Jul 20 06:09:21 PM PDT 24
Peak memory 200052 kb
Host smart-2e22a151-aa52-4176-8d9c-3738baf5aaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634107566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1634107566
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1577932732
Short name T542
Test name
Test status
Simulation time 19806152781 ps
CPU time 226.95 seconds
Started Jul 20 06:06:51 PM PDT 24
Finished Jul 20 06:10:38 PM PDT 24
Peak memory 200164 kb
Host smart-719a8d29-2b8b-4119-bb31-73c9ee928b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577932732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1577932732
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3780478861
Short name T830
Test name
Test status
Simulation time 2532043443 ps
CPU time 3.42 seconds
Started Jul 20 06:06:53 PM PDT 24
Finished Jul 20 06:06:57 PM PDT 24
Peak memory 199132 kb
Host smart-1a11e600-fc46-41cc-ba2b-223321dc4dd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3780478861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3780478861
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3508873034
Short name T1062
Test name
Test status
Simulation time 115496920849 ps
CPU time 208.28 seconds
Started Jul 20 06:06:53 PM PDT 24
Finished Jul 20 06:10:22 PM PDT 24
Peak memory 200128 kb
Host smart-45bd1830-6f52-4980-b382-f81647547a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508873034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3508873034
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.55659026
Short name T522
Test name
Test status
Simulation time 34814215678 ps
CPU time 27.48 seconds
Started Jul 20 06:06:53 PM PDT 24
Finished Jul 20 06:07:21 PM PDT 24
Peak memory 196968 kb
Host smart-56bd75e2-f2d4-4fdc-ac05-2bdea156f3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55659026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.55659026
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.879721123
Short name T737
Test name
Test status
Simulation time 666106380 ps
CPU time 2.51 seconds
Started Jul 20 06:06:42 PM PDT 24
Finished Jul 20 06:06:46 PM PDT 24
Peak memory 199848 kb
Host smart-42169544-532f-4ff2-ba97-89d6d14b4c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879721123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.879721123
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3012565733
Short name T1063
Test name
Test status
Simulation time 338543149113 ps
CPU time 157.82 seconds
Started Jul 20 06:06:54 PM PDT 24
Finished Jul 20 06:09:32 PM PDT 24
Peak memory 200260 kb
Host smart-49792c58-a737-46f6-a983-2d2972c20a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012565733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3012565733
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3039615487
Short name T30
Test name
Test status
Simulation time 88205002798 ps
CPU time 494.66 seconds
Started Jul 20 06:06:55 PM PDT 24
Finished Jul 20 06:15:10 PM PDT 24
Peak memory 216556 kb
Host smart-bd45b9dc-172b-4f16-8619-9c9c4d1b1420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039615487 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3039615487
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1299366198
Short name T979
Test name
Test status
Simulation time 2085639811 ps
CPU time 2.13 seconds
Started Jul 20 06:06:56 PM PDT 24
Finished Jul 20 06:06:59 PM PDT 24
Peak memory 198480 kb
Host smart-e2a0739a-3b22-4448-ae85-9f735049f63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299366198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1299366198
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1191601
Short name T796
Test name
Test status
Simulation time 10136548113 ps
CPU time 4.78 seconds
Started Jul 20 06:06:45 PM PDT 24
Finished Jul 20 06:06:51 PM PDT 24
Peak memory 198952 kb
Host smart-87053a8f-4154-447b-82c7-a456612f035c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1191601
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3034733685
Short name T364
Test name
Test status
Simulation time 30766518 ps
CPU time 0.56 seconds
Started Jul 20 06:02:56 PM PDT 24
Finished Jul 20 06:02:58 PM PDT 24
Peak memory 195496 kb
Host smart-167c20a5-401f-4464-9a3f-b6dce0253ce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034733685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3034733685
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1621779370
Short name T987
Test name
Test status
Simulation time 38060789543 ps
CPU time 37.89 seconds
Started Jul 20 06:02:43 PM PDT 24
Finished Jul 20 06:03:22 PM PDT 24
Peak memory 200176 kb
Host smart-724475f8-0ee5-48f0-bd9b-a05ac9967d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621779370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1621779370
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1042304526
Short name T1072
Test name
Test status
Simulation time 62580455982 ps
CPU time 27.98 seconds
Started Jul 20 06:02:40 PM PDT 24
Finished Jul 20 06:03:08 PM PDT 24
Peak memory 200192 kb
Host smart-fdffa008-3cbc-4f8f-af77-8828ba3a5b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042304526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1042304526
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3377112762
Short name T679
Test name
Test status
Simulation time 133409546493 ps
CPU time 176.45 seconds
Started Jul 20 06:02:41 PM PDT 24
Finished Jul 20 06:05:38 PM PDT 24
Peak memory 200116 kb
Host smart-79c00d71-8184-4391-bfd4-6273b5d938c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377112762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3377112762
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3165609661
Short name T1082
Test name
Test status
Simulation time 3665867426 ps
CPU time 7.38 seconds
Started Jul 20 06:02:44 PM PDT 24
Finished Jul 20 06:02:52 PM PDT 24
Peak memory 200136 kb
Host smart-15fe4ec8-c7d7-418d-b34e-66977aba7d38
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165609661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3165609661
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3467677748
Short name T36
Test name
Test status
Simulation time 104584487654 ps
CPU time 381.21 seconds
Started Jul 20 06:02:48 PM PDT 24
Finished Jul 20 06:09:10 PM PDT 24
Peak memory 200104 kb
Host smart-c99c5134-8f38-4ffc-a87d-d7b57bb3b556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3467677748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3467677748
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3684622469
Short name T605
Test name
Test status
Simulation time 2609495342 ps
CPU time 3.14 seconds
Started Jul 20 06:02:49 PM PDT 24
Finished Jul 20 06:02:52 PM PDT 24
Peak memory 199392 kb
Host smart-e316f068-57cc-4ef3-9f64-c981610c4667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684622469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3684622469
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3543660687
Short name T65
Test name
Test status
Simulation time 39432489925 ps
CPU time 46.87 seconds
Started Jul 20 06:02:46 PM PDT 24
Finished Jul 20 06:03:33 PM PDT 24
Peak memory 200424 kb
Host smart-e27e46b4-8324-4e7b-a0d0-a02af509bc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543660687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3543660687
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.4212486034
Short name T352
Test name
Test status
Simulation time 12271686427 ps
CPU time 178.14 seconds
Started Jul 20 06:02:48 PM PDT 24
Finished Jul 20 06:05:47 PM PDT 24
Peak memory 200096 kb
Host smart-a26ec648-ea6e-413e-9152-75ad9b606012
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4212486034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.4212486034
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3360072894
Short name T878
Test name
Test status
Simulation time 2537920280 ps
CPU time 15.35 seconds
Started Jul 20 06:02:37 PM PDT 24
Finished Jul 20 06:02:52 PM PDT 24
Peak memory 198656 kb
Host smart-cdc987ac-6e10-4dd3-8d09-c5d1a8f3271b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360072894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3360072894
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1091141274
Short name T720
Test name
Test status
Simulation time 53186058951 ps
CPU time 67.06 seconds
Started Jul 20 06:02:49 PM PDT 24
Finished Jul 20 06:03:56 PM PDT 24
Peak memory 200184 kb
Host smart-6cce9607-d375-4f1a-812c-4969fec6c30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091141274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1091141274
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3866952065
Short name T1067
Test name
Test status
Simulation time 1660941781 ps
CPU time 1.24 seconds
Started Jul 20 06:02:49 PM PDT 24
Finished Jul 20 06:02:51 PM PDT 24
Peak memory 195648 kb
Host smart-19491335-5807-4fc9-9177-b295516a409b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866952065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3866952065
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.322984907
Short name T24
Test name
Test status
Simulation time 65896736 ps
CPU time 0.83 seconds
Started Jul 20 06:02:48 PM PDT 24
Finished Jul 20 06:02:49 PM PDT 24
Peak memory 218380 kb
Host smart-33aeeb72-3ddb-4730-931a-fb715ce7a969
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322984907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.322984907
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.486270311
Short name T619
Test name
Test status
Simulation time 265248262 ps
CPU time 0.92 seconds
Started Jul 20 06:02:38 PM PDT 24
Finished Jul 20 06:02:39 PM PDT 24
Peak memory 198480 kb
Host smart-7f6afe98-0cae-4bb1-9536-2616f74e8af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486270311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.486270311
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3163718061
Short name T192
Test name
Test status
Simulation time 177040165741 ps
CPU time 710.4 seconds
Started Jul 20 06:02:48 PM PDT 24
Finished Jul 20 06:14:39 PM PDT 24
Peak memory 200084 kb
Host smart-531d9594-1fda-4015-aff0-b88b72e0b7d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163718061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3163718061
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1014472279
Short name T939
Test name
Test status
Simulation time 59436010753 ps
CPU time 552.54 seconds
Started Jul 20 06:02:46 PM PDT 24
Finished Jul 20 06:11:59 PM PDT 24
Peak memory 216708 kb
Host smart-885b51af-3cc5-47e2-8e7e-a7651e9a9002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014472279 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1014472279
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2874369733
Short name T540
Test name
Test status
Simulation time 995715090 ps
CPU time 3.37 seconds
Started Jul 20 06:02:47 PM PDT 24
Finished Jul 20 06:02:50 PM PDT 24
Peak memory 199936 kb
Host smart-bd5d4bc0-004d-4759-85c8-58ed18090eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874369733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2874369733
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1302727499
Short name T609
Test name
Test status
Simulation time 6514016751 ps
CPU time 11.09 seconds
Started Jul 20 06:02:39 PM PDT 24
Finished Jul 20 06:02:51 PM PDT 24
Peak memory 197888 kb
Host smart-b8f03c6f-6903-4011-98de-f291febc3d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302727499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1302727499
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.697142515
Short name T476
Test name
Test status
Simulation time 30218574 ps
CPU time 0.55 seconds
Started Jul 20 06:07:01 PM PDT 24
Finished Jul 20 06:07:02 PM PDT 24
Peak memory 194464 kb
Host smart-9078ab53-a306-472a-801f-10916ff0c3a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697142515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.697142515
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1556414945
Short name T1107
Test name
Test status
Simulation time 123718670167 ps
CPU time 29.46 seconds
Started Jul 20 06:06:50 PM PDT 24
Finished Jul 20 06:07:20 PM PDT 24
Peak memory 200104 kb
Host smart-cd32b821-cdbc-4064-bcf6-a8d83992a54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556414945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1556414945
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.583761726
Short name T154
Test name
Test status
Simulation time 21261209939 ps
CPU time 31.72 seconds
Started Jul 20 06:06:54 PM PDT 24
Finished Jul 20 06:07:26 PM PDT 24
Peak memory 199256 kb
Host smart-84327276-7136-4c91-bf7e-8cf3a3bf1a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583761726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.583761726
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.56700848
Short name T1133
Test name
Test status
Simulation time 17539230589 ps
CPU time 35.42 seconds
Started Jul 20 06:06:50 PM PDT 24
Finished Jul 20 06:07:26 PM PDT 24
Peak memory 200152 kb
Host smart-66499977-d8b6-4e97-ade3-f3bcf0b7854c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56700848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.56700848
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3265775965
Short name T816
Test name
Test status
Simulation time 21990914193 ps
CPU time 35.04 seconds
Started Jul 20 06:06:53 PM PDT 24
Finished Jul 20 06:07:29 PM PDT 24
Peak memory 200072 kb
Host smart-caefa6cd-5763-4a36-adce-ed1381ec3bb2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265775965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3265775965
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2823555340
Short name T624
Test name
Test status
Simulation time 90244058644 ps
CPU time 197.22 seconds
Started Jul 20 06:07:01 PM PDT 24
Finished Jul 20 06:10:19 PM PDT 24
Peak memory 200120 kb
Host smart-98ef9c14-26eb-459a-b703-3d902ac0571f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2823555340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2823555340
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2663516284
Short name T650
Test name
Test status
Simulation time 9356248877 ps
CPU time 10.9 seconds
Started Jul 20 06:07:00 PM PDT 24
Finished Jul 20 06:07:12 PM PDT 24
Peak memory 199808 kb
Host smart-0ae5d53e-ca76-4526-98c1-4d3740070bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663516284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2663516284
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.879697120
Short name T334
Test name
Test status
Simulation time 38527411466 ps
CPU time 62.55 seconds
Started Jul 20 06:06:49 PM PDT 24
Finished Jul 20 06:07:52 PM PDT 24
Peak memory 200308 kb
Host smart-fd8abfdc-6d2a-41aa-bf5d-e086867e28be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879697120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.879697120
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3337058451
Short name T271
Test name
Test status
Simulation time 18202718660 ps
CPU time 935.18 seconds
Started Jul 20 06:07:00 PM PDT 24
Finished Jul 20 06:22:36 PM PDT 24
Peak memory 200132 kb
Host smart-0c596174-b27d-48ee-b31e-315db89b8d35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3337058451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3337058451
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2143001665
Short name T377
Test name
Test status
Simulation time 4730430891 ps
CPU time 36.23 seconds
Started Jul 20 06:06:56 PM PDT 24
Finished Jul 20 06:07:33 PM PDT 24
Peak memory 199428 kb
Host smart-627b067f-4eb0-4d62-8028-550c66961246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2143001665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2143001665
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1119927139
Short name T544
Test name
Test status
Simulation time 39663890344 ps
CPU time 58.24 seconds
Started Jul 20 06:07:00 PM PDT 24
Finished Jul 20 06:07:59 PM PDT 24
Peak memory 199820 kb
Host smart-365def67-3b7e-463f-8138-529525fd75e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119927139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1119927139
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.4267858779
Short name T997
Test name
Test status
Simulation time 4112060947 ps
CPU time 1.7 seconds
Started Jul 20 06:06:52 PM PDT 24
Finished Jul 20 06:06:54 PM PDT 24
Peak memory 196488 kb
Host smart-df5aaef2-63eb-4d69-83c5-ae5e52de6f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267858779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.4267858779
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2727312968
Short name T719
Test name
Test status
Simulation time 983512346 ps
CPU time 2.85 seconds
Started Jul 20 06:06:56 PM PDT 24
Finished Jul 20 06:07:00 PM PDT 24
Peak memory 198876 kb
Host smart-e8d18973-df54-4aca-a2a2-c1be2a3247f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727312968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2727312968
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2923899149
Short name T430
Test name
Test status
Simulation time 155800874461 ps
CPU time 74.12 seconds
Started Jul 20 06:07:04 PM PDT 24
Finished Jul 20 06:08:19 PM PDT 24
Peak memory 200168 kb
Host smart-acf8b454-a306-43fb-a413-b3afc7d50c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923899149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2923899149
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.689371388
Short name T196
Test name
Test status
Simulation time 222950919005 ps
CPU time 522.69 seconds
Started Jul 20 06:07:00 PM PDT 24
Finished Jul 20 06:15:43 PM PDT 24
Peak memory 227336 kb
Host smart-7952a7c8-4c2b-4904-b4da-719ffa305586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689371388 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.689371388
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3640616108
Short name T1020
Test name
Test status
Simulation time 6226649277 ps
CPU time 14.67 seconds
Started Jul 20 06:07:02 PM PDT 24
Finished Jul 20 06:07:18 PM PDT 24
Peak memory 200176 kb
Host smart-a5718f84-6b25-4ec5-97b4-fb11f7004a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640616108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3640616108
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3144716965
Short name T556
Test name
Test status
Simulation time 109918703767 ps
CPU time 17.4 seconds
Started Jul 20 06:06:53 PM PDT 24
Finished Jul 20 06:07:11 PM PDT 24
Peak memory 200124 kb
Host smart-4e7e0a96-1e98-4ece-bcb3-627ba4f2b08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144716965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3144716965
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.416367188
Short name T854
Test name
Test status
Simulation time 48989033 ps
CPU time 0.57 seconds
Started Jul 20 06:07:09 PM PDT 24
Finished Jul 20 06:07:11 PM PDT 24
Peak memory 195568 kb
Host smart-60c2c5ae-1397-4bb3-9597-f76863884e03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416367188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.416367188
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2085089903
Short name T1169
Test name
Test status
Simulation time 96409471845 ps
CPU time 84.67 seconds
Started Jul 20 06:06:59 PM PDT 24
Finished Jul 20 06:08:24 PM PDT 24
Peak memory 200180 kb
Host smart-9465a994-682f-4657-b2ef-41c6cdd2cdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085089903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2085089903
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3975419846
Short name T753
Test name
Test status
Simulation time 91767459622 ps
CPU time 40.87 seconds
Started Jul 20 06:07:00 PM PDT 24
Finished Jul 20 06:07:42 PM PDT 24
Peak memory 200204 kb
Host smart-f60c990d-0111-4506-bd35-62596b278e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975419846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3975419846
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3345594896
Short name T475
Test name
Test status
Simulation time 31178699383 ps
CPU time 59.63 seconds
Started Jul 20 06:07:03 PM PDT 24
Finished Jul 20 06:08:03 PM PDT 24
Peak memory 200180 kb
Host smart-fb6e3425-1bba-4ca1-9967-2fc39b53274b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345594896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3345594896
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2237387930
Short name T945
Test name
Test status
Simulation time 25419152418 ps
CPU time 17.02 seconds
Started Jul 20 06:07:03 PM PDT 24
Finished Jul 20 06:07:20 PM PDT 24
Peak memory 200200 kb
Host smart-a2e9c2f7-0263-48a5-bad1-0a3e76efeb63
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237387930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2237387930
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1683024492
Short name T765
Test name
Test status
Simulation time 110195068608 ps
CPU time 820.92 seconds
Started Jul 20 06:07:10 PM PDT 24
Finished Jul 20 06:20:52 PM PDT 24
Peak memory 200120 kb
Host smart-9d15167e-6989-45ea-9b23-403c39e1a4f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1683024492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1683024492
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.27002023
Short name T455
Test name
Test status
Simulation time 1835583401 ps
CPU time 1.43 seconds
Started Jul 20 06:07:09 PM PDT 24
Finished Jul 20 06:07:11 PM PDT 24
Peak memory 197676 kb
Host smart-e2f9a969-85b8-4fbc-baa8-e862151336b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27002023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.27002023
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2114749357
Short name T635
Test name
Test status
Simulation time 42701956059 ps
CPU time 37.08 seconds
Started Jul 20 06:07:01 PM PDT 24
Finished Jul 20 06:07:39 PM PDT 24
Peak memory 199220 kb
Host smart-11d794f5-1067-49c4-9ac2-6c30f6777a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114749357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2114749357
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.967448606
Short name T1034
Test name
Test status
Simulation time 14218736336 ps
CPU time 900.48 seconds
Started Jul 20 06:07:11 PM PDT 24
Finished Jul 20 06:22:12 PM PDT 24
Peak memory 200156 kb
Host smart-c51f6140-b6a4-48e5-9d5a-a0e9d6d89656
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967448606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.967448606
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3924286283
Short name T550
Test name
Test status
Simulation time 5249614631 ps
CPU time 47.58 seconds
Started Jul 20 06:07:02 PM PDT 24
Finished Jul 20 06:07:50 PM PDT 24
Peak memory 198160 kb
Host smart-62437008-5c6f-476b-b925-888099b25ff6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3924286283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3924286283
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3102888754
Short name T935
Test name
Test status
Simulation time 51193960578 ps
CPU time 46.66 seconds
Started Jul 20 06:07:06 PM PDT 24
Finished Jul 20 06:07:53 PM PDT 24
Peak memory 200184 kb
Host smart-521ac9fd-c00c-4be4-a1a3-c6d3b64037d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102888754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3102888754
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3381123534
Short name T293
Test name
Test status
Simulation time 27225710290 ps
CPU time 37.51 seconds
Started Jul 20 06:07:04 PM PDT 24
Finished Jul 20 06:07:42 PM PDT 24
Peak memory 196960 kb
Host smart-ffae7e0d-47cf-49ab-9bcf-7b99fa8d485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381123534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3381123534
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1544181896
Short name T263
Test name
Test status
Simulation time 690538549 ps
CPU time 2.73 seconds
Started Jul 20 06:07:05 PM PDT 24
Finished Jul 20 06:07:08 PM PDT 24
Peak memory 199948 kb
Host smart-633ad39a-56c9-4790-b402-bf04b6d2c079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544181896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1544181896
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1691628706
Short name T218
Test name
Test status
Simulation time 223933729621 ps
CPU time 108.69 seconds
Started Jul 20 06:07:06 PM PDT 24
Finished Jul 20 06:08:56 PM PDT 24
Peak memory 200168 kb
Host smart-602b0be1-fe71-4c28-a561-fe4aab6e40e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691628706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1691628706
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.677391064
Short name T356
Test name
Test status
Simulation time 2130644601 ps
CPU time 3.06 seconds
Started Jul 20 06:07:08 PM PDT 24
Finished Jul 20 06:07:11 PM PDT 24
Peak memory 199120 kb
Host smart-be9e441d-e3a1-4ebc-a5ef-60cea77d4739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677391064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.677391064
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2422842285
Short name T665
Test name
Test status
Simulation time 32077978718 ps
CPU time 46.29 seconds
Started Jul 20 06:07:01 PM PDT 24
Finished Jul 20 06:07:48 PM PDT 24
Peak memory 200208 kb
Host smart-3a8a1aa5-81fe-4bf3-bdc5-ac9e4c5575c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422842285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2422842285
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.4080775178
Short name T844
Test name
Test status
Simulation time 16941895 ps
CPU time 0.55 seconds
Started Jul 20 06:07:06 PM PDT 24
Finished Jul 20 06:07:08 PM PDT 24
Peak memory 194860 kb
Host smart-dde2ee5e-1c70-49e5-baeb-57c7278022bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080775178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.4080775178
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2286080932
Short name T1066
Test name
Test status
Simulation time 128165907597 ps
CPU time 88.58 seconds
Started Jul 20 06:07:11 PM PDT 24
Finished Jul 20 06:08:41 PM PDT 24
Peak memory 200112 kb
Host smart-27fb10cf-5c06-4cec-a286-2a97287fafd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286080932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2286080932
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.4139891546
Short name T43
Test name
Test status
Simulation time 16810133293 ps
CPU time 27.91 seconds
Started Jul 20 06:07:10 PM PDT 24
Finished Jul 20 06:07:39 PM PDT 24
Peak memory 200112 kb
Host smart-5ba0a1cd-7552-4c6c-b2f9-132ff62a6d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139891546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.4139891546
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3174802931
Short name T182
Test name
Test status
Simulation time 95543545073 ps
CPU time 42.81 seconds
Started Jul 20 06:07:15 PM PDT 24
Finished Jul 20 06:07:58 PM PDT 24
Peak memory 198988 kb
Host smart-a442f409-13b3-4a39-81d3-5e1000d1c766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174802931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3174802931
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2621989146
Short name T564
Test name
Test status
Simulation time 12834043749 ps
CPU time 27.14 seconds
Started Jul 20 06:07:09 PM PDT 24
Finished Jul 20 06:07:37 PM PDT 24
Peak memory 200112 kb
Host smart-1fd9f2b1-a948-4bc8-839d-7873185c9ab8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621989146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2621989146
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3769646239
Short name T1026
Test name
Test status
Simulation time 241215090345 ps
CPU time 279.22 seconds
Started Jul 20 06:07:15 PM PDT 24
Finished Jul 20 06:11:55 PM PDT 24
Peak memory 200068 kb
Host smart-60cdcde0-5570-4616-917e-74947ba532c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769646239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3769646239
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3421431239
Short name T1052
Test name
Test status
Simulation time 6787821640 ps
CPU time 19.71 seconds
Started Jul 20 06:07:09 PM PDT 24
Finished Jul 20 06:07:30 PM PDT 24
Peak memory 199812 kb
Host smart-4d6bd28b-8272-4809-8494-cf0b8e2d09dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421431239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3421431239
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2483874829
Short name T33
Test name
Test status
Simulation time 169828088638 ps
CPU time 38.26 seconds
Started Jul 20 06:07:15 PM PDT 24
Finished Jul 20 06:07:54 PM PDT 24
Peak memory 199052 kb
Host smart-8e95db00-f514-4180-85c7-ea6684ffc2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483874829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2483874829
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2423452966
Short name T286
Test name
Test status
Simulation time 18480427264 ps
CPU time 938.07 seconds
Started Jul 20 06:07:11 PM PDT 24
Finished Jul 20 06:22:50 PM PDT 24
Peak memory 200140 kb
Host smart-1e4c26ad-550d-4f20-b4c2-d52612a24e58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423452966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2423452966
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2182832772
Short name T9
Test name
Test status
Simulation time 7114968154 ps
CPU time 65.08 seconds
Started Jul 20 06:07:06 PM PDT 24
Finished Jul 20 06:08:12 PM PDT 24
Peak memory 199660 kb
Host smart-5ce68519-ccf7-45dd-9542-07c7d2f5d2cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2182832772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2182832772
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3364240093
Short name T932
Test name
Test status
Simulation time 21849077370 ps
CPU time 19.3 seconds
Started Jul 20 06:07:08 PM PDT 24
Finished Jul 20 06:07:28 PM PDT 24
Peak memory 200164 kb
Host smart-7501ee46-d243-4803-be32-f961d4adb0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364240093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3364240093
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4085876005
Short name T834
Test name
Test status
Simulation time 36573431921 ps
CPU time 24.47 seconds
Started Jul 20 06:07:10 PM PDT 24
Finished Jul 20 06:07:36 PM PDT 24
Peak memory 196032 kb
Host smart-d672856c-5d87-4644-b140-2adfabe73048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085876005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4085876005
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.508997198
Short name T681
Test name
Test status
Simulation time 446069815 ps
CPU time 1.94 seconds
Started Jul 20 06:07:09 PM PDT 24
Finished Jul 20 06:07:12 PM PDT 24
Peak memory 198840 kb
Host smart-7d2f4036-c204-4e41-a63e-0c99388bc741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508997198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.508997198
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.91891114
Short name T109
Test name
Test status
Simulation time 154056599266 ps
CPU time 54.87 seconds
Started Jul 20 06:07:09 PM PDT 24
Finished Jul 20 06:08:04 PM PDT 24
Peak memory 200196 kb
Host smart-9b3ad35a-9982-474f-b2a2-54911326645a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91891114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.91891114
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1758396236
Short name T118
Test name
Test status
Simulation time 20085465391 ps
CPU time 265 seconds
Started Jul 20 06:07:15 PM PDT 24
Finished Jul 20 06:11:41 PM PDT 24
Peak memory 208380 kb
Host smart-bb595e32-a14c-4c4e-bcc3-6e0a6ae13ac1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758396236 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1758396236
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2739184450
Short name T776
Test name
Test status
Simulation time 6856160746 ps
CPU time 18.39 seconds
Started Jul 20 06:07:07 PM PDT 24
Finished Jul 20 06:07:26 PM PDT 24
Peak memory 200080 kb
Host smart-28fe2e7a-f0eb-409e-bc19-f3006f1f529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739184450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2739184450
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1197889504
Short name T304
Test name
Test status
Simulation time 55046634035 ps
CPU time 87.38 seconds
Started Jul 20 06:07:11 PM PDT 24
Finished Jul 20 06:08:39 PM PDT 24
Peak memory 200148 kb
Host smart-8a1c60a3-a151-47a0-9c6c-30847ce796a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197889504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1197889504
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2243055857
Short name T344
Test name
Test status
Simulation time 21787491 ps
CPU time 0.56 seconds
Started Jul 20 06:07:16 PM PDT 24
Finished Jul 20 06:07:17 PM PDT 24
Peak memory 195780 kb
Host smart-3fd527d8-25e9-4b66-af4b-1beeed05baa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243055857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2243055857
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1168207006
Short name T819
Test name
Test status
Simulation time 61222670828 ps
CPU time 21.91 seconds
Started Jul 20 06:07:18 PM PDT 24
Finished Jul 20 06:07:40 PM PDT 24
Peak memory 200192 kb
Host smart-3e3b2138-d822-4535-806f-7fd419a9065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168207006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1168207006
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3023068790
Short name T661
Test name
Test status
Simulation time 18479391086 ps
CPU time 16.23 seconds
Started Jul 20 06:07:16 PM PDT 24
Finished Jul 20 06:07:34 PM PDT 24
Peak memory 198896 kb
Host smart-fb506320-27c6-40b5-a2e5-d7676a2ac9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023068790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3023068790
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_intr.1482192495
Short name T420
Test name
Test status
Simulation time 21531405455 ps
CPU time 8.82 seconds
Started Jul 20 06:07:15 PM PDT 24
Finished Jul 20 06:07:25 PM PDT 24
Peak memory 200164 kb
Host smart-8f445f30-19fd-4f2c-bef8-f0b4f6a6d66b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482192495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1482192495
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.396937433
Short name T452
Test name
Test status
Simulation time 214893202358 ps
CPU time 945.1 seconds
Started Jul 20 06:07:18 PM PDT 24
Finished Jul 20 06:23:04 PM PDT 24
Peak memory 200080 kb
Host smart-f3be21d0-126e-4293-8d1f-64f9bf71dea9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=396937433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.396937433
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3773916885
Short name T1036
Test name
Test status
Simulation time 9795472684 ps
CPU time 5.97 seconds
Started Jul 20 06:07:17 PM PDT 24
Finished Jul 20 06:07:24 PM PDT 24
Peak memory 200028 kb
Host smart-9b02b838-26d9-434d-b826-f00e691e2c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773916885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3773916885
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.4195432121
Short name T761
Test name
Test status
Simulation time 13668296010 ps
CPU time 690.08 seconds
Started Jul 20 06:07:15 PM PDT 24
Finished Jul 20 06:18:46 PM PDT 24
Peak memory 200112 kb
Host smart-4f253cc5-9f35-46ad-90b0-accc6aedc0be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4195432121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.4195432121
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.534201456
Short name T1045
Test name
Test status
Simulation time 5570228558 ps
CPU time 17.26 seconds
Started Jul 20 06:07:16 PM PDT 24
Finished Jul 20 06:07:34 PM PDT 24
Peak memory 200188 kb
Host smart-dbe28fc0-0243-44c6-9a89-49aa8a269342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=534201456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.534201456
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.246073945
Short name T1069
Test name
Test status
Simulation time 26901472837 ps
CPU time 18.52 seconds
Started Jul 20 06:07:16 PM PDT 24
Finished Jul 20 06:07:36 PM PDT 24
Peak memory 199532 kb
Host smart-e4004095-e100-4210-aae9-f9930250f914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246073945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.246073945
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.162008708
Short name T405
Test name
Test status
Simulation time 7134408761 ps
CPU time 2.04 seconds
Started Jul 20 06:07:18 PM PDT 24
Finished Jul 20 06:07:20 PM PDT 24
Peak memory 196324 kb
Host smart-0b897f69-739c-4fbd-aad7-bce9650226ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162008708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.162008708
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.4274006575
Short name T280
Test name
Test status
Simulation time 269730872 ps
CPU time 1.21 seconds
Started Jul 20 06:07:16 PM PDT 24
Finished Jul 20 06:07:18 PM PDT 24
Peak memory 198680 kb
Host smart-812a60ac-70d1-44e6-84be-a44a37cf8881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274006575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.4274006575
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3306945106
Short name T1008
Test name
Test status
Simulation time 175388980340 ps
CPU time 146.08 seconds
Started Jul 20 06:07:19 PM PDT 24
Finished Jul 20 06:09:46 PM PDT 24
Peak memory 200168 kb
Host smart-cd2b447c-7d29-4710-83b7-2c70e811c641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306945106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3306945106
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2722391703
Short name T784
Test name
Test status
Simulation time 505195249910 ps
CPU time 1326.26 seconds
Started Jul 20 06:07:18 PM PDT 24
Finished Jul 20 06:29:25 PM PDT 24
Peak memory 233164 kb
Host smart-d93d0ffd-8b07-4e78-86fd-cbc1271b5aa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722391703 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2722391703
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3841032990
Short name T631
Test name
Test status
Simulation time 7605648130 ps
CPU time 11.41 seconds
Started Jul 20 06:07:14 PM PDT 24
Finished Jul 20 06:07:26 PM PDT 24
Peak memory 200172 kb
Host smart-d8be1e8e-3a50-4b00-898e-e76c0d449761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841032990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3841032990
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1590282335
Short name T801
Test name
Test status
Simulation time 63162038255 ps
CPU time 51.25 seconds
Started Jul 20 06:07:17 PM PDT 24
Finished Jul 20 06:08:09 PM PDT 24
Peak memory 200196 kb
Host smart-524d8a19-62c1-408b-839e-d038b33a94a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590282335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1590282335
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1695140414
Short name T464
Test name
Test status
Simulation time 17208734 ps
CPU time 0.55 seconds
Started Jul 20 06:07:24 PM PDT 24
Finished Jul 20 06:07:25 PM PDT 24
Peak memory 195564 kb
Host smart-29989c89-3a9e-45d2-bd46-19784b21f303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695140414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1695140414
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1322296094
Short name T96
Test name
Test status
Simulation time 76003904901 ps
CPU time 31.57 seconds
Started Jul 20 06:07:16 PM PDT 24
Finished Jul 20 06:07:48 PM PDT 24
Peak memory 200180 kb
Host smart-0ed7cdcd-bda1-4c73-84de-de0af02e8871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322296094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1322296094
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2094308528
Short name T919
Test name
Test status
Simulation time 10816332722 ps
CPU time 11.16 seconds
Started Jul 20 06:07:17 PM PDT 24
Finished Jul 20 06:07:29 PM PDT 24
Peak memory 200096 kb
Host smart-4a69fe38-7130-4004-bc85-e8eec4d7851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094308528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2094308528
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.4001788739
Short name T697
Test name
Test status
Simulation time 67802581439 ps
CPU time 8.8 seconds
Started Jul 20 06:07:17 PM PDT 24
Finished Jul 20 06:07:27 PM PDT 24
Peak memory 200172 kb
Host smart-f8e7c757-c78a-4f71-b349-0052c725f163
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001788739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.4001788739
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1531539813
Short name T103
Test name
Test status
Simulation time 104861111342 ps
CPU time 526.87 seconds
Started Jul 20 06:07:27 PM PDT 24
Finished Jul 20 06:16:14 PM PDT 24
Peak memory 200144 kb
Host smart-c0f2e5cf-c9b3-473a-8bdf-e5876294de1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531539813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1531539813
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1107972705
Short name T946
Test name
Test status
Simulation time 6862499615 ps
CPU time 8.67 seconds
Started Jul 20 06:07:26 PM PDT 24
Finished Jul 20 06:07:35 PM PDT 24
Peak memory 199548 kb
Host smart-57d84dd4-59c2-4ee3-8517-155615a2593e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107972705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1107972705
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3586284623
Short name T258
Test name
Test status
Simulation time 200326654059 ps
CPU time 126.51 seconds
Started Jul 20 06:07:18 PM PDT 24
Finished Jul 20 06:09:25 PM PDT 24
Peak memory 208444 kb
Host smart-c9c75413-b99d-4ccf-840c-bf600b6eba58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586284623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3586284623
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2650526319
Short name T912
Test name
Test status
Simulation time 28998436842 ps
CPU time 698.01 seconds
Started Jul 20 06:07:23 PM PDT 24
Finished Jul 20 06:19:01 PM PDT 24
Peak memory 200180 kb
Host smart-17d9e849-4637-41c9-96dd-3f311fc82059
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2650526319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2650526319
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2005159708
Short name T434
Test name
Test status
Simulation time 5567719186 ps
CPU time 44.02 seconds
Started Jul 20 06:07:18 PM PDT 24
Finished Jul 20 06:08:02 PM PDT 24
Peak memory 199448 kb
Host smart-8c391415-a2ee-43a9-96de-41d13bc1eccf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005159708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2005159708
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.873261390
Short name T436
Test name
Test status
Simulation time 54071911711 ps
CPU time 21.65 seconds
Started Jul 20 06:07:15 PM PDT 24
Finished Jul 20 06:07:38 PM PDT 24
Peak memory 200192 kb
Host smart-65dc17c2-10e8-41a5-8e6c-fe9b7b4f7a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873261390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.873261390
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.4127537554
Short name T315
Test name
Test status
Simulation time 7517846403 ps
CPU time 3.35 seconds
Started Jul 20 06:07:18 PM PDT 24
Finished Jul 20 06:07:22 PM PDT 24
Peak memory 196340 kb
Host smart-bd7ed253-1faa-48a2-989f-4e9319a2f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127537554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.4127537554
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2253985125
Short name T1031
Test name
Test status
Simulation time 772731669 ps
CPU time 1.36 seconds
Started Jul 20 06:07:16 PM PDT 24
Finished Jul 20 06:07:18 PM PDT 24
Peak memory 200156 kb
Host smart-c86b4a08-d5b4-4be7-83a6-49033f116afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253985125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2253985125
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2819110262
Short name T1084
Test name
Test status
Simulation time 295730596733 ps
CPU time 669 seconds
Started Jul 20 06:07:24 PM PDT 24
Finished Jul 20 06:18:33 PM PDT 24
Peak memory 200112 kb
Host smart-13d471ca-53cb-454e-b4ce-52d98d911e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819110262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2819110262
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3908768558
Short name T773
Test name
Test status
Simulation time 6989487692 ps
CPU time 93.36 seconds
Started Jul 20 06:07:25 PM PDT 24
Finished Jul 20 06:08:59 PM PDT 24
Peak memory 208452 kb
Host smart-cfb801ea-dc0f-478b-98f3-41d1732311d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908768558 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3908768558
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2417991819
Short name T302
Test name
Test status
Simulation time 7863611814 ps
CPU time 7.99 seconds
Started Jul 20 06:07:26 PM PDT 24
Finished Jul 20 06:07:35 PM PDT 24
Peak memory 200028 kb
Host smart-6c52be92-bac5-4622-b8f0-d1f6001afb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417991819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2417991819
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.768269181
Short name T969
Test name
Test status
Simulation time 42191866107 ps
CPU time 20.04 seconds
Started Jul 20 06:07:16 PM PDT 24
Finished Jul 20 06:07:37 PM PDT 24
Peak memory 200192 kb
Host smart-c1589317-8489-4199-871d-5b584eb58fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768269181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.768269181
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.4154109022
Short name T598
Test name
Test status
Simulation time 32126625 ps
CPU time 0.53 seconds
Started Jul 20 06:07:23 PM PDT 24
Finished Jul 20 06:07:24 PM PDT 24
Peak memory 195592 kb
Host smart-a45952e3-c58e-473b-822a-52dbad3d8c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154109022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.4154109022
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.4123563005
Short name T373
Test name
Test status
Simulation time 104575001022 ps
CPU time 39.99 seconds
Started Jul 20 06:07:27 PM PDT 24
Finished Jul 20 06:08:07 PM PDT 24
Peak memory 200172 kb
Host smart-452d41f6-dedd-4003-8f51-ddfe0057f25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123563005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.4123563005
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.417051673
Short name T536
Test name
Test status
Simulation time 132541591212 ps
CPU time 50.05 seconds
Started Jul 20 06:07:25 PM PDT 24
Finished Jul 20 06:08:16 PM PDT 24
Peak memory 200188 kb
Host smart-a75f10a2-815a-42f7-bb80-923b3a82eda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417051673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.417051673
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_intr.792914534
Short name T98
Test name
Test status
Simulation time 90573745614 ps
CPU time 24.11 seconds
Started Jul 20 06:07:25 PM PDT 24
Finished Jul 20 06:07:50 PM PDT 24
Peak memory 196960 kb
Host smart-97bd4dcd-108e-48c1-a7aa-650738aac63e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792914534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.792914534
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.4256370897
Short name T456
Test name
Test status
Simulation time 86718588092 ps
CPU time 596.8 seconds
Started Jul 20 06:07:22 PM PDT 24
Finished Jul 20 06:17:19 PM PDT 24
Peak memory 200140 kb
Host smart-c8827f04-7fe2-424e-8ee3-a034b2de54aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256370897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.4256370897
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.193581357
Short name T867
Test name
Test status
Simulation time 9801232323 ps
CPU time 7.49 seconds
Started Jul 20 06:07:23 PM PDT 24
Finished Jul 20 06:07:31 PM PDT 24
Peak memory 200184 kb
Host smart-4c6ac7a3-aedc-4891-95b4-c75dd79cd43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193581357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.193581357
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2156987664
Short name T1079
Test name
Test status
Simulation time 102058845765 ps
CPU time 45.54 seconds
Started Jul 20 06:07:29 PM PDT 24
Finished Jul 20 06:08:15 PM PDT 24
Peak memory 200212 kb
Host smart-ee19a431-bbc8-4e62-86e1-ec28c1865d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156987664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2156987664
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2860219447
Short name T310
Test name
Test status
Simulation time 8826171545 ps
CPU time 143.6 seconds
Started Jul 20 06:07:25 PM PDT 24
Finished Jul 20 06:09:49 PM PDT 24
Peak memory 200172 kb
Host smart-4381c066-9e17-455e-8845-783e9698ffc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2860219447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2860219447
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2623439288
Short name T1158
Test name
Test status
Simulation time 1912355188 ps
CPU time 12.93 seconds
Started Jul 20 06:07:24 PM PDT 24
Finished Jul 20 06:07:37 PM PDT 24
Peak memory 199056 kb
Host smart-38863a0d-eca7-4bc3-8930-26748e1e402b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623439288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2623439288
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3534320483
Short name T537
Test name
Test status
Simulation time 67401222328 ps
CPU time 48.52 seconds
Started Jul 20 06:07:28 PM PDT 24
Finished Jul 20 06:08:18 PM PDT 24
Peak memory 200016 kb
Host smart-35ff85d1-7a12-4cba-8b92-c15da029c5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534320483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3534320483
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2322022355
Short name T1110
Test name
Test status
Simulation time 4255074464 ps
CPU time 6.86 seconds
Started Jul 20 06:07:26 PM PDT 24
Finished Jul 20 06:07:33 PM PDT 24
Peak memory 196456 kb
Host smart-eab47b1c-57b4-41bf-8c1c-6113931fe2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322022355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2322022355
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2223493066
Short name T479
Test name
Test status
Simulation time 713017841 ps
CPU time 1.49 seconds
Started Jul 20 06:07:24 PM PDT 24
Finished Jul 20 06:07:26 PM PDT 24
Peak memory 198868 kb
Host smart-e45ef525-fc95-4e38-829b-1cb2e65ed7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223493066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2223493066
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1234061101
Short name T562
Test name
Test status
Simulation time 116289867534 ps
CPU time 100.47 seconds
Started Jul 20 06:07:25 PM PDT 24
Finished Jul 20 06:09:06 PM PDT 24
Peak memory 200120 kb
Host smart-de3fcb43-5485-48fd-a0c8-f2b7e2eba730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234061101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1234061101
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1694056352
Short name T51
Test name
Test status
Simulation time 70528114919 ps
CPU time 542.28 seconds
Started Jul 20 06:07:21 PM PDT 24
Finished Jul 20 06:16:24 PM PDT 24
Peak memory 208420 kb
Host smart-bec98fcf-60fe-494d-be4b-b9482481733b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694056352 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1694056352
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1740192288
Short name T396
Test name
Test status
Simulation time 2591967714 ps
CPU time 2.6 seconds
Started Jul 20 06:07:26 PM PDT 24
Finished Jul 20 06:07:29 PM PDT 24
Peak memory 199312 kb
Host smart-8b7fc0ce-ca29-43db-a3c7-cad4aa2e5b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740192288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1740192288
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3902330964
Short name T291
Test name
Test status
Simulation time 8338837222 ps
CPU time 3.33 seconds
Started Jul 20 06:07:23 PM PDT 24
Finished Jul 20 06:07:27 PM PDT 24
Peak memory 199852 kb
Host smart-07c02f62-19df-4c6b-9dca-3d9928dba8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902330964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3902330964
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3279610901
Short name T1154
Test name
Test status
Simulation time 37569967 ps
CPU time 0.52 seconds
Started Jul 20 06:07:33 PM PDT 24
Finished Jul 20 06:07:34 PM PDT 24
Peak memory 195028 kb
Host smart-5fb4f560-ace1-4750-8f01-c023696c0b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279610901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3279610901
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1077287116
Short name T444
Test name
Test status
Simulation time 69060643710 ps
CPU time 54.58 seconds
Started Jul 20 06:07:26 PM PDT 24
Finished Jul 20 06:08:21 PM PDT 24
Peak memory 200168 kb
Host smart-57b3d227-a466-49f3-bf55-a5a90aaa12c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077287116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1077287116
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1823758767
Short name T417
Test name
Test status
Simulation time 24280052394 ps
CPU time 18.88 seconds
Started Jul 20 06:07:33 PM PDT 24
Finished Jul 20 06:07:53 PM PDT 24
Peak memory 199980 kb
Host smart-bbd4922b-0363-4341-9986-b31307db5e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823758767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1823758767
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2623057844
Short name T213
Test name
Test status
Simulation time 31880862410 ps
CPU time 26.33 seconds
Started Jul 20 06:07:35 PM PDT 24
Finished Jul 20 06:08:02 PM PDT 24
Peak memory 200108 kb
Host smart-110ef156-0ef4-465f-a4b8-29e66b9825e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623057844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2623057844
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3144771763
Short name T499
Test name
Test status
Simulation time 46949238410 ps
CPU time 16.25 seconds
Started Jul 20 06:07:31 PM PDT 24
Finished Jul 20 06:07:48 PM PDT 24
Peak memory 199628 kb
Host smart-5441a8a2-05cb-4aa4-b6e3-b8b920044501
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144771763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3144771763
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.4073309770
Short name T247
Test name
Test status
Simulation time 81292558948 ps
CPU time 271.51 seconds
Started Jul 20 06:07:33 PM PDT 24
Finished Jul 20 06:12:05 PM PDT 24
Peak memory 200072 kb
Host smart-75295f2e-87de-4e5e-a4ff-02d4e62954be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073309770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.4073309770
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2479677510
Short name T617
Test name
Test status
Simulation time 2302721959 ps
CPU time 1.87 seconds
Started Jul 20 06:07:33 PM PDT 24
Finished Jul 20 06:07:35 PM PDT 24
Peak memory 198260 kb
Host smart-26271eb7-5548-4398-a125-8446330b5d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479677510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2479677510
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1009067432
Short name T253
Test name
Test status
Simulation time 273381122208 ps
CPU time 22.51 seconds
Started Jul 20 06:07:31 PM PDT 24
Finished Jul 20 06:07:54 PM PDT 24
Peak memory 200324 kb
Host smart-f86982e5-0a6d-413d-8bd3-8f7a5bf2e2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009067432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1009067432
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1102755615
Short name T812
Test name
Test status
Simulation time 14157386649 ps
CPU time 679.57 seconds
Started Jul 20 06:07:31 PM PDT 24
Finished Jul 20 06:18:51 PM PDT 24
Peak memory 200208 kb
Host smart-dcfb4e8e-2837-4df6-ad13-042baaa38038
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1102755615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1102755615
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1627059622
Short name T19
Test name
Test status
Simulation time 6797504208 ps
CPU time 36.08 seconds
Started Jul 20 06:07:32 PM PDT 24
Finished Jul 20 06:08:09 PM PDT 24
Peak memory 200144 kb
Host smart-c484d372-74ec-48e0-9cca-8298c6aca5bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627059622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1627059622
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.52376338
Short name T345
Test name
Test status
Simulation time 19938597202 ps
CPU time 15.6 seconds
Started Jul 20 06:07:33 PM PDT 24
Finished Jul 20 06:07:49 PM PDT 24
Peak memory 200104 kb
Host smart-416101b8-2586-49f7-9dc4-542d6b4c26cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52376338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.52376338
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.4012426011
Short name T1097
Test name
Test status
Simulation time 35290966133 ps
CPU time 21.02 seconds
Started Jul 20 06:07:31 PM PDT 24
Finished Jul 20 06:07:53 PM PDT 24
Peak memory 196080 kb
Host smart-00090c1f-c17f-4ea7-b383-6e5fa282776d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012426011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.4012426011
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.8005895
Short name T517
Test name
Test status
Simulation time 463761552 ps
CPU time 1.04 seconds
Started Jul 20 06:07:26 PM PDT 24
Finished Jul 20 06:07:28 PM PDT 24
Peak memory 198524 kb
Host smart-3cb26cb2-b1c9-42d7-bf75-486fd56d72b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8005895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.8005895
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1538947882
Short name T8
Test name
Test status
Simulation time 118025997575 ps
CPU time 46.54 seconds
Started Jul 20 06:07:32 PM PDT 24
Finished Jul 20 06:08:20 PM PDT 24
Peak memory 200272 kb
Host smart-60180704-4fe4-4106-bf03-9ca295edab46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538947882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1538947882
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.825361031
Short name T696
Test name
Test status
Simulation time 102411140547 ps
CPU time 990.11 seconds
Started Jul 20 06:07:34 PM PDT 24
Finished Jul 20 06:24:05 PM PDT 24
Peak memory 216712 kb
Host smart-94f8012d-0e05-41d0-be1c-e712ad1cef83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825361031 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.825361031
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1357819599
Short name T427
Test name
Test status
Simulation time 7572298192 ps
CPU time 14.47 seconds
Started Jul 20 06:07:33 PM PDT 24
Finished Jul 20 06:07:48 PM PDT 24
Peak memory 200180 kb
Host smart-1ce111e6-4c27-4cb1-9fd1-1359f5aaeb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357819599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1357819599
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2583171711
Short name T791
Test name
Test status
Simulation time 22293713885 ps
CPU time 40.96 seconds
Started Jul 20 06:07:24 PM PDT 24
Finished Jul 20 06:08:06 PM PDT 24
Peak memory 200088 kb
Host smart-f4468fe2-565d-4f7b-83ba-0efa28e8ced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583171711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2583171711
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3959995009
Short name T534
Test name
Test status
Simulation time 31044592 ps
CPU time 0.54 seconds
Started Jul 20 06:07:46 PM PDT 24
Finished Jul 20 06:07:47 PM PDT 24
Peak memory 195868 kb
Host smart-067bf596-f6c2-4672-b8da-57272b3851a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959995009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3959995009
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3003912135
Short name T729
Test name
Test status
Simulation time 123243425911 ps
CPU time 72.15 seconds
Started Jul 20 06:07:34 PM PDT 24
Finished Jul 20 06:08:46 PM PDT 24
Peak memory 200192 kb
Host smart-282ccd5f-0611-428f-b3d8-629a45fc50a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003912135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3003912135
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1580384876
Short name T886
Test name
Test status
Simulation time 32455213129 ps
CPU time 13.15 seconds
Started Jul 20 06:07:31 PM PDT 24
Finished Jul 20 06:07:45 PM PDT 24
Peak memory 198144 kb
Host smart-cc915402-d009-4d29-a3f7-bb852f957981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580384876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1580384876
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.384017995
Short name T406
Test name
Test status
Simulation time 9487013220 ps
CPU time 14.1 seconds
Started Jul 20 06:07:46 PM PDT 24
Finished Jul 20 06:08:00 PM PDT 24
Peak memory 199104 kb
Host smart-5cb6f68b-f2e6-449e-a8a4-a56e11788ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384017995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.384017995
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3328348991
Short name T1014
Test name
Test status
Simulation time 26698838897 ps
CPU time 38.5 seconds
Started Jul 20 06:07:43 PM PDT 24
Finished Jul 20 06:08:22 PM PDT 24
Peak memory 197936 kb
Host smart-a93cd7da-7c67-4f92-86d0-2ab4b5eb9472
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328348991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3328348991
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.195469617
Short name T376
Test name
Test status
Simulation time 77547354252 ps
CPU time 557.14 seconds
Started Jul 20 06:07:47 PM PDT 24
Finished Jul 20 06:17:05 PM PDT 24
Peak memory 200108 kb
Host smart-af3befce-91a2-4577-8e22-b226214778c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195469617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.195469617
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2459645615
Short name T1060
Test name
Test status
Simulation time 3315410776 ps
CPU time 5.53 seconds
Started Jul 20 06:07:44 PM PDT 24
Finished Jul 20 06:07:50 PM PDT 24
Peak memory 199260 kb
Host smart-a41c42f0-c484-4812-93a1-f30704b76e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459645615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2459645615
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1539768596
Short name T99
Test name
Test status
Simulation time 126854992343 ps
CPU time 52.62 seconds
Started Jul 20 06:07:42 PM PDT 24
Finished Jul 20 06:08:35 PM PDT 24
Peak memory 208328 kb
Host smart-e614aabc-111b-4d25-b48b-c0d4baf66a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539768596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1539768596
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1063981418
Short name T512
Test name
Test status
Simulation time 14573419143 ps
CPU time 183.19 seconds
Started Jul 20 06:07:41 PM PDT 24
Finished Jul 20 06:10:45 PM PDT 24
Peak memory 200104 kb
Host smart-8ded3d55-4a81-40c6-964d-38bf632ae527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063981418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1063981418
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.227287876
Short name T653
Test name
Test status
Simulation time 1279940518 ps
CPU time 1.56 seconds
Started Jul 20 06:07:45 PM PDT 24
Finished Jul 20 06:07:47 PM PDT 24
Peak memory 197008 kb
Host smart-0d0e8bdd-afa2-44f3-bb44-283413e0aa6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227287876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.227287876
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2387840503
Short name T1137
Test name
Test status
Simulation time 98964808671 ps
CPU time 25.37 seconds
Started Jul 20 06:07:44 PM PDT 24
Finished Jul 20 06:08:10 PM PDT 24
Peak memory 199532 kb
Host smart-092ca3ef-6de1-4dc5-a1fe-7bf721594a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387840503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2387840503
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2801216728
Short name T325
Test name
Test status
Simulation time 5606612826 ps
CPU time 4.86 seconds
Started Jul 20 06:07:45 PM PDT 24
Finished Jul 20 06:07:50 PM PDT 24
Peak memory 196376 kb
Host smart-e90298f4-2964-421e-8f4f-94a44419309b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801216728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2801216728
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.480871659
Short name T595
Test name
Test status
Simulation time 6081742108 ps
CPU time 19.93 seconds
Started Jul 20 06:07:32 PM PDT 24
Finished Jul 20 06:07:52 PM PDT 24
Peak memory 200152 kb
Host smart-78a7356b-0b80-40ad-b4cf-26faa4d20544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480871659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.480871659
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2325112359
Short name T110
Test name
Test status
Simulation time 315503484022 ps
CPU time 643.24 seconds
Started Jul 20 06:07:45 PM PDT 24
Finished Jul 20 06:18:29 PM PDT 24
Peak memory 208448 kb
Host smart-2506921d-3b8b-49b3-86fa-cf8c244a0554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325112359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2325112359
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1014248820
Short name T357
Test name
Test status
Simulation time 5328358933 ps
CPU time 1.63 seconds
Started Jul 20 06:07:46 PM PDT 24
Finished Jul 20 06:07:48 PM PDT 24
Peak memory 199744 kb
Host smart-c170edcb-f06f-40e8-90d6-4dab401930df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014248820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1014248820
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.940445426
Short name T707
Test name
Test status
Simulation time 32437521566 ps
CPU time 21.74 seconds
Started Jul 20 06:07:32 PM PDT 24
Finished Jul 20 06:07:55 PM PDT 24
Peak memory 200164 kb
Host smart-bc7aae15-6780-4b89-8640-893794d5f43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940445426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.940445426
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3866842340
Short name T21
Test name
Test status
Simulation time 16193769 ps
CPU time 0.58 seconds
Started Jul 20 06:07:53 PM PDT 24
Finished Jul 20 06:07:54 PM PDT 24
Peak memory 195568 kb
Host smart-c98cec41-c7e4-4990-941c-fe276c430ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866842340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3866842340
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3519316828
Short name T279
Test name
Test status
Simulation time 167430673623 ps
CPU time 163.91 seconds
Started Jul 20 06:07:57 PM PDT 24
Finished Jul 20 06:10:41 PM PDT 24
Peak memory 200192 kb
Host smart-92084be1-8129-4d7d-9fbb-505af4270ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519316828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3519316828
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2619190857
Short name T114
Test name
Test status
Simulation time 51177533242 ps
CPU time 46.73 seconds
Started Jul 20 06:07:51 PM PDT 24
Finished Jul 20 06:08:38 PM PDT 24
Peak memory 200052 kb
Host smart-213961b7-237b-4a70-9932-32216cb87c91
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619190857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2619190857
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.965667146
Short name T728
Test name
Test status
Simulation time 105463641902 ps
CPU time 266.28 seconds
Started Jul 20 06:07:53 PM PDT 24
Finished Jul 20 06:12:20 PM PDT 24
Peak memory 200136 kb
Host smart-a948fef7-7b7e-4906-aa60-87e3ebca6ca0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965667146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.965667146
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2757793892
Short name T509
Test name
Test status
Simulation time 6387070695 ps
CPU time 5.74 seconds
Started Jul 20 06:07:53 PM PDT 24
Finished Jul 20 06:08:00 PM PDT 24
Peak memory 199560 kb
Host smart-3cafa16b-5719-4d89-b6fc-79a6cb94815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757793892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2757793892
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3538943722
Short name T257
Test name
Test status
Simulation time 129058317486 ps
CPU time 15.84 seconds
Started Jul 20 06:07:53 PM PDT 24
Finished Jul 20 06:08:10 PM PDT 24
Peak memory 199508 kb
Host smart-83b6f73f-e5f1-4080-81ae-a0e0296190e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538943722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3538943722
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.1367818011
Short name T684
Test name
Test status
Simulation time 6939361150 ps
CPU time 326.71 seconds
Started Jul 20 06:07:52 PM PDT 24
Finished Jul 20 06:13:19 PM PDT 24
Peak memory 200100 kb
Host smart-f22761d0-d124-42a6-a252-c51c5d0f847a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1367818011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1367818011
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2182238947
Short name T324
Test name
Test status
Simulation time 2114422501 ps
CPU time 6.09 seconds
Started Jul 20 06:07:53 PM PDT 24
Finished Jul 20 06:08:00 PM PDT 24
Peak memory 198324 kb
Host smart-60e69c7a-2ef1-4ba8-84e5-6bca5ea7020a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2182238947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2182238947
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2367832814
Short name T1053
Test name
Test status
Simulation time 53676704394 ps
CPU time 80.21 seconds
Started Jul 20 06:07:53 PM PDT 24
Finished Jul 20 06:09:14 PM PDT 24
Peak memory 200212 kb
Host smart-37cf5ec9-846c-4e61-a90e-98b28b7609b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367832814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2367832814
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1602549330
Short name T591
Test name
Test status
Simulation time 2940938550 ps
CPU time 1.82 seconds
Started Jul 20 06:07:52 PM PDT 24
Finished Jul 20 06:07:55 PM PDT 24
Peak memory 196248 kb
Host smart-f34f2c1a-e4bf-4649-bd21-37c09669bb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602549330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1602549330
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3895956379
Short name T658
Test name
Test status
Simulation time 526124242 ps
CPU time 1.57 seconds
Started Jul 20 06:07:46 PM PDT 24
Finished Jul 20 06:07:48 PM PDT 24
Peak memory 198584 kb
Host smart-76a54772-c49e-4f88-92f6-7bd6ce24ad41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895956379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3895956379
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3380530735
Short name T727
Test name
Test status
Simulation time 1261416090 ps
CPU time 4.56 seconds
Started Jul 20 06:07:54 PM PDT 24
Finished Jul 20 06:07:59 PM PDT 24
Peak memory 199868 kb
Host smart-dde0afdf-b0f9-439d-80a0-7fbf7e244af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380530735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3380530735
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.805956987
Short name T779
Test name
Test status
Simulation time 43755056955 ps
CPU time 535.15 seconds
Started Jul 20 06:07:52 PM PDT 24
Finished Jul 20 06:16:47 PM PDT 24
Peak memory 216396 kb
Host smart-e089c003-1b7d-4bfb-9ed2-0a887c93292c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805956987 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.805956987
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2654979609
Short name T1140
Test name
Test status
Simulation time 1101003097 ps
CPU time 1.63 seconds
Started Jul 20 06:07:52 PM PDT 24
Finished Jul 20 06:07:55 PM PDT 24
Peak memory 199660 kb
Host smart-4357a6ec-fe58-4e18-b865-5f7533e5ff8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654979609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2654979609
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1634010401
Short name T839
Test name
Test status
Simulation time 46420948414 ps
CPU time 81.44 seconds
Started Jul 20 06:07:43 PM PDT 24
Finished Jul 20 06:09:04 PM PDT 24
Peak memory 200204 kb
Host smart-2984dbac-4206-4f29-a1ad-f204213bacb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634010401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1634010401
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2209817855
Short name T1076
Test name
Test status
Simulation time 12136710 ps
CPU time 0.56 seconds
Started Jul 20 06:08:07 PM PDT 24
Finished Jul 20 06:08:08 PM PDT 24
Peak memory 195240 kb
Host smart-334297c4-55e3-4de4-8e24-722053692d8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209817855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2209817855
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.729131990
Short name T583
Test name
Test status
Simulation time 111679781165 ps
CPU time 395.85 seconds
Started Jul 20 06:07:53 PM PDT 24
Finished Jul 20 06:14:30 PM PDT 24
Peak memory 200040 kb
Host smart-95f44951-db60-4b12-b148-54b2e4afecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729131990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.729131990
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.459666804
Short name T160
Test name
Test status
Simulation time 124391979126 ps
CPU time 95.99 seconds
Started Jul 20 06:07:53 PM PDT 24
Finished Jul 20 06:09:29 PM PDT 24
Peak memory 200148 kb
Host smart-020b87c4-7fbe-4350-8900-c0a4d3bbea53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459666804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.459666804
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.20703126
Short name T702
Test name
Test status
Simulation time 40431937321 ps
CPU time 58.86 seconds
Started Jul 20 06:07:54 PM PDT 24
Finished Jul 20 06:08:54 PM PDT 24
Peak memory 199920 kb
Host smart-a7d8cd0f-f953-4cbd-ab52-9ba721bb74f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20703126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.20703126
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.4176444747
Short name T526
Test name
Test status
Simulation time 13241287840 ps
CPU time 16.81 seconds
Started Jul 20 06:07:53 PM PDT 24
Finished Jul 20 06:08:11 PM PDT 24
Peak memory 198032 kb
Host smart-da32fe79-df79-41f6-ac36-ea1aa75257b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176444747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.4176444747
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1646812793
Short name T462
Test name
Test status
Simulation time 93463518767 ps
CPU time 799.33 seconds
Started Jul 20 06:07:58 PM PDT 24
Finished Jul 20 06:21:18 PM PDT 24
Peak memory 200068 kb
Host smart-92a3a0f3-6c7c-4b70-8afb-bfe0c4fc04a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646812793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1646812793
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1847585446
Short name T922
Test name
Test status
Simulation time 2223447138 ps
CPU time 5.4 seconds
Started Jul 20 06:08:06 PM PDT 24
Finished Jul 20 06:08:12 PM PDT 24
Peak memory 198880 kb
Host smart-8d6030d4-e5fa-4e10-a592-ed732164729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847585446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1847585446
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3854226286
Short name T527
Test name
Test status
Simulation time 22679563376 ps
CPU time 33.57 seconds
Started Jul 20 06:07:55 PM PDT 24
Finished Jul 20 06:08:29 PM PDT 24
Peak memory 198360 kb
Host smart-4ef5ba8d-2e16-4b90-936b-4bbdefdaf172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854226286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3854226286
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.520523593
Short name T1033
Test name
Test status
Simulation time 17835425144 ps
CPU time 248.96 seconds
Started Jul 20 06:08:07 PM PDT 24
Finished Jul 20 06:12:16 PM PDT 24
Peak memory 200200 kb
Host smart-150aba14-58bd-4abb-b1d9-6eddeb1a3d4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520523593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.520523593
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.898683842
Short name T358
Test name
Test status
Simulation time 1908528920 ps
CPU time 13.04 seconds
Started Jul 20 06:07:52 PM PDT 24
Finished Jul 20 06:08:06 PM PDT 24
Peak memory 198244 kb
Host smart-8c04b574-a5fe-4d8a-803e-a464498da75e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=898683842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.898683842
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2439988695
Short name T1024
Test name
Test status
Simulation time 147963441728 ps
CPU time 72.27 seconds
Started Jul 20 06:08:03 PM PDT 24
Finished Jul 20 06:09:16 PM PDT 24
Peak memory 200168 kb
Host smart-d06b108e-addb-401b-96b0-ea53017781c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439988695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2439988695
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3927890336
Short name T896
Test name
Test status
Simulation time 36812843574 ps
CPU time 11.5 seconds
Started Jul 20 06:08:01 PM PDT 24
Finished Jul 20 06:08:14 PM PDT 24
Peak memory 196304 kb
Host smart-753214cd-cedb-4a98-bd97-ab488f0a6e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927890336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3927890336
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3997376897
Short name T359
Test name
Test status
Simulation time 671283531 ps
CPU time 2.77 seconds
Started Jul 20 06:07:50 PM PDT 24
Finished Jul 20 06:07:53 PM PDT 24
Peak memory 198556 kb
Host smart-2bffbf0a-bbfa-4f20-a95a-d0d8b6066938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997376897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3997376897
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2079340964
Short name T775
Test name
Test status
Simulation time 89182455 ps
CPU time 0.7 seconds
Started Jul 20 06:08:07 PM PDT 24
Finished Jul 20 06:08:08 PM PDT 24
Peak memory 196228 kb
Host smart-b6f0104c-575c-425f-b2a3-b7112986d2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079340964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2079340964
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3802013727
Short name T314
Test name
Test status
Simulation time 68862631185 ps
CPU time 191.85 seconds
Started Jul 20 06:08:02 PM PDT 24
Finished Jul 20 06:11:14 PM PDT 24
Peak memory 216860 kb
Host smart-ef0fcc40-dfbe-4f5f-9cb8-e8e5240c0910
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802013727 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3802013727
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.841230404
Short name T800
Test name
Test status
Simulation time 3855673235 ps
CPU time 2.02 seconds
Started Jul 20 06:08:02 PM PDT 24
Finished Jul 20 06:08:05 PM PDT 24
Peak memory 200120 kb
Host smart-002a0c37-dd43-43c5-9f0f-4a963aa2c9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841230404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.841230404
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1293845406
Short name T409
Test name
Test status
Simulation time 10066256680 ps
CPU time 14.35 seconds
Started Jul 20 06:07:51 PM PDT 24
Finished Jul 20 06:08:06 PM PDT 24
Peak memory 200108 kb
Host smart-e84ae94d-3788-4230-8b79-a26083b60c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293845406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1293845406
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.4217979998
Short name T431
Test name
Test status
Simulation time 123925571 ps
CPU time 0.58 seconds
Started Jul 20 06:03:08 PM PDT 24
Finished Jul 20 06:03:09 PM PDT 24
Peak memory 195568 kb
Host smart-23efb2d8-3a3a-4e7d-b2bb-d54ae6776211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217979998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.4217979998
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3424257437
Short name T317
Test name
Test status
Simulation time 315070395992 ps
CPU time 783.84 seconds
Started Jul 20 06:02:56 PM PDT 24
Finished Jul 20 06:16:00 PM PDT 24
Peak memory 200124 kb
Host smart-9e36509c-d307-4d1f-bc1c-f643ba811c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424257437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3424257437
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1698982385
Short name T1094
Test name
Test status
Simulation time 149702721207 ps
CPU time 52.11 seconds
Started Jul 20 06:02:53 PM PDT 24
Finished Jul 20 06:03:46 PM PDT 24
Peak memory 199884 kb
Host smart-45af8d5e-2a85-4868-a206-dbb51d6ac9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698982385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1698982385
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1909356134
Short name T558
Test name
Test status
Simulation time 21096082910 ps
CPU time 36.65 seconds
Started Jul 20 06:02:57 PM PDT 24
Finished Jul 20 06:03:34 PM PDT 24
Peak memory 200180 kb
Host smart-77a55d73-567a-46cd-b217-2e0fd966f71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909356134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1909356134
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1381218140
Short name T435
Test name
Test status
Simulation time 22847756393 ps
CPU time 25.02 seconds
Started Jul 20 06:02:53 PM PDT 24
Finished Jul 20 06:03:18 PM PDT 24
Peak memory 197752 kb
Host smart-34b08c08-7997-4533-8a5d-203d833917c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381218140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1381218140
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2467716524
Short name T5
Test name
Test status
Simulation time 70208732118 ps
CPU time 224.45 seconds
Started Jul 20 06:03:06 PM PDT 24
Finished Jul 20 06:06:51 PM PDT 24
Peak memory 200172 kb
Host smart-dfb1113e-701e-4da7-aaf7-1ccf7eb19551
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467716524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2467716524
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.906265367
Short name T748
Test name
Test status
Simulation time 94561930 ps
CPU time 0.73 seconds
Started Jul 20 06:02:56 PM PDT 24
Finished Jul 20 06:02:57 PM PDT 24
Peak memory 196164 kb
Host smart-371b2341-0af4-48af-890c-2ae366bd09e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906265367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.906265367
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3973433535
Short name T255
Test name
Test status
Simulation time 95970850521 ps
CPU time 81.03 seconds
Started Jul 20 06:02:56 PM PDT 24
Finished Jul 20 06:04:18 PM PDT 24
Peak memory 208332 kb
Host smart-668546b0-77ba-426b-b8ff-a85349939802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973433535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3973433535
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3182724774
Short name T510
Test name
Test status
Simulation time 15639183078 ps
CPU time 76.38 seconds
Started Jul 20 06:03:08 PM PDT 24
Finished Jul 20 06:04:25 PM PDT 24
Peak memory 200172 kb
Host smart-60dfa2d6-9d85-4f12-9f94-bedd2e0ded59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3182724774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3182724774
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2584024666
Short name T336
Test name
Test status
Simulation time 7410880627 ps
CPU time 6.84 seconds
Started Jul 20 06:02:56 PM PDT 24
Finished Jul 20 06:03:04 PM PDT 24
Peak memory 199448 kb
Host smart-e7bbfef2-ffc6-4dcb-b1c4-0c930f47fc23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2584024666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2584024666
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3595073107
Short name T474
Test name
Test status
Simulation time 97075664269 ps
CPU time 125.66 seconds
Started Jul 20 06:02:56 PM PDT 24
Finished Jul 20 06:05:02 PM PDT 24
Peak memory 200056 kb
Host smart-5c893fd1-c93e-423b-99c8-be443f15d4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595073107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3595073107
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1960640995
Short name T287
Test name
Test status
Simulation time 2756500546 ps
CPU time 1.74 seconds
Started Jul 20 06:02:56 PM PDT 24
Finished Jul 20 06:02:58 PM PDT 24
Peak memory 196652 kb
Host smart-b0acb81a-f37c-4a6d-ad54-3966173ac47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960640995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1960640995
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.727540168
Short name T11
Test name
Test status
Simulation time 5891752883 ps
CPU time 10.43 seconds
Started Jul 20 06:02:55 PM PDT 24
Finished Jul 20 06:03:06 PM PDT 24
Peak memory 199972 kb
Host smart-8ba8c42c-34d2-4ff9-8426-e42c1e387a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727540168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.727540168
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.191852243
Short name T718
Test name
Test status
Simulation time 286832342597 ps
CPU time 224.39 seconds
Started Jul 20 06:03:08 PM PDT 24
Finished Jul 20 06:06:53 PM PDT 24
Peak memory 211048 kb
Host smart-6aebf466-eca0-42cc-af1b-c621d411ec9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191852243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.191852243
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.622778201
Short name T732
Test name
Test status
Simulation time 246218027458 ps
CPU time 363.61 seconds
Started Jul 20 06:03:04 PM PDT 24
Finished Jul 20 06:09:08 PM PDT 24
Peak memory 216728 kb
Host smart-ac77027c-089d-4a30-994e-95a948be636b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622778201 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.622778201
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1981507447
Short name T866
Test name
Test status
Simulation time 1193139417 ps
CPU time 1.56 seconds
Started Jul 20 06:02:54 PM PDT 24
Finished Jul 20 06:02:56 PM PDT 24
Peak memory 198648 kb
Host smart-fa5948e7-4c69-4caf-bfb3-872758ea344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981507447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1981507447
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2823033435
Short name T1012
Test name
Test status
Simulation time 127386148078 ps
CPU time 214.49 seconds
Started Jul 20 06:02:56 PM PDT 24
Finished Jul 20 06:06:32 PM PDT 24
Peak memory 200184 kb
Host smart-460a2772-5d0b-4d7e-a3c6-c427f13f3e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823033435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2823033435
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.350172132
Short name T1111
Test name
Test status
Simulation time 49505560881 ps
CPU time 42.19 seconds
Started Jul 20 06:08:00 PM PDT 24
Finished Jul 20 06:08:43 PM PDT 24
Peak memory 200116 kb
Host smart-55bdc48d-472f-4b84-b6b8-ac2986b6a191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350172132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.350172132
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3730358527
Short name T1001
Test name
Test status
Simulation time 71345733486 ps
CPU time 762.92 seconds
Started Jul 20 06:07:59 PM PDT 24
Finished Jul 20 06:20:42 PM PDT 24
Peak memory 216644 kb
Host smart-aea091c7-95e5-489e-a03c-8b64cff946a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730358527 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3730358527
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3842829582
Short name T1151
Test name
Test status
Simulation time 165274247094 ps
CPU time 365.76 seconds
Started Jul 20 06:07:59 PM PDT 24
Finished Jul 20 06:14:06 PM PDT 24
Peak memory 200140 kb
Host smart-bf361e3d-a664-4d7e-ae84-aacabc13ef01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842829582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3842829582
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.435344397
Short name T860
Test name
Test status
Simulation time 348111166959 ps
CPU time 1279.72 seconds
Started Jul 20 06:07:59 PM PDT 24
Finished Jul 20 06:29:20 PM PDT 24
Peak memory 226248 kb
Host smart-0512623d-fd9a-4e97-a939-079f529a2a6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435344397 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.435344397
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1924947831
Short name T514
Test name
Test status
Simulation time 58438730205 ps
CPU time 99.57 seconds
Started Jul 20 06:08:01 PM PDT 24
Finished Jul 20 06:09:41 PM PDT 24
Peak memory 200192 kb
Host smart-0ab0d9d3-e213-49d0-a513-65af16574357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924947831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1924947831
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2524946755
Short name T991
Test name
Test status
Simulation time 39400871460 ps
CPU time 461.85 seconds
Started Jul 20 06:07:58 PM PDT 24
Finished Jul 20 06:15:41 PM PDT 24
Peak memory 216860 kb
Host smart-d2db3a3b-7092-474c-b672-b911c2ce5e1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524946755 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2524946755
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2351671679
Short name T62
Test name
Test status
Simulation time 150314917162 ps
CPU time 1242.76 seconds
Started Jul 20 06:07:58 PM PDT 24
Finished Jul 20 06:28:42 PM PDT 24
Peak memory 230280 kb
Host smart-de2641f8-132d-4687-b0dc-7fb056034c4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351671679 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2351671679
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1054116883
Short name T1105
Test name
Test status
Simulation time 37040974304 ps
CPU time 17.6 seconds
Started Jul 20 06:08:07 PM PDT 24
Finished Jul 20 06:08:25 PM PDT 24
Peak memory 200196 kb
Host smart-c02b9bf6-e5ae-468a-9d05-0d4c38c5430e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054116883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1054116883
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.71977506
Short name T49
Test name
Test status
Simulation time 50913959988 ps
CPU time 1075.6 seconds
Started Jul 20 06:08:04 PM PDT 24
Finished Jul 20 06:26:00 PM PDT 24
Peak memory 225048 kb
Host smart-d1b55a4b-b404-4a38-b5a7-b20ba4fcc509
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71977506 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.71977506
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2243364139
Short name T260
Test name
Test status
Simulation time 74683041915 ps
CPU time 230.42 seconds
Started Jul 20 06:08:01 PM PDT 24
Finished Jul 20 06:11:52 PM PDT 24
Peak memory 200192 kb
Host smart-148190f1-20ea-4bf1-8dc0-d723078a0212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243364139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2243364139
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2891265142
Short name T958
Test name
Test status
Simulation time 40806638268 ps
CPU time 297.36 seconds
Started Jul 20 06:08:03 PM PDT 24
Finished Jul 20 06:13:01 PM PDT 24
Peak memory 215464 kb
Host smart-cddf2a40-d8f6-4b31-93d6-b1cb5c63211d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891265142 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2891265142
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1836755377
Short name T1129
Test name
Test status
Simulation time 42886444880 ps
CPU time 15.97 seconds
Started Jul 20 06:08:04 PM PDT 24
Finished Jul 20 06:08:21 PM PDT 24
Peak memory 200180 kb
Host smart-15230b89-30a8-40fc-8dcd-1228f20d7c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836755377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1836755377
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2014702847
Short name T104
Test name
Test status
Simulation time 29031095028 ps
CPU time 238.44 seconds
Started Jul 20 06:08:03 PM PDT 24
Finished Jul 20 06:12:02 PM PDT 24
Peak memory 216804 kb
Host smart-4cb15058-c33f-43d1-9212-b93da3912798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014702847 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2014702847
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1533336573
Short name T990
Test name
Test status
Simulation time 132729229734 ps
CPU time 59.01 seconds
Started Jul 20 06:08:07 PM PDT 24
Finished Jul 20 06:09:07 PM PDT 24
Peak memory 200156 kb
Host smart-ca341e63-8240-4ab0-acea-f80623b2c5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533336573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1533336573
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1133471229
Short name T1090
Test name
Test status
Simulation time 28413694821 ps
CPU time 348.98 seconds
Started Jul 20 06:08:10 PM PDT 24
Finished Jul 20 06:14:00 PM PDT 24
Peak memory 214836 kb
Host smart-6ebff3b7-dc75-4ee2-b8d9-909d5d0fcbe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133471229 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1133471229
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.769108200
Short name T695
Test name
Test status
Simulation time 22868314754 ps
CPU time 38.22 seconds
Started Jul 20 06:08:11 PM PDT 24
Finished Jul 20 06:08:50 PM PDT 24
Peak memory 200076 kb
Host smart-cc0293c4-56f8-489f-b64c-423b21b82bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769108200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.769108200
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3844698680
Short name T956
Test name
Test status
Simulation time 148251807330 ps
CPU time 242.16 seconds
Started Jul 20 06:08:09 PM PDT 24
Finished Jul 20 06:12:12 PM PDT 24
Peak memory 215028 kb
Host smart-18d075d1-62fa-42e8-9e04-248c42abe777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844698680 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3844698680
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1098627237
Short name T884
Test name
Test status
Simulation time 39181191937 ps
CPU time 30.36 seconds
Started Jul 20 06:08:09 PM PDT 24
Finished Jul 20 06:08:40 PM PDT 24
Peak memory 200128 kb
Host smart-43d654d0-7dab-45c6-80bb-0dee70009a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098627237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1098627237
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3608430239
Short name T241
Test name
Test status
Simulation time 153292324262 ps
CPU time 686.87 seconds
Started Jul 20 06:08:06 PM PDT 24
Finished Jul 20 06:19:33 PM PDT 24
Peak memory 216716 kb
Host smart-fd246c45-91e0-4456-ad09-b22e8434278a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608430239 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3608430239
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2881438664
Short name T640
Test name
Test status
Simulation time 40566528 ps
CPU time 0.54 seconds
Started Jul 20 06:03:21 PM PDT 24
Finished Jul 20 06:03:22 PM PDT 24
Peak memory 195572 kb
Host smart-1d3839fa-d95a-4c07-aaf9-980f0e5b2fc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881438664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2881438664
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2175386376
Short name T500
Test name
Test status
Simulation time 46943957949 ps
CPU time 22.35 seconds
Started Jul 20 06:03:08 PM PDT 24
Finished Jul 20 06:03:31 PM PDT 24
Peak memory 200172 kb
Host smart-9f13ee94-086d-47f2-aa08-cff33b030c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175386376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2175386376
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3997566666
Short name T1068
Test name
Test status
Simulation time 230506867732 ps
CPU time 33.6 seconds
Started Jul 20 06:03:06 PM PDT 24
Finished Jul 20 06:03:40 PM PDT 24
Peak memory 200124 kb
Host smart-3fdddac2-dfdb-4a5e-b2eb-ab9089c2a0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997566666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3997566666
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1111836863
Short name T766
Test name
Test status
Simulation time 105232816564 ps
CPU time 42.91 seconds
Started Jul 20 06:03:06 PM PDT 24
Finished Jul 20 06:03:50 PM PDT 24
Peak memory 200084 kb
Host smart-9df58295-d485-40ec-8803-ed0c1df9ee29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111836863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1111836863
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1989535119
Short name T1127
Test name
Test status
Simulation time 18572831564 ps
CPU time 7.76 seconds
Started Jul 20 06:03:04 PM PDT 24
Finished Jul 20 06:03:12 PM PDT 24
Peak memory 199648 kb
Host smart-b82c9019-abd7-4eaf-a727-1a66c5486786
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989535119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1989535119
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3522769519
Short name T964
Test name
Test status
Simulation time 177607667538 ps
CPU time 482.63 seconds
Started Jul 20 06:03:19 PM PDT 24
Finished Jul 20 06:11:22 PM PDT 24
Peak memory 200104 kb
Host smart-66180e4d-db86-4d8d-a0bb-5b56fe0d7930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522769519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3522769519
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.476945437
Short name T469
Test name
Test status
Simulation time 8843015255 ps
CPU time 13.42 seconds
Started Jul 20 06:03:18 PM PDT 24
Finished Jul 20 06:03:32 PM PDT 24
Peak memory 198668 kb
Host smart-f03adda7-b6e2-4ed0-8052-9c7de8b2d581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476945437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.476945437
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3462810637
Short name T318
Test name
Test status
Simulation time 157107507482 ps
CPU time 96.36 seconds
Started Jul 20 06:03:08 PM PDT 24
Finished Jul 20 06:04:45 PM PDT 24
Peak memory 208484 kb
Host smart-192bec45-0f47-44cd-9fdd-80b8d800b139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462810637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3462810637
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1005625410
Short name T879
Test name
Test status
Simulation time 26860122424 ps
CPU time 909.22 seconds
Started Jul 20 06:03:17 PM PDT 24
Finished Jul 20 06:18:26 PM PDT 24
Peak memory 200112 kb
Host smart-48223e5a-6ead-48d3-9d98-339b718408f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1005625410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1005625410
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2901965754
Short name T513
Test name
Test status
Simulation time 3286680221 ps
CPU time 26.1 seconds
Started Jul 20 06:03:08 PM PDT 24
Finished Jul 20 06:03:35 PM PDT 24
Peak memory 199124 kb
Host smart-6367300e-e770-4a9e-99e9-d1c1e1dc3c39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901965754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2901965754
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3253936543
Short name T573
Test name
Test status
Simulation time 4775495475 ps
CPU time 2.54 seconds
Started Jul 20 06:03:17 PM PDT 24
Finished Jul 20 06:03:20 PM PDT 24
Peak memory 196532 kb
Host smart-16bdfa5d-95be-4277-a189-2c0199c55d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253936543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3253936543
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3123055105
Short name T309
Test name
Test status
Simulation time 295128638 ps
CPU time 1.04 seconds
Started Jul 20 06:03:08 PM PDT 24
Finished Jul 20 06:03:10 PM PDT 24
Peak memory 199728 kb
Host smart-4b368ced-79da-4126-b73a-4b62d4f764b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123055105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3123055105
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3867410069
Short name T498
Test name
Test status
Simulation time 2428282107 ps
CPU time 2.19 seconds
Started Jul 20 06:03:18 PM PDT 24
Finished Jul 20 06:03:21 PM PDT 24
Peak memory 200140 kb
Host smart-3f06b0a4-ce06-4753-be06-bc89744a7c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867410069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3867410069
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1972012659
Short name T629
Test name
Test status
Simulation time 29152804257 ps
CPU time 59.98 seconds
Started Jul 20 06:03:07 PM PDT 24
Finished Jul 20 06:04:08 PM PDT 24
Peak memory 200176 kb
Host smart-b1e90724-cbcb-4cd4-9509-d90081dd3c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972012659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1972012659
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1803998402
Short name T789
Test name
Test status
Simulation time 19669966335 ps
CPU time 30.57 seconds
Started Jul 20 06:08:14 PM PDT 24
Finished Jul 20 06:08:45 PM PDT 24
Peak memory 200136 kb
Host smart-a084c337-ee29-47a9-897e-ed3cd1038113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803998402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1803998402
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3225265522
Short name T292
Test name
Test status
Simulation time 43800318819 ps
CPU time 459.01 seconds
Started Jul 20 06:08:15 PM PDT 24
Finished Jul 20 06:15:55 PM PDT 24
Peak memory 216600 kb
Host smart-53c92213-2785-43d1-9e5e-7770de9b5946
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225265522 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3225265522
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1615332552
Short name T975
Test name
Test status
Simulation time 33485915849 ps
CPU time 546.73 seconds
Started Jul 20 06:08:09 PM PDT 24
Finished Jul 20 06:17:17 PM PDT 24
Peak memory 215928 kb
Host smart-13da7378-ce2d-4529-8df6-c7b886959c19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615332552 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1615332552
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.306510860
Short name T117
Test name
Test status
Simulation time 203117118233 ps
CPU time 682.1 seconds
Started Jul 20 06:08:07 PM PDT 24
Finished Jul 20 06:19:30 PM PDT 24
Peak memory 216664 kb
Host smart-4147bcca-7f17-42b3-8ff2-ccd4b25ffcc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306510860 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.306510860
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3218030505
Short name T124
Test name
Test status
Simulation time 20193142370 ps
CPU time 33.69 seconds
Started Jul 20 06:08:10 PM PDT 24
Finished Jul 20 06:08:44 PM PDT 24
Peak memory 200192 kb
Host smart-0ef71ec9-30bf-4bfb-ab8d-c53e8e0bd73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218030505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3218030505
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2723141061
Short name T963
Test name
Test status
Simulation time 64351419165 ps
CPU time 245.39 seconds
Started Jul 20 06:08:10 PM PDT 24
Finished Jul 20 06:12:16 PM PDT 24
Peak memory 216708 kb
Host smart-2ccaf894-04d7-4829-b4ed-17382e275c36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723141061 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2723141061
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3116186748
Short name T894
Test name
Test status
Simulation time 88197559647 ps
CPU time 62.37 seconds
Started Jul 20 06:08:12 PM PDT 24
Finished Jul 20 06:09:15 PM PDT 24
Peak memory 200148 kb
Host smart-86a2d79a-6e6e-40aa-aa7f-db30915d0eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116186748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3116186748
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1256240723
Short name T26
Test name
Test status
Simulation time 28771261163 ps
CPU time 345.58 seconds
Started Jul 20 06:08:11 PM PDT 24
Finished Jul 20 06:13:57 PM PDT 24
Peak memory 208508 kb
Host smart-6f6b4c13-f422-49e5-be00-27b0221c1120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256240723 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1256240723
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2033280407
Short name T141
Test name
Test status
Simulation time 230206137766 ps
CPU time 367.19 seconds
Started Jul 20 06:08:11 PM PDT 24
Finished Jul 20 06:14:19 PM PDT 24
Peak memory 210752 kb
Host smart-655282a8-32f1-4aa4-ae5f-0d18041c551c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033280407 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2033280407
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.408583520
Short name T194
Test name
Test status
Simulation time 53531503240 ps
CPU time 16.61 seconds
Started Jul 20 06:08:11 PM PDT 24
Finished Jul 20 06:08:28 PM PDT 24
Peak memory 199468 kb
Host smart-f3e88f6a-c84f-466d-be58-66b44f1a2988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408583520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.408583520
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1728227783
Short name T600
Test name
Test status
Simulation time 51091940981 ps
CPU time 326.74 seconds
Started Jul 20 06:08:10 PM PDT 24
Finished Jul 20 06:13:37 PM PDT 24
Peak memory 208508 kb
Host smart-00d417f3-fea3-444d-99de-d9101776333f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728227783 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1728227783
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.4140462123
Short name T237
Test name
Test status
Simulation time 46710583479 ps
CPU time 76.03 seconds
Started Jul 20 06:08:10 PM PDT 24
Finished Jul 20 06:09:27 PM PDT 24
Peak memory 199992 kb
Host smart-83dab43f-ff42-40ce-a217-b047c61d30a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140462123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.4140462123
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1227537375
Short name T52
Test name
Test status
Simulation time 61301803291 ps
CPU time 576.01 seconds
Started Jul 20 06:08:15 PM PDT 24
Finished Jul 20 06:17:52 PM PDT 24
Peak memory 216840 kb
Host smart-94002c2c-cd80-445c-ac3f-73478de63137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227537375 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1227537375
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3748733072
Short name T1029
Test name
Test status
Simulation time 171164631776 ps
CPU time 189.29 seconds
Started Jul 20 06:08:08 PM PDT 24
Finished Jul 20 06:11:18 PM PDT 24
Peak memory 200020 kb
Host smart-98c26a74-f787-472c-99c0-39ad0e51a031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748733072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3748733072
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3262560355
Short name T73
Test name
Test status
Simulation time 281760797299 ps
CPU time 897.64 seconds
Started Jul 20 06:08:15 PM PDT 24
Finished Jul 20 06:23:14 PM PDT 24
Peak memory 216784 kb
Host smart-5b033a5f-6185-4cc9-8d4c-f0ce6c20f63b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262560355 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3262560355
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1201172111
Short name T1157
Test name
Test status
Simulation time 24787391415 ps
CPU time 10.07 seconds
Started Jul 20 06:08:09 PM PDT 24
Finished Jul 20 06:08:19 PM PDT 24
Peak memory 199988 kb
Host smart-f3d13223-f0a2-451b-9ea5-40d17ca9cf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201172111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1201172111
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.607253600
Short name T874
Test name
Test status
Simulation time 1150660871283 ps
CPU time 1591.61 seconds
Started Jul 20 06:08:11 PM PDT 24
Finished Jul 20 06:34:43 PM PDT 24
Peak memory 229596 kb
Host smart-9876b654-7eb8-425e-b2fa-cff1598fa4f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607253600 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.607253600
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.653241726
Short name T1043
Test name
Test status
Simulation time 41528185 ps
CPU time 0.56 seconds
Started Jul 20 06:03:30 PM PDT 24
Finished Jul 20 06:03:31 PM PDT 24
Peak memory 195868 kb
Host smart-3b42ab22-bdbd-4f83-96a6-7505ba6c9e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653241726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.653241726
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1884999644
Short name T1132
Test name
Test status
Simulation time 163584747366 ps
CPU time 179.16 seconds
Started Jul 20 06:03:21 PM PDT 24
Finished Jul 20 06:06:20 PM PDT 24
Peak memory 200200 kb
Host smart-3c475408-fb53-406b-a7b3-bdfd80839170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884999644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1884999644
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3296823083
Short name T638
Test name
Test status
Simulation time 20295409486 ps
CPU time 35.94 seconds
Started Jul 20 06:03:20 PM PDT 24
Finished Jul 20 06:03:56 PM PDT 24
Peak memory 200144 kb
Host smart-a2b3e253-694f-431d-bb08-813eb693b573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296823083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3296823083
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.242590184
Short name T244
Test name
Test status
Simulation time 126605111052 ps
CPU time 252.75 seconds
Started Jul 20 06:03:19 PM PDT 24
Finished Jul 20 06:07:33 PM PDT 24
Peak memory 200196 kb
Host smart-d5a0d28d-ac48-4bce-bed9-b22fa71bd68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242590184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.242590184
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3669254897
Short name T1011
Test name
Test status
Simulation time 264107743764 ps
CPU time 408.63 seconds
Started Jul 20 06:03:18 PM PDT 24
Finished Jul 20 06:10:08 PM PDT 24
Peak memory 199024 kb
Host smart-f5d295af-8294-4c9f-8de3-374993b720fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669254897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3669254897
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2248487219
Short name T940
Test name
Test status
Simulation time 166108396267 ps
CPU time 1082.45 seconds
Started Jul 20 06:03:30 PM PDT 24
Finished Jul 20 06:21:33 PM PDT 24
Peak memory 200112 kb
Host smart-5d378b72-eb75-4e1a-aabd-839d830443eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2248487219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2248487219
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.760135488
Short name T568
Test name
Test status
Simulation time 3200340877 ps
CPU time 5.37 seconds
Started Jul 20 06:03:17 PM PDT 24
Finished Jul 20 06:03:23 PM PDT 24
Peak memory 197580 kb
Host smart-27ed3e63-11ac-4788-a9c2-8779b354f590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760135488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.760135488
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.464768281
Short name T682
Test name
Test status
Simulation time 1365553995 ps
CPU time 2.66 seconds
Started Jul 20 06:03:20 PM PDT 24
Finished Jul 20 06:03:23 PM PDT 24
Peak memory 200028 kb
Host smart-1281d2bb-12f0-471d-bf3e-087d1e2a2229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464768281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.464768281
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.810405666
Short name T911
Test name
Test status
Simulation time 22719208126 ps
CPU time 1197.14 seconds
Started Jul 20 06:03:17 PM PDT 24
Finished Jul 20 06:23:15 PM PDT 24
Peak memory 200136 kb
Host smart-ab5147e0-e155-4a13-8bf9-c0bb22865f1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810405666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.810405666
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.992260789
Short name T989
Test name
Test status
Simulation time 2130148568 ps
CPU time 3.02 seconds
Started Jul 20 06:03:17 PM PDT 24
Finished Jul 20 06:03:20 PM PDT 24
Peak memory 198304 kb
Host smart-c1df3b84-5364-4044-8586-e21b16c620e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992260789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.992260789
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2901142594
Short name T369
Test name
Test status
Simulation time 26721059320 ps
CPU time 41.27 seconds
Started Jul 20 06:03:19 PM PDT 24
Finished Jul 20 06:04:01 PM PDT 24
Peak memory 199896 kb
Host smart-fc8f2a53-aa51-41cb-9666-80fb964e7ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901142594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2901142594
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3069815572
Short name T34
Test name
Test status
Simulation time 46285151490 ps
CPU time 8.18 seconds
Started Jul 20 06:03:21 PM PDT 24
Finished Jul 20 06:03:30 PM PDT 24
Peak memory 196684 kb
Host smart-9b00ec38-bf19-47e4-b14e-7bfbdc4c5afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069815572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3069815572
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3919235680
Short name T295
Test name
Test status
Simulation time 499614570 ps
CPU time 2.2 seconds
Started Jul 20 06:03:21 PM PDT 24
Finished Jul 20 06:03:24 PM PDT 24
Peak memory 198536 kb
Host smart-a6085e86-2001-4035-a0f1-c8557b2183b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919235680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3919235680
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1626138829
Short name T557
Test name
Test status
Simulation time 61258953274 ps
CPU time 89.98 seconds
Started Jul 20 06:03:31 PM PDT 24
Finished Jul 20 06:05:02 PM PDT 24
Peak memory 200212 kb
Host smart-15e91b1a-b752-44d7-8a7d-dccf009f687c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626138829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1626138829
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3800460059
Short name T300
Test name
Test status
Simulation time 6810085505 ps
CPU time 20.24 seconds
Started Jul 20 06:03:21 PM PDT 24
Finished Jul 20 06:03:42 PM PDT 24
Peak memory 200176 kb
Host smart-e0afb158-e403-48a4-8915-49504e694aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800460059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3800460059
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.766786994
Short name T571
Test name
Test status
Simulation time 35611837535 ps
CPU time 25.65 seconds
Started Jul 20 06:03:20 PM PDT 24
Finished Jul 20 06:03:46 PM PDT 24
Peak memory 200080 kb
Host smart-ebff4d78-7ac7-40f3-9ba8-6d7cbe24c574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766786994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.766786994
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.979208979
Short name T333
Test name
Test status
Simulation time 16805962512 ps
CPU time 13.04 seconds
Started Jul 20 06:08:11 PM PDT 24
Finished Jul 20 06:08:24 PM PDT 24
Peak memory 200100 kb
Host smart-bd343874-c6a3-4cab-91d5-b2460f4d6a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979208979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.979208979
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1298346047
Short name T962
Test name
Test status
Simulation time 509420592885 ps
CPU time 591.51 seconds
Started Jul 20 06:08:09 PM PDT 24
Finished Jul 20 06:18:01 PM PDT 24
Peak memory 214020 kb
Host smart-303cb733-5c8a-4629-86b5-afb78aec6089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298346047 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1298346047
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.581085209
Short name T1048
Test name
Test status
Simulation time 10092252100 ps
CPU time 17.63 seconds
Started Jul 20 06:08:08 PM PDT 24
Finished Jul 20 06:08:26 PM PDT 24
Peak memory 200068 kb
Host smart-096a1007-69fe-443a-8d36-f56437c3499b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581085209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.581085209
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1191547141
Short name T458
Test name
Test status
Simulation time 7561843950 ps
CPU time 16.2 seconds
Started Jul 20 06:08:19 PM PDT 24
Finished Jul 20 06:08:36 PM PDT 24
Peak memory 200180 kb
Host smart-59c4d18d-2327-46a5-8627-a498edf5d54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191547141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1191547141
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3312994097
Short name T981
Test name
Test status
Simulation time 13775999007 ps
CPU time 126.64 seconds
Started Jul 20 06:08:19 PM PDT 24
Finished Jul 20 06:10:26 PM PDT 24
Peak memory 200632 kb
Host smart-fa9c9477-738d-4696-8bc7-6ab733f31978
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312994097 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3312994097
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2997280771
Short name T385
Test name
Test status
Simulation time 9216317140 ps
CPU time 15.72 seconds
Started Jul 20 06:08:16 PM PDT 24
Finished Jul 20 06:08:33 PM PDT 24
Peak memory 200200 kb
Host smart-a3d233b4-4be2-4528-852b-50aceaac59de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997280771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2997280771
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3768485391
Short name T943
Test name
Test status
Simulation time 153791659468 ps
CPU time 493.07 seconds
Started Jul 20 06:08:18 PM PDT 24
Finished Jul 20 06:16:32 PM PDT 24
Peak memory 225040 kb
Host smart-f7484547-1a5d-45fe-8f2d-c7dd989b04a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768485391 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3768485391
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2058110888
Short name T515
Test name
Test status
Simulation time 4414127437 ps
CPU time 9.19 seconds
Started Jul 20 06:08:20 PM PDT 24
Finished Jul 20 06:08:30 PM PDT 24
Peak memory 200128 kb
Host smart-23ae6ec1-88b9-468c-974e-105f0e16602a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058110888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2058110888
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2012828320
Short name T760
Test name
Test status
Simulation time 170282272028 ps
CPU time 67.5 seconds
Started Jul 20 06:08:19 PM PDT 24
Finished Jul 20 06:09:28 PM PDT 24
Peak memory 200192 kb
Host smart-4458ba98-9063-4ed6-87a3-b8be42dc77b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012828320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2012828320
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3359337041
Short name T184
Test name
Test status
Simulation time 80808477499 ps
CPU time 36.05 seconds
Started Jul 20 06:08:20 PM PDT 24
Finished Jul 20 06:08:56 PM PDT 24
Peak memory 199892 kb
Host smart-7d4437a6-b5d2-49ad-a1a5-16e1961521b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359337041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3359337041
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.649940993
Short name T211
Test name
Test status
Simulation time 133404797867 ps
CPU time 106.05 seconds
Started Jul 20 06:08:18 PM PDT 24
Finished Jul 20 06:10:04 PM PDT 24
Peak memory 200172 kb
Host smart-f28f8f1e-2470-422c-bab5-4f3ad6e3c5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649940993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.649940993
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2684375024
Short name T572
Test name
Test status
Simulation time 110108266125 ps
CPU time 239.34 seconds
Started Jul 20 06:08:20 PM PDT 24
Finished Jul 20 06:12:20 PM PDT 24
Peak memory 216712 kb
Host smart-797ebd54-c3f1-4641-98c6-a46eaaa3ebce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684375024 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2684375024
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.612106752
Short name T153
Test name
Test status
Simulation time 111045697845 ps
CPU time 149.15 seconds
Started Jul 20 06:08:20 PM PDT 24
Finished Jul 20 06:10:50 PM PDT 24
Peak memory 200196 kb
Host smart-dd8b53e6-ad81-4329-af6c-bf64040fb75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612106752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.612106752
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2672275055
Short name T1051
Test name
Test status
Simulation time 26551385495 ps
CPU time 181.54 seconds
Started Jul 20 06:08:17 PM PDT 24
Finished Jul 20 06:11:19 PM PDT 24
Peak memory 216732 kb
Host smart-14699dcd-1def-47a9-9157-10511353c2bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672275055 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2672275055
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1383360845
Short name T264
Test name
Test status
Simulation time 9144352210 ps
CPU time 17.94 seconds
Started Jul 20 06:08:20 PM PDT 24
Finished Jul 20 06:08:39 PM PDT 24
Peak memory 200180 kb
Host smart-7a6cf6c1-5ddf-4dc2-93db-ed5c9f09e499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383360845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1383360845
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.4118425076
Short name T780
Test name
Test status
Simulation time 59748030665 ps
CPU time 447.77 seconds
Started Jul 20 06:08:20 PM PDT 24
Finished Jul 20 06:15:49 PM PDT 24
Peak memory 216780 kb
Host smart-85fd3231-c3da-4847-b7f7-09240a8fec40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118425076 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.4118425076
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1749780294
Short name T353
Test name
Test status
Simulation time 10806092 ps
CPU time 0.53 seconds
Started Jul 20 06:03:29 PM PDT 24
Finished Jul 20 06:03:30 PM PDT 24
Peak memory 194472 kb
Host smart-0e053dc1-c29b-4fa1-9809-032d027d5703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749780294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1749780294
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3999547303
Short name T590
Test name
Test status
Simulation time 158434208956 ps
CPU time 305.7 seconds
Started Jul 20 06:03:28 PM PDT 24
Finished Jul 20 06:08:35 PM PDT 24
Peak memory 200100 kb
Host smart-30b7e734-a7ed-4e11-9faa-cf054afdc919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999547303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3999547303
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1290125592
Short name T632
Test name
Test status
Simulation time 23783750852 ps
CPU time 38.61 seconds
Started Jul 20 06:03:30 PM PDT 24
Finished Jul 20 06:04:09 PM PDT 24
Peak memory 200132 kb
Host smart-e2c90fd9-fc17-4924-81bf-8ce26ac4dc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290125592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1290125592
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.145066144
Short name T757
Test name
Test status
Simulation time 105823090144 ps
CPU time 175.93 seconds
Started Jul 20 06:03:30 PM PDT 24
Finished Jul 20 06:06:26 PM PDT 24
Peak memory 200136 kb
Host smart-7b329fb5-b820-4bf1-9300-9d8f46094241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145066144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.145066144
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2406278266
Short name T17
Test name
Test status
Simulation time 19917387471 ps
CPU time 26.78 seconds
Started Jul 20 06:03:29 PM PDT 24
Finished Jul 20 06:03:56 PM PDT 24
Peak memory 198316 kb
Host smart-45dc59c0-c707-4962-a0df-18e18b822fe3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406278266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2406278266
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2393696466
Short name T630
Test name
Test status
Simulation time 102060942656 ps
CPU time 597.23 seconds
Started Jul 20 06:03:27 PM PDT 24
Finished Jul 20 06:13:25 PM PDT 24
Peak memory 200136 kb
Host smart-8607f58e-84fe-400c-a866-2cadc803224a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393696466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2393696466
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1374853569
Short name T394
Test name
Test status
Simulation time 3597050761 ps
CPU time 3.1 seconds
Started Jul 20 06:03:33 PM PDT 24
Finished Jul 20 06:03:36 PM PDT 24
Peak memory 197852 kb
Host smart-ce740d1d-e902-459e-ad7d-147fad4be36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374853569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1374853569
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3500608155
Short name T664
Test name
Test status
Simulation time 28925415534 ps
CPU time 25.29 seconds
Started Jul 20 06:03:28 PM PDT 24
Finished Jul 20 06:03:54 PM PDT 24
Peak memory 199156 kb
Host smart-5d02092b-d558-4a6b-ba22-f2c11675b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500608155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3500608155
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2686813984
Short name T853
Test name
Test status
Simulation time 15691773085 ps
CPU time 394.83 seconds
Started Jul 20 06:03:28 PM PDT 24
Finished Jul 20 06:10:03 PM PDT 24
Peak memory 200036 kb
Host smart-0e1dd518-4d03-420c-88d7-dc5793502e23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2686813984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2686813984
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.836883676
Short name T698
Test name
Test status
Simulation time 3669856592 ps
CPU time 24.66 seconds
Started Jul 20 06:03:26 PM PDT 24
Finished Jul 20 06:03:52 PM PDT 24
Peak memory 198032 kb
Host smart-335c248b-2c75-4ccc-8907-1c108648ebf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836883676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.836883676
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2099532193
Short name T840
Test name
Test status
Simulation time 27493591924 ps
CPU time 50.17 seconds
Started Jul 20 06:03:29 PM PDT 24
Finished Jul 20 06:04:20 PM PDT 24
Peak memory 200200 kb
Host smart-d4e6a535-e4f9-4677-9afa-78df690a2451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099532193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2099532193
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1473842154
Short name T581
Test name
Test status
Simulation time 4712099541 ps
CPU time 1.96 seconds
Started Jul 20 06:03:30 PM PDT 24
Finished Jul 20 06:03:33 PM PDT 24
Peak memory 197028 kb
Host smart-ef2d3615-92d9-4da6-9b49-d9f2218ddcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473842154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1473842154
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.640938726
Short name T382
Test name
Test status
Simulation time 646312639 ps
CPU time 2.94 seconds
Started Jul 20 06:03:29 PM PDT 24
Finished Jul 20 06:03:32 PM PDT 24
Peak memory 199992 kb
Host smart-c1582b19-7ed0-404b-8140-3157b91935d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640938726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.640938726
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2033948160
Short name T528
Test name
Test status
Simulation time 96241544541 ps
CPU time 88.25 seconds
Started Jul 20 06:03:29 PM PDT 24
Finished Jul 20 06:04:58 PM PDT 24
Peak memory 200396 kb
Host smart-d5fea1fa-0523-42d8-9a7a-a87f952ee2d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033948160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2033948160
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3160469620
Short name T179
Test name
Test status
Simulation time 197800524839 ps
CPU time 605.75 seconds
Started Jul 20 06:03:28 PM PDT 24
Finished Jul 20 06:13:35 PM PDT 24
Peak memory 216684 kb
Host smart-f6974c41-ae40-4ed9-8a18-1e94a9ba7a64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160469620 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3160469620
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1748964246
Short name T467
Test name
Test status
Simulation time 8228120691 ps
CPU time 8.62 seconds
Started Jul 20 06:03:33 PM PDT 24
Finished Jul 20 06:03:42 PM PDT 24
Peak memory 199884 kb
Host smart-86838990-4e89-4b01-a858-1addeed94424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748964246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1748964246
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.11039548
Short name T1015
Test name
Test status
Simulation time 29078867428 ps
CPU time 45.1 seconds
Started Jul 20 06:03:28 PM PDT 24
Finished Jul 20 06:04:14 PM PDT 24
Peak memory 200100 kb
Host smart-71837f49-3a68-4799-a945-b4e85cb1f12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11039548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.11039548
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1428851914
Short name T1
Test name
Test status
Simulation time 19979788790 ps
CPU time 31.18 seconds
Started Jul 20 06:08:21 PM PDT 24
Finished Jul 20 06:08:52 PM PDT 24
Peak memory 200120 kb
Host smart-cbbc0b91-71b1-4b26-a048-32e3572fd23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428851914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1428851914
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3940119726
Short name T105
Test name
Test status
Simulation time 15852280455 ps
CPU time 185.59 seconds
Started Jul 20 06:08:19 PM PDT 24
Finished Jul 20 06:11:26 PM PDT 24
Peak memory 216164 kb
Host smart-908ae7d7-3ff1-495d-877d-23f37b7b68dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940119726 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3940119726
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3288297587
Short name T40
Test name
Test status
Simulation time 33256754947 ps
CPU time 14.07 seconds
Started Jul 20 06:08:16 PM PDT 24
Finished Jul 20 06:08:30 PM PDT 24
Peak memory 200120 kb
Host smart-fb59c48d-329f-4f21-9772-e3a348ec0750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288297587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3288297587
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3797995314
Short name T72
Test name
Test status
Simulation time 377819383911 ps
CPU time 850.94 seconds
Started Jul 20 06:08:21 PM PDT 24
Finished Jul 20 06:22:33 PM PDT 24
Peak memory 225056 kb
Host smart-26fe4761-f452-42f9-9989-f1f65843c332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797995314 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3797995314
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.4036260684
Short name T817
Test name
Test status
Simulation time 77288015340 ps
CPU time 62.09 seconds
Started Jul 20 06:08:17 PM PDT 24
Finished Jul 20 06:09:19 PM PDT 24
Peak memory 199764 kb
Host smart-96d347f5-c8a3-4d4d-81fa-f2836d78046e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036260684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.4036260684
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3937347851
Short name T201
Test name
Test status
Simulation time 107216696487 ps
CPU time 903.3 seconds
Started Jul 20 06:08:20 PM PDT 24
Finished Jul 20 06:23:24 PM PDT 24
Peak memory 224972 kb
Host smart-41a26822-e848-4baa-b222-1fd1a8579f32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937347851 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3937347851
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3125037839
Short name T725
Test name
Test status
Simulation time 209414110190 ps
CPU time 150.97 seconds
Started Jul 20 06:08:19 PM PDT 24
Finished Jul 20 06:10:50 PM PDT 24
Peak memory 200156 kb
Host smart-0a9ef9a2-d799-446f-925b-cf7b02b03614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125037839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3125037839
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1411221406
Short name T505
Test name
Test status
Simulation time 581501088323 ps
CPU time 575.74 seconds
Started Jul 20 06:08:19 PM PDT 24
Finished Jul 20 06:17:56 PM PDT 24
Peak memory 216864 kb
Host smart-a5671929-cb25-4e77-b8f5-7d34a69db030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411221406 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1411221406
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3554739308
Short name T603
Test name
Test status
Simulation time 8391669991 ps
CPU time 14.04 seconds
Started Jul 20 06:08:25 PM PDT 24
Finished Jul 20 06:08:39 PM PDT 24
Peak memory 200208 kb
Host smart-dd6f425c-a412-4931-b227-af4e3622684d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554739308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3554739308
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3999661587
Short name T197
Test name
Test status
Simulation time 120126059653 ps
CPU time 1439.87 seconds
Started Jul 20 06:08:28 PM PDT 24
Finished Jul 20 06:32:29 PM PDT 24
Peak memory 216724 kb
Host smart-09f5734c-8d44-4f7e-aefc-deb0ccf157a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999661587 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3999661587
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.594952958
Short name T787
Test name
Test status
Simulation time 88381246362 ps
CPU time 15.81 seconds
Started Jul 20 06:08:28 PM PDT 24
Finished Jul 20 06:08:44 PM PDT 24
Peak memory 200184 kb
Host smart-02c42061-5630-4cb1-9c8a-eebd22cde9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594952958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.594952958
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3675999949
Short name T131
Test name
Test status
Simulation time 72001236379 ps
CPU time 31.53 seconds
Started Jul 20 06:08:31 PM PDT 24
Finished Jul 20 06:09:03 PM PDT 24
Peak memory 200048 kb
Host smart-08544648-7dcc-4ab2-9af9-e2c22e5da2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675999949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3675999949
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.544021842
Short name T711
Test name
Test status
Simulation time 52135815186 ps
CPU time 487.35 seconds
Started Jul 20 06:08:26 PM PDT 24
Finished Jul 20 06:16:34 PM PDT 24
Peak memory 216580 kb
Host smart-38514f74-04b4-4a1d-aa1c-51b35fea3e85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544021842 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.544021842
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.30534554
Short name T230
Test name
Test status
Simulation time 77635209523 ps
CPU time 32.94 seconds
Started Jul 20 06:08:29 PM PDT 24
Finished Jul 20 06:09:03 PM PDT 24
Peak memory 200120 kb
Host smart-c8f58192-7f19-4f3c-93c4-c11b46b29fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30534554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.30534554
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.4197849999
Short name T965
Test name
Test status
Simulation time 40137224521 ps
CPU time 34.53 seconds
Started Jul 20 06:08:28 PM PDT 24
Finished Jul 20 06:09:04 PM PDT 24
Peak memory 200192 kb
Host smart-999c1bd3-bcbe-4921-8725-6137eda68cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197849999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.4197849999
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.4270794755
Short name T832
Test name
Test status
Simulation time 29424050354 ps
CPU time 1002.24 seconds
Started Jul 20 06:08:29 PM PDT 24
Finished Jul 20 06:25:12 PM PDT 24
Peak memory 208472 kb
Host smart-45186c97-1e5c-40c6-9956-d34e8f673b69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270794755 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.4270794755
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3732168456
Short name T950
Test name
Test status
Simulation time 31085215 ps
CPU time 0.55 seconds
Started Jul 20 06:03:35 PM PDT 24
Finished Jul 20 06:03:36 PM PDT 24
Peak memory 194552 kb
Host smart-b66a0c2a-3410-425f-8e4b-025216b98758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732168456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3732168456
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3848046349
Short name T764
Test name
Test status
Simulation time 83442233763 ps
CPU time 87.58 seconds
Started Jul 20 06:03:29 PM PDT 24
Finished Jul 20 06:04:58 PM PDT 24
Peak memory 200204 kb
Host smart-fcc9058a-1975-462e-892e-e1b81e21c0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848046349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3848046349
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.949045543
Short name T871
Test name
Test status
Simulation time 86976698214 ps
CPU time 135.21 seconds
Started Jul 20 06:03:30 PM PDT 24
Finished Jul 20 06:05:46 PM PDT 24
Peak memory 200128 kb
Host smart-9eb81a71-ea37-4b70-8731-4a9b9ff7f3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949045543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.949045543
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_intr.2735199779
Short name T539
Test name
Test status
Simulation time 16998871202 ps
CPU time 25.28 seconds
Started Jul 20 06:03:28 PM PDT 24
Finished Jul 20 06:03:54 PM PDT 24
Peak memory 199596 kb
Host smart-e45391da-5c9b-4c19-be88-85f64836a0d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735199779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2735199779
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2499074213
Short name T1092
Test name
Test status
Simulation time 141143539487 ps
CPU time 186.43 seconds
Started Jul 20 06:03:36 PM PDT 24
Finished Jul 20 06:06:43 PM PDT 24
Peak memory 200188 kb
Host smart-eb937b56-0b27-437a-bc52-85feff031539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499074213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2499074213
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3578626850
Short name T743
Test name
Test status
Simulation time 739784253 ps
CPU time 0.84 seconds
Started Jul 20 06:03:38 PM PDT 24
Finished Jul 20 06:03:39 PM PDT 24
Peak memory 195768 kb
Host smart-dd433b52-fe17-43bc-ae92-aff6b2b21929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578626850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3578626850
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.823366405
Short name T678
Test name
Test status
Simulation time 110555171676 ps
CPU time 36.01 seconds
Started Jul 20 06:03:31 PM PDT 24
Finished Jul 20 06:04:08 PM PDT 24
Peak memory 208240 kb
Host smart-5a871523-dc80-4524-a256-a7133d1c6594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823366405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.823366405
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3976141619
Short name T1118
Test name
Test status
Simulation time 16107223974 ps
CPU time 220.54 seconds
Started Jul 20 06:03:39 PM PDT 24
Finished Jul 20 06:07:20 PM PDT 24
Peak memory 200204 kb
Host smart-31cf409e-9965-4a45-8004-fbee62fb790c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3976141619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3976141619
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3096447890
Short name T607
Test name
Test status
Simulation time 1477604049 ps
CPU time 4.51 seconds
Started Jul 20 06:03:30 PM PDT 24
Finished Jul 20 06:03:35 PM PDT 24
Peak memory 198228 kb
Host smart-b4499f2a-aad9-4cc7-8646-83b55e0e0eb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3096447890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3096447890
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.976074759
Short name T298
Test name
Test status
Simulation time 17748650856 ps
CPU time 29.73 seconds
Started Jul 20 06:03:36 PM PDT 24
Finished Jul 20 06:04:07 PM PDT 24
Peak memory 200188 kb
Host smart-37ed10c5-fe49-4860-85a2-1128d6a84a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976074759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.976074759
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.315853874
Short name T805
Test name
Test status
Simulation time 2396048340 ps
CPU time 4.07 seconds
Started Jul 20 06:03:38 PM PDT 24
Finished Jul 20 06:03:43 PM PDT 24
Peak memory 196016 kb
Host smart-7e14798d-23e1-45e0-a245-64c7cb6a90c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315853874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.315853874
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1908178166
Short name T688
Test name
Test status
Simulation time 475964333 ps
CPU time 2.69 seconds
Started Jul 20 06:03:34 PM PDT 24
Finished Jul 20 06:03:37 PM PDT 24
Peak memory 198836 kb
Host smart-ccb8fdcd-d4fa-4a77-bc4b-dbeb5a55536d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908178166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1908178166
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2723808499
Short name T656
Test name
Test status
Simulation time 152420053015 ps
CPU time 94.69 seconds
Started Jul 20 06:03:48 PM PDT 24
Finished Jul 20 06:05:23 PM PDT 24
Peak memory 199996 kb
Host smart-3e4fe8a0-9301-4acb-bf72-b960870b0ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723808499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2723808499
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2854467746
Short name T670
Test name
Test status
Simulation time 151737564016 ps
CPU time 1147.45 seconds
Started Jul 20 06:03:48 PM PDT 24
Finished Jul 20 06:22:56 PM PDT 24
Peak memory 216544 kb
Host smart-2ed886e9-92f1-46ea-88c8-c2af6da4baf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854467746 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2854467746
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.4204200493
Short name T365
Test name
Test status
Simulation time 994556862 ps
CPU time 1.32 seconds
Started Jul 20 06:03:39 PM PDT 24
Finished Jul 20 06:03:41 PM PDT 24
Peak memory 198412 kb
Host smart-110ee6b7-b131-4b92-adff-8b320083caf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204200493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.4204200493
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2734255439
Short name T250
Test name
Test status
Simulation time 116403654888 ps
CPU time 212.24 seconds
Started Jul 20 06:03:32 PM PDT 24
Finished Jul 20 06:07:04 PM PDT 24
Peak memory 200184 kb
Host smart-b51f71e8-767b-4e72-be3f-7ff578208102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734255439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2734255439
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.227470229
Short name T846
Test name
Test status
Simulation time 27347709827 ps
CPU time 39.9 seconds
Started Jul 20 06:08:29 PM PDT 24
Finished Jul 20 06:09:09 PM PDT 24
Peak memory 200196 kb
Host smart-d29eb645-cab6-42ee-ae7e-3bbec2a9c9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227470229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.227470229
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1571458569
Short name T55
Test name
Test status
Simulation time 276045471769 ps
CPU time 638.38 seconds
Started Jul 20 06:08:27 PM PDT 24
Finished Jul 20 06:19:06 PM PDT 24
Peak memory 216692 kb
Host smart-b7e7effd-3517-4dd0-bc14-7bb72aa36dcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571458569 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1571458569
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.797884323
Short name T622
Test name
Test status
Simulation time 27920136022 ps
CPU time 25.33 seconds
Started Jul 20 06:08:25 PM PDT 24
Finished Jul 20 06:08:50 PM PDT 24
Peak memory 200148 kb
Host smart-6fe394cc-df0d-4fa4-a828-3bcaa7bf7f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797884323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.797884323
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1605585737
Short name T930
Test name
Test status
Simulation time 22413023390 ps
CPU time 37.08 seconds
Started Jul 20 06:08:28 PM PDT 24
Finished Jul 20 06:09:06 PM PDT 24
Peak memory 200192 kb
Host smart-b0dd5340-dc58-4bbe-b4a8-a94de4cea1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605585737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1605585737
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3522353345
Short name T454
Test name
Test status
Simulation time 58805201761 ps
CPU time 90.02 seconds
Started Jul 20 06:08:29 PM PDT 24
Finished Jul 20 06:09:59 PM PDT 24
Peak memory 200076 kb
Host smart-cce855db-2d26-4add-a690-d63bd2bd2ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522353345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3522353345
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1125223287
Short name T625
Test name
Test status
Simulation time 90778907640 ps
CPU time 1149.52 seconds
Started Jul 20 06:08:26 PM PDT 24
Finished Jul 20 06:27:37 PM PDT 24
Peak memory 218992 kb
Host smart-0bd7a50a-cec4-4cfa-8737-ca5e4d2954f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125223287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1125223287
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3466692709
Short name T1149
Test name
Test status
Simulation time 22138086928 ps
CPU time 9.32 seconds
Started Jul 20 06:08:29 PM PDT 24
Finished Jul 20 06:08:39 PM PDT 24
Peak memory 199460 kb
Host smart-4c31d2a2-dab5-469d-a571-8c7d2e437144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466692709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3466692709
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1387636892
Short name T54
Test name
Test status
Simulation time 43033697099 ps
CPU time 347.65 seconds
Started Jul 20 06:08:29 PM PDT 24
Finished Jul 20 06:14:17 PM PDT 24
Peak memory 209628 kb
Host smart-8a6ba911-aeb9-4a11-89ad-d331d5ecd326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387636892 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1387636892
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2527746440
Short name T907
Test name
Test status
Simulation time 156384506199 ps
CPU time 366.24 seconds
Started Jul 20 06:08:29 PM PDT 24
Finished Jul 20 06:14:36 PM PDT 24
Peak memory 216584 kb
Host smart-9769faff-1f55-4364-b193-45f5a63deaca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527746440 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2527746440
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1751750990
Short name T433
Test name
Test status
Simulation time 53737783532 ps
CPU time 22.32 seconds
Started Jul 20 06:08:28 PM PDT 24
Finished Jul 20 06:08:51 PM PDT 24
Peak memory 199964 kb
Host smart-af8659bc-0ad6-4ccd-be7b-e53e553cfc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751750990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1751750990
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1884514506
Short name T31
Test name
Test status
Simulation time 31162477429 ps
CPU time 98.17 seconds
Started Jul 20 06:08:26 PM PDT 24
Finished Jul 20 06:10:05 PM PDT 24
Peak memory 216788 kb
Host smart-f50c1633-e03c-4624-8562-c46647274bdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884514506 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1884514506
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.176337777
Short name T1108
Test name
Test status
Simulation time 204054135049 ps
CPU time 236.83 seconds
Started Jul 20 06:08:30 PM PDT 24
Finished Jul 20 06:12:27 PM PDT 24
Peak memory 200192 kb
Host smart-3b2c421a-2997-4bab-9e26-f088672cdad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176337777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.176337777
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3084866389
Short name T692
Test name
Test status
Simulation time 6137065215 ps
CPU time 5.66 seconds
Started Jul 20 06:08:35 PM PDT 24
Finished Jul 20 06:08:41 PM PDT 24
Peak memory 200080 kb
Host smart-f6c72d5c-4d68-415a-ba2b-640e40fb7de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084866389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3084866389
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1166063928
Short name T1138
Test name
Test status
Simulation time 21167229897 ps
CPU time 17.42 seconds
Started Jul 20 06:08:37 PM PDT 24
Finished Jul 20 06:08:55 PM PDT 24
Peak memory 200188 kb
Host smart-b01a5dd9-3e60-4388-a5c3-8ce71d3ef220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166063928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1166063928
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.714670567
Short name T669
Test name
Test status
Simulation time 40630828938 ps
CPU time 611.4 seconds
Started Jul 20 06:08:34 PM PDT 24
Finished Jul 20 06:18:46 PM PDT 24
Peak memory 216664 kb
Host smart-9193862d-45d1-4730-8429-a206193abb94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714670567 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.714670567
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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