Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	113292	1			T2	47		T3	1		T4	31
all_values[1]	113292	1			T2	47		T3	1		T4	31
all_values[2]	113292	1			T2	47		T3	1		T4	31
all_values[3]	113292	1			T2	47		T3	1		T4	31
all_values[4]	113292	1			T2	47		T3	1		T4	31
all_values[5]	113292	1			T2	47		T3	1		T4	31
all_values[6]	113292	1			T2	47		T3	1		T4	31
all_values[7]	113292	1			T2	47		T3	1		T4	31
all_values[8]	113292	1			T2	47		T3	1		T4	31

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

511231

1

T2

237

T3

3

T4

146

auto[1]

508397

1

T2

186

T3

6

T4

133

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

924660

1

T2

317

T3

7

T4

251

auto[1]

94968

1

T2

106

T3

2

T4

28

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	33384	1			T2	4		T4	8		T6	11
all_values[0]	auto[0]	auto[1]	24506	1			T2	31		T4	22		T5	2
all_values[0]	auto[1]	auto[0]	32150	1			T7	3		T8	3		T9	8
all_values[0]	auto[1]	auto[1]	23252	1			T2	12		T3	1		T4	1
all_values[1]	auto[0]	auto[0]	52698	1			T2	35		T3	1		T4	27
all_values[1]	auto[0]	auto[1]	1558	1			T2	1		T6	8		T14	8
all_values[1]	auto[1]	auto[0]	57301	1			T2	11		T4	4		T7	8
all_values[1]	auto[1]	auto[1]	1735	1			T7	4		T9	11		T12	1
all_values[2]	auto[0]	auto[0]	55787	1			T2	39		T4	1		T5	1
all_values[2]	auto[0]	auto[1]	2915	1			T2	1		T5	1		T6	1
all_values[2]	auto[1]	auto[0]	51988	1			T2	2		T3	1		T4	30
all_values[2]	auto[1]	auto[1]	2602	1			T2	5		T7	2		T8	1
all_values[3]	auto[0]	auto[0]	55457	1			T2	15		T4	5		T5	2
all_values[3]	auto[0]	auto[1]	325	1			T2	1		T13	1		T14	5
all_values[3]	auto[1]	auto[0]	57174	1			T2	31		T3	1		T4	22
all_values[3]	auto[1]	auto[1]	336	1			T4	4		T6	1		T14	6
all_values[4]	auto[0]	auto[0]	57412	1			T2	31		T5	2		T6	32
all_values[4]	auto[0]	auto[1]	384	1			T14	3		T15	2		T42	4
all_values[4]	auto[1]	auto[0]	55064	1			T2	11		T3	1		T4	31
all_values[4]	auto[1]	auto[1]	432	1			T2	5		T13	2		T14	7
all_values[5]	auto[0]	auto[0]	55972	1			T2	5		T4	27		T5	2
all_values[5]	auto[0]	auto[1]	196	1			T2	3		T14	2		T42	6
all_values[5]	auto[1]	auto[0]	56931	1			T2	39		T3	1		T4	4
all_values[5]	auto[1]	auto[1]	193	1			T14	2		T15	9		T42	2
all_values[6]	auto[0]	auto[0]	54689	1			T2	4		T3	1		T4	26
all_values[6]	auto[0]	auto[1]	206	1			T2	1		T14	3		T15	3
all_values[6]	auto[1]	auto[0]	58181	1			T2	40		T4	5		T6	21
all_values[6]	auto[1]	auto[1]	216	1			T2	2		T14	8		T15	1
all_values[7]	auto[0]	auto[0]	58314	1			T2	30		T3	1		T4	30
all_values[7]	auto[0]	auto[1]	355	1			T2	3		T89	1		T14	6
all_values[7]	auto[1]	auto[0]	54301	1			T2	11		T4	1		T6	21
all_values[7]	auto[1]	auto[1]	322	1			T2	3		T10	2		T12	1
all_values[8]	auto[0]	auto[0]	38750	1			T2	9		T6	31		T8	3
all_values[8]	auto[0]	auto[1]	18323	1			T2	24		T5	2		T6	1
all_values[8]	auto[1]	auto[0]	39107	1			T4	30		T7	5		T9	9
all_values[8]	auto[1]	auto[1]	17112	1			T2	14		T3	1		T4	1