Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2609

1

T1

1

T2

4

T3

1

auto[UartRx]

2609

1

T1

1

T2

4

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4587	1			T1	2		T2	8		T3	2
values[1]	51	1			T14	1		T19	2		T28	1
values[2]	60	1			T19	1		T29	1		T30	2
values[3]	52	1			T14	1		T15	2		T33	1
values[4]	58	1			T15	1		T18	1		T19	1
values[5]	58	1			T18	1		T28	1		T32	1
values[6]	60	1			T30	2		T33	3		T158	1
values[7]	75	1			T15	2		T19	1		T28	2
values[8]	64	1			T15	2		T28	1		T29	1
values[9]	48	1			T15	1		T19	1		T28	1
values[10]	63	1			T18	4		T19	3		T28	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2383	1			T1	1		T2	4		T3	1
auto[UartTx]	values[1]	18	1			T14	1		T56	1		T306	1
auto[UartTx]	values[2]	19	1			T19	1		T31	1		T56	1
auto[UartTx]	values[3]	22	1			T158	1		T307	1		T104	1
auto[UartTx]	values[4]	23	1			T15	1		T158	1		T279	1
auto[UartTx]	values[5]	24	1			T18	1		T28	1		T308	1
auto[UartTx]	values[6]	19	1			T30	2		T33	3		T54	1
auto[UartTx]	values[7]	32	1			T15	1		T28	1		T158	1
auto[UartTx]	values[8]	21	1			T15	1		T158	1		T102	2
auto[UartTx]	values[9]	18	1			T33	1		T102	1		T159	1
auto[UartTx]	values[10]	17	1			T18	2		T29	1		T32	1
auto[UartRx]	values[0]	2204	1			T1	1		T2	4		T3	1
auto[UartRx]	values[1]	33	1			T19	2		T28	1		T30	1
auto[UartRx]	values[2]	41	1			T29	1		T30	2		T32	1
auto[UartRx]	values[3]	30	1			T14	1		T15	2		T33	1
auto[UartRx]	values[4]	35	1			T18	1		T19	1		T30	1
auto[UartRx]	values[5]	34	1			T32	1		T33	2		T308	1
auto[UartRx]	values[6]	41	1			T158	1		T308	1		T54	2
auto[UartRx]	values[7]	43	1			T15	1		T19	1		T28	1
auto[UartRx]	values[8]	43	1			T15	1		T28	1		T29	1
auto[UartRx]	values[9]	30	1			T15	1		T19	1		T28	1
auto[UartRx]	values[10]	46	1			T18	2		T19	3		T28	1