Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2318	1			T2	1		T3	5		T4	2
auto[BaudRate115200]	2175	1			T4	1		T6	1		T7	1
auto[BaudRate230400]	2102	1			T2	1		T5	1		T6	2
auto[BaudRate128Kbps]	2086	1			T2	1		T7	2		T8	2
auto[BaudRate256Kbps]	2294	1			T2	1		T4	4		T6	1
auto[BaudRate1Mbps]	1874	1			T6	1		T8	3		T10	2
auto[BaudRate1p5Mbps]	1418	1			T4	2		T7	1		T9	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1451	1			T13	1		T120	5		T155	10
freqs[25]	1106	1			T6	6		T11	5		T89	8
freqs[48]	815	1			T4	9		T250	2		T44	6
freqs[50]	624	1			T8	7		T10	6		T107	9
freqs[100]	1399	1			T9	10		T12	9		T21	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	190	1			T13	1		T120	1		T155	1
auto[BaudRate9600]	freqs[25]	154	1			T6	1		T89	1		T36	3
auto[BaudRate9600]	freqs[48]	136	1			T4	2		T249	3		T167	1
auto[BaudRate9600]	freqs[50]	119	1			T10	1		T126	1		T74	2
auto[BaudRate9600]	freqs[100]	289	1			T9	1		T12	1		T15	2
auto[BaudRate115200]	freqs[24]	230	1			T120	2		T155	1		T42	1
auto[BaudRate115200]	freqs[25]	164	1			T6	1		T11	2		T89	2
auto[BaudRate115200]	freqs[48]	92	1			T4	1		T249	2		T167	1
auto[BaudRate115200]	freqs[50]	75	1			T107	1		T126	3		T74	1
auto[BaudRate115200]	freqs[100]	176	1			T9	1		T12	1		T15	3
auto[BaudRate230400]	freqs[24]	243	1			T120	1		T155	2		T42	5
auto[BaudRate230400]	freqs[25]	181	1			T6	2		T11	1		T89	1
auto[BaudRate230400]	freqs[48]	102	1			T250	1		T249	3		T167	2
auto[BaudRate230400]	freqs[50]	96	1			T8	1		T10	1		T126	2
auto[BaudRate230400]	freqs[100]	179	1			T9	2		T12	1		T21	1
auto[BaudRate128Kbps]	freqs[24]	220	1			T120	1		T42	5		T109	1
auto[BaudRate128Kbps]	freqs[25]	161	1			T11	2		T89	1		T248	2
auto[BaudRate128Kbps]	freqs[48]	118	1			T249	1		T289	2		T176	3
auto[BaudRate128Kbps]	freqs[50]	61	1			T8	2		T107	4		T126	1
auto[BaudRate128Kbps]	freqs[100]	171	1			T9	1		T12	2		T21	1
auto[BaudRate256Kbps]	freqs[24]	237	1			T42	8		T111	1		T112	3
auto[BaudRate256Kbps]	freqs[25]	178	1			T6	1		T36	1		T178	1
auto[BaudRate256Kbps]	freqs[48]	116	1			T4	4		T44	1		T249	6
auto[BaudRate256Kbps]	freqs[50]	82	1			T8	1		T10	1		T107	2
auto[BaudRate256Kbps]	freqs[100]	188	1			T9	4		T15	8		T123	3
auto[BaudRate1Mbps]	freqs[24]	223	1			T155	2		T42	4		T109	2
auto[BaudRate1Mbps]	freqs[25]	172	1			T6	1		T89	3		T36	1
auto[BaudRate1Mbps]	freqs[48]	103	1			T250	1		T44	2		T249	1
auto[BaudRate1Mbps]	freqs[50]	100	1			T8	3		T10	2		T126	1
auto[BaudRate1Mbps]	freqs[100]	197	1			T12	2		T15	5		T123	1
auto[BaudRate1p5Mbps]	freqs[25]	96	1			T128	1		T130	2		T75	3
auto[BaudRate1p5Mbps]	freqs[48]	148	1			T4	2		T44	3		T249	2
auto[BaudRate1p5Mbps]	freqs[50]	91	1			T10	1		T107	2		T263	1
auto[BaudRate1p5Mbps]	freqs[100]	199	1			T9	1		T12	2		T15	11

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded