Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.45	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	7	123	94.62

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	7	123	94.62	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	33098022	1			T2	38230		T3	1		T4	52
all_levels[1]	192676	1			T4	15		T6	18		T9	7
all_levels[2]	2574	1			T4	4		T6	9		T9	5
all_levels[3]	1072	1			T4	2		T6	4		T9	3
all_levels[4]	667	1			T9	3		T14	1		T20	9
all_levels[5]	557	1			T9	2		T20	7		T120	6
all_levels[6]	415	1			T7	1		T9	2		T14	1
all_levels[7]	370	1			T6	1		T9	3		T89	1
all_levels[8]	292	1			T9	2		T14	1		T20	3
all_levels[9]	267	1			T7	7		T9	1		T20	2
all_levels[10]	219	1			T14	2		T20	2		T40	2
all_levels[11]	180	1			T9	2		T40	1		T120	1
all_levels[12]	150	1			T6	1		T7	1		T20	1
all_levels[13]	148	1			T9	1		T10	1		T37	1
all_levels[14]	127	1			T45	1		T121	1		T122	1
all_levels[15]	131	1			T9	3		T89	1		T18	2
all_levels[16]	116	1			T20	2		T123	2		T124	1
all_levels[17]	91	1			T6	1		T9	2		T14	2
all_levels[18]	90	1			T20	3		T15	1		T42	1
all_levels[19]	82	1			T112	1		T125	1		T126	1
all_levels[20]	62	1			T12	1		T15	1		T109	2
all_levels[21]	50	1			T111	1		T127	1		T128	1
all_levels[22]	77	1			T6	1		T20	1		T129	2
all_levels[23]	58	1			T123	1		T130	1		T126	1
all_levels[24]	65	1			T89	1		T131	2		T129	1
all_levels[25]	47	1			T9	1		T89	1		T20	1
all_levels[26]	56	1			T7	1		T42	1		T111	2
all_levels[27]	37	1			T4	1		T123	1		T45	1
all_levels[28]	46	1			T7	1		T9	2		T123	1
all_levels[29]	30	1			T127	1		T129	1		T132	1
all_levels[30]	32	1			T9	1		T112	1		T123	2
all_levels[31]	46	1			T41	2		T131	1		T133	1
all_levels[32]	25	1			T14	1		T134	1		T33	2
all_levels[33]	29	1			T14	1		T32	1		T117	1
all_levels[34]	20	1			T128	1		T133	1		T135	1
all_levels[35]	29	1			T19	1		T32	1		T136	1
all_levels[36]	23	1			T15	1		T19	1		T134	3
all_levels[37]	23	1			T51	3		T137	1		T136	1
all_levels[38]	20	1			T89	1		T110	2		T115	2
all_levels[39]	26	1			T14	1		T42	1		T128	2
all_levels[40]	14	1			T126	1		T138	2		T139	1
all_levels[41]	24	1			T4	2		T140	1		T141	2
all_levels[42]	6	1			T89	1		T33	1		T142	1
all_levels[43]	15	1			T120	1		T32	1		T143	1
all_levels[44]	18	1			T127	1		T126	2		T132	1
all_levels[45]	12	1			T128	1		T45	1		T75	2
all_levels[46]	16	1			T144	2		T56	1		T145	1
all_levels[47]	13	1			T109	1		T146	1		T147	1
all_levels[48]	15	1			T75	1		T148	1		T117	1
all_levels[49]	20	1			T12	2		T42	1		T134	1
all_levels[50]	10	1			T42	1		T140	1		T149	1
all_levels[51]	7	1			T150	1		T151	1		T152	1
all_levels[52]	13	1			T117	1		T153	1		T154	1
all_levels[53]	20	1			T155	2		T117	1		T114	1
all_levels[54]	14	1			T14	1		T36	1		T127	1
all_levels[55]	12	1			T89	1		T137	2		T156	1
all_levels[56]	6	1			T30	1		T33	1		T157	1
all_levels[57]	7	1			T120	1		T33	1		T158	1
all_levels[58]	10	1			T159	1		T143	1		T160	2
all_levels[59]	19	1			T10	2		T116	2		T140	1
all_levels[60]	7	1			T30	1		T161	1		T157	1
all_levels[61]	9	1			T117	1		T158	1		T162	1
all_levels[62]	7	1			T163	2		T140	1		T164	1
all_levels[63]	12	1			T140	2		T165	1		T166	1
all_levels[64]	105	1			T6	1		T36	1		T134	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33294934

1

T2

38212

T4

69

T6

62

auto[1]

4524

1

T2

18

T3

1

T4

7

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	7	123	94.62	7

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[42]]	[auto[1]]	0	1	1
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[51] , all_levels[52]]	[auto[1]]	--	--	2
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[60] , all_levels[61]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	33094009	1			T2	38212		T4	46		T6	26
all_levels[0]	auto[1]	4013	1			T2	18		T3	1		T4	6
all_levels[1]	auto[0]	192578	1			T4	15		T6	18		T9	7
all_levels[1]	auto[1]	98	1			T125	3		T73	1		T167	1
all_levels[2]	auto[0]	2549	1			T4	4		T6	9		T9	5
all_levels[2]	auto[1]	25	1			T168	1		T166	2		T169	1
all_levels[3]	auto[0]	1057	1			T4	2		T6	4		T9	3
all_levels[3]	auto[1]	15	1			T170	2		T171	1		T172	1
all_levels[4]	auto[0]	649	1			T9	3		T14	1		T20	9
all_levels[4]	auto[1]	18	1			T122	1		T173	2		T174	1
all_levels[5]	auto[0]	527	1			T9	2		T20	7		T120	6
all_levels[5]	auto[1]	30	1			T128	1		T175	1		T176	4
all_levels[6]	auto[0]	392	1			T7	1		T9	2		T14	1
all_levels[6]	auto[1]	23	1			T155	1		T47	1		T177	1
all_levels[7]	auto[0]	345	1			T6	1		T9	3		T89	1
all_levels[7]	auto[1]	25	1			T178	1		T115	3		T179	2
all_levels[8]	auto[0]	276	1			T9	2		T14	1		T20	3
all_levels[8]	auto[1]	16	1			T155	3		T117	1		T180	3
all_levels[9]	auto[0]	243	1			T7	3		T9	1		T20	2
all_levels[9]	auto[1]	24	1			T7	4		T181	1		T182	1
all_levels[10]	auto[0]	206	1			T14	2		T20	2		T40	2
all_levels[10]	auto[1]	13	1			T126	1		T167	1		T175	1
all_levels[11]	auto[0]	167	1			T9	2		T40	1		T120	1
all_levels[11]	auto[1]	13	1			T179	1		T135	2		T146	1
all_levels[12]	auto[0]	143	1			T6	1		T7	1		T20	1
all_levels[12]	auto[1]	7	1			T59	1		T183	3		T184	2
all_levels[13]	auto[0]	139	1			T9	1		T10	1		T37	1
all_levels[13]	auto[1]	9	1			T185	1		T186	1		T146	1
all_levels[14]	auto[0]	117	1			T45	1		T121	1		T122	1
all_levels[14]	auto[1]	10	1			T51	1		T187	2		T188	1
all_levels[15]	auto[0]	119	1			T9	3		T89	1		T18	2
all_levels[15]	auto[1]	12	1			T123	1		T189	1		T138	1
all_levels[16]	auto[0]	103	1			T20	2		T123	2		T124	1
all_levels[16]	auto[1]	13	1			T190	2		T163	3		T191	1
all_levels[17]	auto[0]	83	1			T6	1		T9	2		T14	2
all_levels[17]	auto[1]	8	1			T192	1		T193	2		T194	1
all_levels[18]	auto[0]	79	1			T20	3		T15	1		T42	1
all_levels[18]	auto[1]	11	1			T195	2		T172	1		T186	1
all_levels[19]	auto[0]	73	1			T112	1		T125	1		T126	1
all_levels[19]	auto[1]	9	1			T171	1		T196	1		T197	1
all_levels[20]	auto[0]	56	1			T12	1		T15	1		T109	1
all_levels[20]	auto[1]	6	1			T109	1		T187	1		T198	1
all_levels[21]	auto[0]	49	1			T111	1		T127	1		T128	1
all_levels[21]	auto[1]	1	1			T199	1		-	-		-	-
all_levels[22]	auto[0]	71	1			T6	1		T20	1		T129	1
all_levels[22]	auto[1]	6	1			T129	1		T59	1		T200	1
all_levels[23]	auto[0]	53	1			T123	1		T130	1		T126	1
all_levels[23]	auto[1]	5	1			T201	1		T202	1		T203	2
all_levels[24]	auto[0]	60	1			T89	1		T131	1		T129	1
all_levels[24]	auto[1]	5	1			T131	1		T204	1		T205	2
all_levels[25]	auto[0]	39	1			T9	1		T89	1		T20	1
all_levels[25]	auto[1]	8	1			T206	4		T207	1		T208	1
all_levels[26]	auto[0]	48	1			T7	1		T42	1		T111	2
all_levels[26]	auto[1]	8	1			T209	2		T210	3		T211	1
all_levels[27]	auto[0]	35	1			T4	1		T123	1		T45	1
all_levels[27]	auto[1]	2	1			T212	1		T213	1		-	-
all_levels[28]	auto[0]	41	1			T7	1		T9	2		T123	1
all_levels[28]	auto[1]	5	1			T178	2		T193	1		T169	2
all_levels[29]	auto[0]	26	1			T127	1		T129	1		T132	1
all_levels[29]	auto[1]	4	1			T214	2		T215	2		-	-
all_levels[30]	auto[0]	28	1			T9	1		T112	1		T123	2
all_levels[30]	auto[1]	4	1			T141	1		T216	2		T217	1
all_levels[31]	auto[0]	43	1			T41	2		T131	1		T133	1
all_levels[31]	auto[1]	3	1			T149	1		T218	1		T219	1
all_levels[32]	auto[0]	22	1			T14	1		T134	1		T33	2
all_levels[32]	auto[1]	3	1			T220	1		T212	1		T205	1
all_levels[33]	auto[0]	26	1			T14	1		T32	1		T117	1
all_levels[33]	auto[1]	3	1			T221	2		T222	1		-	-
all_levels[34]	auto[0]	18	1			T128	1		T133	1		T135	1
all_levels[34]	auto[1]	2	1			T223	1		T224	1		-	-
all_levels[35]	auto[0]	27	1			T19	1		T32	1		T136	1
all_levels[35]	auto[1]	2	1			T183	2		-	-		-	-
all_levels[36]	auto[0]	20	1			T15	1		T19	1		T134	1
all_levels[36]	auto[1]	3	1			T134	2		T225	1		-	-
all_levels[37]	auto[0]	19	1			T51	1		T137	1		T136	1
all_levels[37]	auto[1]	4	1			T51	2		T226	1		T227	1
all_levels[38]	auto[0]	18	1			T89	1		T110	1		T115	2
all_levels[38]	auto[1]	2	1			T110	1		T228	1		-	-
all_levels[39]	auto[0]	23	1			T14	1		T42	1		T128	1
all_levels[39]	auto[1]	3	1			T128	1		T229	1		T230	1
all_levels[40]	auto[0]	13	1			T126	1		T138	1		T139	1
all_levels[40]	auto[1]	1	1			T138	1		-	-		-	-
all_levels[41]	auto[0]	21	1			T4	1		T140	1		T141	1
all_levels[41]	auto[1]	3	1			T4	1		T141	1		T206	1
all_levels[42]	auto[0]	6	1			T89	1		T33	1		T142	1
all_levels[43]	auto[0]	12	1			T120	1		T32	1		T143	1
all_levels[43]	auto[1]	3	1			T231	3		-	-		-	-
all_levels[44]	auto[0]	17	1			T127	1		T126	1		T132	1
all_levels[44]	auto[1]	1	1			T126	1		-	-		-	-
all_levels[45]	auto[0]	10	1			T128	1		T45	1		T75	2
all_levels[45]	auto[1]	2	1			T232	1		T233	1		-	-
all_levels[46]	auto[0]	14	1			T144	2		T56	1		T145	1
all_levels[46]	auto[1]	2	1			T200	2		-	-		-	-
all_levels[47]	auto[0]	13	1			T109	1		T146	1		T147	1
all_levels[48]	auto[0]	13	1			T75	1		T148	1		T117	1
all_levels[48]	auto[1]	2	1			T142	2		-	-		-	-
all_levels[49]	auto[0]	15	1			T12	2		T42	1		T134	1
all_levels[49]	auto[1]	5	1			T234	4		T235	1		-	-
all_levels[50]	auto[0]	9	1			T42	1		T140	1		T149	1
all_levels[50]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[51]	auto[0]	7	1			T150	1		T151	1		T152	1
all_levels[52]	auto[0]	13	1			T117	1		T153	1		T154	1
all_levels[53]	auto[0]	10	1			T155	1		T117	1		T114	1
all_levels[53]	auto[1]	10	1			T155	1		T194	6		T145	1
all_levels[54]	auto[0]	13	1			T14	1		T36	1		T127	1
all_levels[54]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[55]	auto[0]	10	1			T89	1		T137	1		T156	1
all_levels[55]	auto[1]	2	1			T137	1		T142	1		-	-
all_levels[56]	auto[0]	6	1			T30	1		T33	1		T157	1
all_levels[57]	auto[0]	6	1			T120	1		T33	1		T158	1
all_levels[57]	auto[1]	1	1			T238	1		-	-		-	-
all_levels[58]	auto[0]	6	1			T159	1		T143	1		T160	1
all_levels[58]	auto[1]	4	1			T160	1		T239	2		T240	1
all_levels[59]	auto[0]	18	1			T10	2		T116	2		T140	1
all_levels[59]	auto[1]	1	1			T241	1		-	-		-	-
all_levels[60]	auto[0]	7	1			T30	1		T161	1		T157	1
all_levels[61]	auto[0]	9	1			T117	1		T158	1		T162	1
all_levels[62]	auto[0]	6	1			T163	1		T140	1		T164	1
all_levels[62]	auto[1]	1	1			T163	1		-	-		-	-
all_levels[63]	auto[0]	9	1			T140	2		T165	1		T166	1
all_levels[63]	auto[1]	3	1			T172	1		T242	2		-	-
all_levels[64]	auto[0]	95	1			T6	1		T36	1		T134	1
all_levels[64]	auto[1]	10	1			T134	1		T148	2		T163	1