Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	113292	1			T2	47		T3	1		T4	31
all_pins[1]	113292	1			T2	47		T3	1		T4	31
all_pins[2]	113292	1			T2	47		T3	1		T4	31
all_pins[3]	113292	1			T2	47		T3	1		T4	31
all_pins[4]	113292	1			T2	47		T3	1		T4	31
all_pins[5]	113292	1			T2	47		T3	1		T4	31
all_pins[6]	113292	1			T2	47		T3	1		T4	31
all_pins[7]	113292	1			T2	47		T3	1		T4	31
all_pins[8]	113292	1			T2	47		T3	1		T4	31

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	972422	1			T2	382		T3	7		T4	273
values[0x1]	47206	1			T2	41		T3	2		T4	6
transitions[0x0=>0x1]	36425	1			T2	26		T3	1		T4	6
transitions[0x1=>0x0]	36231	1			T2	27		T3	1		T4	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	89968	1			T2	35		T4	30		T5	2
all_pins[0]	values[0x1]	23324	1			T2	12		T3	1		T4	1
all_pins[0]	transitions[0x0=>0x1]	22701	1			T2	12		T3	1		T4	1
all_pins[0]	transitions[0x1=>0x0]	1107	1			T7	4		T9	3		T12	1
all_pins[1]	values[0x0]	111562	1			T2	47		T3	1		T4	31
all_pins[1]	values[0x1]	1730	1			T7	4		T9	11		T12	1
all_pins[1]	transitions[0x0=>0x1]	1594	1			T7	3		T9	10		T12	1
all_pins[1]	transitions[0x1=>0x0]	2518	1			T2	5		T7	1		T8	1
all_pins[2]	values[0x0]	110638	1			T2	42		T3	1		T4	31
all_pins[2]	values[0x1]	2654	1			T2	5		T7	2		T8	1
all_pins[2]	transitions[0x0=>0x1]	2592	1			T2	5		T7	2		T8	1
all_pins[2]	transitions[0x1=>0x0]	274	1			T4	4		T6	1		T14	4
all_pins[3]	values[0x0]	112956	1			T2	47		T3	1		T4	27
all_pins[3]	values[0x1]	336	1			T4	4		T6	1		T14	6
all_pins[3]	transitions[0x0=>0x1]	285	1			T4	4		T6	1		T14	3
all_pins[3]	transitions[0x1=>0x0]	381	1			T2	5		T13	2		T14	4
all_pins[4]	values[0x0]	112860	1			T2	42		T3	1		T4	31
all_pins[4]	values[0x1]	432	1			T2	5		T13	2		T14	7
all_pins[4]	transitions[0x0=>0x1]	356	1			T2	5		T13	2		T14	7
all_pins[4]	transitions[0x1=>0x0]	160	1			T14	2		T15	6		T42	2
all_pins[5]	values[0x0]	113056	1			T2	47		T3	1		T4	31
all_pins[5]	values[0x1]	236	1			T14	2		T15	9		T42	2
all_pins[5]	transitions[0x0=>0x1]	188	1			T15	9		T42	1		T16	1
all_pins[5]	transitions[0x1=>0x0]	935	1			T2	2		T6	3		T7	1
all_pins[6]	values[0x0]	112309	1			T2	45		T3	1		T4	31
all_pins[6]	values[0x1]	983	1			T2	2		T6	3		T7	1
all_pins[6]	transitions[0x0=>0x1]	923	1			T6	3		T7	1		T9	5
all_pins[6]	transitions[0x1=>0x0]	262	1			T2	1		T10	2		T89	2
all_pins[7]	values[0x0]	112970	1			T2	44		T3	1		T4	31
all_pins[7]	values[0x1]	322	1			T2	3		T10	2		T12	1
all_pins[7]	transitions[0x0=>0x1]	178	1			T2	1		T12	1		T89	2
all_pins[7]	transitions[0x1=>0x0]	17045	1			T2	12		T3	1		T4	1
all_pins[8]	values[0x0]	96103	1			T2	33		T4	30		T5	2
all_pins[8]	values[0x1]	17189	1			T2	14		T3	1		T4	1
all_pins[8]	transitions[0x0=>0x1]	7608	1			T2	3		T4	1		T9	2
all_pins[8]	transitions[0x1=>0x0]	13549	1			T2	2		T6	20		T7	3