Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8821677	1			T2	14		T4	16		T6	6
all_levels[1]	2168374	1			T2	18846		T4	42		T6	51
all_levels[2]	490823	1			T9	8		T11	1666		T14	2822
all_levels[3]	260201	1			T9	2		T11	1680		T89	3
all_levels[4]	227758	1			T9	3		T11	1680		T14	2331
all_levels[5]	309892	1			T9	2		T11	1677		T89	1
all_levels[6]	288368	1			T11	1679		T12	6		T14	2460
all_levels[7]	276392	1			T2	6		T7	1		T9	1
all_levels[8]	301494	1			T2	19364		T9	4		T11	1683
all_levels[9]	329439	1			T10	1		T11	1681		T12	1
all_levels[10]	229341	1			T7	1		T11	1664		T12	6
all_levels[11]	744613	1			T9	1		T11	1680		T12	1
all_levels[12]	228835	1			T7	1		T11	1680		T14	1185
all_levels[13]	214269	1			T11	1658		T12	3		T89	2
all_levels[14]	209512	1			T6	1		T11	1658		T12	2
all_levels[15]	308461	1			T11	1678		T12	1		T89	1
all_levels[16]	298087	1			T4	6		T11	1681		T12	5
all_levels[17]	241958	1			T10	3		T11	1675		T89	2
all_levels[18]	475361	1			T4	11		T11	1673		T12	2
all_levels[19]	215424	1			T7	1		T11	1664		T89	1
all_levels[20]	399681	1			T11	1670		T89	3		T14	802
all_levels[21]	290234	1			T10	3		T11	1679		T14	996
all_levels[22]	301577	1			T11	1681		T89	1		T14	885
all_levels[23]	321493	1			T7	38		T11	2093		T12	1
all_levels[24]	231957	1			T11	1139		T12	1		T89	2
all_levels[25]	213485	1			T11	1136		T12	1		T89	1
all_levels[26]	153673	1			T9	2		T11	1145		T12	2
all_levels[27]	181305	1			T7	1		T9	3		T11	1140
all_levels[28]	171290	1			T11	1103		T12	2		T89	1
all_levels[29]	271993	1			T7	1		T11	1143		T12	3
all_levels[30]	271246	1			T11	1133		T12	5		T14	1367
all_levels[31]	562610	1			T11	1125		T12	5		T89	1
all_levels[32]	13288202	1			T4	3		T6	10		T7	7

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33294934

1

T2

38212

T4

69

T6

62

auto[1]

4091

1

T2

18

T4

9

T6

6

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8819361	1			T2	1		T4	13		T6	5
all_levels[0]	auto[1]	2316	1			T2	13		T4	3		T6	1
all_levels[1]	auto[0]	2168105	1			T2	18846		T4	41		T6	50
all_levels[1]	auto[1]	269	1			T4	1		T6	1		T7	1
all_levels[2]	auto[0]	490783	1			T9	8		T11	1666		T14	2822
all_levels[2]	auto[1]	40	1			T41	2		T130	3		T187	3
all_levels[3]	auto[0]	260059	1			T9	2		T11	1680		T89	3
all_levels[3]	auto[1]	142	1			T128	1		T189	1		T115	11
all_levels[4]	auto[0]	227736	1			T9	3		T11	1680		T14	2331
all_levels[4]	auto[1]	22	1			T255	2		T312	1		T166	1
all_levels[5]	auto[0]	309866	1			T9	2		T11	1677		T89	1
all_levels[5]	auto[1]	26	1			T36	1		T167	1		T192	1
all_levels[6]	auto[0]	288333	1			T11	1679		T12	6		T14	2460
all_levels[6]	auto[1]	35	1			T15	1		T277	3		T51	2
all_levels[7]	auto[0]	276256	1			T2	1		T7	1		T9	1
all_levels[7]	auto[1]	136	1			T2	5		T15	4		T134	1
all_levels[8]	auto[0]	301469	1			T2	19364		T9	4		T11	1683
all_levels[8]	auto[1]	25	1			T36	1		T37	1		T249	1
all_levels[9]	auto[0]	329413	1			T10	1		T11	1681		T12	1
all_levels[9]	auto[1]	26	1			T251	2		T279	1		T55	1
all_levels[10]	auto[0]	229320	1			T7	1		T11	1664		T12	6
all_levels[10]	auto[1]	21	1			T41	1		T293	1		T313	1
all_levels[11]	auto[0]	744590	1			T9	1		T11	1680		T12	1
all_levels[11]	auto[1]	23	1			T40	1		T173	1		T166	1
all_levels[12]	auto[0]	228794	1			T7	1		T11	1680		T14	1185
all_levels[12]	auto[1]	41	1			T42	1		T314	1		T194	7
all_levels[13]	auto[0]	214252	1			T11	1658		T12	3		T89	2
all_levels[13]	auto[1]	17	1			T270	1		T45	1		T305	1
all_levels[14]	auto[0]	209493	1			T6	1		T11	1658		T12	2
all_levels[14]	auto[1]	19	1			T125	1		T131	1		T277	1
all_levels[15]	auto[0]	308381	1			T11	1678		T12	1		T89	1
all_levels[15]	auto[1]	80	1			T248	1		T41	1		T75	4
all_levels[16]	auto[0]	298064	1			T4	6		T11	1681		T12	5
all_levels[16]	auto[1]	23	1			T123	2		T134	1		T315	3
all_levels[17]	auto[0]	241942	1			T10	3		T11	1675		T89	2
all_levels[17]	auto[1]	16	1			T190	2		T157	2		T316	3
all_levels[18]	auto[0]	475335	1			T4	7		T11	1673		T12	2
all_levels[18]	auto[1]	26	1			T4	4		T73	1		T137	1
all_levels[19]	auto[0]	215405	1			T7	1		T11	1664		T89	1
all_levels[19]	auto[1]	19	1			T272	1		T181	2		T179	1
all_levels[20]	auto[0]	399657	1			T11	1670		T89	3		T14	802
all_levels[20]	auto[1]	24	1			T115	1		T126	1		T229	1
all_levels[21]	auto[0]	290213	1			T10	3		T11	1679		T14	996
all_levels[21]	auto[1]	21	1			T155	2		T30	1		T193	2
all_levels[22]	auto[0]	301561	1			T11	1681		T89	1		T14	885
all_levels[22]	auto[1]	16	1			T20	1		T193	2		T317	1
all_levels[23]	auto[0]	321474	1			T7	38		T11	2093		T12	1
all_levels[23]	auto[1]	19	1			T130	1		T132	1		T313	1
all_levels[24]	auto[0]	231914	1			T11	1139		T12	1		T89	2
all_levels[24]	auto[1]	43	1			T155	1		T115	3		T117	1
all_levels[25]	auto[0]	213461	1			T11	1136		T12	1		T89	1
all_levels[25]	auto[1]	24	1			T122	1		T300	1		T141	1
all_levels[26]	auto[0]	153655	1			T9	2		T11	1145		T12	2
all_levels[26]	auto[1]	18	1			T255	2		T251	4		T32	1
all_levels[27]	auto[0]	181289	1			T7	1		T9	3		T11	1140
all_levels[27]	auto[1]	16	1			T129	2		T318	1		T166	1
all_levels[28]	auto[0]	171277	1			T11	1103		T12	2		T89	1
all_levels[28]	auto[1]	13	1			T155	1		T301	1		T262	1
all_levels[29]	auto[0]	271967	1			T7	1		T11	1143		T12	3
all_levels[29]	auto[1]	26	1			T123	1		T187	1		T17	1
all_levels[30]	auto[0]	271221	1			T11	1133		T12	5		T14	1367
all_levels[30]	auto[1]	25	1			T129	1		T148	1		T181	1
all_levels[31]	auto[0]	562589	1			T11	1125		T12	5		T89	1
all_levels[31]	auto[1]	21	1			T281	1		T33	1		T319	2
all_levels[32]	auto[0]	13287699	1			T4	2		T6	6		T7	5
all_levels[32]	auto[1]	503	1			T4	1		T6	4		T7	2